Searched refs:AMDGPU_IRQ_STATE_ENABLE (Results 1 – 25 of 28) sorted by relevance
12
38 AMDGPU_IRQ_STATE_ENABLE, enumerator
229 (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0); in xgpu_ai_set_mailbox_ack_irq()281 (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0); in xgpu_ai_set_mailbox_rcv_irq()
506 (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0); in xgpu_vi_set_mailbox_ack_irq()535 (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0); in xgpu_vi_set_mailbox_rcv_irq()
617 case AMDGPU_IRQ_STATE_ENABLE: in si_dma_set_trap_irq_state()633 case AMDGPU_IRQ_STATE_ENABLE: in si_dma_set_trap_irq_state()
422 state = AMDGPU_IRQ_STATE_ENABLE; in amdgpu_irq_update()
528 if (state == AMDGPU_IRQ_STATE_ENABLE) in vce_v2_0_set_interrupt_state()
1141 case AMDGPU_IRQ_STATE_ENABLE: in cik_sdma_set_trap_irq_state()1157 case AMDGPU_IRQ_STATE_ENABLE: in cik_sdma_set_trap_irq_state()
1075 case AMDGPU_IRQ_STATE_ENABLE: in sdma_v2_4_set_trap_irq_state()1091 case AMDGPU_IRQ_STATE_ENABLE: in sdma_v2_4_set_trap_irq_state()
4367 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_0_set_gfx_eop_interrupt_state()4370 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_0_set_gfx_eop_interrupt_state()4419 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_0_set_compute_eop_interrupt_state()4437 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_0_set_priv_reg_fault_state()4440 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_0_set_priv_reg_fault_state()4456 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_0_set_priv_inst_fault_state()4459 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_0_set_priv_inst_fault_state()
1411 case AMDGPU_IRQ_STATE_ENABLE: in sdma_v3_0_set_trap_irq_state()1427 case AMDGPU_IRQ_STATE_ENABLE: in sdma_v3_0_set_trap_irq_state()
3257 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v6_0_set_gfx_eop_interrupt_state()3286 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v6_0_set_compute_eop_interrupt_state()3320 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v6_0_set_priv_reg_fault_state()3345 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v6_0_set_priv_inst_fault_state()
1089 case AMDGPU_IRQ_STATE_ENABLE: in gmc_v6_0_vm_fault_interrupt_state()
714 if (state == AMDGPU_IRQ_STATE_ENABLE) in vce_v3_0_set_interrupt_state()
228 case AMDGPU_IRQ_STATE_ENABLE: in gmc_v9_0_vm_fault_interrupt_state()
2863 case AMDGPU_IRQ_STATE_ENABLE: in dce_v8_0_set_crtc_vblank_interrupt_state()2914 case AMDGPU_IRQ_STATE_ENABLE: in dce_v8_0_set_crtc_vline_interrupt_state()2942 case AMDGPU_IRQ_STATE_ENABLE: in dce_v8_0_set_hpd_interrupt_state()
4801 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v7_0_set_gfx_eop_interrupt_state()4852 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v7_0_set_compute_eop_interrupt_state()4875 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v7_0_set_priv_reg_fault_state()4900 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v7_0_set_priv_inst_fault_state()
1013 if (state == AMDGPU_IRQ_STATE_ENABLE) in vce_v4_0_set_interrupt_state()
3077 case AMDGPU_IRQ_STATE_ENABLE: in dce_v11_0_set_crtc_vblank_interrupt_state()3106 case AMDGPU_IRQ_STATE_ENABLE: in dce_v11_0_set_crtc_vline_interrupt_state()3135 case AMDGPU_IRQ_STATE_ENABLE: in dce_v11_0_set_hpd_irq_state()
2951 case AMDGPU_IRQ_STATE_ENABLE: in dce_v10_0_set_crtc_vblank_interrupt_state()2980 case AMDGPU_IRQ_STATE_ENABLE: in dce_v10_0_set_crtc_vline_interrupt_state()3009 case AMDGPU_IRQ_STATE_ENABLE: in dce_v10_0_set_hpd_irq_state()
1254 case AMDGPU_IRQ_STATE_ENABLE: in gmc_v7_0_vm_fault_interrupt_state()
1404 case AMDGPU_IRQ_STATE_ENABLE: in gmc_v8_0_vm_fault_interrupt_state()
2812 case AMDGPU_IRQ_STATE_ENABLE: in dce_v6_0_set_crtc_vblank_interrupt_state()2847 case AMDGPU_IRQ_STATE_ENABLE: in dce_v6_0_set_hpd_interrupt_state()
3154 case AMDGPU_IRQ_STATE_ENABLE: in kv_dpm_set_interrupt_state()3171 case AMDGPU_IRQ_STATE_ENABLE: in kv_dpm_set_interrupt_state()
1383 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in sdma_v4_0_set_trap_irq_state()
532 bool st = (state == AMDGPU_IRQ_STATE_ENABLE); in amdgpu_dm_set_hpd_irq_state()563 st = (state == AMDGPU_IRQ_STATE_ENABLE); in dm_irq_state()