Home
last modified time | relevance | path

Searched refs:AF11 (Results 1 – 5 of 5) sorted by relevance

/Linux-v4.19/arch/arm/boot/dts/
Dstm32mp157-pinctrl.dtsi162 pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
163 <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
164 <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
165 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
166 <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
167 <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
168 <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
169 <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
170 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
176 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
[all …]
Dstm32f4-pinctrl.dtsi236 pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_MII_TXD0_ETH_RMII_TXD0 */
237 <STM32_PINMUX('G', 14, AF11)>, /* ETH_MII_TXD1_ETH_RMII_TXD1 */
238 <STM32_PINMUX('C', 2, AF11)>, /* ETH_MII_TXD2 */
239 <STM32_PINMUX('B', 8, AF11)>, /* ETH_MII_TXD3 */
240 <STM32_PINMUX('C', 3, AF11)>, /* ETH_MII_TX_CLK */
241 <STM32_PINMUX('G', 11,AF11)>, /* ETH_MII_TX_EN_ETH_RMII_TX_EN */
242 <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
243 <STM32_PINMUX('C', 1, AF11)>, /* ETH_MDC */
244 <STM32_PINMUX('A', 1, AF11)>, /* ETH_MII_RX_CLK_ETH_RMII_REF_CLK */
245 <STM32_PINMUX('A', 7, AF11)>, /* ETH_MII_RX_DV_ETH_RMII_CRS_DV */
[all …]
Dstm32f7-pinctrl.dtsi259 pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */
260 <STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */
263 <STM32_PINMUX('D', 6, AF11)>, /* SDMMC2 CLK */
264 <STM32_PINMUX('D', 7, AF11)>; /* SDMMC2 CMD */
272 pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */
273 <STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */
276 <STM32_PINMUX('D', 6, AF11)>; /* SDMMC2 CLK */
282 pinmux = <STM32_PINMUX('D', 7, AF11)>; /* SDMMC2 CMD */
/Linux-v4.19/include/dt-bindings/pinctrl/
Dstm32-pinfunc.h23 #define AF11 0xc macro
/Linux-v4.19/Documentation/networking/
Dpktgen.txt218 pgset "tos XX" set former IPv4 TOS field (e.g. "tos 28" for AF11 no ECN, default 00)