1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (C) 2012-2018 ARM Limited or its affiliates. */
3
4 #ifndef __CC_HW_QUEUE_DEFS_H__
5 #define __CC_HW_QUEUE_DEFS_H__
6
7 #include <linux/types.h>
8
9 #include "cc_kernel_regs.h"
10 #include <linux/bitfield.h>
11
12 /******************************************************************************
13 * DEFINITIONS
14 ******************************************************************************/
15
16 #define HW_DESC_SIZE_WORDS 6
17 /* Define max. available slots in HW queue */
18 #define HW_QUEUE_SLOTS_MAX 15
19
20 #define CC_REG_LOW(word, name) \
21 (CC_DSCRPTR_QUEUE_WORD ## word ## _ ## name ## _BIT_SHIFT)
22
23 #define CC_REG_HIGH(word, name) \
24 (CC_REG_LOW(word, name) + \
25 CC_DSCRPTR_QUEUE_WORD ## word ## _ ## name ## _BIT_SIZE - 1)
26
27 #define CC_GENMASK(word, name) \
28 GENMASK(CC_REG_HIGH(word, name), CC_REG_LOW(word, name))
29
30 #define WORD0_VALUE CC_GENMASK(0, VALUE)
31 #define WORD1_DIN_CONST_VALUE CC_GENMASK(1, DIN_CONST_VALUE)
32 #define WORD1_DIN_DMA_MODE CC_GENMASK(1, DIN_DMA_MODE)
33 #define WORD1_DIN_SIZE CC_GENMASK(1, DIN_SIZE)
34 #define WORD1_NOT_LAST CC_GENMASK(1, NOT_LAST)
35 #define WORD1_NS_BIT CC_GENMASK(1, NS_BIT)
36 #define WORD2_VALUE CC_GENMASK(2, VALUE)
37 #define WORD3_DOUT_DMA_MODE CC_GENMASK(3, DOUT_DMA_MODE)
38 #define WORD3_DOUT_LAST_IND CC_GENMASK(3, DOUT_LAST_IND)
39 #define WORD3_DOUT_SIZE CC_GENMASK(3, DOUT_SIZE)
40 #define WORD3_HASH_XOR_BIT CC_GENMASK(3, HASH_XOR_BIT)
41 #define WORD3_NS_BIT CC_GENMASK(3, NS_BIT)
42 #define WORD3_QUEUE_LAST_IND CC_GENMASK(3, QUEUE_LAST_IND)
43 #define WORD4_ACK_NEEDED CC_GENMASK(4, ACK_NEEDED)
44 #define WORD4_AES_SEL_N_HASH CC_GENMASK(4, AES_SEL_N_HASH)
45 #define WORD4_BYTES_SWAP CC_GENMASK(4, BYTES_SWAP)
46 #define WORD4_CIPHER_CONF0 CC_GENMASK(4, CIPHER_CONF0)
47 #define WORD4_CIPHER_CONF1 CC_GENMASK(4, CIPHER_CONF1)
48 #define WORD4_CIPHER_CONF2 CC_GENMASK(4, CIPHER_CONF2)
49 #define WORD4_CIPHER_DO CC_GENMASK(4, CIPHER_DO)
50 #define WORD4_CIPHER_MODE CC_GENMASK(4, CIPHER_MODE)
51 #define WORD4_CMAC_SIZE0 CC_GENMASK(4, CMAC_SIZE0)
52 #define WORD4_DATA_FLOW_MODE CC_GENMASK(4, DATA_FLOW_MODE)
53 #define WORD4_KEY_SIZE CC_GENMASK(4, KEY_SIZE)
54 #define WORD4_SETUP_OPERATION CC_GENMASK(4, SETUP_OPERATION)
55 #define WORD5_DIN_ADDR_HIGH CC_GENMASK(5, DIN_ADDR_HIGH)
56 #define WORD5_DOUT_ADDR_HIGH CC_GENMASK(5, DOUT_ADDR_HIGH)
57
58 /******************************************************************************
59 * TYPE DEFINITIONS
60 ******************************************************************************/
61
62 struct cc_hw_desc {
63 union {
64 u32 word[HW_DESC_SIZE_WORDS];
65 u16 hword[HW_DESC_SIZE_WORDS * 2];
66 };
67 };
68
69 enum cc_axi_sec {
70 AXI_SECURE = 0,
71 AXI_NOT_SECURE = 1
72 };
73
74 enum cc_desc_direction {
75 DESC_DIRECTION_ILLEGAL = -1,
76 DESC_DIRECTION_ENCRYPT_ENCRYPT = 0,
77 DESC_DIRECTION_DECRYPT_DECRYPT = 1,
78 DESC_DIRECTION_DECRYPT_ENCRYPT = 3,
79 DESC_DIRECTION_END = S32_MAX,
80 };
81
82 enum cc_dma_mode {
83 DMA_MODE_NULL = -1,
84 NO_DMA = 0,
85 DMA_SRAM = 1,
86 DMA_DLLI = 2,
87 DMA_MLLI = 3,
88 DMA_MODE_END = S32_MAX,
89 };
90
91 enum cc_flow_mode {
92 FLOW_MODE_NULL = -1,
93 /* data flows */
94 BYPASS = 0,
95 DIN_AES_DOUT = 1,
96 AES_to_HASH = 2,
97 AES_and_HASH = 3,
98 DIN_DES_DOUT = 4,
99 DES_to_HASH = 5,
100 DES_and_HASH = 6,
101 DIN_HASH = 7,
102 DIN_HASH_and_BYPASS = 8,
103 AESMAC_and_BYPASS = 9,
104 AES_to_HASH_and_DOUT = 10,
105 DIN_RC4_DOUT = 11,
106 DES_to_HASH_and_DOUT = 12,
107 AES_to_AES_to_HASH_and_DOUT = 13,
108 AES_to_AES_to_HASH = 14,
109 AES_to_HASH_and_AES = 15,
110 DIN_AES_AESMAC = 17,
111 HASH_to_DOUT = 18,
112 /* setup flows */
113 S_DIN_to_AES = 32,
114 S_DIN_to_AES2 = 33,
115 S_DIN_to_DES = 34,
116 S_DIN_to_RC4 = 35,
117 S_DIN_to_HASH = 37,
118 S_AES_to_DOUT = 38,
119 S_AES2_to_DOUT = 39,
120 S_RC4_to_DOUT = 41,
121 S_DES_to_DOUT = 42,
122 S_HASH_to_DOUT = 43,
123 SET_FLOW_ID = 44,
124 FLOW_MODE_END = S32_MAX,
125 };
126
127 enum cc_setup_op {
128 SETUP_LOAD_NOP = 0,
129 SETUP_LOAD_STATE0 = 1,
130 SETUP_LOAD_STATE1 = 2,
131 SETUP_LOAD_STATE2 = 3,
132 SETUP_LOAD_KEY0 = 4,
133 SETUP_LOAD_XEX_KEY = 5,
134 SETUP_WRITE_STATE0 = 8,
135 SETUP_WRITE_STATE1 = 9,
136 SETUP_WRITE_STATE2 = 10,
137 SETUP_WRITE_STATE3 = 11,
138 SETUP_OP_END = S32_MAX,
139 };
140
141 enum cc_hash_conf_pad {
142 HASH_PADDING_DISABLED = 0,
143 HASH_PADDING_ENABLED = 1,
144 HASH_DIGEST_RESULT_LITTLE_ENDIAN = 2,
145 HASH_CONFIG1_PADDING_RESERVE32 = S32_MAX,
146 };
147
148 enum cc_aes_mac_selector {
149 AES_SK = 1,
150 AES_CMAC_INIT = 2,
151 AES_CMAC_SIZE0 = 3,
152 AES_MAC_END = S32_MAX,
153 };
154
155 #define HW_KEY_MASK_CIPHER_DO 0x3
156 #define HW_KEY_SHIFT_CIPHER_CFG2 2
157
158 /* HwCryptoKey[1:0] is mapped to cipher_do[1:0] */
159 /* HwCryptoKey[2:3] is mapped to cipher_config2[1:0] */
160 enum cc_hw_crypto_key {
161 USER_KEY = 0, /* 0x0000 */
162 ROOT_KEY = 1, /* 0x0001 */
163 PROVISIONING_KEY = 2, /* 0x0010 */ /* ==KCP */
164 SESSION_KEY = 3, /* 0x0011 */
165 RESERVED_KEY = 4, /* NA */
166 PLATFORM_KEY = 5, /* 0x0101 */
167 CUSTOMER_KEY = 6, /* 0x0110 */
168 KFDE0_KEY = 7, /* 0x0111 */
169 KFDE1_KEY = 9, /* 0x1001 */
170 KFDE2_KEY = 10, /* 0x1010 */
171 KFDE3_KEY = 11, /* 0x1011 */
172 END_OF_KEYS = S32_MAX,
173 };
174
175 enum cc_hw_aes_key_size {
176 AES_128_KEY = 0,
177 AES_192_KEY = 1,
178 AES_256_KEY = 2,
179 END_OF_AES_KEYS = S32_MAX,
180 };
181
182 enum cc_hash_cipher_pad {
183 DO_NOT_PAD = 0,
184 DO_PAD = 1,
185 HASH_CIPHER_DO_PADDING_RESERVE32 = S32_MAX,
186 };
187
188 /*****************************/
189 /* Descriptor packing macros */
190 /*****************************/
191
192 /*
193 * Init a HW descriptor struct
194 * @pdesc: pointer HW descriptor struct
195 */
hw_desc_init(struct cc_hw_desc * pdesc)196 static inline void hw_desc_init(struct cc_hw_desc *pdesc)
197 {
198 memset(pdesc, 0, sizeof(struct cc_hw_desc));
199 }
200
201 /*
202 * Indicates the end of current HW descriptors flow and release the HW engines.
203 *
204 * @pdesc: pointer HW descriptor struct
205 */
set_queue_last_ind_bit(struct cc_hw_desc * pdesc)206 static inline void set_queue_last_ind_bit(struct cc_hw_desc *pdesc)
207 {
208 pdesc->word[3] |= FIELD_PREP(WORD3_QUEUE_LAST_IND, 1);
209 }
210
211 /*
212 * Set the DIN field of a HW descriptors
213 *
214 * @pdesc: pointer HW descriptor struct
215 * @dma_mode: dmaMode The DMA mode: NO_DMA, SRAM, DLLI, MLLI, CONSTANT
216 * @addr: dinAdr DIN address
217 * @size: Data size in bytes
218 * @axi_sec: AXI secure bit
219 */
set_din_type(struct cc_hw_desc * pdesc,enum cc_dma_mode dma_mode,dma_addr_t addr,u32 size,enum cc_axi_sec axi_sec)220 static inline void set_din_type(struct cc_hw_desc *pdesc,
221 enum cc_dma_mode dma_mode, dma_addr_t addr,
222 u32 size, enum cc_axi_sec axi_sec)
223 {
224 pdesc->word[0] = (u32)addr;
225 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
226 pdesc->word[5] |= FIELD_PREP(WORD5_DIN_ADDR_HIGH, ((u16)(addr >> 32)));
227 #endif
228 pdesc->word[1] |= FIELD_PREP(WORD1_DIN_DMA_MODE, dma_mode) |
229 FIELD_PREP(WORD1_DIN_SIZE, size) |
230 FIELD_PREP(WORD1_NS_BIT, axi_sec);
231 }
232
233 /*
234 * Set the DIN field of a HW descriptors to NO DMA mode.
235 * Used for NOP descriptor, register patches and other special modes.
236 *
237 * @pdesc: pointer HW descriptor struct
238 * @addr: DIN address
239 * @size: Data size in bytes
240 */
set_din_no_dma(struct cc_hw_desc * pdesc,u32 addr,u32 size)241 static inline void set_din_no_dma(struct cc_hw_desc *pdesc, u32 addr, u32 size)
242 {
243 pdesc->word[0] = addr;
244 pdesc->word[1] |= FIELD_PREP(WORD1_DIN_SIZE, size);
245 }
246
247 /*
248 * Set the DIN field of a HW descriptors to SRAM mode.
249 * Note: No need to check SRAM alignment since host requests do not use SRAM and
250 * adaptor will enforce alignment check.
251 *
252 * @pdesc: pointer HW descriptor struct
253 * @addr: DIN address
254 * @size Data size in bytes
255 */
set_din_sram(struct cc_hw_desc * pdesc,dma_addr_t addr,u32 size)256 static inline void set_din_sram(struct cc_hw_desc *pdesc, dma_addr_t addr,
257 u32 size)
258 {
259 pdesc->word[0] = (u32)addr;
260 pdesc->word[1] |= FIELD_PREP(WORD1_DIN_SIZE, size) |
261 FIELD_PREP(WORD1_DIN_DMA_MODE, DMA_SRAM);
262 }
263
264 /*
265 * Set the DIN field of a HW descriptors to CONST mode
266 *
267 * @pdesc: pointer HW descriptor struct
268 * @val: DIN const value
269 * @size: Data size in bytes
270 */
set_din_const(struct cc_hw_desc * pdesc,u32 val,u32 size)271 static inline void set_din_const(struct cc_hw_desc *pdesc, u32 val, u32 size)
272 {
273 pdesc->word[0] = val;
274 pdesc->word[1] |= FIELD_PREP(WORD1_DIN_CONST_VALUE, 1) |
275 FIELD_PREP(WORD1_DIN_DMA_MODE, DMA_SRAM) |
276 FIELD_PREP(WORD1_DIN_SIZE, size);
277 }
278
279 /*
280 * Set the DIN not last input data indicator
281 *
282 * @pdesc: pointer HW descriptor struct
283 */
set_din_not_last_indication(struct cc_hw_desc * pdesc)284 static inline void set_din_not_last_indication(struct cc_hw_desc *pdesc)
285 {
286 pdesc->word[1] |= FIELD_PREP(WORD1_NOT_LAST, 1);
287 }
288
289 /*
290 * Set the DOUT field of a HW descriptors
291 *
292 * @pdesc: pointer HW descriptor struct
293 * @dma_mode: The DMA mode: NO_DMA, SRAM, DLLI, MLLI, CONSTANT
294 * @addr: DOUT address
295 * @size: Data size in bytes
296 * @axi_sec: AXI secure bit
297 */
set_dout_type(struct cc_hw_desc * pdesc,enum cc_dma_mode dma_mode,dma_addr_t addr,u32 size,enum cc_axi_sec axi_sec)298 static inline void set_dout_type(struct cc_hw_desc *pdesc,
299 enum cc_dma_mode dma_mode, dma_addr_t addr,
300 u32 size, enum cc_axi_sec axi_sec)
301 {
302 pdesc->word[2] = (u32)addr;
303 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
304 pdesc->word[5] |= FIELD_PREP(WORD5_DOUT_ADDR_HIGH, ((u16)(addr >> 32)));
305 #endif
306 pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_DMA_MODE, dma_mode) |
307 FIELD_PREP(WORD3_DOUT_SIZE, size) |
308 FIELD_PREP(WORD3_NS_BIT, axi_sec);
309 }
310
311 /*
312 * Set the DOUT field of a HW descriptors to DLLI type
313 * The LAST INDICATION is provided by the user
314 *
315 * @pdesc pointer HW descriptor struct
316 * @addr: DOUT address
317 * @size: Data size in bytes
318 * @last_ind: The last indication bit
319 * @axi_sec: AXI secure bit
320 */
set_dout_dlli(struct cc_hw_desc * pdesc,dma_addr_t addr,u32 size,enum cc_axi_sec axi_sec,u32 last_ind)321 static inline void set_dout_dlli(struct cc_hw_desc *pdesc, dma_addr_t addr,
322 u32 size, enum cc_axi_sec axi_sec,
323 u32 last_ind)
324 {
325 set_dout_type(pdesc, DMA_DLLI, addr, size, axi_sec);
326 pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_LAST_IND, last_ind);
327 }
328
329 /*
330 * Set the DOUT field of a HW descriptors to DLLI type
331 * The LAST INDICATION is provided by the user
332 *
333 * @pdesc: pointer HW descriptor struct
334 * @addr: DOUT address
335 * @size: Data size in bytes
336 * @last_ind: The last indication bit
337 * @axi_sec: AXI secure bit
338 */
set_dout_mlli(struct cc_hw_desc * pdesc,dma_addr_t addr,u32 size,enum cc_axi_sec axi_sec,bool last_ind)339 static inline void set_dout_mlli(struct cc_hw_desc *pdesc, dma_addr_t addr,
340 u32 size, enum cc_axi_sec axi_sec,
341 bool last_ind)
342 {
343 set_dout_type(pdesc, DMA_MLLI, addr, size, axi_sec);
344 pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_LAST_IND, last_ind);
345 }
346
347 /*
348 * Set the DOUT field of a HW descriptors to NO DMA mode.
349 * Used for NOP descriptor, register patches and other special modes.
350 *
351 * @pdesc: pointer HW descriptor struct
352 * @addr: DOUT address
353 * @size: Data size in bytes
354 * @write_enable: Enables a write operation to a register
355 */
set_dout_no_dma(struct cc_hw_desc * pdesc,u32 addr,u32 size,bool write_enable)356 static inline void set_dout_no_dma(struct cc_hw_desc *pdesc, u32 addr,
357 u32 size, bool write_enable)
358 {
359 pdesc->word[2] = addr;
360 pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_SIZE, size) |
361 FIELD_PREP(WORD3_DOUT_LAST_IND, write_enable);
362 }
363
364 /*
365 * Set the word for the XOR operation.
366 *
367 * @pdesc: pointer HW descriptor struct
368 * @val: xor data value
369 */
set_xor_val(struct cc_hw_desc * pdesc,u32 val)370 static inline void set_xor_val(struct cc_hw_desc *pdesc, u32 val)
371 {
372 pdesc->word[2] = val;
373 }
374
375 /*
376 * Sets the XOR indicator bit in the descriptor
377 *
378 * @pdesc: pointer HW descriptor struct
379 */
set_xor_active(struct cc_hw_desc * pdesc)380 static inline void set_xor_active(struct cc_hw_desc *pdesc)
381 {
382 pdesc->word[3] |= FIELD_PREP(WORD3_HASH_XOR_BIT, 1);
383 }
384
385 /*
386 * Select the AES engine instead of HASH engine when setting up combined mode
387 * with AES XCBC MAC
388 *
389 * @pdesc: pointer HW descriptor struct
390 */
set_aes_not_hash_mode(struct cc_hw_desc * pdesc)391 static inline void set_aes_not_hash_mode(struct cc_hw_desc *pdesc)
392 {
393 pdesc->word[4] |= FIELD_PREP(WORD4_AES_SEL_N_HASH, 1);
394 }
395
396 /*
397 * Set the DOUT field of a HW descriptors to SRAM mode
398 * Note: No need to check SRAM alignment since host requests do not use SRAM and
399 * adaptor will enforce alignment check.
400 *
401 * @pdesc: pointer HW descriptor struct
402 * @addr: DOUT address
403 * @size: Data size in bytes
404 */
set_dout_sram(struct cc_hw_desc * pdesc,u32 addr,u32 size)405 static inline void set_dout_sram(struct cc_hw_desc *pdesc, u32 addr, u32 size)
406 {
407 pdesc->word[2] = addr;
408 pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_DMA_MODE, DMA_SRAM) |
409 FIELD_PREP(WORD3_DOUT_SIZE, size);
410 }
411
412 /*
413 * Sets the data unit size for XEX mode in data_out_addr[15:0]
414 *
415 * @pdesc: pDesc pointer HW descriptor struct
416 * @size: data unit size for XEX mode
417 */
set_xex_data_unit_size(struct cc_hw_desc * pdesc,u32 size)418 static inline void set_xex_data_unit_size(struct cc_hw_desc *pdesc, u32 size)
419 {
420 pdesc->word[2] = size;
421 }
422
423 /*
424 * Set the number of rounds for Multi2 in data_out_addr[15:0]
425 *
426 * @pdesc: pointer HW descriptor struct
427 * @num: number of rounds for Multi2
428 */
set_multi2_num_rounds(struct cc_hw_desc * pdesc,u32 num)429 static inline void set_multi2_num_rounds(struct cc_hw_desc *pdesc, u32 num)
430 {
431 pdesc->word[2] = num;
432 }
433
434 /*
435 * Set the flow mode.
436 *
437 * @pdesc: pointer HW descriptor struct
438 * @mode: Any one of the modes defined in [CC7x-DESC]
439 */
set_flow_mode(struct cc_hw_desc * pdesc,enum cc_flow_mode mode)440 static inline void set_flow_mode(struct cc_hw_desc *pdesc,
441 enum cc_flow_mode mode)
442 {
443 pdesc->word[4] |= FIELD_PREP(WORD4_DATA_FLOW_MODE, mode);
444 }
445
446 /*
447 * Set the cipher mode.
448 *
449 * @pdesc: pointer HW descriptor struct
450 * @mode: Any one of the modes defined in [CC7x-DESC]
451 */
set_cipher_mode(struct cc_hw_desc * pdesc,enum drv_cipher_mode mode)452 static inline void set_cipher_mode(struct cc_hw_desc *pdesc,
453 enum drv_cipher_mode mode)
454 {
455 pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_MODE, mode);
456 }
457
458 /*
459 * Set the cipher configuration fields.
460 *
461 * @pdesc: pointer HW descriptor struct
462 * @mode: Any one of the modes defined in [CC7x-DESC]
463 */
set_cipher_config0(struct cc_hw_desc * pdesc,enum drv_crypto_direction mode)464 static inline void set_cipher_config0(struct cc_hw_desc *pdesc,
465 enum drv_crypto_direction mode)
466 {
467 pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_CONF0, mode);
468 }
469
470 /*
471 * Set the cipher configuration fields.
472 *
473 * @pdesc: pointer HW descriptor struct
474 * @config: Any one of the modes defined in [CC7x-DESC]
475 */
set_cipher_config1(struct cc_hw_desc * pdesc,enum cc_hash_conf_pad config)476 static inline void set_cipher_config1(struct cc_hw_desc *pdesc,
477 enum cc_hash_conf_pad config)
478 {
479 pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_CONF1, config);
480 }
481
482 /*
483 * Set HW key configuration fields.
484 *
485 * @pdesc: pointer HW descriptor struct
486 * @hw_key: The HW key slot asdefined in enum cc_hw_crypto_key
487 */
set_hw_crypto_key(struct cc_hw_desc * pdesc,enum cc_hw_crypto_key hw_key)488 static inline void set_hw_crypto_key(struct cc_hw_desc *pdesc,
489 enum cc_hw_crypto_key hw_key)
490 {
491 pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_DO,
492 (hw_key & HW_KEY_MASK_CIPHER_DO)) |
493 FIELD_PREP(WORD4_CIPHER_CONF2,
494 (hw_key >> HW_KEY_SHIFT_CIPHER_CFG2));
495 }
496
497 /*
498 * Set byte order of all setup-finalize descriptors.
499 *
500 * @pdesc: pointer HW descriptor struct
501 * @config: Any one of the modes defined in [CC7x-DESC]
502 */
set_bytes_swap(struct cc_hw_desc * pdesc,bool config)503 static inline void set_bytes_swap(struct cc_hw_desc *pdesc, bool config)
504 {
505 pdesc->word[4] |= FIELD_PREP(WORD4_BYTES_SWAP, config);
506 }
507
508 /*
509 * Set CMAC_SIZE0 mode.
510 *
511 * @pdesc: pointer HW descriptor struct
512 */
set_cmac_size0_mode(struct cc_hw_desc * pdesc)513 static inline void set_cmac_size0_mode(struct cc_hw_desc *pdesc)
514 {
515 pdesc->word[4] |= FIELD_PREP(WORD4_CMAC_SIZE0, 1);
516 }
517
518 /*
519 * Set key size descriptor field.
520 *
521 * @pdesc: pointer HW descriptor struct
522 * @size: key size in bytes (NOT size code)
523 */
set_key_size(struct cc_hw_desc * pdesc,u32 size)524 static inline void set_key_size(struct cc_hw_desc *pdesc, u32 size)
525 {
526 pdesc->word[4] |= FIELD_PREP(WORD4_KEY_SIZE, size);
527 }
528
529 /*
530 * Set AES key size.
531 *
532 * @pdesc: pointer HW descriptor struct
533 * @size: key size in bytes (NOT size code)
534 */
set_key_size_aes(struct cc_hw_desc * pdesc,u32 size)535 static inline void set_key_size_aes(struct cc_hw_desc *pdesc, u32 size)
536 {
537 set_key_size(pdesc, ((size >> 3) - 2));
538 }
539
540 /*
541 * Set DES key size.
542 *
543 * @pdesc: pointer HW descriptor struct
544 * @size: key size in bytes (NOT size code)
545 */
set_key_size_des(struct cc_hw_desc * pdesc,u32 size)546 static inline void set_key_size_des(struct cc_hw_desc *pdesc, u32 size)
547 {
548 set_key_size(pdesc, ((size >> 3) - 1));
549 }
550
551 /*
552 * Set the descriptor setup mode
553 *
554 * @pdesc: pointer HW descriptor struct
555 * @mode: Any one of the setup modes defined in [CC7x-DESC]
556 */
set_setup_mode(struct cc_hw_desc * pdesc,enum cc_setup_op mode)557 static inline void set_setup_mode(struct cc_hw_desc *pdesc,
558 enum cc_setup_op mode)
559 {
560 pdesc->word[4] |= FIELD_PREP(WORD4_SETUP_OPERATION, mode);
561 }
562
563 /*
564 * Set the descriptor cipher DO
565 *
566 * @pdesc: pointer HW descriptor struct
567 * @config: Any one of the cipher do defined in [CC7x-DESC]
568 */
set_cipher_do(struct cc_hw_desc * pdesc,enum cc_hash_cipher_pad config)569 static inline void set_cipher_do(struct cc_hw_desc *pdesc,
570 enum cc_hash_cipher_pad config)
571 {
572 pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_DO,
573 (config & HW_KEY_MASK_CIPHER_DO));
574 }
575
576 #endif /*__CC_HW_QUEUE_DEFS_H__*/
577
