1 /*
2 * AD7280A Lithium Ion Battery Monitoring System
3 *
4 * Copyright 2011 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2.
7 */
8
9 #include <linux/device.h>
10 #include <linux/kernel.h>
11 #include <linux/slab.h>
12 #include <linux/sysfs.h>
13 #include <linux/spi/spi.h>
14 #include <linux/err.h>
15 #include <linux/delay.h>
16 #include <linux/interrupt.h>
17 #include <linux/module.h>
18
19 #include <linux/iio/iio.h>
20 #include <linux/iio/sysfs.h>
21 #include <linux/iio/events.h>
22
23 #include "ad7280a.h"
24
25 /* Registers */
26 #define AD7280A_CELL_VOLTAGE_1 0x0 /* D11 to D0, Read only */
27 #define AD7280A_CELL_VOLTAGE_2 0x1 /* D11 to D0, Read only */
28 #define AD7280A_CELL_VOLTAGE_3 0x2 /* D11 to D0, Read only */
29 #define AD7280A_CELL_VOLTAGE_4 0x3 /* D11 to D0, Read only */
30 #define AD7280A_CELL_VOLTAGE_5 0x4 /* D11 to D0, Read only */
31 #define AD7280A_CELL_VOLTAGE_6 0x5 /* D11 to D0, Read only */
32 #define AD7280A_AUX_ADC_1 0x6 /* D11 to D0, Read only */
33 #define AD7280A_AUX_ADC_2 0x7 /* D11 to D0, Read only */
34 #define AD7280A_AUX_ADC_3 0x8 /* D11 to D0, Read only */
35 #define AD7280A_AUX_ADC_4 0x9 /* D11 to D0, Read only */
36 #define AD7280A_AUX_ADC_5 0xA /* D11 to D0, Read only */
37 #define AD7280A_AUX_ADC_6 0xB /* D11 to D0, Read only */
38 #define AD7280A_SELF_TEST 0xC /* D11 to D0, Read only */
39 #define AD7280A_CONTROL_HB 0xD /* D15 to D8, Read/write */
40 #define AD7280A_CONTROL_LB 0xE /* D7 to D0, Read/write */
41 #define AD7280A_CELL_OVERVOLTAGE 0xF /* D7 to D0, Read/write */
42 #define AD7280A_CELL_UNDERVOLTAGE 0x10 /* D7 to D0, Read/write */
43 #define AD7280A_AUX_ADC_OVERVOLTAGE 0x11 /* D7 to D0, Read/write */
44 #define AD7280A_AUX_ADC_UNDERVOLTAGE 0x12 /* D7 to D0, Read/write */
45 #define AD7280A_ALERT 0x13 /* D7 to D0, Read/write */
46 #define AD7280A_CELL_BALANCE 0x14 /* D7 to D0, Read/write */
47 #define AD7280A_CB1_TIMER 0x15 /* D7 to D0, Read/write */
48 #define AD7280A_CB2_TIMER 0x16 /* D7 to D0, Read/write */
49 #define AD7280A_CB3_TIMER 0x17 /* D7 to D0, Read/write */
50 #define AD7280A_CB4_TIMER 0x18 /* D7 to D0, Read/write */
51 #define AD7280A_CB5_TIMER 0x19 /* D7 to D0, Read/write */
52 #define AD7280A_CB6_TIMER 0x1A /* D7 to D0, Read/write */
53 #define AD7280A_PD_TIMER 0x1B /* D7 to D0, Read/write */
54 #define AD7280A_READ 0x1C /* D7 to D0, Read/write */
55 #define AD7280A_CNVST_CONTROL 0x1D /* D7 to D0, Read/write */
56
57 /* Bits and Masks */
58 #define AD7280A_CTRL_HB_CONV_INPUT_ALL 0
59 #define AD7280A_CTRL_HB_CONV_INPUT_6CELL_AUX1_3_4 BIT(6)
60 #define AD7280A_CTRL_HB_CONV_INPUT_6CELL BIT(7)
61 #define AD7280A_CTRL_HB_CONV_INPUT_SELF_TEST (BIT(7) | BIT(6))
62 #define AD7280A_CTRL_HB_CONV_RES_READ_ALL 0
63 #define AD7280A_CTRL_HB_CONV_RES_READ_6CELL_AUX1_3_4 BIT(4)
64 #define AD7280A_CTRL_HB_CONV_RES_READ_6CELL BIT(5)
65 #define AD7280A_CTRL_HB_CONV_RES_READ_NO (BIT(5) | BIT(4))
66 #define AD7280A_CTRL_HB_CONV_START_CNVST 0
67 #define AD7280A_CTRL_HB_CONV_START_CS BIT(3)
68 #define AD7280A_CTRL_HB_CONV_AVG_DIS 0
69 #define AD7280A_CTRL_HB_CONV_AVG_2 BIT(1)
70 #define AD7280A_CTRL_HB_CONV_AVG_4 BIT(2)
71 #define AD7280A_CTRL_HB_CONV_AVG_8 (BIT(2) | BIT(1))
72 #define AD7280A_CTRL_HB_CONV_AVG(x) ((x) << 1)
73 #define AD7280A_CTRL_HB_PWRDN_SW BIT(0)
74
75 #define AD7280A_CTRL_LB_SWRST BIT(7)
76 #define AD7280A_CTRL_LB_ACQ_TIME_400ns 0
77 #define AD7280A_CTRL_LB_ACQ_TIME_800ns BIT(5)
78 #define AD7280A_CTRL_LB_ACQ_TIME_1200ns BIT(6)
79 #define AD7280A_CTRL_LB_ACQ_TIME_1600ns (BIT(6) | BIT(5))
80 #define AD7280A_CTRL_LB_ACQ_TIME(x) ((x) << 5)
81 #define AD7280A_CTRL_LB_MUST_SET BIT(4)
82 #define AD7280A_CTRL_LB_THERMISTOR_EN BIT(3)
83 #define AD7280A_CTRL_LB_LOCK_DEV_ADDR BIT(2)
84 #define AD7280A_CTRL_LB_INC_DEV_ADDR BIT(1)
85 #define AD7280A_CTRL_LB_DAISY_CHAIN_RB_EN BIT(0)
86
87 #define AD7280A_ALERT_GEN_STATIC_HIGH BIT(6)
88 #define AD7280A_ALERT_RELAY_SIG_CHAIN_DOWN (BIT(7) | BIT(6))
89
90 #define AD7280A_ALL_CELLS (0xAD << 16)
91
92 #define AD7280A_MAX_SPI_CLK_HZ 700000 /* < 1MHz */
93 #define AD7280A_MAX_CHAIN 8
94 #define AD7280A_CELLS_PER_DEV 6
95 #define AD7280A_BITS 12
96 #define AD7280A_NUM_CH (AD7280A_AUX_ADC_6 - \
97 AD7280A_CELL_VOLTAGE_1 + 1)
98
99 #define AD7280A_DEVADDR_MASTER 0
100 #define AD7280A_DEVADDR_ALL 0x1F
101 /* 5-bit device address is sent LSB first */
ad7280a_devaddr(unsigned int addr)102 static unsigned int ad7280a_devaddr(unsigned int addr)
103 {
104 return ((addr & 0x1) << 4) |
105 ((addr & 0x2) << 3) |
106 (addr & 0x4) |
107 ((addr & 0x8) >> 3) |
108 ((addr & 0x10) >> 4);
109 }
110
111 /* During a read a valid write is mandatory.
112 * So writing to the highest available address (Address 0x1F)
113 * and setting the address all parts bit to 0 is recommended
114 * So the TXVAL is AD7280A_DEVADDR_ALL + CRC
115 */
116 #define AD7280A_READ_TXVAL 0xF800030A
117
118 /*
119 * AD7280 CRC
120 *
121 * P(x) = x^8 + x^5 + x^3 + x^2 + x^1 + x^0 = 0b100101111 => 0x2F
122 */
123 #define POLYNOM 0x2F
124 #define POLYNOM_ORDER 8
125 #define HIGHBIT (1 << (POLYNOM_ORDER - 1))
126
127 struct ad7280_state {
128 struct spi_device *spi;
129 struct iio_chan_spec *channels;
130 struct iio_dev_attr *iio_attr;
131 int slave_num;
132 int scan_cnt;
133 int readback_delay_us;
134 unsigned char crc_tab[256];
135 unsigned char ctrl_hb;
136 unsigned char ctrl_lb;
137 unsigned char cell_threshhigh;
138 unsigned char cell_threshlow;
139 unsigned char aux_threshhigh;
140 unsigned char aux_threshlow;
141 unsigned char cb_mask[AD7280A_MAX_CHAIN];
142 struct mutex lock; /* protect sensor state */
143
144 __be32 buf[2] ____cacheline_aligned;
145 };
146
ad7280_crc8_build_table(unsigned char * crc_tab)147 static void ad7280_crc8_build_table(unsigned char *crc_tab)
148 {
149 unsigned char bit, crc;
150 int cnt, i;
151
152 for (cnt = 0; cnt < 256; cnt++) {
153 crc = cnt;
154 for (i = 0; i < 8; i++) {
155 bit = crc & HIGHBIT;
156 crc <<= 1;
157 if (bit)
158 crc ^= POLYNOM;
159 }
160 crc_tab[cnt] = crc;
161 }
162 }
163
ad7280_calc_crc8(unsigned char * crc_tab,unsigned int val)164 static unsigned char ad7280_calc_crc8(unsigned char *crc_tab, unsigned int val)
165 {
166 unsigned char crc;
167
168 crc = crc_tab[val >> 16 & 0xFF];
169 crc = crc_tab[crc ^ (val >> 8 & 0xFF)];
170
171 return crc ^ (val & 0xFF);
172 }
173
ad7280_check_crc(struct ad7280_state * st,unsigned int val)174 static int ad7280_check_crc(struct ad7280_state *st, unsigned int val)
175 {
176 unsigned char crc = ad7280_calc_crc8(st->crc_tab, val >> 10);
177
178 if (crc != ((val >> 2) & 0xFF))
179 return -EIO;
180
181 return 0;
182 }
183
184 /* After initiating a conversion sequence we need to wait until the
185 * conversion is done. The delay is typically in the range of 15..30 us
186 * however depending an the number of devices in the daisy chain and the
187 * number of averages taken, conversion delays and acquisition time options
188 * it may take up to 250us, in this case we better sleep instead of busy
189 * wait.
190 */
191
ad7280_delay(struct ad7280_state * st)192 static void ad7280_delay(struct ad7280_state *st)
193 {
194 if (st->readback_delay_us < 50)
195 udelay(st->readback_delay_us);
196 else
197 usleep_range(250, 500);
198 }
199
__ad7280_read32(struct ad7280_state * st,unsigned int * val)200 static int __ad7280_read32(struct ad7280_state *st, unsigned int *val)
201 {
202 int ret;
203 struct spi_transfer t = {
204 .tx_buf = &st->buf[0],
205 .rx_buf = &st->buf[1],
206 .len = 4,
207 };
208
209 st->buf[0] = cpu_to_be32(AD7280A_READ_TXVAL);
210
211 ret = spi_sync_transfer(st->spi, &t, 1);
212 if (ret)
213 return ret;
214
215 *val = be32_to_cpu(st->buf[1]);
216
217 return 0;
218 }
219
ad7280_write(struct ad7280_state * st,unsigned int devaddr,unsigned int addr,bool all,unsigned int val)220 static int ad7280_write(struct ad7280_state *st, unsigned int devaddr,
221 unsigned int addr, bool all, unsigned int val)
222 {
223 unsigned int reg = devaddr << 27 | addr << 21 |
224 (val & 0xFF) << 13 | all << 12;
225
226 reg |= ad7280_calc_crc8(st->crc_tab, reg >> 11) << 3 | 0x2;
227 st->buf[0] = cpu_to_be32(reg);
228
229 return spi_write(st->spi, &st->buf[0], 4);
230 }
231
ad7280_read(struct ad7280_state * st,unsigned int devaddr,unsigned int addr)232 static int ad7280_read(struct ad7280_state *st, unsigned int devaddr,
233 unsigned int addr)
234 {
235 int ret;
236 unsigned int tmp;
237
238 /* turns off the read operation on all parts */
239 ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, AD7280A_CONTROL_HB, 1,
240 AD7280A_CTRL_HB_CONV_INPUT_ALL |
241 AD7280A_CTRL_HB_CONV_RES_READ_NO |
242 st->ctrl_hb);
243 if (ret)
244 return ret;
245
246 /* turns on the read operation on the addressed part */
247 ret = ad7280_write(st, devaddr, AD7280A_CONTROL_HB, 0,
248 AD7280A_CTRL_HB_CONV_INPUT_ALL |
249 AD7280A_CTRL_HB_CONV_RES_READ_ALL |
250 st->ctrl_hb);
251 if (ret)
252 return ret;
253
254 /* Set register address on the part to be read from */
255 ret = ad7280_write(st, devaddr, AD7280A_READ, 0, addr << 2);
256 if (ret)
257 return ret;
258
259 __ad7280_read32(st, &tmp);
260
261 if (ad7280_check_crc(st, tmp))
262 return -EIO;
263
264 if (((tmp >> 27) != devaddr) || (((tmp >> 21) & 0x3F) != addr))
265 return -EFAULT;
266
267 return (tmp >> 13) & 0xFF;
268 }
269
ad7280_read_channel(struct ad7280_state * st,unsigned int devaddr,unsigned int addr)270 static int ad7280_read_channel(struct ad7280_state *st, unsigned int devaddr,
271 unsigned int addr)
272 {
273 int ret;
274 unsigned int tmp;
275
276 ret = ad7280_write(st, devaddr, AD7280A_READ, 0, addr << 2);
277 if (ret)
278 return ret;
279
280 ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, AD7280A_CONTROL_HB, 1,
281 AD7280A_CTRL_HB_CONV_INPUT_ALL |
282 AD7280A_CTRL_HB_CONV_RES_READ_NO |
283 st->ctrl_hb);
284 if (ret)
285 return ret;
286
287 ret = ad7280_write(st, devaddr, AD7280A_CONTROL_HB, 0,
288 AD7280A_CTRL_HB_CONV_INPUT_ALL |
289 AD7280A_CTRL_HB_CONV_RES_READ_ALL |
290 AD7280A_CTRL_HB_CONV_START_CS |
291 st->ctrl_hb);
292 if (ret)
293 return ret;
294
295 ad7280_delay(st);
296
297 __ad7280_read32(st, &tmp);
298
299 if (ad7280_check_crc(st, tmp))
300 return -EIO;
301
302 if (((tmp >> 27) != devaddr) || (((tmp >> 23) & 0xF) != addr))
303 return -EFAULT;
304
305 return (tmp >> 11) & 0xFFF;
306 }
307
ad7280_read_all_channels(struct ad7280_state * st,unsigned int cnt,unsigned int * array)308 static int ad7280_read_all_channels(struct ad7280_state *st, unsigned int cnt,
309 unsigned int *array)
310 {
311 int i, ret;
312 unsigned int tmp, sum = 0;
313
314 ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, AD7280A_READ, 1,
315 AD7280A_CELL_VOLTAGE_1 << 2);
316 if (ret)
317 return ret;
318
319 ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, AD7280A_CONTROL_HB, 1,
320 AD7280A_CTRL_HB_CONV_INPUT_ALL |
321 AD7280A_CTRL_HB_CONV_RES_READ_ALL |
322 AD7280A_CTRL_HB_CONV_START_CS |
323 st->ctrl_hb);
324 if (ret)
325 return ret;
326
327 ad7280_delay(st);
328
329 for (i = 0; i < cnt; i++) {
330 __ad7280_read32(st, &tmp);
331
332 if (ad7280_check_crc(st, tmp))
333 return -EIO;
334
335 if (array)
336 array[i] = tmp;
337 /* only sum cell voltages */
338 if (((tmp >> 23) & 0xF) <= AD7280A_CELL_VOLTAGE_6)
339 sum += ((tmp >> 11) & 0xFFF);
340 }
341
342 return sum;
343 }
344
ad7280_chain_setup(struct ad7280_state * st)345 static int ad7280_chain_setup(struct ad7280_state *st)
346 {
347 unsigned int val, n;
348 int ret;
349
350 ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, AD7280A_CONTROL_LB, 1,
351 AD7280A_CTRL_LB_DAISY_CHAIN_RB_EN |
352 AD7280A_CTRL_LB_LOCK_DEV_ADDR |
353 AD7280A_CTRL_LB_MUST_SET |
354 AD7280A_CTRL_LB_SWRST |
355 st->ctrl_lb);
356 if (ret)
357 return ret;
358
359 ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, AD7280A_CONTROL_LB, 1,
360 AD7280A_CTRL_LB_DAISY_CHAIN_RB_EN |
361 AD7280A_CTRL_LB_LOCK_DEV_ADDR |
362 AD7280A_CTRL_LB_MUST_SET |
363 st->ctrl_lb);
364 if (ret)
365 return ret;
366
367 ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, AD7280A_READ, 1,
368 AD7280A_CONTROL_LB << 2);
369 if (ret)
370 return ret;
371
372 for (n = 0; n <= AD7280A_MAX_CHAIN; n++) {
373 __ad7280_read32(st, &val);
374 if (val == 0)
375 return n - 1;
376
377 if (ad7280_check_crc(st, val))
378 return -EIO;
379
380 if (n != ad7280a_devaddr(val >> 27))
381 return -EIO;
382 }
383
384 return -EFAULT;
385 }
386
ad7280_show_balance_sw(struct device * dev,struct device_attribute * attr,char * buf)387 static ssize_t ad7280_show_balance_sw(struct device *dev,
388 struct device_attribute *attr,
389 char *buf)
390 {
391 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
392 struct ad7280_state *st = iio_priv(indio_dev);
393 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
394
395 return sprintf(buf, "%d\n",
396 !!(st->cb_mask[this_attr->address >> 8] &
397 (1 << ((this_attr->address & 0xFF) + 2))));
398 }
399
ad7280_store_balance_sw(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)400 static ssize_t ad7280_store_balance_sw(struct device *dev,
401 struct device_attribute *attr,
402 const char *buf,
403 size_t len)
404 {
405 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
406 struct ad7280_state *st = iio_priv(indio_dev);
407 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
408 bool readin;
409 int ret;
410 unsigned int devaddr, ch;
411
412 ret = strtobool(buf, &readin);
413 if (ret)
414 return ret;
415
416 devaddr = this_attr->address >> 8;
417 ch = this_attr->address & 0xFF;
418
419 mutex_lock(&st->lock);
420 if (readin)
421 st->cb_mask[devaddr] |= 1 << (ch + 2);
422 else
423 st->cb_mask[devaddr] &= ~(1 << (ch + 2));
424
425 ret = ad7280_write(st, devaddr, AD7280A_CELL_BALANCE,
426 0, st->cb_mask[devaddr]);
427 mutex_unlock(&st->lock);
428
429 return ret ? ret : len;
430 }
431
ad7280_show_balance_timer(struct device * dev,struct device_attribute * attr,char * buf)432 static ssize_t ad7280_show_balance_timer(struct device *dev,
433 struct device_attribute *attr,
434 char *buf)
435 {
436 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
437 struct ad7280_state *st = iio_priv(indio_dev);
438 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
439 int ret;
440 unsigned int msecs;
441
442 mutex_lock(&st->lock);
443 ret = ad7280_read(st, this_attr->address >> 8,
444 this_attr->address & 0xFF);
445 mutex_unlock(&st->lock);
446
447 if (ret < 0)
448 return ret;
449
450 msecs = (ret >> 3) * 71500;
451
452 return sprintf(buf, "%u\n", msecs);
453 }
454
ad7280_store_balance_timer(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)455 static ssize_t ad7280_store_balance_timer(struct device *dev,
456 struct device_attribute *attr,
457 const char *buf,
458 size_t len)
459 {
460 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
461 struct ad7280_state *st = iio_priv(indio_dev);
462 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
463 unsigned long val;
464 int ret;
465
466 ret = kstrtoul(buf, 10, &val);
467 if (ret)
468 return ret;
469
470 val /= 71500;
471
472 if (val > 31)
473 return -EINVAL;
474
475 mutex_lock(&st->lock);
476 ret = ad7280_write(st, this_attr->address >> 8,
477 this_attr->address & 0xFF,
478 0, (val & 0x1F) << 3);
479 mutex_unlock(&st->lock);
480
481 return ret ? ret : len;
482 }
483
484 static struct attribute *ad7280_attributes[AD7280A_MAX_CHAIN *
485 AD7280A_CELLS_PER_DEV * 2 + 1];
486
487 static const struct attribute_group ad7280_attrs_group = {
488 .attrs = ad7280_attributes,
489 };
490
ad7280_channel_init(struct ad7280_state * st)491 static int ad7280_channel_init(struct ad7280_state *st)
492 {
493 int dev, ch, cnt;
494
495 st->channels = kcalloc((st->slave_num + 1) * 12 + 2,
496 sizeof(*st->channels), GFP_KERNEL);
497 if (!st->channels)
498 return -ENOMEM;
499
500 for (dev = 0, cnt = 0; dev <= st->slave_num; dev++)
501 for (ch = AD7280A_CELL_VOLTAGE_1; ch <= AD7280A_AUX_ADC_6;
502 ch++, cnt++) {
503 if (ch < AD7280A_AUX_ADC_1) {
504 st->channels[cnt].type = IIO_VOLTAGE;
505 st->channels[cnt].differential = 1;
506 st->channels[cnt].channel = (dev * 6) + ch;
507 st->channels[cnt].channel2 =
508 st->channels[cnt].channel + 1;
509 } else {
510 st->channels[cnt].type = IIO_TEMP;
511 st->channels[cnt].channel = (dev * 6) + ch - 6;
512 }
513 st->channels[cnt].indexed = 1;
514 st->channels[cnt].info_mask_separate =
515 BIT(IIO_CHAN_INFO_RAW);
516 st->channels[cnt].info_mask_shared_by_type =
517 BIT(IIO_CHAN_INFO_SCALE);
518 st->channels[cnt].address =
519 ad7280a_devaddr(dev) << 8 | ch;
520 st->channels[cnt].scan_index = cnt;
521 st->channels[cnt].scan_type.sign = 'u';
522 st->channels[cnt].scan_type.realbits = 12;
523 st->channels[cnt].scan_type.storagebits = 32;
524 st->channels[cnt].scan_type.shift = 0;
525 }
526
527 st->channels[cnt].type = IIO_VOLTAGE;
528 st->channels[cnt].differential = 1;
529 st->channels[cnt].channel = 0;
530 st->channels[cnt].channel2 = dev * 6;
531 st->channels[cnt].address = AD7280A_ALL_CELLS;
532 st->channels[cnt].indexed = 1;
533 st->channels[cnt].info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
534 st->channels[cnt].info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
535 st->channels[cnt].scan_index = cnt;
536 st->channels[cnt].scan_type.sign = 'u';
537 st->channels[cnt].scan_type.realbits = 32;
538 st->channels[cnt].scan_type.storagebits = 32;
539 st->channels[cnt].scan_type.shift = 0;
540 cnt++;
541 st->channels[cnt].type = IIO_TIMESTAMP;
542 st->channels[cnt].channel = -1;
543 st->channels[cnt].scan_index = cnt;
544 st->channels[cnt].scan_type.sign = 's';
545 st->channels[cnt].scan_type.realbits = 64;
546 st->channels[cnt].scan_type.storagebits = 64;
547 st->channels[cnt].scan_type.shift = 0;
548
549 return cnt + 1;
550 }
551
ad7280_attr_init(struct ad7280_state * st)552 static int ad7280_attr_init(struct ad7280_state *st)
553 {
554 int dev, ch, cnt;
555
556 st->iio_attr = kcalloc(2, sizeof(*st->iio_attr) *
557 (st->slave_num + 1) * AD7280A_CELLS_PER_DEV,
558 GFP_KERNEL);
559 if (!st->iio_attr)
560 return -ENOMEM;
561
562 for (dev = 0, cnt = 0; dev <= st->slave_num; dev++)
563 for (ch = AD7280A_CELL_VOLTAGE_1; ch <= AD7280A_CELL_VOLTAGE_6;
564 ch++, cnt++) {
565 st->iio_attr[cnt].address =
566 ad7280a_devaddr(dev) << 8 | ch;
567 st->iio_attr[cnt].dev_attr.attr.mode =
568 0644;
569 st->iio_attr[cnt].dev_attr.show =
570 ad7280_show_balance_sw;
571 st->iio_attr[cnt].dev_attr.store =
572 ad7280_store_balance_sw;
573 st->iio_attr[cnt].dev_attr.attr.name =
574 kasprintf(GFP_KERNEL,
575 "in%d-in%d_balance_switch_en",
576 dev * AD7280A_CELLS_PER_DEV + ch,
577 dev * AD7280A_CELLS_PER_DEV + ch + 1);
578 ad7280_attributes[cnt] =
579 &st->iio_attr[cnt].dev_attr.attr;
580 cnt++;
581 st->iio_attr[cnt].address =
582 ad7280a_devaddr(dev) << 8 |
583 (AD7280A_CB1_TIMER + ch);
584 st->iio_attr[cnt].dev_attr.attr.mode =
585 0644;
586 st->iio_attr[cnt].dev_attr.show =
587 ad7280_show_balance_timer;
588 st->iio_attr[cnt].dev_attr.store =
589 ad7280_store_balance_timer;
590 st->iio_attr[cnt].dev_attr.attr.name =
591 kasprintf(GFP_KERNEL,
592 "in%d-in%d_balance_timer",
593 dev * AD7280A_CELLS_PER_DEV + ch,
594 dev * AD7280A_CELLS_PER_DEV + ch + 1);
595 ad7280_attributes[cnt] =
596 &st->iio_attr[cnt].dev_attr.attr;
597 }
598
599 ad7280_attributes[cnt] = NULL;
600
601 return 0;
602 }
603
ad7280_read_channel_config(struct device * dev,struct device_attribute * attr,char * buf)604 static ssize_t ad7280_read_channel_config(struct device *dev,
605 struct device_attribute *attr,
606 char *buf)
607 {
608 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
609 struct ad7280_state *st = iio_priv(indio_dev);
610 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
611 unsigned int val;
612
613 switch ((u32)this_attr->address) {
614 case AD7280A_CELL_OVERVOLTAGE:
615 val = 1000 + (st->cell_threshhigh * 1568) / 100;
616 break;
617 case AD7280A_CELL_UNDERVOLTAGE:
618 val = 1000 + (st->cell_threshlow * 1568) / 100;
619 break;
620 case AD7280A_AUX_ADC_OVERVOLTAGE:
621 val = (st->aux_threshhigh * 196) / 10;
622 break;
623 case AD7280A_AUX_ADC_UNDERVOLTAGE:
624 val = (st->aux_threshlow * 196) / 10;
625 break;
626 default:
627 return -EINVAL;
628 }
629
630 return sprintf(buf, "%u\n", val);
631 }
632
ad7280_write_channel_config(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)633 static ssize_t ad7280_write_channel_config(struct device *dev,
634 struct device_attribute *attr,
635 const char *buf,
636 size_t len)
637 {
638 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
639 struct ad7280_state *st = iio_priv(indio_dev);
640 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
641
642 long val;
643 int ret;
644
645 ret = kstrtol(buf, 10, &val);
646 if (ret)
647 return ret;
648
649 switch ((u32)this_attr->address) {
650 case AD7280A_CELL_OVERVOLTAGE:
651 case AD7280A_CELL_UNDERVOLTAGE:
652 val = ((val - 1000) * 100) / 1568; /* LSB 15.68mV */
653 break;
654 case AD7280A_AUX_ADC_OVERVOLTAGE:
655 case AD7280A_AUX_ADC_UNDERVOLTAGE:
656 val = (val * 10) / 196; /* LSB 19.6mV */
657 break;
658 default:
659 return -EFAULT;
660 }
661
662 val = clamp(val, 0L, 0xFFL);
663
664 mutex_lock(&st->lock);
665 switch ((u32)this_attr->address) {
666 case AD7280A_CELL_OVERVOLTAGE:
667 st->cell_threshhigh = val;
668 break;
669 case AD7280A_CELL_UNDERVOLTAGE:
670 st->cell_threshlow = val;
671 break;
672 case AD7280A_AUX_ADC_OVERVOLTAGE:
673 st->aux_threshhigh = val;
674 break;
675 case AD7280A_AUX_ADC_UNDERVOLTAGE:
676 st->aux_threshlow = val;
677 break;
678 }
679
680 ret = ad7280_write(st, AD7280A_DEVADDR_MASTER,
681 this_attr->address, 1, val);
682
683 mutex_unlock(&st->lock);
684
685 return ret ? ret : len;
686 }
687
ad7280_event_handler(int irq,void * private)688 static irqreturn_t ad7280_event_handler(int irq, void *private)
689 {
690 struct iio_dev *indio_dev = private;
691 struct ad7280_state *st = iio_priv(indio_dev);
692 unsigned int *channels;
693 int i, ret;
694
695 channels = kcalloc(st->scan_cnt, sizeof(*channels), GFP_KERNEL);
696 if (!channels)
697 return IRQ_HANDLED;
698
699 ret = ad7280_read_all_channels(st, st->scan_cnt, channels);
700 if (ret < 0)
701 goto out;
702
703 for (i = 0; i < st->scan_cnt; i++) {
704 if (((channels[i] >> 23) & 0xF) <= AD7280A_CELL_VOLTAGE_6) {
705 if (((channels[i] >> 11) & 0xFFF) >=
706 st->cell_threshhigh)
707 iio_push_event(indio_dev,
708 IIO_EVENT_CODE(IIO_VOLTAGE,
709 1,
710 0,
711 IIO_EV_DIR_RISING,
712 IIO_EV_TYPE_THRESH,
713 0, 0, 0),
714 iio_get_time_ns(indio_dev));
715 else if (((channels[i] >> 11) & 0xFFF) <=
716 st->cell_threshlow)
717 iio_push_event(indio_dev,
718 IIO_EVENT_CODE(IIO_VOLTAGE,
719 1,
720 0,
721 IIO_EV_DIR_FALLING,
722 IIO_EV_TYPE_THRESH,
723 0, 0, 0),
724 iio_get_time_ns(indio_dev));
725 } else {
726 if (((channels[i] >> 11) & 0xFFF) >= st->aux_threshhigh)
727 iio_push_event(indio_dev,
728 IIO_UNMOD_EVENT_CODE(
729 IIO_TEMP,
730 0,
731 IIO_EV_TYPE_THRESH,
732 IIO_EV_DIR_RISING),
733 iio_get_time_ns(indio_dev));
734 else if (((channels[i] >> 11) & 0xFFF) <=
735 st->aux_threshlow)
736 iio_push_event(indio_dev,
737 IIO_UNMOD_EVENT_CODE(
738 IIO_TEMP,
739 0,
740 IIO_EV_TYPE_THRESH,
741 IIO_EV_DIR_FALLING),
742 iio_get_time_ns(indio_dev));
743 }
744 }
745
746 out:
747 kfree(channels);
748
749 return IRQ_HANDLED;
750 }
751
752 static IIO_DEVICE_ATTR_NAMED(in_thresh_low_value,
753 in_voltage-voltage_thresh_low_value,
754 0644,
755 ad7280_read_channel_config,
756 ad7280_write_channel_config,
757 AD7280A_CELL_UNDERVOLTAGE);
758
759 static IIO_DEVICE_ATTR_NAMED(in_thresh_high_value,
760 in_voltage-voltage_thresh_high_value,
761 0644,
762 ad7280_read_channel_config,
763 ad7280_write_channel_config,
764 AD7280A_CELL_OVERVOLTAGE);
765
766 static IIO_DEVICE_ATTR(in_temp_thresh_low_value,
767 0644,
768 ad7280_read_channel_config,
769 ad7280_write_channel_config,
770 AD7280A_AUX_ADC_UNDERVOLTAGE);
771
772 static IIO_DEVICE_ATTR(in_temp_thresh_high_value,
773 0644,
774 ad7280_read_channel_config,
775 ad7280_write_channel_config,
776 AD7280A_AUX_ADC_OVERVOLTAGE);
777
778 static struct attribute *ad7280_event_attributes[] = {
779 &iio_dev_attr_in_thresh_low_value.dev_attr.attr,
780 &iio_dev_attr_in_thresh_high_value.dev_attr.attr,
781 &iio_dev_attr_in_temp_thresh_low_value.dev_attr.attr,
782 &iio_dev_attr_in_temp_thresh_high_value.dev_attr.attr,
783 NULL,
784 };
785
786 static const struct attribute_group ad7280_event_attrs_group = {
787 .attrs = ad7280_event_attributes,
788 };
789
ad7280_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long m)790 static int ad7280_read_raw(struct iio_dev *indio_dev,
791 struct iio_chan_spec const *chan,
792 int *val,
793 int *val2,
794 long m)
795 {
796 struct ad7280_state *st = iio_priv(indio_dev);
797 int ret;
798
799 switch (m) {
800 case IIO_CHAN_INFO_RAW:
801 mutex_lock(&st->lock);
802 if (chan->address == AD7280A_ALL_CELLS)
803 ret = ad7280_read_all_channels(st, st->scan_cnt, NULL);
804 else
805 ret = ad7280_read_channel(st, chan->address >> 8,
806 chan->address & 0xFF);
807 mutex_unlock(&st->lock);
808
809 if (ret < 0)
810 return ret;
811
812 *val = ret;
813
814 return IIO_VAL_INT;
815 case IIO_CHAN_INFO_SCALE:
816 if ((chan->address & 0xFF) <= AD7280A_CELL_VOLTAGE_6)
817 *val = 4000;
818 else
819 *val = 5000;
820
821 *val2 = AD7280A_BITS;
822 return IIO_VAL_FRACTIONAL_LOG2;
823 }
824 return -EINVAL;
825 }
826
827 static const struct iio_info ad7280_info = {
828 .read_raw = ad7280_read_raw,
829 .event_attrs = &ad7280_event_attrs_group,
830 .attrs = &ad7280_attrs_group,
831 };
832
833 static const struct ad7280_platform_data ad7793_default_pdata = {
834 .acquisition_time = AD7280A_ACQ_TIME_400ns,
835 .conversion_averaging = AD7280A_CONV_AVG_DIS,
836 .thermistor_term_en = true,
837 };
838
ad7280_probe(struct spi_device * spi)839 static int ad7280_probe(struct spi_device *spi)
840 {
841 const struct ad7280_platform_data *pdata = dev_get_platdata(&spi->dev);
842 struct ad7280_state *st;
843 int ret;
844 const unsigned short tACQ_ns[4] = {465, 1010, 1460, 1890};
845 const unsigned short nAVG[4] = {1, 2, 4, 8};
846 struct iio_dev *indio_dev;
847
848 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
849 if (!indio_dev)
850 return -ENOMEM;
851
852 st = iio_priv(indio_dev);
853 spi_set_drvdata(spi, indio_dev);
854 st->spi = spi;
855 mutex_init(&st->lock);
856
857 if (!pdata)
858 pdata = &ad7793_default_pdata;
859
860 ad7280_crc8_build_table(st->crc_tab);
861
862 st->spi->max_speed_hz = AD7280A_MAX_SPI_CLK_HZ;
863 st->spi->mode = SPI_MODE_1;
864 spi_setup(st->spi);
865
866 st->ctrl_lb = AD7280A_CTRL_LB_ACQ_TIME(pdata->acquisition_time & 0x3);
867 st->ctrl_hb = AD7280A_CTRL_HB_CONV_AVG(pdata->conversion_averaging
868 & 0x3) | (pdata->thermistor_term_en ?
869 AD7280A_CTRL_LB_THERMISTOR_EN : 0);
870
871 ret = ad7280_chain_setup(st);
872 if (ret < 0)
873 return ret;
874
875 st->slave_num = ret;
876 st->scan_cnt = (st->slave_num + 1) * AD7280A_NUM_CH;
877 st->cell_threshhigh = 0xFF;
878 st->aux_threshhigh = 0xFF;
879
880 /*
881 * Total Conversion Time = ((tACQ + tCONV) *
882 * (Number of Conversions per Part)) −
883 * tACQ + ((N - 1) * tDELAY)
884 *
885 * Readback Delay = Total Conversion Time + tWAIT
886 */
887
888 st->readback_delay_us =
889 ((tACQ_ns[pdata->acquisition_time & 0x3] + 695) *
890 (AD7280A_NUM_CH * nAVG[pdata->conversion_averaging & 0x3]))
891 - tACQ_ns[pdata->acquisition_time & 0x3] +
892 st->slave_num * 250;
893
894 /* Convert to usecs */
895 st->readback_delay_us = DIV_ROUND_UP(st->readback_delay_us, 1000);
896 st->readback_delay_us += 5; /* Add tWAIT */
897
898 indio_dev->name = spi_get_device_id(spi)->name;
899 indio_dev->dev.parent = &spi->dev;
900 indio_dev->modes = INDIO_DIRECT_MODE;
901
902 ret = ad7280_channel_init(st);
903 if (ret < 0)
904 return ret;
905
906 indio_dev->num_channels = ret;
907 indio_dev->channels = st->channels;
908 indio_dev->info = &ad7280_info;
909
910 ret = ad7280_attr_init(st);
911 if (ret < 0)
912 goto error_free_channels;
913
914 ret = iio_device_register(indio_dev);
915 if (ret)
916 goto error_free_attr;
917
918 if (spi->irq > 0) {
919 ret = ad7280_write(st, AD7280A_DEVADDR_MASTER,
920 AD7280A_ALERT, 1,
921 AD7280A_ALERT_RELAY_SIG_CHAIN_DOWN);
922 if (ret)
923 goto error_unregister;
924
925 ret = ad7280_write(st, ad7280a_devaddr(st->slave_num),
926 AD7280A_ALERT, 0,
927 AD7280A_ALERT_GEN_STATIC_HIGH |
928 (pdata->chain_last_alert_ignore & 0xF));
929 if (ret)
930 goto error_unregister;
931
932 ret = request_threaded_irq(spi->irq,
933 NULL,
934 ad7280_event_handler,
935 IRQF_TRIGGER_FALLING |
936 IRQF_ONESHOT,
937 indio_dev->name,
938 indio_dev);
939 if (ret)
940 goto error_unregister;
941 }
942
943 return 0;
944 error_unregister:
945 iio_device_unregister(indio_dev);
946
947 error_free_attr:
948 kfree(st->iio_attr);
949
950 error_free_channels:
951 kfree(st->channels);
952
953 return ret;
954 }
955
ad7280_remove(struct spi_device * spi)956 static int ad7280_remove(struct spi_device *spi)
957 {
958 struct iio_dev *indio_dev = spi_get_drvdata(spi);
959 struct ad7280_state *st = iio_priv(indio_dev);
960
961 if (spi->irq > 0)
962 free_irq(spi->irq, indio_dev);
963 iio_device_unregister(indio_dev);
964
965 ad7280_write(st, AD7280A_DEVADDR_MASTER, AD7280A_CONTROL_HB, 1,
966 AD7280A_CTRL_HB_PWRDN_SW | st->ctrl_hb);
967
968 kfree(st->channels);
969 kfree(st->iio_attr);
970
971 return 0;
972 }
973
974 static const struct spi_device_id ad7280_id[] = {
975 {"ad7280a", 0},
976 {}
977 };
978 MODULE_DEVICE_TABLE(spi, ad7280_id);
979
980 static struct spi_driver ad7280_driver = {
981 .driver = {
982 .name = "ad7280",
983 },
984 .probe = ad7280_probe,
985 .remove = ad7280_remove,
986 .id_table = ad7280_id,
987 };
988 module_spi_driver(ad7280_driver);
989
990 MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
991 MODULE_DESCRIPTION("Analog Devices AD7280A");
992 MODULE_LICENSE("GPL v2");
993
