Searched refs:A23 (Results 1 – 25 of 31) sorted by relevance
12
46 - Allwinner A23 (sun8i)48 http://dl.linux-sunxi.org/A23/A23%20Datasheet%20V1.0%2020130830.pdf50 http://dl.linux-sunxi.org/A23/A23%20User%20Manual%20V1.0%2020130830.pdf
12 "allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A2321 "allwinner,sun8i-a23-axi-clk" - for the AXI clock on A2336 "allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A2342 "allwinner,sun8i-a23-apb0-clk" - for the APB0 clock on A2350 "allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A2360 "allwinner,sun8i-a23-apb1-gates-clk" - for the APB1 gates on A2363 "allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A2376 "allwinner,sun8i-a23-mbus-clk" - for the MBUS clock on A2384 "allwinner,sun8i-a23-usb-clk" - for usb gates + resets on A23
41 bool "Support for the Allwinner A23 CCU"
48 model = "Q8 A23 Tablet";
53 model = "Allwinner A23 Evaluation Board";
356 gpios = <&pioE 23 GPIO_ACTIVE_LOW>; /* PE23, conflicts with A23, CTS2 */
914 <AT91_PIOE 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE23 periph B, conflicts with A23 */
48 The valid sections compatible for A23/A33 are:
106 || STDW .D1T1 A23:A22,*A15--[1]140 LDDW .D1T1 *++A15[1],A23:A22
187 A25, A24, A23, A22, IRQ5, IRQ4_BS, enumerator581 PINMUX_DATA(A23_MARK, A23),1067 GPIO_FN(A23),1283 A23, PTE5_OUT, 0, PTE5_IN,
762 GPIO_FN(A23),
705 PINMUX_IPSR_GPSR(IP1_15_14, A23),1410 GPIO_FN(A23), GPIO_FN(ST1_D0), GPIO_FN(LCD_M_DISP_A),
928 GPIO_FN(A23),
531 PINMUX_IPSR_GPSR(IP1_20, A23),
1268 GPIO_FN(A23),
724 PINMUX_IPSR_GPSR(IP7_3_0, A23),
1470 GPIO_FN(A23),
191 #define IP4_19_16 FM(VI0_DATA9) FM(HCTS2_N) FM(PWM1_A) FM(A23) FM(FSO_CFE_0_N_B) F_(0, 0) F_(0,…
222 #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) FM(A23) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0…659 PINMUX_IPSR_GPSR(IP1_15_12, A23),
1415 GPIO_FN(A23),
1606 GPIO_FN(A23),
1690 GPIO_FN(A23),
189 And on the A23, A31, A31s and A33, you need one more clock line:253 (A31, A23, A33, A80), allows to dynamically adjust pixel
