| /Linux-v4.19/arch/c6x/kernel/ |
| D | entry.S | 112 || STDW .D1T1 A17:A16,*A15--[1]
134 LDDW .D1T1 *++A15[1],A17:A16
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| /Linux-v4.19/arch/arm/boot/dts/ |
| D | am335x-pocketbeagle.dts | 97 AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0) /* (A17) spi0_sclk.spi0_sclk */
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| D | am335x-boneblue.dts | 181 AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE1) /* (A17) spi0_sclk.uart2_rxd */
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| D | am335x-icev2.dts | 189 AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0) /* (A17) spi0_sclk.spi0_sclk */
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| D | sama5d3.dtsi | 929 AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE17 periph B, conflicts with A17 */
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| /Linux-v4.19/drivers/pinctrl/aspeed/ |
| D | pinctrl-aspeed-g4.c | 224 #define A17 27 macro
229 MS_PIN_DECL(A17, GPIOD3, SD2DAT1, GPID2OUT);
231 FUNC_GROUP_DECL(GPID2, B17, A17);
268 FUNC_GROUP_DECL(SD2, A18, D16, B17, A17, C16, B16, A16, E15);
269 FUNC_GROUP_DECL(GPID, A18, D16, B17, A17, C16, B16, A16, E15);
1765 ASPEED_PINCTRL_PIN(A17),
2384 { PIN_CONFIG_INPUT_DEBOUNCE, { B17, A17 }, SCUA8, 21 },
|
| D | pinctrl-aspeed-g5.c | 466 #define A17 60 macro
469 MS_PIN_DECL(A17, GPIOH4, DASHA17, NDTR6);
484 FUNC_GROUP_DECL(UART6, A18, B18, D17, C17, A17, B17, A16, D18);
1779 ASPEED_PINCTRL_PIN(A17),
|
| /Linux-v4.19/arch/arm/ |
| D | Kconfig | 1190 bool "ARM errata: A17: DMB ST might fail to create order between stores"
1193 This option enables the workaround for the 852421 Cortex-A17
1199 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1203 - Cortex-A17 852423: Execution of a sequence of instructions might
1205 any Cortex-A17 cores yet.
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| /Linux-v4.19/arch/arm/mm/ |
| D | proc-v7.S | 499 ldr r10, =0x00000c0e @ Cortex-A17 primary part number
|
| /Linux-v4.19/drivers/pinctrl/sh-pfc/ |
| D | pfc-r8a77970.c | 172 #define IP2_7_4 FM(DU_DB7) F_(0, 0) F_(0, 0) FM(A17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0…
458 PINMUX_IPSR_GPSR(IP2_7_4, A17),
|
| D | pfc-r8a77990.c | 61 #define GPSR1_17 F_(A17, IP5_3_0)
224 #define IP5_3_0 FM(A17) FM(MSIOF1_RXD) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA6_A) FM(DU_DB6) F_…
760 PINMUX_IPSR_GPSR(IP5_3_0, A17),
|
| D | pfc-r8a77980.c | 202 #define IP2_7_4 FM(DU_DB7) FM(MSIOF3_TXD) F_(0, 0) FM(A17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0…
536 PINMUX_IPSR_GPSR(IP2_7_4, A17),
|
| D | pfc-sh7734.c | 678 PINMUX_IPSR_GPSR(IP1_3_2, A17),
1401 GPIO_FN(A17), GPIO_FN(ST1_VCO_CLKIN), GPIO_FN(LCD_CL1_A),
|
| D | pfc-r8a77965.c | 72 #define GPSR1_17 F_(A17, IP4_3_0)
250 #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_…
813 PINMUX_IPSR_GPSR(IP4_3_0, A17),
|
| D | pfc-r8a7795-es1.c | 67 #define GPSR1_17 F_(A17, IP4_3_0)
245 #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_…
804 PINMUX_IPSR_GPSR(IP4_3_0, A17),
|
| D | pfc-r8a7796.c | 74 #define GPSR1_17 F_(A17, IP4_3_0)
252 #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_…
813 PINMUX_IPSR_GPSR(IP4_3_0, A17),
|
| D | pfc-r8a7795.c | 69 #define GPSR1_17 F_(A17, IP4_3_0)
247 #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_…
812 PINMUX_IPSR_GPSR(IP4_3_0, A17),
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| D | pfc-r8a7792.c | 383 PINMUX_SINGLE(A17),
|
| D | pfc-sh7264.c | 1274 GPIO_FN(A17),
|
| D | pfc-r8a77470.c | 706 PINMUX_IPSR_GPSR(IP6_11_8, A17),
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| D | pfc-sh7757.c | 1612 GPIO_FN(A17),
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| D | pfc-sh7269.c | 1696 GPIO_FN(A17),
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| D | pfc-r8a7778.c | 608 PINMUX_IPSR_GPSR(IP0_28, A17),
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| D | pfc-r8a7779.c | 607 PINMUX_SINGLE(A17),
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| D | pfc-r8a7794.c | 837 PINMUX_IPSR_GPSR(IP2_23_21, A17),
|
