Searched refs:A15 (Results 1 – 25 of 50) sorted by relevance
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| /Linux-v4.19/arch/c6x/kernel/ |
| D | entry.S | 68 ADD .D1X SP,-8,A15
69 || STDW .D2T1 A15:A14,*SP--[16] ; save A15:A14
72 || STDW .D1T1 A13:A12,*A15--[1]
76 || STDW .D1T1 A11:A10,*A15--[1]
80 || STDW .D1T1 A9:A8,*A15--[1]
83 || STDW .D1T1 A7:A6,*A15--[1]
87 || STDW .D1T1 A5:A4,*A15--[1]
90 || STDW .D1T1 A3:A2,*A15--[1]
94 || STDW .D1T1 A1:A0,*A15--[1]
98 || STDW .D1T1 A31:A30,*A15--[1]
[all …]
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| D | switch_to.S | 40 || STDW .D1T1 A15:A14,*+A4(THREAD_A15_14)
56 || LDDW .D1T1 *+A5(THREAD_A15_14),A15:A14
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| /Linux-v4.19/arch/arm/boot/dts/ |
| D | vexpress-v2p-ca15_a7.dts | 238 /* A15 PLL 0 reference clock */
247 /* A15 PLL 1 reference clock */
319 /* A15 CPU core voltage */
322 regulator-name = "A15 Vcore";
326 label = "A15 Vcore";
341 /* Total current for the two A15 cores */
344 label = "A15 Icore";
362 /* Total power for the two A15 cores */
365 label = "A15 Pcore";
376 /* Total energy for the two A15 cores */
[all …]
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| D | exynos5420-cpus.dtsi | 9 * boards: CPU[0123] being the A15.
14 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
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| D | exynos5422-odroidxu3.dts | 23 /* A15 cluster: VDD_ARM */
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| D | xenvm-4.2.dts | 6 * Cortex-A15 MPCore (V2P-CA15)
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| D | exynos5422-cpus.dtsi | 13 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
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| D | am335x-pocketbeagle.dts | 109 AM33XX_IOPAD(0x9b0, PIN_INPUT_PULLUP | MUX_MODE4) /* (A15) xdma_event_intr0.spi1_cs1 */
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| D | vexpress-v2p-ca15-tc1.dts | 6 * Cortex-A15 MPCore (V2P-CA15)
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| /Linux-v4.19/arch/arm/include/debug/ |
| D | exynos.S | 23 teq \tmp, #0xf0 @@ A15
27 teq \tmp, #0x100 @@ A15 + A7 but boot to A7
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| /Linux-v4.19/Documentation/devicetree/bindings/arm/ |
| D | calxeda.txt | 11 Boards with Calxeda Cortex-A15 based ECX-2000 SOC shall have the following
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| D | l2c2x0.txt | 111 cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
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| /Linux-v4.19/Documentation/devicetree/bindings/hwmon/ |
| D | vexpress.txt | 22 label = "A15 Jcore";
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| /Linux-v4.19/arch/arm/mach-hisi/ |
| D | Kconfig | 36 bool "Hisilicon HiP04 Cortex A15 family"
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| /Linux-v4.19/arch/c6x/lib/ |
| D | pop_rts.S | 28 lddw .d2t1 *++B15, A15:A14
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| D | push_rts.S | 24 stdw .d2t1 A15:A14, *B15--
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| /Linux-v4.19/Documentation/arm/keystone/ |
| D | Overview.txt | 6 Keystone range of SoCs are based on ARM Cortex-A15 MPCore Processors
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| /Linux-v4.19/arch/arm/mach-exynos/ |
| D | Kconfig | 71 Samsung EXYNOS5 (Cortex-A15/A7) SoC based systems
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| /Linux-v4.19/arch/arm/mach-vexpress/ |
| D | Kconfig | 34 - LogicTile Express 13MG (V2F-2XV6) with A5, A7, A9 or A15 SMMs
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| /Linux-v4.19/Documentation/arm/sunxi/ |
| D | README | 85 * Quad ARM Cortex-A15, Quad ARM Cortex-A7 based SoCs
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| /Linux-v4.19/drivers/soc/tegra/ |
| D | Kconfig | 72 Tegra124's "4+1" Cortex-A15 CPU complex.
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| /Linux-v4.19/arch/arm/crypto/ |
| D | Kconfig | 82 Bit sliced AES gives around 45% speedup on Cortex-A15 for CTR mode
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| /Linux-v4.19/drivers/pinctrl/aspeed/ |
| D | pinctrl-aspeed-g5.c | 549 #define A15 71 macro
557 MS_PIN_DECL(A15, GPIOI7, SPI1MISO, VBMISO);
559 FUNC_GROUP_DECL(SPI1, B15, C15, A14, A15);
560 FUNC_GROUP_DECL(SPI1DEBUG, C18, E15, B16, C16, B15, C15, A14, A15);
561 FUNC_GROUP_DECL(SPI1PASSTHRU, C18, E15, B16, C16, B15, C15, A14, A15);
562 FUNC_GROUP_DECL(VGABIOSROM, B15, C15, A14, A15);
1777 ASPEED_PINCTRL_PIN(A15),
2394 { PIN_CONFIG_BIAS_PULL_DOWN, { C18, A15 }, SCU8C, 24 },
2395 { PIN_CONFIG_BIAS_DISABLE, { C18, A15 }, SCU8C, 24 },
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| /Linux-v4.19/arch/arm/kernel/ |
| D | entry-header.S | 339 @ We must avoid clrex due to Cortex-A15 erratum #830321
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| /Linux-v4.19/arch/arm/mm/ |
| D | proc-v7.S | 504 ldr r10, =0x00000c0f @ Cortex-A15 primary part number
614 @ Cortex-A15 - needs iciallu switch_mm for hardening
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