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/Linux-v4.19/Documentation/arm/sunxi/
DREADME28 - Allwinner A13 / R8 (sun5i)
30 http://dl.linux-sunxi.org/A13/A13%20Datasheet%20-%20v1.12%20%282012-03-29%29.pdf
32 http://dl.linux-sunxi.org/A13/A13%20User%20Manual%20-%20v1.2%20%282013-01-08%29.pdf
/Linux-v4.19/arch/c6x/kernel/
Dswitch_to.S27 || STDW .D1T1 A13:A12,*+A4(THREAD_A13_12)
31 || LDDW .D1T1 *+A5(THREAD_A13_12),A13:A12
Dentry.S72 || STDW .D1T1 A13:A12,*A15--[1]
172 LDDW .D1T1 *++A15[1],A13:A12
/Linux-v4.19/Documentation/devicetree/bindings/clock/
Dsunxi.txt25 "allwinner,sun5i-a13-ahb-clk" - for the AHB clock on A13
28 "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
46 "allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
56 "allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
69 "allwinner,sun5i-a13-dram-gates-clk" - for the DRAM gates on A13
70 "allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
82 "allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13
/Linux-v4.19/arch/arm/mach-sunxi/
DKconfig20 bool "Allwinner A10s / A13 (sun5i) SoCs support"
/Linux-v4.19/arch/c6x/lib/
Dpop_rts.S26 lddw .d2t1 *++B15, A13:A12
Dpush_rts.S27 stdw .d2t1 A13:A12, *B15--
/Linux-v4.19/arch/arm/boot/dts/
Dsun5i-a13-q8-tablet.dts48 model = "Q8 A13 Tablet";
Dsun5i-a13-olinuxino-micro.dts51 model = "Olimex A13-Olinuxino Micro";
Dam335x-pocketbeagle.dts72 AM33XX_IOPAD(0x990, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* (A13) mcasp0_aclkx.ehrpwm0A */
Dsun5i-a13-olinuxino.dts53 model = "Olimex A13-Olinuxino";
/Linux-v4.19/arch/m68k/fpsp040/
Dbindec.S40 | ICTR is a flag used in A13. It must be set before the
85 | A13. Check for LEN digits.
270 | ICTR is a flag used in A13. It must be set before the
606 | A13. Check for LEN digits.
/Linux-v4.19/Documentation/devicetree/bindings/sram/
Dsunxi-sram.txt38 The valid sections compatible for A13 are:
/Linux-v4.19/drivers/usb/musb/
DKconfig21 Allwinner SoCs using this IP include A10, A13, A20, ...
/Linux-v4.19/drivers/pinctrl/aspeed/
Dpinctrl-aspeed-g4.c1211 #define A13 157 macro
1215 MS_PIN_DECL_(A13, SIG_EXPR_LIST_PTR(GPIOT5), SIG_EXPR_LIST_PTR(DASHA13),
1346 FUNC_GROUP_DECL(RMII1, A12, B12, C12, D12, E12, A13, E11, D11, C11, B11, A11,
1348 FUNC_GROUP_DECL(RGMII1, A12, B12, C12, D12, E12, A13, E11, D11, C11, B11, A11,
1761 ASPEED_PINCTRL_PIN(A13),
2323 { PIN_CONFIG_DRIVE_STRENGTH, { A12, A13 }, SCU90, 9 },
2324 { PIN_CONFIG_BIAS_PULL_DOWN, { A12, A13 }, SCU90, 12 },
2325 { PIN_CONFIG_BIAS_DISABLE, { A12, A13 }, SCU90, 12 },
Dpinctrl-aspeed-g5.c62 #define A13 5 macro
65 MS_PIN_DECL(A13, GPIOA5, SDA9, TIMER6);
67 FUNC_GROUP_DECL(TIMER6, A13);
69 FUNC_GROUP_DECL(I2C9, C14, A13);
1775 ASPEED_PINCTRL_PIN(A13),
/Linux-v4.19/drivers/pinctrl/sh-pfc/
Dpfc-r8a77970.c168 #define IP1_23_20 FM(DU_DB3) F_(0, 0) F_(0, 0) FM(A13) FM(FXR_CLKOUT1) F_(0, 0) F_(0, 0) F_(0,…
441 PINMUX_IPSR_GPSR(IP1_23_20, A13),
Dpfc-r8a77990.c65 #define GPSR1_13 F_(A13, IP4_19_16)
220 #define IP4_19_16 FM(A13) FM(SCK5_A) FM(MSIOF2_SCK_B) FM(VI4_DATA14) FM(HRX4_D) FM(DU_DB2) F_(…
727 PINMUX_IPSR_GPSR(IP4_19_16, A13),
Dpfc-r8a77980.c198 #define IP1_23_20 FM(DU_DB3) FM(HRTS0_N_A) F_(0, 0) FM(A13) FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0…
516 PINMUX_IPSR_GPSR(IP1_23_20, A13),
Dpfc-sh7734.c658 PINMUX_IPSR_GPSR(IP0_27_26, A13),
1393 GPIO_FN(A13), GPIO_FN(LCD_DATA13_A), GPIO_FN(TIOC3B_C),
Dpfc-r8a77965.c76 #define GPSR1_13 F_(A13, IP3_19_16)
246 #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(D…
786 PINMUX_IPSR_GPSR(IP3_19_16, A13),
Dpfc-r8a7795-es1.c71 #define GPSR1_13 F_(A13, IP3_19_16)
241 #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(D…
777 PINMUX_IPSR_GPSR(IP3_19_16, A13),
Dpfc-r8a7796.c78 #define GPSR1_13 F_(A13, IP3_19_16)
248 #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(D…
786 PINMUX_IPSR_GPSR(IP3_19_16, A13),
Dpfc-r8a7795.c73 #define GPSR1_13 F_(A13, IP3_19_16)
243 #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(D…
785 PINMUX_IPSR_GPSR(IP3_19_16, A13),
/Linux-v4.19/Documentation/devicetree/bindings/display/sunxi/
Dsun4i-drm.txt186 in A13, H3, H5 and V3s SoCs), you need one more reset line:

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