1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Clock specification for Xilinx ZynqMP
4 *
5 * (C) Copyright 2015 - 2018, Xilinx, Inc.
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9
10/ {
11	clk100: clk100 {
12		compatible = "fixed-clock";
13		#clock-cells = <0>;
14		clock-frequency = <100000000>;
15	};
16
17	clk125: clk125 {
18		compatible = "fixed-clock";
19		#clock-cells = <0>;
20		clock-frequency = <125000000>;
21	};
22
23	clk200: clk200 {
24		compatible = "fixed-clock";
25		#clock-cells = <0>;
26		clock-frequency = <200000000>;
27	};
28
29	clk250: clk250 {
30		compatible = "fixed-clock";
31		#clock-cells = <0>;
32		clock-frequency = <250000000>;
33	};
34
35	clk300: clk300 {
36		compatible = "fixed-clock";
37		#clock-cells = <0>;
38		clock-frequency = <300000000>;
39	};
40
41	clk600: clk600 {
42		compatible = "fixed-clock";
43		#clock-cells = <0>;
44		clock-frequency = <600000000>;
45	};
46
47	dp_aclk: clock0 {
48		compatible = "fixed-clock";
49		#clock-cells = <0>;
50		clock-frequency = <100000000>;
51		clock-accuracy = <100>;
52	};
53
54	dp_aud_clk: clock1 {
55		compatible = "fixed-clock";
56		#clock-cells = <0>;
57		clock-frequency = <24576000>;
58		clock-accuracy = <100>;
59	};
60
61	dpdma_clk: dpdma_clk {
62		compatible = "fixed-clock";
63		#clock-cells = <0x0>;
64		clock-frequency = <533000000>;
65	};
66
67	drm_clock: drm_clock {
68		compatible = "fixed-clock";
69		#clock-cells = <0x0>;
70		clock-frequency = <262750000>;
71		clock-accuracy = <0x64>;
72	};
73};
74
75&can0 {
76	clocks = <&clk100 &clk100>;
77};
78
79&can1 {
80	clocks = <&clk100 &clk100>;
81};
82
83&fpd_dma_chan1 {
84	clocks = <&clk600>, <&clk100>;
85};
86
87&fpd_dma_chan2 {
88	clocks = <&clk600>, <&clk100>;
89};
90
91&fpd_dma_chan3 {
92	clocks = <&clk600>, <&clk100>;
93};
94
95&fpd_dma_chan4 {
96	clocks = <&clk600>, <&clk100>;
97};
98
99&fpd_dma_chan5 {
100	clocks = <&clk600>, <&clk100>;
101};
102
103&fpd_dma_chan6 {
104	clocks = <&clk600>, <&clk100>;
105};
106
107&fpd_dma_chan7 {
108	clocks = <&clk600>, <&clk100>;
109};
110
111&fpd_dma_chan8 {
112	clocks = <&clk600>, <&clk100>;
113};
114
115&lpd_dma_chan1 {
116	clocks = <&clk600>, <&clk100>;
117};
118
119&lpd_dma_chan2 {
120	clocks = <&clk600>, <&clk100>;
121};
122
123&lpd_dma_chan3 {
124	clocks = <&clk600>, <&clk100>;
125};
126
127&lpd_dma_chan4 {
128	clocks = <&clk600>, <&clk100>;
129};
130
131&lpd_dma_chan5 {
132	clocks = <&clk600>, <&clk100>;
133};
134
135&lpd_dma_chan6 {
136	clocks = <&clk600>, <&clk100>;
137};
138
139&lpd_dma_chan7 {
140	clocks = <&clk600>, <&clk100>;
141};
142
143&lpd_dma_chan8 {
144	clocks = <&clk600>, <&clk100>;
145};
146
147&gem0 {
148	clocks = <&clk125>, <&clk125>, <&clk125>;
149};
150
151&gem1 {
152	clocks = <&clk125>, <&clk125>, <&clk125>;
153};
154
155&gem2 {
156	clocks = <&clk125>, <&clk125>, <&clk125>;
157};
158
159&gem3 {
160	clocks = <&clk125>, <&clk125>, <&clk125>;
161};
162
163&gpio {
164	clocks = <&clk100>;
165};
166
167&i2c0 {
168	clocks = <&clk100>;
169};
170
171&i2c1 {
172	clocks = <&clk100>;
173};
174
175&sata {
176	clocks = <&clk250>;
177};
178
179&sdhci0 {
180	clocks = <&clk200 &clk200>;
181};
182
183&sdhci1 {
184	clocks = <&clk200 &clk200>;
185};
186
187&spi0 {
188	clocks = <&clk200 &clk200>;
189};
190
191&spi1 {
192	clocks = <&clk200 &clk200>;
193};
194
195&uart0 {
196	clocks = <&clk100 &clk100>;
197};
198
199&uart1 {
200	clocks = <&clk100 &clk100>;
201};
202
203&usb0 {
204	clocks = <&clk250>, <&clk250>;
205};
206
207&usb1 {
208	clocks = <&clk250>, <&clk250>;
209};
210
211&watchdog0 {
212	clocks = <&clk250>;
213};
214