1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef _vcn_4_0_3_SH_MASK_HEADER 24 #define _vcn_4_0_3_SH_MASK_HEADER 25 26 27 // addressBlock: aid_uvd0_uvddec 28 //UVD_TOP_CTRL 29 #define UVD_TOP_CTRL__STANDARD__SHIFT 0x0 30 #define UVD_TOP_CTRL__STD_VERSION__SHIFT 0x4 31 #define UVD_TOP_CTRL__STANDARD_MASK 0x0000000FL 32 #define UVD_TOP_CTRL__STD_VERSION_MASK 0x00000010L 33 //UVD_CGC_GATE 34 #define UVD_CGC_GATE__SYS__SHIFT 0x0 35 #define UVD_CGC_GATE__UDEC__SHIFT 0x1 36 #define UVD_CGC_GATE__MPEG2__SHIFT 0x2 37 #define UVD_CGC_GATE__REGS__SHIFT 0x3 38 #define UVD_CGC_GATE__RBC__SHIFT 0x4 39 #define UVD_CGC_GATE__LMI_MC__SHIFT 0x5 40 #define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6 41 #define UVD_CGC_GATE__IDCT__SHIFT 0x7 42 #define UVD_CGC_GATE__MPRD__SHIFT 0x8 43 #define UVD_CGC_GATE__MPC__SHIFT 0x9 44 #define UVD_CGC_GATE__LBSI__SHIFT 0xa 45 #define UVD_CGC_GATE__LRBBM__SHIFT 0xb 46 #define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc 47 #define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd 48 #define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe 49 #define UVD_CGC_GATE__UDEC_DB__SHIFT 0xf 50 #define UVD_CGC_GATE__UDEC_MP__SHIFT 0x10 51 #define UVD_CGC_GATE__WCB__SHIFT 0x11 52 #define UVD_CGC_GATE__VCPU__SHIFT 0x12 53 #define UVD_CGC_GATE__MMSCH__SHIFT 0x14 54 #define UVD_CGC_GATE__LCM0__SHIFT 0x15 55 #define UVD_CGC_GATE__LCM1__SHIFT 0x16 56 #define UVD_CGC_GATE__MIF__SHIFT 0x17 57 #define UVD_CGC_GATE__VREG__SHIFT 0x18 58 #define UVD_CGC_GATE__PE__SHIFT 0x19 59 #define UVD_CGC_GATE__PPU__SHIFT 0x1a 60 #define UVD_CGC_GATE__SYS_MASK 0x00000001L 61 #define UVD_CGC_GATE__UDEC_MASK 0x00000002L 62 #define UVD_CGC_GATE__MPEG2_MASK 0x00000004L 63 #define UVD_CGC_GATE__REGS_MASK 0x00000008L 64 #define UVD_CGC_GATE__RBC_MASK 0x00000010L 65 #define UVD_CGC_GATE__LMI_MC_MASK 0x00000020L 66 #define UVD_CGC_GATE__LMI_UMC_MASK 0x00000040L 67 #define UVD_CGC_GATE__IDCT_MASK 0x00000080L 68 #define UVD_CGC_GATE__MPRD_MASK 0x00000100L 69 #define UVD_CGC_GATE__MPC_MASK 0x00000200L 70 #define UVD_CGC_GATE__LBSI_MASK 0x00000400L 71 #define UVD_CGC_GATE__LRBBM_MASK 0x00000800L 72 #define UVD_CGC_GATE__UDEC_RE_MASK 0x00001000L 73 #define UVD_CGC_GATE__UDEC_CM_MASK 0x00002000L 74 #define UVD_CGC_GATE__UDEC_IT_MASK 0x00004000L 75 #define UVD_CGC_GATE__UDEC_DB_MASK 0x00008000L 76 #define UVD_CGC_GATE__UDEC_MP_MASK 0x00010000L 77 #define UVD_CGC_GATE__WCB_MASK 0x00020000L 78 #define UVD_CGC_GATE__VCPU_MASK 0x00040000L 79 #define UVD_CGC_GATE__MMSCH_MASK 0x00100000L 80 #define UVD_CGC_GATE__LCM0_MASK 0x00200000L 81 #define UVD_CGC_GATE__LCM1_MASK 0x00400000L 82 #define UVD_CGC_GATE__MIF_MASK 0x00800000L 83 #define UVD_CGC_GATE__VREG_MASK 0x01000000L 84 #define UVD_CGC_GATE__PE_MASK 0x02000000L 85 #define UVD_CGC_GATE__PPU_MASK 0x04000000L 86 //UVD_CGC_CTRL 87 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 88 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2 89 #define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6 90 #define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb 91 #define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc 92 #define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd 93 #define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0xe 94 #define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf 95 #define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10 96 #define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11 97 #define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12 98 #define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13 99 #define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14 100 #define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15 101 #define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16 102 #define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17 103 #define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18 104 #define UVD_CGC_CTRL__MPC_MODE__SHIFT 0x19 105 #define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a 106 #define UVD_CGC_CTRL__LRBBM_MODE__SHIFT 0x1b 107 #define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c 108 #define UVD_CGC_CTRL__VCPU_MODE__SHIFT 0x1d 109 #define UVD_CGC_CTRL__MMSCH_MODE__SHIFT 0x1f 110 #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L 111 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003CL 112 #define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007C0L 113 #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x00000800L 114 #define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x00001000L 115 #define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x00002000L 116 #define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x00004000L 117 #define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x00008000L 118 #define UVD_CGC_CTRL__SYS_MODE_MASK 0x00010000L 119 #define UVD_CGC_CTRL__UDEC_MODE_MASK 0x00020000L 120 #define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x00040000L 121 #define UVD_CGC_CTRL__REGS_MODE_MASK 0x00080000L 122 #define UVD_CGC_CTRL__RBC_MODE_MASK 0x00100000L 123 #define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x00200000L 124 #define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x00400000L 125 #define UVD_CGC_CTRL__IDCT_MODE_MASK 0x00800000L 126 #define UVD_CGC_CTRL__MPRD_MODE_MASK 0x01000000L 127 #define UVD_CGC_CTRL__MPC_MODE_MASK 0x02000000L 128 #define UVD_CGC_CTRL__LBSI_MODE_MASK 0x04000000L 129 #define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x08000000L 130 #define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000L 131 #define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000L 132 #define UVD_CGC_CTRL__MMSCH_MODE_MASK 0x80000000L 133 //AVM_SUVD_CGC_GATE 134 #define AVM_SUVD_CGC_GATE__SRE__SHIFT 0x0 135 #define AVM_SUVD_CGC_GATE__SIT__SHIFT 0x1 136 #define AVM_SUVD_CGC_GATE__SMP__SHIFT 0x2 137 #define AVM_SUVD_CGC_GATE__SCM__SHIFT 0x3 138 #define AVM_SUVD_CGC_GATE__SDB__SHIFT 0x4 139 #define AVM_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 140 #define AVM_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 141 #define AVM_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 142 #define AVM_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 143 #define AVM_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 144 #define AVM_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 145 #define AVM_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 146 #define AVM_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 147 #define AVM_SUVD_CGC_GATE__SCLR__SHIFT 0xd 148 #define AVM_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 149 #define AVM_SUVD_CGC_GATE__ENT__SHIFT 0xf 150 #define AVM_SUVD_CGC_GATE__IME__SHIFT 0x10 151 #define AVM_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 152 #define AVM_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 153 #define AVM_SUVD_CGC_GATE__SITE__SHIFT 0x13 154 #define AVM_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 155 #define AVM_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 156 #define AVM_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 157 #define AVM_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 158 #define AVM_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 159 #define AVM_SUVD_CGC_GATE__EFC__SHIFT 0x19 160 #define AVM_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 161 #define AVM_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 162 #define AVM_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 163 #define AVM_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 164 #define AVM_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 165 #define AVM_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 166 #define AVM_SUVD_CGC_GATE__SRE_MASK 0x00000001L 167 #define AVM_SUVD_CGC_GATE__SIT_MASK 0x00000002L 168 #define AVM_SUVD_CGC_GATE__SMP_MASK 0x00000004L 169 #define AVM_SUVD_CGC_GATE__SCM_MASK 0x00000008L 170 #define AVM_SUVD_CGC_GATE__SDB_MASK 0x00000010L 171 #define AVM_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 172 #define AVM_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 173 #define AVM_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 174 #define AVM_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 175 #define AVM_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 176 #define AVM_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 177 #define AVM_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 178 #define AVM_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 179 #define AVM_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 180 #define AVM_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 181 #define AVM_SUVD_CGC_GATE__ENT_MASK 0x00008000L 182 #define AVM_SUVD_CGC_GATE__IME_MASK 0x00010000L 183 #define AVM_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 184 #define AVM_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 185 #define AVM_SUVD_CGC_GATE__SITE_MASK 0x00080000L 186 #define AVM_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 187 #define AVM_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 188 #define AVM_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 189 #define AVM_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 190 #define AVM_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 191 #define AVM_SUVD_CGC_GATE__EFC_MASK 0x02000000L 192 #define AVM_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 193 #define AVM_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 194 #define AVM_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 195 #define AVM_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 196 #define AVM_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 197 #define AVM_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 198 //CDEFE_SUVD_CGC_GATE 199 #define CDEFE_SUVD_CGC_GATE__SRE__SHIFT 0x0 200 #define CDEFE_SUVD_CGC_GATE__SIT__SHIFT 0x1 201 #define CDEFE_SUVD_CGC_GATE__SMP__SHIFT 0x2 202 #define CDEFE_SUVD_CGC_GATE__SCM__SHIFT 0x3 203 #define CDEFE_SUVD_CGC_GATE__SDB__SHIFT 0x4 204 #define CDEFE_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 205 #define CDEFE_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 206 #define CDEFE_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 207 #define CDEFE_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 208 #define CDEFE_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 209 #define CDEFE_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 210 #define CDEFE_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 211 #define CDEFE_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 212 #define CDEFE_SUVD_CGC_GATE__SCLR__SHIFT 0xd 213 #define CDEFE_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 214 #define CDEFE_SUVD_CGC_GATE__ENT__SHIFT 0xf 215 #define CDEFE_SUVD_CGC_GATE__IME__SHIFT 0x10 216 #define CDEFE_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 217 #define CDEFE_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 218 #define CDEFE_SUVD_CGC_GATE__SITE__SHIFT 0x13 219 #define CDEFE_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 220 #define CDEFE_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 221 #define CDEFE_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 222 #define CDEFE_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 223 #define CDEFE_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 224 #define CDEFE_SUVD_CGC_GATE__EFC__SHIFT 0x19 225 #define CDEFE_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 226 #define CDEFE_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 227 #define CDEFE_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 228 #define CDEFE_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 229 #define CDEFE_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 230 #define CDEFE_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 231 #define CDEFE_SUVD_CGC_GATE__SRE_MASK 0x00000001L 232 #define CDEFE_SUVD_CGC_GATE__SIT_MASK 0x00000002L 233 #define CDEFE_SUVD_CGC_GATE__SMP_MASK 0x00000004L 234 #define CDEFE_SUVD_CGC_GATE__SCM_MASK 0x00000008L 235 #define CDEFE_SUVD_CGC_GATE__SDB_MASK 0x00000010L 236 #define CDEFE_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 237 #define CDEFE_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 238 #define CDEFE_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 239 #define CDEFE_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 240 #define CDEFE_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 241 #define CDEFE_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 242 #define CDEFE_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 243 #define CDEFE_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 244 #define CDEFE_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 245 #define CDEFE_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 246 #define CDEFE_SUVD_CGC_GATE__ENT_MASK 0x00008000L 247 #define CDEFE_SUVD_CGC_GATE__IME_MASK 0x00010000L 248 #define CDEFE_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 249 #define CDEFE_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 250 #define CDEFE_SUVD_CGC_GATE__SITE_MASK 0x00080000L 251 #define CDEFE_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 252 #define CDEFE_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 253 #define CDEFE_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 254 #define CDEFE_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 255 #define CDEFE_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 256 #define CDEFE_SUVD_CGC_GATE__EFC_MASK 0x02000000L 257 #define CDEFE_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 258 #define CDEFE_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 259 #define CDEFE_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 260 #define CDEFE_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 261 #define CDEFE_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 262 #define CDEFE_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 263 //EFC_SUVD_CGC_GATE 264 #define EFC_SUVD_CGC_GATE__SRE__SHIFT 0x0 265 #define EFC_SUVD_CGC_GATE__SIT__SHIFT 0x1 266 #define EFC_SUVD_CGC_GATE__SMP__SHIFT 0x2 267 #define EFC_SUVD_CGC_GATE__SCM__SHIFT 0x3 268 #define EFC_SUVD_CGC_GATE__SDB__SHIFT 0x4 269 #define EFC_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 270 #define EFC_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 271 #define EFC_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 272 #define EFC_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 273 #define EFC_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 274 #define EFC_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 275 #define EFC_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 276 #define EFC_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 277 #define EFC_SUVD_CGC_GATE__SCLR__SHIFT 0xd 278 #define EFC_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 279 #define EFC_SUVD_CGC_GATE__ENT__SHIFT 0xf 280 #define EFC_SUVD_CGC_GATE__IME__SHIFT 0x10 281 #define EFC_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 282 #define EFC_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 283 #define EFC_SUVD_CGC_GATE__SITE__SHIFT 0x13 284 #define EFC_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 285 #define EFC_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 286 #define EFC_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 287 #define EFC_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 288 #define EFC_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 289 #define EFC_SUVD_CGC_GATE__EFC__SHIFT 0x19 290 #define EFC_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 291 #define EFC_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 292 #define EFC_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 293 #define EFC_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 294 #define EFC_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 295 #define EFC_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 296 #define EFC_SUVD_CGC_GATE__SRE_MASK 0x00000001L 297 #define EFC_SUVD_CGC_GATE__SIT_MASK 0x00000002L 298 #define EFC_SUVD_CGC_GATE__SMP_MASK 0x00000004L 299 #define EFC_SUVD_CGC_GATE__SCM_MASK 0x00000008L 300 #define EFC_SUVD_CGC_GATE__SDB_MASK 0x00000010L 301 #define EFC_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 302 #define EFC_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 303 #define EFC_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 304 #define EFC_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 305 #define EFC_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 306 #define EFC_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 307 #define EFC_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 308 #define EFC_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 309 #define EFC_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 310 #define EFC_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 311 #define EFC_SUVD_CGC_GATE__ENT_MASK 0x00008000L 312 #define EFC_SUVD_CGC_GATE__IME_MASK 0x00010000L 313 #define EFC_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 314 #define EFC_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 315 #define EFC_SUVD_CGC_GATE__SITE_MASK 0x00080000L 316 #define EFC_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 317 #define EFC_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 318 #define EFC_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 319 #define EFC_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 320 #define EFC_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 321 #define EFC_SUVD_CGC_GATE__EFC_MASK 0x02000000L 322 #define EFC_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 323 #define EFC_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 324 #define EFC_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 325 #define EFC_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 326 #define EFC_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 327 #define EFC_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 328 //ENT_SUVD_CGC_GATE 329 #define ENT_SUVD_CGC_GATE__SRE__SHIFT 0x0 330 #define ENT_SUVD_CGC_GATE__SIT__SHIFT 0x1 331 #define ENT_SUVD_CGC_GATE__SMP__SHIFT 0x2 332 #define ENT_SUVD_CGC_GATE__SCM__SHIFT 0x3 333 #define ENT_SUVD_CGC_GATE__SDB__SHIFT 0x4 334 #define ENT_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 335 #define ENT_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 336 #define ENT_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 337 #define ENT_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 338 #define ENT_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 339 #define ENT_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 340 #define ENT_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 341 #define ENT_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 342 #define ENT_SUVD_CGC_GATE__SCLR__SHIFT 0xd 343 #define ENT_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 344 #define ENT_SUVD_CGC_GATE__ENT__SHIFT 0xf 345 #define ENT_SUVD_CGC_GATE__IME__SHIFT 0x10 346 #define ENT_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 347 #define ENT_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 348 #define ENT_SUVD_CGC_GATE__SITE__SHIFT 0x13 349 #define ENT_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 350 #define ENT_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 351 #define ENT_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 352 #define ENT_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 353 #define ENT_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 354 #define ENT_SUVD_CGC_GATE__EFC__SHIFT 0x19 355 #define ENT_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 356 #define ENT_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 357 #define ENT_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 358 #define ENT_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 359 #define ENT_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 360 #define ENT_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 361 #define ENT_SUVD_CGC_GATE__SRE_MASK 0x00000001L 362 #define ENT_SUVD_CGC_GATE__SIT_MASK 0x00000002L 363 #define ENT_SUVD_CGC_GATE__SMP_MASK 0x00000004L 364 #define ENT_SUVD_CGC_GATE__SCM_MASK 0x00000008L 365 #define ENT_SUVD_CGC_GATE__SDB_MASK 0x00000010L 366 #define ENT_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 367 #define ENT_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 368 #define ENT_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 369 #define ENT_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 370 #define ENT_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 371 #define ENT_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 372 #define ENT_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 373 #define ENT_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 374 #define ENT_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 375 #define ENT_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 376 #define ENT_SUVD_CGC_GATE__ENT_MASK 0x00008000L 377 #define ENT_SUVD_CGC_GATE__IME_MASK 0x00010000L 378 #define ENT_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 379 #define ENT_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 380 #define ENT_SUVD_CGC_GATE__SITE_MASK 0x00080000L 381 #define ENT_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 382 #define ENT_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 383 #define ENT_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 384 #define ENT_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 385 #define ENT_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 386 #define ENT_SUVD_CGC_GATE__EFC_MASK 0x02000000L 387 #define ENT_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 388 #define ENT_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 389 #define ENT_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 390 #define ENT_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 391 #define ENT_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 392 #define ENT_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 393 //IME_SUVD_CGC_GATE 394 #define IME_SUVD_CGC_GATE__SRE__SHIFT 0x0 395 #define IME_SUVD_CGC_GATE__SIT__SHIFT 0x1 396 #define IME_SUVD_CGC_GATE__SMP__SHIFT 0x2 397 #define IME_SUVD_CGC_GATE__SCM__SHIFT 0x3 398 #define IME_SUVD_CGC_GATE__SDB__SHIFT 0x4 399 #define IME_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 400 #define IME_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 401 #define IME_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 402 #define IME_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 403 #define IME_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 404 #define IME_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 405 #define IME_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 406 #define IME_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 407 #define IME_SUVD_CGC_GATE__SCLR__SHIFT 0xd 408 #define IME_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 409 #define IME_SUVD_CGC_GATE__ENT__SHIFT 0xf 410 #define IME_SUVD_CGC_GATE__IME__SHIFT 0x10 411 #define IME_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 412 #define IME_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 413 #define IME_SUVD_CGC_GATE__SITE__SHIFT 0x13 414 #define IME_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 415 #define IME_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 416 #define IME_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 417 #define IME_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 418 #define IME_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 419 #define IME_SUVD_CGC_GATE__EFC__SHIFT 0x19 420 #define IME_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 421 #define IME_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 422 #define IME_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 423 #define IME_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 424 #define IME_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 425 #define IME_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 426 #define IME_SUVD_CGC_GATE__SRE_MASK 0x00000001L 427 #define IME_SUVD_CGC_GATE__SIT_MASK 0x00000002L 428 #define IME_SUVD_CGC_GATE__SMP_MASK 0x00000004L 429 #define IME_SUVD_CGC_GATE__SCM_MASK 0x00000008L 430 #define IME_SUVD_CGC_GATE__SDB_MASK 0x00000010L 431 #define IME_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 432 #define IME_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 433 #define IME_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 434 #define IME_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 435 #define IME_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 436 #define IME_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 437 #define IME_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 438 #define IME_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 439 #define IME_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 440 #define IME_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 441 #define IME_SUVD_CGC_GATE__ENT_MASK 0x00008000L 442 #define IME_SUVD_CGC_GATE__IME_MASK 0x00010000L 443 #define IME_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 444 #define IME_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 445 #define IME_SUVD_CGC_GATE__SITE_MASK 0x00080000L 446 #define IME_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 447 #define IME_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 448 #define IME_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 449 #define IME_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 450 #define IME_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 451 #define IME_SUVD_CGC_GATE__EFC_MASK 0x02000000L 452 #define IME_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 453 #define IME_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 454 #define IME_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 455 #define IME_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 456 #define IME_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 457 #define IME_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 458 //PPU_SUVD_CGC_GATE 459 #define PPU_SUVD_CGC_GATE__SRE__SHIFT 0x0 460 #define PPU_SUVD_CGC_GATE__SIT__SHIFT 0x1 461 #define PPU_SUVD_CGC_GATE__SMP__SHIFT 0x2 462 #define PPU_SUVD_CGC_GATE__SCM__SHIFT 0x3 463 #define PPU_SUVD_CGC_GATE__SDB__SHIFT 0x4 464 #define PPU_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 465 #define PPU_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 466 #define PPU_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 467 #define PPU_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 468 #define PPU_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 469 #define PPU_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 470 #define PPU_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 471 #define PPU_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 472 #define PPU_SUVD_CGC_GATE__SCLR__SHIFT 0xd 473 #define PPU_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 474 #define PPU_SUVD_CGC_GATE__ENT__SHIFT 0xf 475 #define PPU_SUVD_CGC_GATE__IME__SHIFT 0x10 476 #define PPU_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 477 #define PPU_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 478 #define PPU_SUVD_CGC_GATE__SITE__SHIFT 0x13 479 #define PPU_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 480 #define PPU_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 481 #define PPU_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 482 #define PPU_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 483 #define PPU_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 484 #define PPU_SUVD_CGC_GATE__EFC__SHIFT 0x19 485 #define PPU_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 486 #define PPU_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 487 #define PPU_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 488 #define PPU_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 489 #define PPU_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 490 #define PPU_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 491 #define PPU_SUVD_CGC_GATE__SRE_MASK 0x00000001L 492 #define PPU_SUVD_CGC_GATE__SIT_MASK 0x00000002L 493 #define PPU_SUVD_CGC_GATE__SMP_MASK 0x00000004L 494 #define PPU_SUVD_CGC_GATE__SCM_MASK 0x00000008L 495 #define PPU_SUVD_CGC_GATE__SDB_MASK 0x00000010L 496 #define PPU_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 497 #define PPU_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 498 #define PPU_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 499 #define PPU_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 500 #define PPU_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 501 #define PPU_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 502 #define PPU_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 503 #define PPU_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 504 #define PPU_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 505 #define PPU_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 506 #define PPU_SUVD_CGC_GATE__ENT_MASK 0x00008000L 507 #define PPU_SUVD_CGC_GATE__IME_MASK 0x00010000L 508 #define PPU_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 509 #define PPU_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 510 #define PPU_SUVD_CGC_GATE__SITE_MASK 0x00080000L 511 #define PPU_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 512 #define PPU_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 513 #define PPU_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 514 #define PPU_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 515 #define PPU_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 516 #define PPU_SUVD_CGC_GATE__EFC_MASK 0x02000000L 517 #define PPU_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 518 #define PPU_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 519 #define PPU_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 520 #define PPU_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 521 #define PPU_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 522 #define PPU_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 523 //SAOE_SUVD_CGC_GATE 524 #define SAOE_SUVD_CGC_GATE__SRE__SHIFT 0x0 525 #define SAOE_SUVD_CGC_GATE__SIT__SHIFT 0x1 526 #define SAOE_SUVD_CGC_GATE__SMP__SHIFT 0x2 527 #define SAOE_SUVD_CGC_GATE__SCM__SHIFT 0x3 528 #define SAOE_SUVD_CGC_GATE__SDB__SHIFT 0x4 529 #define SAOE_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 530 #define SAOE_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 531 #define SAOE_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 532 #define SAOE_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 533 #define SAOE_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 534 #define SAOE_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 535 #define SAOE_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 536 #define SAOE_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 537 #define SAOE_SUVD_CGC_GATE__SCLR__SHIFT 0xd 538 #define SAOE_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 539 #define SAOE_SUVD_CGC_GATE__ENT__SHIFT 0xf 540 #define SAOE_SUVD_CGC_GATE__IME__SHIFT 0x10 541 #define SAOE_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 542 #define SAOE_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 543 #define SAOE_SUVD_CGC_GATE__SITE__SHIFT 0x13 544 #define SAOE_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 545 #define SAOE_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 546 #define SAOE_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 547 #define SAOE_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 548 #define SAOE_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 549 #define SAOE_SUVD_CGC_GATE__EFC__SHIFT 0x19 550 #define SAOE_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 551 #define SAOE_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 552 #define SAOE_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 553 #define SAOE_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 554 #define SAOE_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 555 #define SAOE_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 556 #define SAOE_SUVD_CGC_GATE__SRE_MASK 0x00000001L 557 #define SAOE_SUVD_CGC_GATE__SIT_MASK 0x00000002L 558 #define SAOE_SUVD_CGC_GATE__SMP_MASK 0x00000004L 559 #define SAOE_SUVD_CGC_GATE__SCM_MASK 0x00000008L 560 #define SAOE_SUVD_CGC_GATE__SDB_MASK 0x00000010L 561 #define SAOE_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 562 #define SAOE_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 563 #define SAOE_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 564 #define SAOE_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 565 #define SAOE_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 566 #define SAOE_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 567 #define SAOE_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 568 #define SAOE_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 569 #define SAOE_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 570 #define SAOE_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 571 #define SAOE_SUVD_CGC_GATE__ENT_MASK 0x00008000L 572 #define SAOE_SUVD_CGC_GATE__IME_MASK 0x00010000L 573 #define SAOE_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 574 #define SAOE_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 575 #define SAOE_SUVD_CGC_GATE__SITE_MASK 0x00080000L 576 #define SAOE_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 577 #define SAOE_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 578 #define SAOE_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 579 #define SAOE_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 580 #define SAOE_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 581 #define SAOE_SUVD_CGC_GATE__EFC_MASK 0x02000000L 582 #define SAOE_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 583 #define SAOE_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 584 #define SAOE_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 585 #define SAOE_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 586 #define SAOE_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 587 #define SAOE_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 588 //SCM_SUVD_CGC_GATE 589 #define SCM_SUVD_CGC_GATE__SRE__SHIFT 0x0 590 #define SCM_SUVD_CGC_GATE__SIT__SHIFT 0x1 591 #define SCM_SUVD_CGC_GATE__SMP__SHIFT 0x2 592 #define SCM_SUVD_CGC_GATE__SCM__SHIFT 0x3 593 #define SCM_SUVD_CGC_GATE__SDB__SHIFT 0x4 594 #define SCM_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 595 #define SCM_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 596 #define SCM_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 597 #define SCM_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 598 #define SCM_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 599 #define SCM_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 600 #define SCM_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 601 #define SCM_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 602 #define SCM_SUVD_CGC_GATE__SCLR__SHIFT 0xd 603 #define SCM_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 604 #define SCM_SUVD_CGC_GATE__ENT__SHIFT 0xf 605 #define SCM_SUVD_CGC_GATE__IME__SHIFT 0x10 606 #define SCM_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 607 #define SCM_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 608 #define SCM_SUVD_CGC_GATE__SITE__SHIFT 0x13 609 #define SCM_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 610 #define SCM_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 611 #define SCM_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 612 #define SCM_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 613 #define SCM_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 614 #define SCM_SUVD_CGC_GATE__EFC__SHIFT 0x19 615 #define SCM_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 616 #define SCM_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 617 #define SCM_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 618 #define SCM_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 619 #define SCM_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 620 #define SCM_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 621 #define SCM_SUVD_CGC_GATE__SRE_MASK 0x00000001L 622 #define SCM_SUVD_CGC_GATE__SIT_MASK 0x00000002L 623 #define SCM_SUVD_CGC_GATE__SMP_MASK 0x00000004L 624 #define SCM_SUVD_CGC_GATE__SCM_MASK 0x00000008L 625 #define SCM_SUVD_CGC_GATE__SDB_MASK 0x00000010L 626 #define SCM_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 627 #define SCM_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 628 #define SCM_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 629 #define SCM_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 630 #define SCM_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 631 #define SCM_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 632 #define SCM_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 633 #define SCM_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 634 #define SCM_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 635 #define SCM_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 636 #define SCM_SUVD_CGC_GATE__ENT_MASK 0x00008000L 637 #define SCM_SUVD_CGC_GATE__IME_MASK 0x00010000L 638 #define SCM_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 639 #define SCM_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 640 #define SCM_SUVD_CGC_GATE__SITE_MASK 0x00080000L 641 #define SCM_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 642 #define SCM_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 643 #define SCM_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 644 #define SCM_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 645 #define SCM_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 646 #define SCM_SUVD_CGC_GATE__EFC_MASK 0x02000000L 647 #define SCM_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 648 #define SCM_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 649 #define SCM_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 650 #define SCM_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 651 #define SCM_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 652 #define SCM_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 653 //SDB_SUVD_CGC_GATE 654 #define SDB_SUVD_CGC_GATE__SRE__SHIFT 0x0 655 #define SDB_SUVD_CGC_GATE__SIT__SHIFT 0x1 656 #define SDB_SUVD_CGC_GATE__SMP__SHIFT 0x2 657 #define SDB_SUVD_CGC_GATE__SCM__SHIFT 0x3 658 #define SDB_SUVD_CGC_GATE__SDB__SHIFT 0x4 659 #define SDB_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 660 #define SDB_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 661 #define SDB_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 662 #define SDB_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 663 #define SDB_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 664 #define SDB_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 665 #define SDB_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 666 #define SDB_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 667 #define SDB_SUVD_CGC_GATE__SCLR__SHIFT 0xd 668 #define SDB_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 669 #define SDB_SUVD_CGC_GATE__ENT__SHIFT 0xf 670 #define SDB_SUVD_CGC_GATE__IME__SHIFT 0x10 671 #define SDB_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 672 #define SDB_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 673 #define SDB_SUVD_CGC_GATE__SITE__SHIFT 0x13 674 #define SDB_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 675 #define SDB_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 676 #define SDB_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 677 #define SDB_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 678 #define SDB_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 679 #define SDB_SUVD_CGC_GATE__EFC__SHIFT 0x19 680 #define SDB_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 681 #define SDB_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 682 #define SDB_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 683 #define SDB_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 684 #define SDB_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 685 #define SDB_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 686 #define SDB_SUVD_CGC_GATE__SRE_MASK 0x00000001L 687 #define SDB_SUVD_CGC_GATE__SIT_MASK 0x00000002L 688 #define SDB_SUVD_CGC_GATE__SMP_MASK 0x00000004L 689 #define SDB_SUVD_CGC_GATE__SCM_MASK 0x00000008L 690 #define SDB_SUVD_CGC_GATE__SDB_MASK 0x00000010L 691 #define SDB_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 692 #define SDB_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 693 #define SDB_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 694 #define SDB_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 695 #define SDB_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 696 #define SDB_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 697 #define SDB_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 698 #define SDB_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 699 #define SDB_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 700 #define SDB_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 701 #define SDB_SUVD_CGC_GATE__ENT_MASK 0x00008000L 702 #define SDB_SUVD_CGC_GATE__IME_MASK 0x00010000L 703 #define SDB_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 704 #define SDB_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 705 #define SDB_SUVD_CGC_GATE__SITE_MASK 0x00080000L 706 #define SDB_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 707 #define SDB_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 708 #define SDB_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 709 #define SDB_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 710 #define SDB_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 711 #define SDB_SUVD_CGC_GATE__EFC_MASK 0x02000000L 712 #define SDB_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 713 #define SDB_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 714 #define SDB_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 715 #define SDB_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 716 #define SDB_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 717 #define SDB_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 718 //SIT0_NXT_SUVD_CGC_GATE 719 #define SIT0_NXT_SUVD_CGC_GATE__SRE__SHIFT 0x0 720 #define SIT0_NXT_SUVD_CGC_GATE__SIT__SHIFT 0x1 721 #define SIT0_NXT_SUVD_CGC_GATE__SMP__SHIFT 0x2 722 #define SIT0_NXT_SUVD_CGC_GATE__SCM__SHIFT 0x3 723 #define SIT0_NXT_SUVD_CGC_GATE__SDB__SHIFT 0x4 724 #define SIT0_NXT_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 725 #define SIT0_NXT_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 726 #define SIT0_NXT_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 727 #define SIT0_NXT_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 728 #define SIT0_NXT_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 729 #define SIT0_NXT_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 730 #define SIT0_NXT_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 731 #define SIT0_NXT_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 732 #define SIT0_NXT_SUVD_CGC_GATE__SCLR__SHIFT 0xd 733 #define SIT0_NXT_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 734 #define SIT0_NXT_SUVD_CGC_GATE__ENT__SHIFT 0xf 735 #define SIT0_NXT_SUVD_CGC_GATE__IME__SHIFT 0x10 736 #define SIT0_NXT_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 737 #define SIT0_NXT_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 738 #define SIT0_NXT_SUVD_CGC_GATE__SITE__SHIFT 0x13 739 #define SIT0_NXT_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 740 #define SIT0_NXT_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 741 #define SIT0_NXT_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 742 #define SIT0_NXT_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 743 #define SIT0_NXT_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 744 #define SIT0_NXT_SUVD_CGC_GATE__EFC__SHIFT 0x19 745 #define SIT0_NXT_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 746 #define SIT0_NXT_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 747 #define SIT0_NXT_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 748 #define SIT0_NXT_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 749 #define SIT0_NXT_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 750 #define SIT0_NXT_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 751 #define SIT0_NXT_SUVD_CGC_GATE__SRE_MASK 0x00000001L 752 #define SIT0_NXT_SUVD_CGC_GATE__SIT_MASK 0x00000002L 753 #define SIT0_NXT_SUVD_CGC_GATE__SMP_MASK 0x00000004L 754 #define SIT0_NXT_SUVD_CGC_GATE__SCM_MASK 0x00000008L 755 #define SIT0_NXT_SUVD_CGC_GATE__SDB_MASK 0x00000010L 756 #define SIT0_NXT_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 757 #define SIT0_NXT_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 758 #define SIT0_NXT_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 759 #define SIT0_NXT_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 760 #define SIT0_NXT_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 761 #define SIT0_NXT_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 762 #define SIT0_NXT_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 763 #define SIT0_NXT_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 764 #define SIT0_NXT_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 765 #define SIT0_NXT_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 766 #define SIT0_NXT_SUVD_CGC_GATE__ENT_MASK 0x00008000L 767 #define SIT0_NXT_SUVD_CGC_GATE__IME_MASK 0x00010000L 768 #define SIT0_NXT_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 769 #define SIT0_NXT_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 770 #define SIT0_NXT_SUVD_CGC_GATE__SITE_MASK 0x00080000L 771 #define SIT0_NXT_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 772 #define SIT0_NXT_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 773 #define SIT0_NXT_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 774 #define SIT0_NXT_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 775 #define SIT0_NXT_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 776 #define SIT0_NXT_SUVD_CGC_GATE__EFC_MASK 0x02000000L 777 #define SIT0_NXT_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 778 #define SIT0_NXT_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 779 #define SIT0_NXT_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 780 #define SIT0_NXT_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 781 #define SIT0_NXT_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 782 #define SIT0_NXT_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 783 //SIT1_NXT_SUVD_CGC_GATE 784 #define SIT1_NXT_SUVD_CGC_GATE__SRE__SHIFT 0x0 785 #define SIT1_NXT_SUVD_CGC_GATE__SIT__SHIFT 0x1 786 #define SIT1_NXT_SUVD_CGC_GATE__SMP__SHIFT 0x2 787 #define SIT1_NXT_SUVD_CGC_GATE__SCM__SHIFT 0x3 788 #define SIT1_NXT_SUVD_CGC_GATE__SDB__SHIFT 0x4 789 #define SIT1_NXT_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 790 #define SIT1_NXT_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 791 #define SIT1_NXT_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 792 #define SIT1_NXT_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 793 #define SIT1_NXT_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 794 #define SIT1_NXT_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 795 #define SIT1_NXT_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 796 #define SIT1_NXT_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 797 #define SIT1_NXT_SUVD_CGC_GATE__SCLR__SHIFT 0xd 798 #define SIT1_NXT_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 799 #define SIT1_NXT_SUVD_CGC_GATE__ENT__SHIFT 0xf 800 #define SIT1_NXT_SUVD_CGC_GATE__IME__SHIFT 0x10 801 #define SIT1_NXT_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 802 #define SIT1_NXT_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 803 #define SIT1_NXT_SUVD_CGC_GATE__SITE__SHIFT 0x13 804 #define SIT1_NXT_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 805 #define SIT1_NXT_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 806 #define SIT1_NXT_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 807 #define SIT1_NXT_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 808 #define SIT1_NXT_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 809 #define SIT1_NXT_SUVD_CGC_GATE__EFC__SHIFT 0x19 810 #define SIT1_NXT_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 811 #define SIT1_NXT_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 812 #define SIT1_NXT_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 813 #define SIT1_NXT_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 814 #define SIT1_NXT_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 815 #define SIT1_NXT_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 816 #define SIT1_NXT_SUVD_CGC_GATE__SRE_MASK 0x00000001L 817 #define SIT1_NXT_SUVD_CGC_GATE__SIT_MASK 0x00000002L 818 #define SIT1_NXT_SUVD_CGC_GATE__SMP_MASK 0x00000004L 819 #define SIT1_NXT_SUVD_CGC_GATE__SCM_MASK 0x00000008L 820 #define SIT1_NXT_SUVD_CGC_GATE__SDB_MASK 0x00000010L 821 #define SIT1_NXT_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 822 #define SIT1_NXT_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 823 #define SIT1_NXT_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 824 #define SIT1_NXT_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 825 #define SIT1_NXT_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 826 #define SIT1_NXT_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 827 #define SIT1_NXT_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 828 #define SIT1_NXT_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 829 #define SIT1_NXT_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 830 #define SIT1_NXT_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 831 #define SIT1_NXT_SUVD_CGC_GATE__ENT_MASK 0x00008000L 832 #define SIT1_NXT_SUVD_CGC_GATE__IME_MASK 0x00010000L 833 #define SIT1_NXT_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 834 #define SIT1_NXT_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 835 #define SIT1_NXT_SUVD_CGC_GATE__SITE_MASK 0x00080000L 836 #define SIT1_NXT_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 837 #define SIT1_NXT_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 838 #define SIT1_NXT_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 839 #define SIT1_NXT_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 840 #define SIT1_NXT_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 841 #define SIT1_NXT_SUVD_CGC_GATE__EFC_MASK 0x02000000L 842 #define SIT1_NXT_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 843 #define SIT1_NXT_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 844 #define SIT1_NXT_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 845 #define SIT1_NXT_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 846 #define SIT1_NXT_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 847 #define SIT1_NXT_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 848 //SIT2_NXT_SUVD_CGC_GATE 849 #define SIT2_NXT_SUVD_CGC_GATE__SRE__SHIFT 0x0 850 #define SIT2_NXT_SUVD_CGC_GATE__SIT__SHIFT 0x1 851 #define SIT2_NXT_SUVD_CGC_GATE__SMP__SHIFT 0x2 852 #define SIT2_NXT_SUVD_CGC_GATE__SCM__SHIFT 0x3 853 #define SIT2_NXT_SUVD_CGC_GATE__SDB__SHIFT 0x4 854 #define SIT2_NXT_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 855 #define SIT2_NXT_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 856 #define SIT2_NXT_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 857 #define SIT2_NXT_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 858 #define SIT2_NXT_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 859 #define SIT2_NXT_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 860 #define SIT2_NXT_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 861 #define SIT2_NXT_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 862 #define SIT2_NXT_SUVD_CGC_GATE__SCLR__SHIFT 0xd 863 #define SIT2_NXT_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 864 #define SIT2_NXT_SUVD_CGC_GATE__ENT__SHIFT 0xf 865 #define SIT2_NXT_SUVD_CGC_GATE__IME__SHIFT 0x10 866 #define SIT2_NXT_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 867 #define SIT2_NXT_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 868 #define SIT2_NXT_SUVD_CGC_GATE__SITE__SHIFT 0x13 869 #define SIT2_NXT_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 870 #define SIT2_NXT_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 871 #define SIT2_NXT_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 872 #define SIT2_NXT_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 873 #define SIT2_NXT_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 874 #define SIT2_NXT_SUVD_CGC_GATE__EFC__SHIFT 0x19 875 #define SIT2_NXT_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 876 #define SIT2_NXT_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 877 #define SIT2_NXT_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 878 #define SIT2_NXT_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 879 #define SIT2_NXT_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 880 #define SIT2_NXT_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 881 #define SIT2_NXT_SUVD_CGC_GATE__SRE_MASK 0x00000001L 882 #define SIT2_NXT_SUVD_CGC_GATE__SIT_MASK 0x00000002L 883 #define SIT2_NXT_SUVD_CGC_GATE__SMP_MASK 0x00000004L 884 #define SIT2_NXT_SUVD_CGC_GATE__SCM_MASK 0x00000008L 885 #define SIT2_NXT_SUVD_CGC_GATE__SDB_MASK 0x00000010L 886 #define SIT2_NXT_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 887 #define SIT2_NXT_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 888 #define SIT2_NXT_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 889 #define SIT2_NXT_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 890 #define SIT2_NXT_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 891 #define SIT2_NXT_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 892 #define SIT2_NXT_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 893 #define SIT2_NXT_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 894 #define SIT2_NXT_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 895 #define SIT2_NXT_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 896 #define SIT2_NXT_SUVD_CGC_GATE__ENT_MASK 0x00008000L 897 #define SIT2_NXT_SUVD_CGC_GATE__IME_MASK 0x00010000L 898 #define SIT2_NXT_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 899 #define SIT2_NXT_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 900 #define SIT2_NXT_SUVD_CGC_GATE__SITE_MASK 0x00080000L 901 #define SIT2_NXT_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 902 #define SIT2_NXT_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 903 #define SIT2_NXT_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 904 #define SIT2_NXT_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 905 #define SIT2_NXT_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 906 #define SIT2_NXT_SUVD_CGC_GATE__EFC_MASK 0x02000000L 907 #define SIT2_NXT_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 908 #define SIT2_NXT_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 909 #define SIT2_NXT_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 910 #define SIT2_NXT_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 911 #define SIT2_NXT_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 912 #define SIT2_NXT_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 913 //SIT_SUVD_CGC_GATE 914 #define SIT_SUVD_CGC_GATE__SRE__SHIFT 0x0 915 #define SIT_SUVD_CGC_GATE__SIT__SHIFT 0x1 916 #define SIT_SUVD_CGC_GATE__SMP__SHIFT 0x2 917 #define SIT_SUVD_CGC_GATE__SCM__SHIFT 0x3 918 #define SIT_SUVD_CGC_GATE__SDB__SHIFT 0x4 919 #define SIT_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 920 #define SIT_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 921 #define SIT_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 922 #define SIT_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 923 #define SIT_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 924 #define SIT_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 925 #define SIT_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 926 #define SIT_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 927 #define SIT_SUVD_CGC_GATE__SCLR__SHIFT 0xd 928 #define SIT_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 929 #define SIT_SUVD_CGC_GATE__ENT__SHIFT 0xf 930 #define SIT_SUVD_CGC_GATE__IME__SHIFT 0x10 931 #define SIT_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 932 #define SIT_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 933 #define SIT_SUVD_CGC_GATE__SITE__SHIFT 0x13 934 #define SIT_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 935 #define SIT_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 936 #define SIT_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 937 #define SIT_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 938 #define SIT_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 939 #define SIT_SUVD_CGC_GATE__EFC__SHIFT 0x19 940 #define SIT_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 941 #define SIT_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 942 #define SIT_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 943 #define SIT_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 944 #define SIT_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 945 #define SIT_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 946 #define SIT_SUVD_CGC_GATE__SRE_MASK 0x00000001L 947 #define SIT_SUVD_CGC_GATE__SIT_MASK 0x00000002L 948 #define SIT_SUVD_CGC_GATE__SMP_MASK 0x00000004L 949 #define SIT_SUVD_CGC_GATE__SCM_MASK 0x00000008L 950 #define SIT_SUVD_CGC_GATE__SDB_MASK 0x00000010L 951 #define SIT_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 952 #define SIT_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 953 #define SIT_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 954 #define SIT_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 955 #define SIT_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 956 #define SIT_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 957 #define SIT_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 958 #define SIT_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 959 #define SIT_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 960 #define SIT_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 961 #define SIT_SUVD_CGC_GATE__ENT_MASK 0x00008000L 962 #define SIT_SUVD_CGC_GATE__IME_MASK 0x00010000L 963 #define SIT_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 964 #define SIT_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 965 #define SIT_SUVD_CGC_GATE__SITE_MASK 0x00080000L 966 #define SIT_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 967 #define SIT_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 968 #define SIT_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 969 #define SIT_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 970 #define SIT_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 971 #define SIT_SUVD_CGC_GATE__EFC_MASK 0x02000000L 972 #define SIT_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 973 #define SIT_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 974 #define SIT_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 975 #define SIT_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 976 #define SIT_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 977 #define SIT_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 978 //SMPA_SUVD_CGC_GATE 979 #define SMPA_SUVD_CGC_GATE__SRE__SHIFT 0x0 980 #define SMPA_SUVD_CGC_GATE__SIT__SHIFT 0x1 981 #define SMPA_SUVD_CGC_GATE__SMP__SHIFT 0x2 982 #define SMPA_SUVD_CGC_GATE__SCM__SHIFT 0x3 983 #define SMPA_SUVD_CGC_GATE__SDB__SHIFT 0x4 984 #define SMPA_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 985 #define SMPA_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 986 #define SMPA_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 987 #define SMPA_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 988 #define SMPA_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 989 #define SMPA_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 990 #define SMPA_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 991 #define SMPA_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 992 #define SMPA_SUVD_CGC_GATE__SCLR__SHIFT 0xd 993 #define SMPA_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 994 #define SMPA_SUVD_CGC_GATE__ENT__SHIFT 0xf 995 #define SMPA_SUVD_CGC_GATE__IME__SHIFT 0x10 996 #define SMPA_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 997 #define SMPA_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 998 #define SMPA_SUVD_CGC_GATE__SITE__SHIFT 0x13 999 #define SMPA_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 1000 #define SMPA_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 1001 #define SMPA_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 1002 #define SMPA_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 1003 #define SMPA_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 1004 #define SMPA_SUVD_CGC_GATE__EFC__SHIFT 0x19 1005 #define SMPA_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 1006 #define SMPA_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 1007 #define SMPA_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 1008 #define SMPA_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 1009 #define SMPA_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 1010 #define SMPA_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 1011 #define SMPA_SUVD_CGC_GATE__SRE_MASK 0x00000001L 1012 #define SMPA_SUVD_CGC_GATE__SIT_MASK 0x00000002L 1013 #define SMPA_SUVD_CGC_GATE__SMP_MASK 0x00000004L 1014 #define SMPA_SUVD_CGC_GATE__SCM_MASK 0x00000008L 1015 #define SMPA_SUVD_CGC_GATE__SDB_MASK 0x00000010L 1016 #define SMPA_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 1017 #define SMPA_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 1018 #define SMPA_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 1019 #define SMPA_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 1020 #define SMPA_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 1021 #define SMPA_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 1022 #define SMPA_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 1023 #define SMPA_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 1024 #define SMPA_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 1025 #define SMPA_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 1026 #define SMPA_SUVD_CGC_GATE__ENT_MASK 0x00008000L 1027 #define SMPA_SUVD_CGC_GATE__IME_MASK 0x00010000L 1028 #define SMPA_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 1029 #define SMPA_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 1030 #define SMPA_SUVD_CGC_GATE__SITE_MASK 0x00080000L 1031 #define SMPA_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 1032 #define SMPA_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 1033 #define SMPA_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 1034 #define SMPA_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 1035 #define SMPA_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 1036 #define SMPA_SUVD_CGC_GATE__EFC_MASK 0x02000000L 1037 #define SMPA_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 1038 #define SMPA_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 1039 #define SMPA_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 1040 #define SMPA_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 1041 #define SMPA_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 1042 #define SMPA_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 1043 //SMP_SUVD_CGC_GATE 1044 #define SMP_SUVD_CGC_GATE__SRE__SHIFT 0x0 1045 #define SMP_SUVD_CGC_GATE__SIT__SHIFT 0x1 1046 #define SMP_SUVD_CGC_GATE__SMP__SHIFT 0x2 1047 #define SMP_SUVD_CGC_GATE__SCM__SHIFT 0x3 1048 #define SMP_SUVD_CGC_GATE__SDB__SHIFT 0x4 1049 #define SMP_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 1050 #define SMP_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 1051 #define SMP_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 1052 #define SMP_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 1053 #define SMP_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 1054 #define SMP_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 1055 #define SMP_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 1056 #define SMP_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 1057 #define SMP_SUVD_CGC_GATE__SCLR__SHIFT 0xd 1058 #define SMP_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 1059 #define SMP_SUVD_CGC_GATE__ENT__SHIFT 0xf 1060 #define SMP_SUVD_CGC_GATE__IME__SHIFT 0x10 1061 #define SMP_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 1062 #define SMP_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 1063 #define SMP_SUVD_CGC_GATE__SITE__SHIFT 0x13 1064 #define SMP_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 1065 #define SMP_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 1066 #define SMP_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 1067 #define SMP_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 1068 #define SMP_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 1069 #define SMP_SUVD_CGC_GATE__EFC__SHIFT 0x19 1070 #define SMP_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 1071 #define SMP_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 1072 #define SMP_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 1073 #define SMP_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 1074 #define SMP_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 1075 #define SMP_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 1076 #define SMP_SUVD_CGC_GATE__SRE_MASK 0x00000001L 1077 #define SMP_SUVD_CGC_GATE__SIT_MASK 0x00000002L 1078 #define SMP_SUVD_CGC_GATE__SMP_MASK 0x00000004L 1079 #define SMP_SUVD_CGC_GATE__SCM_MASK 0x00000008L 1080 #define SMP_SUVD_CGC_GATE__SDB_MASK 0x00000010L 1081 #define SMP_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 1082 #define SMP_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 1083 #define SMP_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 1084 #define SMP_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 1085 #define SMP_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 1086 #define SMP_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 1087 #define SMP_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 1088 #define SMP_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 1089 #define SMP_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 1090 #define SMP_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 1091 #define SMP_SUVD_CGC_GATE__ENT_MASK 0x00008000L 1092 #define SMP_SUVD_CGC_GATE__IME_MASK 0x00010000L 1093 #define SMP_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 1094 #define SMP_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 1095 #define SMP_SUVD_CGC_GATE__SITE_MASK 0x00080000L 1096 #define SMP_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 1097 #define SMP_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 1098 #define SMP_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 1099 #define SMP_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 1100 #define SMP_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 1101 #define SMP_SUVD_CGC_GATE__EFC_MASK 0x02000000L 1102 #define SMP_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 1103 #define SMP_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 1104 #define SMP_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 1105 #define SMP_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 1106 #define SMP_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 1107 #define SMP_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 1108 //SRE_SUVD_CGC_GATE 1109 #define SRE_SUVD_CGC_GATE__SRE__SHIFT 0x0 1110 #define SRE_SUVD_CGC_GATE__SIT__SHIFT 0x1 1111 #define SRE_SUVD_CGC_GATE__SMP__SHIFT 0x2 1112 #define SRE_SUVD_CGC_GATE__SCM__SHIFT 0x3 1113 #define SRE_SUVD_CGC_GATE__SDB__SHIFT 0x4 1114 #define SRE_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 1115 #define SRE_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 1116 #define SRE_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 1117 #define SRE_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 1118 #define SRE_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 1119 #define SRE_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 1120 #define SRE_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 1121 #define SRE_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 1122 #define SRE_SUVD_CGC_GATE__SCLR__SHIFT 0xd 1123 #define SRE_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 1124 #define SRE_SUVD_CGC_GATE__ENT__SHIFT 0xf 1125 #define SRE_SUVD_CGC_GATE__IME__SHIFT 0x10 1126 #define SRE_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 1127 #define SRE_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 1128 #define SRE_SUVD_CGC_GATE__SITE__SHIFT 0x13 1129 #define SRE_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 1130 #define SRE_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 1131 #define SRE_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 1132 #define SRE_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 1133 #define SRE_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 1134 #define SRE_SUVD_CGC_GATE__EFC__SHIFT 0x19 1135 #define SRE_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 1136 #define SRE_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 1137 #define SRE_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 1138 #define SRE_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 1139 #define SRE_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 1140 #define SRE_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 1141 #define SRE_SUVD_CGC_GATE__SRE_MASK 0x00000001L 1142 #define SRE_SUVD_CGC_GATE__SIT_MASK 0x00000002L 1143 #define SRE_SUVD_CGC_GATE__SMP_MASK 0x00000004L 1144 #define SRE_SUVD_CGC_GATE__SCM_MASK 0x00000008L 1145 #define SRE_SUVD_CGC_GATE__SDB_MASK 0x00000010L 1146 #define SRE_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 1147 #define SRE_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 1148 #define SRE_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 1149 #define SRE_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 1150 #define SRE_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 1151 #define SRE_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 1152 #define SRE_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 1153 #define SRE_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 1154 #define SRE_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 1155 #define SRE_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 1156 #define SRE_SUVD_CGC_GATE__ENT_MASK 0x00008000L 1157 #define SRE_SUVD_CGC_GATE__IME_MASK 0x00010000L 1158 #define SRE_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 1159 #define SRE_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 1160 #define SRE_SUVD_CGC_GATE__SITE_MASK 0x00080000L 1161 #define SRE_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 1162 #define SRE_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 1163 #define SRE_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 1164 #define SRE_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 1165 #define SRE_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 1166 #define SRE_SUVD_CGC_GATE__EFC_MASK 0x02000000L 1167 #define SRE_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 1168 #define SRE_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 1169 #define SRE_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 1170 #define SRE_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 1171 #define SRE_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 1172 #define SRE_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 1173 //UVD_MPBE0_SUVD_CGC_GATE 1174 #define UVD_MPBE0_SUVD_CGC_GATE__SRE__SHIFT 0x0 1175 #define UVD_MPBE0_SUVD_CGC_GATE__SIT__SHIFT 0x1 1176 #define UVD_MPBE0_SUVD_CGC_GATE__SMP__SHIFT 0x2 1177 #define UVD_MPBE0_SUVD_CGC_GATE__SCM__SHIFT 0x3 1178 #define UVD_MPBE0_SUVD_CGC_GATE__SDB__SHIFT 0x4 1179 #define UVD_MPBE0_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 1180 #define UVD_MPBE0_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 1181 #define UVD_MPBE0_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 1182 #define UVD_MPBE0_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 1183 #define UVD_MPBE0_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 1184 #define UVD_MPBE0_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 1185 #define UVD_MPBE0_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 1186 #define UVD_MPBE0_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 1187 #define UVD_MPBE0_SUVD_CGC_GATE__SCLR__SHIFT 0xd 1188 #define UVD_MPBE0_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 1189 #define UVD_MPBE0_SUVD_CGC_GATE__ENT__SHIFT 0xf 1190 #define UVD_MPBE0_SUVD_CGC_GATE__IME__SHIFT 0x10 1191 #define UVD_MPBE0_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 1192 #define UVD_MPBE0_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 1193 #define UVD_MPBE0_SUVD_CGC_GATE__SITE__SHIFT 0x13 1194 #define UVD_MPBE0_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 1195 #define UVD_MPBE0_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 1196 #define UVD_MPBE0_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 1197 #define UVD_MPBE0_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 1198 #define UVD_MPBE0_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 1199 #define UVD_MPBE0_SUVD_CGC_GATE__EFC__SHIFT 0x19 1200 #define UVD_MPBE0_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 1201 #define UVD_MPBE0_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 1202 #define UVD_MPBE0_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 1203 #define UVD_MPBE0_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 1204 #define UVD_MPBE0_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 1205 #define UVD_MPBE0_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 1206 #define UVD_MPBE0_SUVD_CGC_GATE__SRE_MASK 0x00000001L 1207 #define UVD_MPBE0_SUVD_CGC_GATE__SIT_MASK 0x00000002L 1208 #define UVD_MPBE0_SUVD_CGC_GATE__SMP_MASK 0x00000004L 1209 #define UVD_MPBE0_SUVD_CGC_GATE__SCM_MASK 0x00000008L 1210 #define UVD_MPBE0_SUVD_CGC_GATE__SDB_MASK 0x00000010L 1211 #define UVD_MPBE0_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 1212 #define UVD_MPBE0_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 1213 #define UVD_MPBE0_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 1214 #define UVD_MPBE0_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 1215 #define UVD_MPBE0_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 1216 #define UVD_MPBE0_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 1217 #define UVD_MPBE0_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 1218 #define UVD_MPBE0_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 1219 #define UVD_MPBE0_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 1220 #define UVD_MPBE0_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 1221 #define UVD_MPBE0_SUVD_CGC_GATE__ENT_MASK 0x00008000L 1222 #define UVD_MPBE0_SUVD_CGC_GATE__IME_MASK 0x00010000L 1223 #define UVD_MPBE0_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 1224 #define UVD_MPBE0_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 1225 #define UVD_MPBE0_SUVD_CGC_GATE__SITE_MASK 0x00080000L 1226 #define UVD_MPBE0_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 1227 #define UVD_MPBE0_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 1228 #define UVD_MPBE0_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 1229 #define UVD_MPBE0_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 1230 #define UVD_MPBE0_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 1231 #define UVD_MPBE0_SUVD_CGC_GATE__EFC_MASK 0x02000000L 1232 #define UVD_MPBE0_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 1233 #define UVD_MPBE0_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 1234 #define UVD_MPBE0_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 1235 #define UVD_MPBE0_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 1236 #define UVD_MPBE0_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 1237 #define UVD_MPBE0_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 1238 //UVD_MPBE1_SUVD_CGC_GATE 1239 #define UVD_MPBE1_SUVD_CGC_GATE__SRE__SHIFT 0x0 1240 #define UVD_MPBE1_SUVD_CGC_GATE__SIT__SHIFT 0x1 1241 #define UVD_MPBE1_SUVD_CGC_GATE__SMP__SHIFT 0x2 1242 #define UVD_MPBE1_SUVD_CGC_GATE__SCM__SHIFT 0x3 1243 #define UVD_MPBE1_SUVD_CGC_GATE__SDB__SHIFT 0x4 1244 #define UVD_MPBE1_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 1245 #define UVD_MPBE1_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 1246 #define UVD_MPBE1_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 1247 #define UVD_MPBE1_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 1248 #define UVD_MPBE1_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 1249 #define UVD_MPBE1_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 1250 #define UVD_MPBE1_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 1251 #define UVD_MPBE1_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 1252 #define UVD_MPBE1_SUVD_CGC_GATE__SCLR__SHIFT 0xd 1253 #define UVD_MPBE1_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 1254 #define UVD_MPBE1_SUVD_CGC_GATE__ENT__SHIFT 0xf 1255 #define UVD_MPBE1_SUVD_CGC_GATE__IME__SHIFT 0x10 1256 #define UVD_MPBE1_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 1257 #define UVD_MPBE1_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 1258 #define UVD_MPBE1_SUVD_CGC_GATE__SITE__SHIFT 0x13 1259 #define UVD_MPBE1_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 1260 #define UVD_MPBE1_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 1261 #define UVD_MPBE1_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 1262 #define UVD_MPBE1_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 1263 #define UVD_MPBE1_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 1264 #define UVD_MPBE1_SUVD_CGC_GATE__EFC__SHIFT 0x19 1265 #define UVD_MPBE1_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 1266 #define UVD_MPBE1_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 1267 #define UVD_MPBE1_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 1268 #define UVD_MPBE1_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 1269 #define UVD_MPBE1_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 1270 #define UVD_MPBE1_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 1271 #define UVD_MPBE1_SUVD_CGC_GATE__SRE_MASK 0x00000001L 1272 #define UVD_MPBE1_SUVD_CGC_GATE__SIT_MASK 0x00000002L 1273 #define UVD_MPBE1_SUVD_CGC_GATE__SMP_MASK 0x00000004L 1274 #define UVD_MPBE1_SUVD_CGC_GATE__SCM_MASK 0x00000008L 1275 #define UVD_MPBE1_SUVD_CGC_GATE__SDB_MASK 0x00000010L 1276 #define UVD_MPBE1_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 1277 #define UVD_MPBE1_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 1278 #define UVD_MPBE1_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 1279 #define UVD_MPBE1_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 1280 #define UVD_MPBE1_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 1281 #define UVD_MPBE1_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 1282 #define UVD_MPBE1_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 1283 #define UVD_MPBE1_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 1284 #define UVD_MPBE1_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 1285 #define UVD_MPBE1_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 1286 #define UVD_MPBE1_SUVD_CGC_GATE__ENT_MASK 0x00008000L 1287 #define UVD_MPBE1_SUVD_CGC_GATE__IME_MASK 0x00010000L 1288 #define UVD_MPBE1_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 1289 #define UVD_MPBE1_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 1290 #define UVD_MPBE1_SUVD_CGC_GATE__SITE_MASK 0x00080000L 1291 #define UVD_MPBE1_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 1292 #define UVD_MPBE1_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 1293 #define UVD_MPBE1_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 1294 #define UVD_MPBE1_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 1295 #define UVD_MPBE1_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 1296 #define UVD_MPBE1_SUVD_CGC_GATE__EFC_MASK 0x02000000L 1297 #define UVD_MPBE1_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 1298 #define UVD_MPBE1_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 1299 #define UVD_MPBE1_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 1300 #define UVD_MPBE1_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 1301 #define UVD_MPBE1_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 1302 #define UVD_MPBE1_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 1303 //UVD_SUVD_CGC_GATE 1304 #define UVD_SUVD_CGC_GATE__SRE__SHIFT 0x0 1305 #define UVD_SUVD_CGC_GATE__SIT__SHIFT 0x1 1306 #define UVD_SUVD_CGC_GATE__SMP__SHIFT 0x2 1307 #define UVD_SUVD_CGC_GATE__SCM__SHIFT 0x3 1308 #define UVD_SUVD_CGC_GATE__SDB__SHIFT 0x4 1309 #define UVD_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 1310 #define UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 1311 #define UVD_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 1312 #define UVD_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 1313 #define UVD_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 1314 #define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 1315 #define UVD_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 1316 #define UVD_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 1317 #define UVD_SUVD_CGC_GATE__SCLR__SHIFT 0xd 1318 #define UVD_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 1319 #define UVD_SUVD_CGC_GATE__ENT__SHIFT 0xf 1320 #define UVD_SUVD_CGC_GATE__IME__SHIFT 0x10 1321 #define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 1322 #define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 1323 #define UVD_SUVD_CGC_GATE__SITE__SHIFT 0x13 1324 #define UVD_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 1325 #define UVD_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 1326 #define UVD_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 1327 #define UVD_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 1328 #define UVD_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 1329 #define UVD_SUVD_CGC_GATE__EFC__SHIFT 0x19 1330 #define UVD_SUVD_CGC_GATE__SAOE__SHIFT 0x1a 1331 #define UVD_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b 1332 #define UVD_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c 1333 #define UVD_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d 1334 #define UVD_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e 1335 #define UVD_SUVD_CGC_GATE__SMPA__SHIFT 0x1f 1336 #define UVD_SUVD_CGC_GATE__SRE_MASK 0x00000001L 1337 #define UVD_SUVD_CGC_GATE__SIT_MASK 0x00000002L 1338 #define UVD_SUVD_CGC_GATE__SMP_MASK 0x00000004L 1339 #define UVD_SUVD_CGC_GATE__SCM_MASK 0x00000008L 1340 #define UVD_SUVD_CGC_GATE__SDB_MASK 0x00000010L 1341 #define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 1342 #define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 1343 #define UVD_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 1344 #define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 1345 #define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 1346 #define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 1347 #define UVD_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 1348 #define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 1349 #define UVD_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 1350 #define UVD_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 1351 #define UVD_SUVD_CGC_GATE__ENT_MASK 0x00008000L 1352 #define UVD_SUVD_CGC_GATE__IME_MASK 0x00010000L 1353 #define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 1354 #define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 1355 #define UVD_SUVD_CGC_GATE__SITE_MASK 0x00080000L 1356 #define UVD_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 1357 #define UVD_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 1358 #define UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 1359 #define UVD_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 1360 #define UVD_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 1361 #define UVD_SUVD_CGC_GATE__EFC_MASK 0x02000000L 1362 #define UVD_SUVD_CGC_GATE__SAOE_MASK 0x04000000L 1363 #define UVD_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L 1364 #define UVD_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L 1365 #define UVD_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L 1366 #define UVD_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L 1367 #define UVD_SUVD_CGC_GATE__SMPA_MASK 0x80000000L 1368 //AVM_SUVD_CGC_GATE2 1369 #define AVM_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 1370 #define AVM_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 1371 #define AVM_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 1372 #define AVM_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 1373 #define AVM_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 1374 #define AVM_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 1375 #define AVM_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 1376 #define AVM_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 1377 #define AVM_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 1378 #define AVM_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 1379 #define AVM_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa 1380 #define AVM_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb 1381 #define AVM_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L 1382 #define AVM_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L 1383 #define AVM_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L 1384 #define AVM_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L 1385 #define AVM_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L 1386 #define AVM_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L 1387 #define AVM_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L 1388 #define AVM_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L 1389 #define AVM_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L 1390 #define AVM_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L 1391 #define AVM_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L 1392 #define AVM_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L 1393 //CDEFE_SUVD_CGC_GATE2 1394 #define CDEFE_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 1395 #define CDEFE_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 1396 #define CDEFE_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 1397 #define CDEFE_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 1398 #define CDEFE_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 1399 #define CDEFE_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 1400 #define CDEFE_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 1401 #define CDEFE_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 1402 #define CDEFE_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 1403 #define CDEFE_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 1404 #define CDEFE_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa 1405 #define CDEFE_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb 1406 #define CDEFE_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L 1407 #define CDEFE_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L 1408 #define CDEFE_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L 1409 #define CDEFE_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L 1410 #define CDEFE_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L 1411 #define CDEFE_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L 1412 #define CDEFE_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L 1413 #define CDEFE_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L 1414 #define CDEFE_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L 1415 #define CDEFE_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L 1416 #define CDEFE_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L 1417 #define CDEFE_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L 1418 //DBR_SUVD_CGC_GATE2 1419 #define DBR_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 1420 #define DBR_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 1421 #define DBR_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 1422 #define DBR_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 1423 #define DBR_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 1424 #define DBR_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 1425 #define DBR_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 1426 #define DBR_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 1427 #define DBR_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 1428 #define DBR_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 1429 #define DBR_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa 1430 #define DBR_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb 1431 #define DBR_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L 1432 #define DBR_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L 1433 #define DBR_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L 1434 #define DBR_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L 1435 #define DBR_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L 1436 #define DBR_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L 1437 #define DBR_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L 1438 #define DBR_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L 1439 #define DBR_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L 1440 #define DBR_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L 1441 #define DBR_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L 1442 #define DBR_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L 1443 //ENT_SUVD_CGC_GATE2 1444 #define ENT_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 1445 #define ENT_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 1446 #define ENT_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 1447 #define ENT_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 1448 #define ENT_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 1449 #define ENT_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 1450 #define ENT_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 1451 #define ENT_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 1452 #define ENT_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 1453 #define ENT_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 1454 #define ENT_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa 1455 #define ENT_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb 1456 #define ENT_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L 1457 #define ENT_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L 1458 #define ENT_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L 1459 #define ENT_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L 1460 #define ENT_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L 1461 #define ENT_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L 1462 #define ENT_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L 1463 #define ENT_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L 1464 #define ENT_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L 1465 #define ENT_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L 1466 #define ENT_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L 1467 #define ENT_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L 1468 //IME_SUVD_CGC_GATE2 1469 #define IME_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 1470 #define IME_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 1471 #define IME_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 1472 #define IME_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 1473 #define IME_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 1474 #define IME_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 1475 #define IME_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 1476 #define IME_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 1477 #define IME_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 1478 #define IME_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 1479 #define IME_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa 1480 #define IME_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb 1481 #define IME_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L 1482 #define IME_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L 1483 #define IME_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L 1484 #define IME_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L 1485 #define IME_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L 1486 #define IME_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L 1487 #define IME_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L 1488 #define IME_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L 1489 #define IME_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L 1490 #define IME_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L 1491 #define IME_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L 1492 #define IME_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L 1493 //MPC1_SUVD_CGC_GATE2 1494 #define MPC1_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 1495 #define MPC1_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 1496 #define MPC1_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 1497 #define MPC1_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 1498 #define MPC1_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 1499 #define MPC1_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 1500 #define MPC1_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 1501 #define MPC1_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 1502 #define MPC1_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 1503 #define MPC1_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 1504 #define MPC1_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa 1505 #define MPC1_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb 1506 #define MPC1_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L 1507 #define MPC1_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L 1508 #define MPC1_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L 1509 #define MPC1_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L 1510 #define MPC1_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L 1511 #define MPC1_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L 1512 #define MPC1_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L 1513 #define MPC1_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L 1514 #define MPC1_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L 1515 #define MPC1_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L 1516 #define MPC1_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L 1517 #define MPC1_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L 1518 //SAOE_SUVD_CGC_GATE2 1519 #define SAOE_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 1520 #define SAOE_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 1521 #define SAOE_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 1522 #define SAOE_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 1523 #define SAOE_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 1524 #define SAOE_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 1525 #define SAOE_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 1526 #define SAOE_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 1527 #define SAOE_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 1528 #define SAOE_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 1529 #define SAOE_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa 1530 #define SAOE_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb 1531 #define SAOE_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L 1532 #define SAOE_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L 1533 #define SAOE_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L 1534 #define SAOE_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L 1535 #define SAOE_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L 1536 #define SAOE_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L 1537 #define SAOE_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L 1538 #define SAOE_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L 1539 #define SAOE_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L 1540 #define SAOE_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L 1541 #define SAOE_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L 1542 #define SAOE_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L 1543 //SDB_SUVD_CGC_GATE2 1544 #define SDB_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 1545 #define SDB_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 1546 #define SDB_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 1547 #define SDB_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 1548 #define SDB_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 1549 #define SDB_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 1550 #define SDB_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 1551 #define SDB_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 1552 #define SDB_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 1553 #define SDB_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 1554 #define SDB_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa 1555 #define SDB_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb 1556 #define SDB_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L 1557 #define SDB_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L 1558 #define SDB_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L 1559 #define SDB_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L 1560 #define SDB_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L 1561 #define SDB_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L 1562 #define SDB_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L 1563 #define SDB_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L 1564 #define SDB_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L 1565 #define SDB_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L 1566 #define SDB_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L 1567 #define SDB_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L 1568 //SIT0_NXT_SUVD_CGC_GATE2 1569 #define SIT0_NXT_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 1570 #define SIT0_NXT_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 1571 #define SIT0_NXT_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 1572 #define SIT0_NXT_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 1573 #define SIT0_NXT_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 1574 #define SIT0_NXT_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 1575 #define SIT0_NXT_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 1576 #define SIT0_NXT_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 1577 #define SIT0_NXT_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 1578 #define SIT0_NXT_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 1579 #define SIT0_NXT_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa 1580 #define SIT0_NXT_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb 1581 #define SIT0_NXT_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L 1582 #define SIT0_NXT_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L 1583 #define SIT0_NXT_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L 1584 #define SIT0_NXT_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L 1585 #define SIT0_NXT_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L 1586 #define SIT0_NXT_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L 1587 #define SIT0_NXT_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L 1588 #define SIT0_NXT_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L 1589 #define SIT0_NXT_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L 1590 #define SIT0_NXT_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L 1591 #define SIT0_NXT_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L 1592 #define SIT0_NXT_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L 1593 //SIT1_NXT_SUVD_CGC_GATE2 1594 #define SIT1_NXT_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 1595 #define SIT1_NXT_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 1596 #define SIT1_NXT_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 1597 #define SIT1_NXT_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 1598 #define SIT1_NXT_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 1599 #define SIT1_NXT_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 1600 #define SIT1_NXT_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 1601 #define SIT1_NXT_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 1602 #define SIT1_NXT_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 1603 #define SIT1_NXT_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 1604 #define SIT1_NXT_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa 1605 #define SIT1_NXT_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb 1606 #define SIT1_NXT_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L 1607 #define SIT1_NXT_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L 1608 #define SIT1_NXT_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L 1609 #define SIT1_NXT_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L 1610 #define SIT1_NXT_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L 1611 #define SIT1_NXT_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L 1612 #define SIT1_NXT_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L 1613 #define SIT1_NXT_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L 1614 #define SIT1_NXT_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L 1615 #define SIT1_NXT_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L 1616 #define SIT1_NXT_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L 1617 #define SIT1_NXT_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L 1618 //SIT2_NXT_SUVD_CGC_GATE2 1619 #define SIT2_NXT_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 1620 #define SIT2_NXT_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 1621 #define SIT2_NXT_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 1622 #define SIT2_NXT_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 1623 #define SIT2_NXT_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 1624 #define SIT2_NXT_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 1625 #define SIT2_NXT_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 1626 #define SIT2_NXT_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 1627 #define SIT2_NXT_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 1628 #define SIT2_NXT_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 1629 #define SIT2_NXT_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa 1630 #define SIT2_NXT_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb 1631 #define SIT2_NXT_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L 1632 #define SIT2_NXT_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L 1633 #define SIT2_NXT_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L 1634 #define SIT2_NXT_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L 1635 #define SIT2_NXT_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L 1636 #define SIT2_NXT_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L 1637 #define SIT2_NXT_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L 1638 #define SIT2_NXT_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L 1639 #define SIT2_NXT_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L 1640 #define SIT2_NXT_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L 1641 #define SIT2_NXT_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L 1642 #define SIT2_NXT_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L 1643 //SIT_SUVD_CGC_GATE2 1644 #define SIT_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 1645 #define SIT_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 1646 #define SIT_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 1647 #define SIT_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 1648 #define SIT_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 1649 #define SIT_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 1650 #define SIT_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 1651 #define SIT_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 1652 #define SIT_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 1653 #define SIT_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 1654 #define SIT_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa 1655 #define SIT_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb 1656 #define SIT_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L 1657 #define SIT_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L 1658 #define SIT_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L 1659 #define SIT_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L 1660 #define SIT_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L 1661 #define SIT_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L 1662 #define SIT_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L 1663 #define SIT_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L 1664 #define SIT_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L 1665 #define SIT_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L 1666 #define SIT_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L 1667 #define SIT_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L 1668 //SMPA_SUVD_CGC_GATE2 1669 #define SMPA_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 1670 #define SMPA_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 1671 #define SMPA_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 1672 #define SMPA_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 1673 #define SMPA_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 1674 #define SMPA_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 1675 #define SMPA_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 1676 #define SMPA_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 1677 #define SMPA_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 1678 #define SMPA_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 1679 #define SMPA_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa 1680 #define SMPA_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb 1681 #define SMPA_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L 1682 #define SMPA_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L 1683 #define SMPA_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L 1684 #define SMPA_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L 1685 #define SMPA_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L 1686 #define SMPA_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L 1687 #define SMPA_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L 1688 #define SMPA_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L 1689 #define SMPA_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L 1690 #define SMPA_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L 1691 #define SMPA_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L 1692 #define SMPA_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L 1693 //SMP_SUVD_CGC_GATE2 1694 #define SMP_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 1695 #define SMP_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 1696 #define SMP_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 1697 #define SMP_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 1698 #define SMP_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 1699 #define SMP_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 1700 #define SMP_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 1701 #define SMP_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 1702 #define SMP_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 1703 #define SMP_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 1704 #define SMP_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa 1705 #define SMP_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb 1706 #define SMP_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L 1707 #define SMP_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L 1708 #define SMP_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L 1709 #define SMP_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L 1710 #define SMP_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L 1711 #define SMP_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L 1712 #define SMP_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L 1713 #define SMP_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L 1714 #define SMP_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L 1715 #define SMP_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L 1716 #define SMP_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L 1717 #define SMP_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L 1718 //SRE_SUVD_CGC_GATE2 1719 #define SRE_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 1720 #define SRE_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 1721 #define SRE_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 1722 #define SRE_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 1723 #define SRE_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 1724 #define SRE_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 1725 #define SRE_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 1726 #define SRE_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 1727 #define SRE_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 1728 #define SRE_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 1729 #define SRE_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa 1730 #define SRE_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb 1731 #define SRE_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L 1732 #define SRE_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L 1733 #define SRE_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L 1734 #define SRE_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L 1735 #define SRE_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L 1736 #define SRE_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L 1737 #define SRE_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L 1738 #define SRE_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L 1739 #define SRE_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L 1740 #define SRE_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L 1741 #define SRE_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L 1742 #define SRE_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L 1743 //UVD_MPBE0_SUVD_CGC_GATE2 1744 #define UVD_MPBE0_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 1745 #define UVD_MPBE0_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 1746 #define UVD_MPBE0_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 1747 #define UVD_MPBE0_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 1748 #define UVD_MPBE0_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 1749 #define UVD_MPBE0_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 1750 #define UVD_MPBE0_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 1751 #define UVD_MPBE0_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L 1752 #define UVD_MPBE0_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L 1753 #define UVD_MPBE0_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L 1754 #define UVD_MPBE0_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L 1755 #define UVD_MPBE0_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L 1756 #define UVD_MPBE0_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L 1757 #define UVD_MPBE0_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L 1758 //UVD_MPBE1_SUVD_CGC_GATE2 1759 #define UVD_MPBE1_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 1760 #define UVD_MPBE1_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 1761 #define UVD_MPBE1_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 1762 #define UVD_MPBE1_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 1763 #define UVD_MPBE1_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 1764 #define UVD_MPBE1_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 1765 #define UVD_MPBE1_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 1766 #define UVD_MPBE1_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L 1767 #define UVD_MPBE1_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L 1768 #define UVD_MPBE1_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L 1769 #define UVD_MPBE1_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L 1770 #define UVD_MPBE1_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L 1771 #define UVD_MPBE1_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L 1772 #define UVD_MPBE1_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L 1773 //UVD_SUVD_CGC_GATE2 1774 #define UVD_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 1775 #define UVD_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 1776 #define UVD_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 1777 #define UVD_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 1778 #define UVD_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 1779 #define UVD_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 1780 #define UVD_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 1781 #define UVD_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 1782 #define UVD_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 1783 #define UVD_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 1784 #define UVD_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa 1785 #define UVD_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb 1786 #define UVD_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L 1787 #define UVD_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L 1788 #define UVD_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L 1789 #define UVD_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L 1790 #define UVD_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L 1791 #define UVD_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L 1792 #define UVD_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L 1793 #define UVD_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L 1794 #define UVD_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L 1795 #define UVD_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L 1796 #define UVD_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L 1797 #define UVD_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L 1798 //AVM_SUVD_CGC_CTRL 1799 #define AVM_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 1800 #define AVM_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 1801 #define AVM_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 1802 #define AVM_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 1803 #define AVM_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 1804 #define AVM_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 1805 #define AVM_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 1806 #define AVM_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 1807 #define AVM_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 1808 #define AVM_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 1809 #define AVM_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 1810 #define AVM_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 1811 #define AVM_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 1812 #define AVM_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 1813 #define AVM_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 1814 #define AVM_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 1815 #define AVM_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 1816 #define AVM_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 1817 #define AVM_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 1818 #define AVM_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 1819 #define AVM_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 1820 #define AVM_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 1821 #define AVM_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 1822 #define AVM_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 1823 #define AVM_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 1824 #define AVM_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 1825 #define AVM_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 1826 #define AVM_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 1827 #define AVM_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 1828 #define AVM_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 1829 #define AVM_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 1830 #define AVM_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 1831 #define AVM_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 1832 #define AVM_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 1833 #define AVM_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 1834 #define AVM_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 1835 #define AVM_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 1836 #define AVM_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 1837 #define AVM_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 1838 #define AVM_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 1839 #define AVM_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 1840 #define AVM_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 1841 #define AVM_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 1842 #define AVM_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 1843 #define AVM_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 1844 #define AVM_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 1845 #define AVM_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 1846 #define AVM_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 1847 #define AVM_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 1848 #define AVM_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 1849 #define AVM_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 1850 #define AVM_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 1851 //CDEFE_SUVD_CGC_CTRL 1852 #define CDEFE_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 1853 #define CDEFE_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 1854 #define CDEFE_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 1855 #define CDEFE_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 1856 #define CDEFE_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 1857 #define CDEFE_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 1858 #define CDEFE_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 1859 #define CDEFE_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 1860 #define CDEFE_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 1861 #define CDEFE_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 1862 #define CDEFE_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 1863 #define CDEFE_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 1864 #define CDEFE_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 1865 #define CDEFE_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 1866 #define CDEFE_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 1867 #define CDEFE_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 1868 #define CDEFE_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 1869 #define CDEFE_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 1870 #define CDEFE_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 1871 #define CDEFE_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 1872 #define CDEFE_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 1873 #define CDEFE_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 1874 #define CDEFE_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 1875 #define CDEFE_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 1876 #define CDEFE_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 1877 #define CDEFE_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 1878 #define CDEFE_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 1879 #define CDEFE_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 1880 #define CDEFE_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 1881 #define CDEFE_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 1882 #define CDEFE_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 1883 #define CDEFE_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 1884 #define CDEFE_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 1885 #define CDEFE_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 1886 #define CDEFE_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 1887 #define CDEFE_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 1888 #define CDEFE_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 1889 #define CDEFE_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 1890 #define CDEFE_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 1891 #define CDEFE_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 1892 #define CDEFE_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 1893 #define CDEFE_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 1894 #define CDEFE_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 1895 #define CDEFE_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 1896 #define CDEFE_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 1897 #define CDEFE_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 1898 #define CDEFE_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 1899 #define CDEFE_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 1900 #define CDEFE_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 1901 #define CDEFE_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 1902 #define CDEFE_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 1903 #define CDEFE_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 1904 //DBR_SUVD_CGC_CTRL 1905 #define DBR_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 1906 #define DBR_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 1907 #define DBR_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 1908 #define DBR_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 1909 #define DBR_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 1910 #define DBR_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 1911 #define DBR_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 1912 #define DBR_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 1913 #define DBR_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 1914 #define DBR_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 1915 #define DBR_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 1916 #define DBR_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 1917 #define DBR_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 1918 #define DBR_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 1919 #define DBR_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 1920 #define DBR_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 1921 #define DBR_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 1922 #define DBR_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 1923 #define DBR_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 1924 #define DBR_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 1925 #define DBR_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 1926 #define DBR_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 1927 #define DBR_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 1928 #define DBR_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 1929 #define DBR_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 1930 #define DBR_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 1931 #define DBR_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 1932 #define DBR_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 1933 #define DBR_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 1934 #define DBR_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 1935 #define DBR_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 1936 #define DBR_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 1937 #define DBR_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 1938 #define DBR_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 1939 #define DBR_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 1940 #define DBR_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 1941 #define DBR_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 1942 #define DBR_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 1943 #define DBR_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 1944 #define DBR_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 1945 #define DBR_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 1946 #define DBR_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 1947 #define DBR_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 1948 #define DBR_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 1949 #define DBR_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 1950 #define DBR_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 1951 #define DBR_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 1952 #define DBR_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 1953 #define DBR_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 1954 #define DBR_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 1955 #define DBR_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 1956 #define DBR_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 1957 //EFC_SUVD_CGC_CTRL 1958 #define EFC_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 1959 #define EFC_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 1960 #define EFC_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 1961 #define EFC_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 1962 #define EFC_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 1963 #define EFC_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 1964 #define EFC_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 1965 #define EFC_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 1966 #define EFC_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 1967 #define EFC_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 1968 #define EFC_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 1969 #define EFC_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 1970 #define EFC_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 1971 #define EFC_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 1972 #define EFC_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 1973 #define EFC_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 1974 #define EFC_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 1975 #define EFC_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 1976 #define EFC_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 1977 #define EFC_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 1978 #define EFC_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 1979 #define EFC_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 1980 #define EFC_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 1981 #define EFC_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 1982 #define EFC_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 1983 #define EFC_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 1984 #define EFC_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 1985 #define EFC_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 1986 #define EFC_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 1987 #define EFC_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 1988 #define EFC_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 1989 #define EFC_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 1990 #define EFC_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 1991 #define EFC_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 1992 #define EFC_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 1993 #define EFC_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 1994 #define EFC_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 1995 #define EFC_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 1996 #define EFC_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 1997 #define EFC_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 1998 #define EFC_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 1999 #define EFC_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 2000 #define EFC_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 2001 #define EFC_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 2002 #define EFC_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 2003 #define EFC_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 2004 #define EFC_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 2005 #define EFC_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 2006 #define EFC_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 2007 #define EFC_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 2008 #define EFC_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 2009 #define EFC_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 2010 //ENT_SUVD_CGC_CTRL 2011 #define ENT_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 2012 #define ENT_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 2013 #define ENT_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 2014 #define ENT_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 2015 #define ENT_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 2016 #define ENT_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 2017 #define ENT_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 2018 #define ENT_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 2019 #define ENT_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 2020 #define ENT_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 2021 #define ENT_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 2022 #define ENT_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 2023 #define ENT_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 2024 #define ENT_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 2025 #define ENT_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 2026 #define ENT_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 2027 #define ENT_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 2028 #define ENT_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 2029 #define ENT_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 2030 #define ENT_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 2031 #define ENT_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 2032 #define ENT_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 2033 #define ENT_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 2034 #define ENT_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 2035 #define ENT_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 2036 #define ENT_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 2037 #define ENT_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 2038 #define ENT_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 2039 #define ENT_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 2040 #define ENT_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 2041 #define ENT_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 2042 #define ENT_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 2043 #define ENT_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 2044 #define ENT_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 2045 #define ENT_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 2046 #define ENT_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 2047 #define ENT_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 2048 #define ENT_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 2049 #define ENT_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 2050 #define ENT_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 2051 #define ENT_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 2052 #define ENT_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 2053 #define ENT_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 2054 #define ENT_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 2055 #define ENT_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 2056 #define ENT_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 2057 #define ENT_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 2058 #define ENT_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 2059 #define ENT_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 2060 #define ENT_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 2061 #define ENT_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 2062 #define ENT_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 2063 //IME_SUVD_CGC_CTRL 2064 #define IME_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 2065 #define IME_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 2066 #define IME_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 2067 #define IME_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 2068 #define IME_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 2069 #define IME_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 2070 #define IME_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 2071 #define IME_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 2072 #define IME_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 2073 #define IME_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 2074 #define IME_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 2075 #define IME_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 2076 #define IME_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 2077 #define IME_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 2078 #define IME_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 2079 #define IME_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 2080 #define IME_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 2081 #define IME_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 2082 #define IME_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 2083 #define IME_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 2084 #define IME_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 2085 #define IME_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 2086 #define IME_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 2087 #define IME_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 2088 #define IME_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 2089 #define IME_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 2090 #define IME_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 2091 #define IME_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 2092 #define IME_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 2093 #define IME_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 2094 #define IME_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 2095 #define IME_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 2096 #define IME_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 2097 #define IME_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 2098 #define IME_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 2099 #define IME_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 2100 #define IME_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 2101 #define IME_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 2102 #define IME_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 2103 #define IME_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 2104 #define IME_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 2105 #define IME_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 2106 #define IME_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 2107 #define IME_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 2108 #define IME_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 2109 #define IME_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 2110 #define IME_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 2111 #define IME_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 2112 #define IME_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 2113 #define IME_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 2114 #define IME_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 2115 #define IME_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 2116 //MPC1_SUVD_CGC_CTRL 2117 #define MPC1_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 2118 #define MPC1_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 2119 #define MPC1_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 2120 #define MPC1_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 2121 #define MPC1_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 2122 #define MPC1_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 2123 #define MPC1_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 2124 #define MPC1_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 2125 #define MPC1_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 2126 #define MPC1_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 2127 #define MPC1_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 2128 #define MPC1_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 2129 #define MPC1_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 2130 #define MPC1_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 2131 #define MPC1_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 2132 #define MPC1_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 2133 #define MPC1_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 2134 #define MPC1_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 2135 #define MPC1_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 2136 #define MPC1_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 2137 #define MPC1_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 2138 #define MPC1_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 2139 #define MPC1_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 2140 #define MPC1_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 2141 #define MPC1_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 2142 #define MPC1_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 2143 #define MPC1_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 2144 #define MPC1_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 2145 #define MPC1_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 2146 #define MPC1_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 2147 #define MPC1_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 2148 #define MPC1_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 2149 #define MPC1_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 2150 #define MPC1_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 2151 #define MPC1_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 2152 #define MPC1_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 2153 #define MPC1_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 2154 #define MPC1_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 2155 #define MPC1_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 2156 #define MPC1_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 2157 #define MPC1_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 2158 #define MPC1_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 2159 #define MPC1_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 2160 #define MPC1_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 2161 #define MPC1_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 2162 #define MPC1_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 2163 #define MPC1_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 2164 #define MPC1_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 2165 #define MPC1_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 2166 #define MPC1_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 2167 #define MPC1_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 2168 #define MPC1_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 2169 //PPU_SUVD_CGC_CTRL 2170 #define PPU_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 2171 #define PPU_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 2172 #define PPU_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 2173 #define PPU_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 2174 #define PPU_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 2175 #define PPU_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 2176 #define PPU_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 2177 #define PPU_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 2178 #define PPU_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 2179 #define PPU_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 2180 #define PPU_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 2181 #define PPU_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 2182 #define PPU_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 2183 #define PPU_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 2184 #define PPU_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 2185 #define PPU_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 2186 #define PPU_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 2187 #define PPU_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 2188 #define PPU_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 2189 #define PPU_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 2190 #define PPU_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 2191 #define PPU_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 2192 #define PPU_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 2193 #define PPU_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 2194 #define PPU_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 2195 #define PPU_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 2196 #define PPU_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 2197 #define PPU_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 2198 #define PPU_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 2199 #define PPU_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 2200 #define PPU_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 2201 #define PPU_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 2202 #define PPU_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 2203 #define PPU_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 2204 #define PPU_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 2205 #define PPU_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 2206 #define PPU_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 2207 #define PPU_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 2208 #define PPU_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 2209 #define PPU_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 2210 #define PPU_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 2211 #define PPU_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 2212 #define PPU_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 2213 #define PPU_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 2214 #define PPU_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 2215 #define PPU_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 2216 #define PPU_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 2217 #define PPU_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 2218 #define PPU_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 2219 #define PPU_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 2220 #define PPU_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 2221 #define PPU_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 2222 //SAOE_SUVD_CGC_CTRL 2223 #define SAOE_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 2224 #define SAOE_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 2225 #define SAOE_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 2226 #define SAOE_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 2227 #define SAOE_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 2228 #define SAOE_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 2229 #define SAOE_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 2230 #define SAOE_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 2231 #define SAOE_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 2232 #define SAOE_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 2233 #define SAOE_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 2234 #define SAOE_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 2235 #define SAOE_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 2236 #define SAOE_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 2237 #define SAOE_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 2238 #define SAOE_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 2239 #define SAOE_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 2240 #define SAOE_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 2241 #define SAOE_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 2242 #define SAOE_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 2243 #define SAOE_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 2244 #define SAOE_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 2245 #define SAOE_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 2246 #define SAOE_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 2247 #define SAOE_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 2248 #define SAOE_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 2249 #define SAOE_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 2250 #define SAOE_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 2251 #define SAOE_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 2252 #define SAOE_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 2253 #define SAOE_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 2254 #define SAOE_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 2255 #define SAOE_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 2256 #define SAOE_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 2257 #define SAOE_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 2258 #define SAOE_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 2259 #define SAOE_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 2260 #define SAOE_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 2261 #define SAOE_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 2262 #define SAOE_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 2263 #define SAOE_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 2264 #define SAOE_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 2265 #define SAOE_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 2266 #define SAOE_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 2267 #define SAOE_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 2268 #define SAOE_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 2269 #define SAOE_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 2270 #define SAOE_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 2271 #define SAOE_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 2272 #define SAOE_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 2273 #define SAOE_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 2274 #define SAOE_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 2275 //SCM_SUVD_CGC_CTRL 2276 #define SCM_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 2277 #define SCM_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 2278 #define SCM_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 2279 #define SCM_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 2280 #define SCM_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 2281 #define SCM_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 2282 #define SCM_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 2283 #define SCM_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 2284 #define SCM_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 2285 #define SCM_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 2286 #define SCM_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 2287 #define SCM_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 2288 #define SCM_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 2289 #define SCM_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 2290 #define SCM_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 2291 #define SCM_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 2292 #define SCM_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 2293 #define SCM_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 2294 #define SCM_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 2295 #define SCM_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 2296 #define SCM_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 2297 #define SCM_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 2298 #define SCM_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 2299 #define SCM_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 2300 #define SCM_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 2301 #define SCM_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 2302 #define SCM_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 2303 #define SCM_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 2304 #define SCM_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 2305 #define SCM_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 2306 #define SCM_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 2307 #define SCM_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 2308 #define SCM_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 2309 #define SCM_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 2310 #define SCM_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 2311 #define SCM_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 2312 #define SCM_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 2313 #define SCM_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 2314 #define SCM_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 2315 #define SCM_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 2316 #define SCM_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 2317 #define SCM_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 2318 #define SCM_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 2319 #define SCM_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 2320 #define SCM_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 2321 #define SCM_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 2322 #define SCM_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 2323 #define SCM_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 2324 #define SCM_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 2325 #define SCM_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 2326 #define SCM_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 2327 #define SCM_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 2328 //SDB_SUVD_CGC_CTRL 2329 #define SDB_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 2330 #define SDB_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 2331 #define SDB_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 2332 #define SDB_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 2333 #define SDB_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 2334 #define SDB_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 2335 #define SDB_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 2336 #define SDB_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 2337 #define SDB_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 2338 #define SDB_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 2339 #define SDB_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 2340 #define SDB_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 2341 #define SDB_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 2342 #define SDB_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 2343 #define SDB_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 2344 #define SDB_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 2345 #define SDB_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 2346 #define SDB_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 2347 #define SDB_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 2348 #define SDB_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 2349 #define SDB_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 2350 #define SDB_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 2351 #define SDB_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 2352 #define SDB_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 2353 #define SDB_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 2354 #define SDB_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 2355 #define SDB_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 2356 #define SDB_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 2357 #define SDB_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 2358 #define SDB_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 2359 #define SDB_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 2360 #define SDB_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 2361 #define SDB_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 2362 #define SDB_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 2363 #define SDB_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 2364 #define SDB_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 2365 #define SDB_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 2366 #define SDB_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 2367 #define SDB_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 2368 #define SDB_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 2369 #define SDB_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 2370 #define SDB_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 2371 #define SDB_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 2372 #define SDB_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 2373 #define SDB_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 2374 #define SDB_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 2375 #define SDB_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 2376 #define SDB_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 2377 #define SDB_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 2378 #define SDB_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 2379 #define SDB_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 2380 #define SDB_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 2381 //SIT0_NXT_SUVD_CGC_CTRL 2382 #define SIT0_NXT_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 2383 #define SIT0_NXT_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 2384 #define SIT0_NXT_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 2385 #define SIT0_NXT_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 2386 #define SIT0_NXT_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 2387 #define SIT0_NXT_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 2388 #define SIT0_NXT_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 2389 #define SIT0_NXT_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 2390 #define SIT0_NXT_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 2391 #define SIT0_NXT_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 2392 #define SIT0_NXT_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 2393 #define SIT0_NXT_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 2394 #define SIT0_NXT_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 2395 #define SIT0_NXT_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 2396 #define SIT0_NXT_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 2397 #define SIT0_NXT_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 2398 #define SIT0_NXT_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 2399 #define SIT0_NXT_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 2400 #define SIT0_NXT_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 2401 #define SIT0_NXT_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 2402 #define SIT0_NXT_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 2403 #define SIT0_NXT_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 2404 #define SIT0_NXT_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 2405 #define SIT0_NXT_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 2406 #define SIT0_NXT_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 2407 #define SIT0_NXT_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 2408 #define SIT0_NXT_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 2409 #define SIT0_NXT_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 2410 #define SIT0_NXT_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 2411 #define SIT0_NXT_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 2412 #define SIT0_NXT_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 2413 #define SIT0_NXT_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 2414 #define SIT0_NXT_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 2415 #define SIT0_NXT_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 2416 #define SIT0_NXT_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 2417 #define SIT0_NXT_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 2418 #define SIT0_NXT_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 2419 #define SIT0_NXT_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 2420 #define SIT0_NXT_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 2421 #define SIT0_NXT_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 2422 #define SIT0_NXT_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 2423 #define SIT0_NXT_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 2424 #define SIT0_NXT_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 2425 #define SIT0_NXT_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 2426 #define SIT0_NXT_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 2427 #define SIT0_NXT_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 2428 #define SIT0_NXT_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 2429 #define SIT0_NXT_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 2430 #define SIT0_NXT_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 2431 #define SIT0_NXT_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 2432 #define SIT0_NXT_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 2433 #define SIT0_NXT_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 2434 //SIT1_NXT_SUVD_CGC_CTRL 2435 #define SIT1_NXT_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 2436 #define SIT1_NXT_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 2437 #define SIT1_NXT_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 2438 #define SIT1_NXT_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 2439 #define SIT1_NXT_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 2440 #define SIT1_NXT_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 2441 #define SIT1_NXT_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 2442 #define SIT1_NXT_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 2443 #define SIT1_NXT_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 2444 #define SIT1_NXT_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 2445 #define SIT1_NXT_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 2446 #define SIT1_NXT_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 2447 #define SIT1_NXT_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 2448 #define SIT1_NXT_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 2449 #define SIT1_NXT_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 2450 #define SIT1_NXT_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 2451 #define SIT1_NXT_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 2452 #define SIT1_NXT_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 2453 #define SIT1_NXT_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 2454 #define SIT1_NXT_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 2455 #define SIT1_NXT_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 2456 #define SIT1_NXT_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 2457 #define SIT1_NXT_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 2458 #define SIT1_NXT_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 2459 #define SIT1_NXT_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 2460 #define SIT1_NXT_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 2461 #define SIT1_NXT_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 2462 #define SIT1_NXT_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 2463 #define SIT1_NXT_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 2464 #define SIT1_NXT_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 2465 #define SIT1_NXT_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 2466 #define SIT1_NXT_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 2467 #define SIT1_NXT_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 2468 #define SIT1_NXT_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 2469 #define SIT1_NXT_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 2470 #define SIT1_NXT_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 2471 #define SIT1_NXT_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 2472 #define SIT1_NXT_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 2473 #define SIT1_NXT_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 2474 #define SIT1_NXT_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 2475 #define SIT1_NXT_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 2476 #define SIT1_NXT_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 2477 #define SIT1_NXT_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 2478 #define SIT1_NXT_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 2479 #define SIT1_NXT_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 2480 #define SIT1_NXT_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 2481 #define SIT1_NXT_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 2482 #define SIT1_NXT_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 2483 #define SIT1_NXT_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 2484 #define SIT1_NXT_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 2485 #define SIT1_NXT_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 2486 #define SIT1_NXT_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 2487 //SIT2_NXT_SUVD_CGC_CTRL 2488 #define SIT2_NXT_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 2489 #define SIT2_NXT_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 2490 #define SIT2_NXT_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 2491 #define SIT2_NXT_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 2492 #define SIT2_NXT_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 2493 #define SIT2_NXT_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 2494 #define SIT2_NXT_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 2495 #define SIT2_NXT_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 2496 #define SIT2_NXT_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 2497 #define SIT2_NXT_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 2498 #define SIT2_NXT_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 2499 #define SIT2_NXT_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 2500 #define SIT2_NXT_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 2501 #define SIT2_NXT_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 2502 #define SIT2_NXT_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 2503 #define SIT2_NXT_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 2504 #define SIT2_NXT_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 2505 #define SIT2_NXT_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 2506 #define SIT2_NXT_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 2507 #define SIT2_NXT_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 2508 #define SIT2_NXT_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 2509 #define SIT2_NXT_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 2510 #define SIT2_NXT_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 2511 #define SIT2_NXT_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 2512 #define SIT2_NXT_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 2513 #define SIT2_NXT_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 2514 #define SIT2_NXT_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 2515 #define SIT2_NXT_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 2516 #define SIT2_NXT_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 2517 #define SIT2_NXT_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 2518 #define SIT2_NXT_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 2519 #define SIT2_NXT_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 2520 #define SIT2_NXT_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 2521 #define SIT2_NXT_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 2522 #define SIT2_NXT_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 2523 #define SIT2_NXT_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 2524 #define SIT2_NXT_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 2525 #define SIT2_NXT_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 2526 #define SIT2_NXT_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 2527 #define SIT2_NXT_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 2528 #define SIT2_NXT_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 2529 #define SIT2_NXT_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 2530 #define SIT2_NXT_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 2531 #define SIT2_NXT_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 2532 #define SIT2_NXT_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 2533 #define SIT2_NXT_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 2534 #define SIT2_NXT_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 2535 #define SIT2_NXT_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 2536 #define SIT2_NXT_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 2537 #define SIT2_NXT_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 2538 #define SIT2_NXT_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 2539 #define SIT2_NXT_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 2540 //SIT_SUVD_CGC_CTRL 2541 #define SIT_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 2542 #define SIT_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 2543 #define SIT_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 2544 #define SIT_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 2545 #define SIT_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 2546 #define SIT_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 2547 #define SIT_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 2548 #define SIT_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 2549 #define SIT_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 2550 #define SIT_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 2551 #define SIT_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 2552 #define SIT_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 2553 #define SIT_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 2554 #define SIT_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 2555 #define SIT_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 2556 #define SIT_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 2557 #define SIT_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 2558 #define SIT_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 2559 #define SIT_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 2560 #define SIT_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 2561 #define SIT_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 2562 #define SIT_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 2563 #define SIT_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 2564 #define SIT_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 2565 #define SIT_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 2566 #define SIT_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 2567 #define SIT_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 2568 #define SIT_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 2569 #define SIT_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 2570 #define SIT_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 2571 #define SIT_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 2572 #define SIT_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 2573 #define SIT_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 2574 #define SIT_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 2575 #define SIT_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 2576 #define SIT_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 2577 #define SIT_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 2578 #define SIT_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 2579 #define SIT_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 2580 #define SIT_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 2581 #define SIT_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 2582 #define SIT_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 2583 #define SIT_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 2584 #define SIT_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 2585 #define SIT_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 2586 #define SIT_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 2587 #define SIT_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 2588 #define SIT_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 2589 #define SIT_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 2590 #define SIT_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 2591 #define SIT_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 2592 #define SIT_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 2593 //SMPA_SUVD_CGC_CTRL 2594 #define SMPA_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 2595 #define SMPA_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 2596 #define SMPA_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 2597 #define SMPA_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 2598 #define SMPA_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 2599 #define SMPA_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 2600 #define SMPA_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 2601 #define SMPA_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 2602 #define SMPA_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 2603 #define SMPA_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 2604 #define SMPA_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 2605 #define SMPA_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 2606 #define SMPA_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 2607 #define SMPA_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 2608 #define SMPA_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 2609 #define SMPA_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 2610 #define SMPA_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 2611 #define SMPA_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 2612 #define SMPA_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 2613 #define SMPA_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 2614 #define SMPA_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 2615 #define SMPA_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 2616 #define SMPA_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 2617 #define SMPA_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 2618 #define SMPA_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 2619 #define SMPA_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 2620 #define SMPA_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 2621 #define SMPA_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 2622 #define SMPA_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 2623 #define SMPA_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 2624 #define SMPA_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 2625 #define SMPA_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 2626 #define SMPA_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 2627 #define SMPA_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 2628 #define SMPA_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 2629 #define SMPA_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 2630 #define SMPA_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 2631 #define SMPA_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 2632 #define SMPA_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 2633 #define SMPA_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 2634 #define SMPA_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 2635 #define SMPA_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 2636 #define SMPA_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 2637 #define SMPA_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 2638 #define SMPA_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 2639 #define SMPA_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 2640 #define SMPA_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 2641 #define SMPA_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 2642 #define SMPA_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 2643 #define SMPA_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 2644 #define SMPA_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 2645 #define SMPA_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 2646 //SMP_SUVD_CGC_CTRL 2647 #define SMP_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 2648 #define SMP_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 2649 #define SMP_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 2650 #define SMP_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 2651 #define SMP_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 2652 #define SMP_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 2653 #define SMP_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 2654 #define SMP_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 2655 #define SMP_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 2656 #define SMP_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 2657 #define SMP_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 2658 #define SMP_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 2659 #define SMP_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 2660 #define SMP_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 2661 #define SMP_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 2662 #define SMP_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 2663 #define SMP_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 2664 #define SMP_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 2665 #define SMP_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 2666 #define SMP_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 2667 #define SMP_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 2668 #define SMP_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 2669 #define SMP_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 2670 #define SMP_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 2671 #define SMP_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 2672 #define SMP_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 2673 #define SMP_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 2674 #define SMP_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 2675 #define SMP_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 2676 #define SMP_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 2677 #define SMP_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 2678 #define SMP_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 2679 #define SMP_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 2680 #define SMP_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 2681 #define SMP_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 2682 #define SMP_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 2683 #define SMP_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 2684 #define SMP_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 2685 #define SMP_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 2686 #define SMP_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 2687 #define SMP_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 2688 #define SMP_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 2689 #define SMP_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 2690 #define SMP_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 2691 #define SMP_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 2692 #define SMP_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 2693 #define SMP_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 2694 #define SMP_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 2695 #define SMP_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 2696 #define SMP_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 2697 #define SMP_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 2698 #define SMP_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 2699 //SRE_SUVD_CGC_CTRL 2700 #define SRE_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 2701 #define SRE_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 2702 #define SRE_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 2703 #define SRE_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 2704 #define SRE_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 2705 #define SRE_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 2706 #define SRE_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 2707 #define SRE_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 2708 #define SRE_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 2709 #define SRE_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 2710 #define SRE_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 2711 #define SRE_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 2712 #define SRE_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 2713 #define SRE_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 2714 #define SRE_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 2715 #define SRE_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 2716 #define SRE_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 2717 #define SRE_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 2718 #define SRE_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 2719 #define SRE_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 2720 #define SRE_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 2721 #define SRE_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 2722 #define SRE_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 2723 #define SRE_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 2724 #define SRE_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 2725 #define SRE_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 2726 #define SRE_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 2727 #define SRE_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 2728 #define SRE_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 2729 #define SRE_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 2730 #define SRE_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 2731 #define SRE_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 2732 #define SRE_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 2733 #define SRE_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 2734 #define SRE_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 2735 #define SRE_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 2736 #define SRE_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 2737 #define SRE_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 2738 #define SRE_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 2739 #define SRE_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 2740 #define SRE_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 2741 #define SRE_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 2742 #define SRE_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 2743 #define SRE_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 2744 #define SRE_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 2745 #define SRE_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 2746 #define SRE_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 2747 #define SRE_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 2748 #define SRE_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 2749 #define SRE_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 2750 #define SRE_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 2751 #define SRE_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 2752 //UVD_MPBE0_SUVD_CGC_CTRL 2753 #define UVD_MPBE0_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 2754 #define UVD_MPBE0_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 2755 #define UVD_MPBE0_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 2756 #define UVD_MPBE0_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 2757 #define UVD_MPBE0_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 2758 #define UVD_MPBE0_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 2759 #define UVD_MPBE0_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 2760 #define UVD_MPBE0_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 2761 #define UVD_MPBE0_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 2762 #define UVD_MPBE0_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 2763 #define UVD_MPBE0_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 2764 #define UVD_MPBE0_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 2765 #define UVD_MPBE0_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 2766 #define UVD_MPBE0_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 2767 #define UVD_MPBE0_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 2768 #define UVD_MPBE0_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 2769 #define UVD_MPBE0_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 2770 #define UVD_MPBE0_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 2771 #define UVD_MPBE0_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 2772 #define UVD_MPBE0_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 2773 #define UVD_MPBE0_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 2774 #define UVD_MPBE0_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 2775 #define UVD_MPBE0_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 2776 #define UVD_MPBE0_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 2777 #define UVD_MPBE0_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 2778 #define UVD_MPBE0_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 2779 #define UVD_MPBE0_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 2780 #define UVD_MPBE0_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 2781 #define UVD_MPBE0_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 2782 #define UVD_MPBE0_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 2783 #define UVD_MPBE0_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 2784 #define UVD_MPBE0_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 2785 #define UVD_MPBE0_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 2786 #define UVD_MPBE0_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 2787 #define UVD_MPBE0_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 2788 #define UVD_MPBE0_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 2789 #define UVD_MPBE0_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 2790 #define UVD_MPBE0_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 2791 #define UVD_MPBE0_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 2792 #define UVD_MPBE0_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 2793 #define UVD_MPBE0_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 2794 #define UVD_MPBE0_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 2795 //UVD_MPBE1_SUVD_CGC_CTRL 2796 #define UVD_MPBE1_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 2797 #define UVD_MPBE1_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 2798 #define UVD_MPBE1_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 2799 #define UVD_MPBE1_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 2800 #define UVD_MPBE1_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 2801 #define UVD_MPBE1_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 2802 #define UVD_MPBE1_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 2803 #define UVD_MPBE1_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 2804 #define UVD_MPBE1_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 2805 #define UVD_MPBE1_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 2806 #define UVD_MPBE1_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 2807 #define UVD_MPBE1_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 2808 #define UVD_MPBE1_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 2809 #define UVD_MPBE1_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 2810 #define UVD_MPBE1_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 2811 #define UVD_MPBE1_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 2812 #define UVD_MPBE1_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 2813 #define UVD_MPBE1_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 2814 #define UVD_MPBE1_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 2815 #define UVD_MPBE1_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 2816 #define UVD_MPBE1_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 2817 #define UVD_MPBE1_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 2818 #define UVD_MPBE1_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 2819 #define UVD_MPBE1_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 2820 #define UVD_MPBE1_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 2821 #define UVD_MPBE1_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 2822 #define UVD_MPBE1_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 2823 #define UVD_MPBE1_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 2824 #define UVD_MPBE1_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 2825 #define UVD_MPBE1_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 2826 #define UVD_MPBE1_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 2827 #define UVD_MPBE1_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 2828 #define UVD_MPBE1_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 2829 #define UVD_MPBE1_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 2830 #define UVD_MPBE1_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 2831 #define UVD_MPBE1_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 2832 #define UVD_MPBE1_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 2833 #define UVD_MPBE1_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 2834 #define UVD_MPBE1_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 2835 #define UVD_MPBE1_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 2836 #define UVD_MPBE1_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 2837 #define UVD_MPBE1_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 2838 //UVD_SUVD_CGC_CTRL 2839 #define UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 2840 #define UVD_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 2841 #define UVD_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 2842 #define UVD_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 2843 #define UVD_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 2844 #define UVD_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 2845 #define UVD_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 2846 #define UVD_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 2847 #define UVD_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 2848 #define UVD_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 2849 #define UVD_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 2850 #define UVD_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb 2851 #define UVD_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc 2852 #define UVD_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd 2853 #define UVD_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe 2854 #define UVD_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf 2855 #define UVD_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 2856 #define UVD_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 2857 #define UVD_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 2858 #define UVD_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 2859 #define UVD_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 2860 #define UVD_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 2861 #define UVD_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 2862 #define UVD_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c 2863 #define UVD_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d 2864 #define UVD_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e 2865 #define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 2866 #define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 2867 #define UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 2868 #define UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 2869 #define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 2870 #define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 2871 #define UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 2872 #define UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 2873 #define UVD_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 2874 #define UVD_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 2875 #define UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 2876 #define UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L 2877 #define UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L 2878 #define UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L 2879 #define UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L 2880 #define UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L 2881 #define UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L 2882 #define UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L 2883 #define UVD_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L 2884 #define UVD_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L 2885 #define UVD_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L 2886 #define UVD_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L 2887 #define UVD_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L 2888 #define UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L 2889 #define UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L 2890 #define UVD_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L 2891 //UVD_CGC_CTRL3 2892 #define UVD_CGC_CTRL3__CGC_CLK_OFF_DELAY__SHIFT 0x0 2893 #define UVD_CGC_CTRL3__LCM0_MODE__SHIFT 0xb 2894 #define UVD_CGC_CTRL3__LCM1_MODE__SHIFT 0xc 2895 #define UVD_CGC_CTRL3__MIF_MODE__SHIFT 0xd 2896 #define UVD_CGC_CTRL3__VREG_MODE__SHIFT 0xe 2897 #define UVD_CGC_CTRL3__PE_MODE__SHIFT 0xf 2898 #define UVD_CGC_CTRL3__PPU_MODE__SHIFT 0x10 2899 #define UVD_CGC_CTRL3__CGC_CLK_OFF_DELAY_MASK 0x000000FFL 2900 #define UVD_CGC_CTRL3__LCM0_MODE_MASK 0x00000800L 2901 #define UVD_CGC_CTRL3__LCM1_MODE_MASK 0x00001000L 2902 #define UVD_CGC_CTRL3__MIF_MODE_MASK 0x00002000L 2903 #define UVD_CGC_CTRL3__VREG_MODE_MASK 0x00004000L 2904 #define UVD_CGC_CTRL3__PE_MODE_MASK 0x00008000L 2905 #define UVD_CGC_CTRL3__PPU_MODE_MASK 0x00010000L 2906 //UVD_GPCOM_VCPU_DATA0 2907 #define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x0 2908 #define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xFFFFFFFFL 2909 //UVD_GPCOM_VCPU_DATA1 2910 #define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0 2911 #define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xFFFFFFFFL 2912 //UVD_GPCOM_SYS_CMD 2913 #define UVD_GPCOM_SYS_CMD__CMD_SEND__SHIFT 0x0 2914 #define UVD_GPCOM_SYS_CMD__CMD__SHIFT 0x1 2915 #define UVD_GPCOM_SYS_CMD__CMD_SOURCE__SHIFT 0x1f 2916 #define UVD_GPCOM_SYS_CMD__CMD_SEND_MASK 0x00000001L 2917 #define UVD_GPCOM_SYS_CMD__CMD_MASK 0x7FFFFFFEL 2918 #define UVD_GPCOM_SYS_CMD__CMD_SOURCE_MASK 0x80000000L 2919 //UVD_GPCOM_SYS_DATA0 2920 #define UVD_GPCOM_SYS_DATA0__DATA0__SHIFT 0x0 2921 #define UVD_GPCOM_SYS_DATA0__DATA0_MASK 0xFFFFFFFFL 2922 //UVD_GPCOM_SYS_DATA1 2923 #define UVD_GPCOM_SYS_DATA1__DATA1__SHIFT 0x0 2924 #define UVD_GPCOM_SYS_DATA1__DATA1_MASK 0xFFFFFFFFL 2925 //UVD_VCPU_INT_EN 2926 #define UVD_VCPU_INT_EN__PIF_ADDR_ERR_EN__SHIFT 0x0 2927 #define UVD_VCPU_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN__SHIFT 0x1 2928 #define UVD_VCPU_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN__SHIFT 0x2 2929 #define UVD_VCPU_INT_EN__NJ_PF_RPT_EN__SHIFT 0x3 2930 #define UVD_VCPU_INT_EN__SW_RB1_INT_EN__SHIFT 0x4 2931 #define UVD_VCPU_INT_EN__SW_RB2_INT_EN__SHIFT 0x5 2932 #define UVD_VCPU_INT_EN__RBC_REG_PRIV_FAULT_EN__SHIFT 0x6 2933 #define UVD_VCPU_INT_EN__SW_RB3_INT_EN__SHIFT 0x7 2934 #define UVD_VCPU_INT_EN__SW_RB4_INT_EN__SHIFT 0x9 2935 #define UVD_VCPU_INT_EN__SW_RB5_INT_EN__SHIFT 0xa 2936 #define UVD_VCPU_INT_EN__LBSI_EN__SHIFT 0xb 2937 #define UVD_VCPU_INT_EN__UDEC_EN__SHIFT 0xc 2938 #define UVD_VCPU_INT_EN__LMI_AXI_UNSUPPORTED_LEN_EN__SHIFT 0xd 2939 #define UVD_VCPU_INT_EN__LMI_AXI_UNSUPPORTED_ADR_ALIGN_EN__SHIFT 0xe 2940 #define UVD_VCPU_INT_EN__SUVD_EN__SHIFT 0xf 2941 #define UVD_VCPU_INT_EN__RPTR_WR_EN__SHIFT 0x10 2942 #define UVD_VCPU_INT_EN__JOB_START_EN__SHIFT 0x11 2943 #define UVD_VCPU_INT_EN__NJ_PF_EN__SHIFT 0x12 2944 #define UVD_VCPU_INT_EN__SEMA_WAIT_FAIL_SIG_EN__SHIFT 0x17 2945 #define UVD_VCPU_INT_EN__IDCT_EN__SHIFT 0x18 2946 #define UVD_VCPU_INT_EN__MPRD_EN__SHIFT 0x19 2947 #define UVD_VCPU_INT_EN__AVM_INT_EN__SHIFT 0x1a 2948 #define UVD_VCPU_INT_EN__CLK_SWT_EN__SHIFT 0x1b 2949 #define UVD_VCPU_INT_EN__MIF_HWINT_EN__SHIFT 0x1c 2950 #define UVD_VCPU_INT_EN__MPRD_ERR_EN__SHIFT 0x1d 2951 #define UVD_VCPU_INT_EN__DRV_FW_REQ_EN__SHIFT 0x1e 2952 #define UVD_VCPU_INT_EN__DRV_FW_ACK_EN__SHIFT 0x1f 2953 #define UVD_VCPU_INT_EN__PIF_ADDR_ERR_EN_MASK 0x00000001L 2954 #define UVD_VCPU_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN_MASK 0x00000002L 2955 #define UVD_VCPU_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN_MASK 0x00000004L 2956 #define UVD_VCPU_INT_EN__NJ_PF_RPT_EN_MASK 0x00000008L 2957 #define UVD_VCPU_INT_EN__SW_RB1_INT_EN_MASK 0x00000010L 2958 #define UVD_VCPU_INT_EN__SW_RB2_INT_EN_MASK 0x00000020L 2959 #define UVD_VCPU_INT_EN__RBC_REG_PRIV_FAULT_EN_MASK 0x00000040L 2960 #define UVD_VCPU_INT_EN__SW_RB3_INT_EN_MASK 0x00000080L 2961 #define UVD_VCPU_INT_EN__SW_RB4_INT_EN_MASK 0x00000200L 2962 #define UVD_VCPU_INT_EN__SW_RB5_INT_EN_MASK 0x00000400L 2963 #define UVD_VCPU_INT_EN__LBSI_EN_MASK 0x00000800L 2964 #define UVD_VCPU_INT_EN__UDEC_EN_MASK 0x00001000L 2965 #define UVD_VCPU_INT_EN__LMI_AXI_UNSUPPORTED_LEN_EN_MASK 0x00002000L 2966 #define UVD_VCPU_INT_EN__LMI_AXI_UNSUPPORTED_ADR_ALIGN_EN_MASK 0x00004000L 2967 #define UVD_VCPU_INT_EN__SUVD_EN_MASK 0x00008000L 2968 #define UVD_VCPU_INT_EN__RPTR_WR_EN_MASK 0x00010000L 2969 #define UVD_VCPU_INT_EN__JOB_START_EN_MASK 0x00020000L 2970 #define UVD_VCPU_INT_EN__NJ_PF_EN_MASK 0x00040000L 2971 #define UVD_VCPU_INT_EN__SEMA_WAIT_FAIL_SIG_EN_MASK 0x00800000L 2972 #define UVD_VCPU_INT_EN__IDCT_EN_MASK 0x01000000L 2973 #define UVD_VCPU_INT_EN__MPRD_EN_MASK 0x02000000L 2974 #define UVD_VCPU_INT_EN__AVM_INT_EN_MASK 0x04000000L 2975 #define UVD_VCPU_INT_EN__CLK_SWT_EN_MASK 0x08000000L 2976 #define UVD_VCPU_INT_EN__MIF_HWINT_EN_MASK 0x10000000L 2977 #define UVD_VCPU_INT_EN__MPRD_ERR_EN_MASK 0x20000000L 2978 #define UVD_VCPU_INT_EN__DRV_FW_REQ_EN_MASK 0x40000000L 2979 #define UVD_VCPU_INT_EN__DRV_FW_ACK_EN_MASK 0x80000000L 2980 //UVD_VCPU_INT_STATUS 2981 #define UVD_VCPU_INT_STATUS__PIF_ADDR_ERR_INT__SHIFT 0x0 2982 #define UVD_VCPU_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT__SHIFT 0x1 2983 #define UVD_VCPU_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT__SHIFT 0x2 2984 #define UVD_VCPU_INT_STATUS__NJ_PF_RPT_INT__SHIFT 0x3 2985 #define UVD_VCPU_INT_STATUS__SW_RB1_INT__SHIFT 0x4 2986 #define UVD_VCPU_INT_STATUS__SW_RB2_INT__SHIFT 0x5 2987 #define UVD_VCPU_INT_STATUS__RBC_REG_PRIV_FAULT_INT__SHIFT 0x6 2988 #define UVD_VCPU_INT_STATUS__SW_RB3_INT__SHIFT 0x7 2989 #define UVD_VCPU_INT_STATUS__SW_RB4_INT__SHIFT 0x9 2990 #define UVD_VCPU_INT_STATUS__SW_RB5_INT__SHIFT 0xa 2991 #define UVD_VCPU_INT_STATUS__LBSI_INT__SHIFT 0xb 2992 #define UVD_VCPU_INT_STATUS__UDEC_INT__SHIFT 0xc 2993 #define UVD_VCPU_INT_STATUS__LMI_AXI_UNSUPPORTED_LEN_INT__SHIFT 0xd 2994 #define UVD_VCPU_INT_STATUS__LMI_AXI_UNSUPPORTED_ADR_ALIGN_INT__SHIFT 0xe 2995 #define UVD_VCPU_INT_STATUS__SUVD_INT__SHIFT 0xf 2996 #define UVD_VCPU_INT_STATUS__RPTR_WR_INT__SHIFT 0x10 2997 #define UVD_VCPU_INT_STATUS__JOB_START_INT__SHIFT 0x11 2998 #define UVD_VCPU_INT_STATUS__NJ_PF_INT__SHIFT 0x12 2999 #define UVD_VCPU_INT_STATUS__GPCOM_INT__SHIFT 0x14 3000 #define UVD_VCPU_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT__SHIFT 0x17 3001 #define UVD_VCPU_INT_STATUS__IDCT_INT__SHIFT 0x18 3002 #define UVD_VCPU_INT_STATUS__MPRD_INT__SHIFT 0x19 3003 #define UVD_VCPU_INT_STATUS__AVM_INT__SHIFT 0x1a 3004 #define UVD_VCPU_INT_STATUS__CLK_SWT_INT__SHIFT 0x1b 3005 #define UVD_VCPU_INT_STATUS__MIF_HWINT__SHIFT 0x1c 3006 #define UVD_VCPU_INT_STATUS__MPRD_ERR_INT__SHIFT 0x1d 3007 #define UVD_VCPU_INT_STATUS__DRV_FW_REQ_INT__SHIFT 0x1e 3008 #define UVD_VCPU_INT_STATUS__DRV_FW_ACK_INT__SHIFT 0x1f 3009 #define UVD_VCPU_INT_STATUS__PIF_ADDR_ERR_INT_MASK 0x00000001L 3010 #define UVD_VCPU_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT_MASK 0x00000002L 3011 #define UVD_VCPU_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT_MASK 0x00000004L 3012 #define UVD_VCPU_INT_STATUS__NJ_PF_RPT_INT_MASK 0x00000008L 3013 #define UVD_VCPU_INT_STATUS__SW_RB1_INT_MASK 0x00000010L 3014 #define UVD_VCPU_INT_STATUS__SW_RB2_INT_MASK 0x00000020L 3015 #define UVD_VCPU_INT_STATUS__RBC_REG_PRIV_FAULT_INT_MASK 0x00000040L 3016 #define UVD_VCPU_INT_STATUS__SW_RB3_INT_MASK 0x00000080L 3017 #define UVD_VCPU_INT_STATUS__SW_RB4_INT_MASK 0x00000200L 3018 #define UVD_VCPU_INT_STATUS__SW_RB5_INT_MASK 0x00000400L 3019 #define UVD_VCPU_INT_STATUS__LBSI_INT_MASK 0x00000800L 3020 #define UVD_VCPU_INT_STATUS__UDEC_INT_MASK 0x00001000L 3021 #define UVD_VCPU_INT_STATUS__LMI_AXI_UNSUPPORTED_LEN_INT_MASK 0x00002000L 3022 #define UVD_VCPU_INT_STATUS__LMI_AXI_UNSUPPORTED_ADR_ALIGN_INT_MASK 0x00004000L 3023 #define UVD_VCPU_INT_STATUS__SUVD_INT_MASK 0x00008000L 3024 #define UVD_VCPU_INT_STATUS__RPTR_WR_INT_MASK 0x00010000L 3025 #define UVD_VCPU_INT_STATUS__JOB_START_INT_MASK 0x00020000L 3026 #define UVD_VCPU_INT_STATUS__NJ_PF_INT_MASK 0x00040000L 3027 #define UVD_VCPU_INT_STATUS__GPCOM_INT_MASK 0x00100000L 3028 #define UVD_VCPU_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT_MASK 0x00800000L 3029 #define UVD_VCPU_INT_STATUS__IDCT_INT_MASK 0x01000000L 3030 #define UVD_VCPU_INT_STATUS__MPRD_INT_MASK 0x02000000L 3031 #define UVD_VCPU_INT_STATUS__AVM_INT_MASK 0x04000000L 3032 #define UVD_VCPU_INT_STATUS__CLK_SWT_INT_MASK 0x08000000L 3033 #define UVD_VCPU_INT_STATUS__MIF_HWINT_MASK 0x10000000L 3034 #define UVD_VCPU_INT_STATUS__MPRD_ERR_INT_MASK 0x20000000L 3035 #define UVD_VCPU_INT_STATUS__DRV_FW_REQ_INT_MASK 0x40000000L 3036 #define UVD_VCPU_INT_STATUS__DRV_FW_ACK_INT_MASK 0x80000000L 3037 //UVD_VCPU_INT_ACK 3038 #define UVD_VCPU_INT_ACK__PIF_ADDR_ERR_ACK__SHIFT 0x0 3039 #define UVD_VCPU_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK__SHIFT 0x1 3040 #define UVD_VCPU_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK__SHIFT 0x2 3041 #define UVD_VCPU_INT_ACK__NJ_PF_RPT_ACK__SHIFT 0x3 3042 #define UVD_VCPU_INT_ACK__SW_RB1_INT_ACK__SHIFT 0x4 3043 #define UVD_VCPU_INT_ACK__SW_RB2_INT_ACK__SHIFT 0x5 3044 #define UVD_VCPU_INT_ACK__RBC_REG_PRIV_FAULT_ACK__SHIFT 0x6 3045 #define UVD_VCPU_INT_ACK__SW_RB3_INT_ACK__SHIFT 0x7 3046 #define UVD_VCPU_INT_ACK__SW_RB4_INT_ACK__SHIFT 0x9 3047 #define UVD_VCPU_INT_ACK__SW_RB5_INT_ACK__SHIFT 0xa 3048 #define UVD_VCPU_INT_ACK__LBSI_ACK__SHIFT 0xb 3049 #define UVD_VCPU_INT_ACK__UDEC_ACK__SHIFT 0xc 3050 #define UVD_VCPU_INT_ACK__LMI_AXI_UNSUPPORTED_LEN_ACK__SHIFT 0xd 3051 #define UVD_VCPU_INT_ACK__LMI_AXI_UNSUPPORTED_ADR_ALIGN_ACK__SHIFT 0xe 3052 #define UVD_VCPU_INT_ACK__SUVD_ACK__SHIFT 0xf 3053 #define UVD_VCPU_INT_ACK__RPTR_WR_ACK__SHIFT 0x10 3054 #define UVD_VCPU_INT_ACK__JOB_START_ACK__SHIFT 0x11 3055 #define UVD_VCPU_INT_ACK__NJ_PF_ACK__SHIFT 0x12 3056 #define UVD_VCPU_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK__SHIFT 0x17 3057 #define UVD_VCPU_INT_ACK__IDCT_ACK__SHIFT 0x18 3058 #define UVD_VCPU_INT_ACK__MPRD_ACK__SHIFT 0x19 3059 #define UVD_VCPU_INT_ACK__AVM_INT_ACK__SHIFT 0x1a 3060 #define UVD_VCPU_INT_ACK__CLK_SWT_ACK__SHIFT 0x1b 3061 #define UVD_VCPU_INT_ACK__MIF_HWINT_ACK__SHIFT 0x1c 3062 #define UVD_VCPU_INT_ACK__MPRD_ERR_ACK__SHIFT 0x1d 3063 #define UVD_VCPU_INT_ACK__DRV_FW_REQ_ACK__SHIFT 0x1e 3064 #define UVD_VCPU_INT_ACK__DRV_FW_ACK_ACK__SHIFT 0x1f 3065 #define UVD_VCPU_INT_ACK__PIF_ADDR_ERR_ACK_MASK 0x00000001L 3066 #define UVD_VCPU_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK_MASK 0x00000002L 3067 #define UVD_VCPU_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK_MASK 0x00000004L 3068 #define UVD_VCPU_INT_ACK__NJ_PF_RPT_ACK_MASK 0x00000008L 3069 #define UVD_VCPU_INT_ACK__SW_RB1_INT_ACK_MASK 0x00000010L 3070 #define UVD_VCPU_INT_ACK__SW_RB2_INT_ACK_MASK 0x00000020L 3071 #define UVD_VCPU_INT_ACK__RBC_REG_PRIV_FAULT_ACK_MASK 0x00000040L 3072 #define UVD_VCPU_INT_ACK__SW_RB3_INT_ACK_MASK 0x00000080L 3073 #define UVD_VCPU_INT_ACK__SW_RB4_INT_ACK_MASK 0x00000200L 3074 #define UVD_VCPU_INT_ACK__SW_RB5_INT_ACK_MASK 0x00000400L 3075 #define UVD_VCPU_INT_ACK__LBSI_ACK_MASK 0x00000800L 3076 #define UVD_VCPU_INT_ACK__UDEC_ACK_MASK 0x00001000L 3077 #define UVD_VCPU_INT_ACK__LMI_AXI_UNSUPPORTED_LEN_ACK_MASK 0x00002000L 3078 #define UVD_VCPU_INT_ACK__LMI_AXI_UNSUPPORTED_ADR_ALIGN_ACK_MASK 0x00004000L 3079 #define UVD_VCPU_INT_ACK__SUVD_ACK_MASK 0x00008000L 3080 #define UVD_VCPU_INT_ACK__RPTR_WR_ACK_MASK 0x00010000L 3081 #define UVD_VCPU_INT_ACK__JOB_START_ACK_MASK 0x00020000L 3082 #define UVD_VCPU_INT_ACK__NJ_PF_ACK_MASK 0x00040000L 3083 #define UVD_VCPU_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK_MASK 0x00800000L 3084 #define UVD_VCPU_INT_ACK__IDCT_ACK_MASK 0x01000000L 3085 #define UVD_VCPU_INT_ACK__MPRD_ACK_MASK 0x02000000L 3086 #define UVD_VCPU_INT_ACK__AVM_INT_ACK_MASK 0x04000000L 3087 #define UVD_VCPU_INT_ACK__CLK_SWT_ACK_MASK 0x08000000L 3088 #define UVD_VCPU_INT_ACK__MIF_HWINT_ACK_MASK 0x10000000L 3089 #define UVD_VCPU_INT_ACK__MPRD_ERR_ACK_MASK 0x20000000L 3090 #define UVD_VCPU_INT_ACK__DRV_FW_REQ_ACK_MASK 0x40000000L 3091 #define UVD_VCPU_INT_ACK__DRV_FW_ACK_ACK_MASK 0x80000000L 3092 //UVD_VCPU_INT_ROUTE 3093 #define UVD_VCPU_INT_ROUTE__DRV_FW_MSG__SHIFT 0x0 3094 #define UVD_VCPU_INT_ROUTE__FW_DRV_MSG_ACK__SHIFT 0x1 3095 #define UVD_VCPU_INT_ROUTE__VCPU_GPCOM__SHIFT 0x2 3096 #define UVD_VCPU_INT_ROUTE__DRV_FW_MSG_MASK 0x00000001L 3097 #define UVD_VCPU_INT_ROUTE__FW_DRV_MSG_ACK_MASK 0x00000002L 3098 #define UVD_VCPU_INT_ROUTE__VCPU_GPCOM_MASK 0x00000004L 3099 //UVD_DRV_FW_MSG 3100 #define UVD_DRV_FW_MSG__MSG__SHIFT 0x0 3101 #define UVD_DRV_FW_MSG__MSG_MASK 0xFFFFFFFFL 3102 //UVD_FW_DRV_MSG_ACK 3103 #define UVD_FW_DRV_MSG_ACK__ACK__SHIFT 0x0 3104 #define UVD_FW_DRV_MSG_ACK__ACK_MASK 0x00000001L 3105 //UVD_SUVD_INT_EN 3106 #define UVD_SUVD_INT_EN__SRE_FUNC_INT_EN__SHIFT 0x0 3107 #define UVD_SUVD_INT_EN__SRE_ERR_INT_EN__SHIFT 0x5 3108 #define UVD_SUVD_INT_EN__SIT_FUNC_INT_EN__SHIFT 0x6 3109 #define UVD_SUVD_INT_EN__SIT_ERR_INT_EN__SHIFT 0xb 3110 #define UVD_SUVD_INT_EN__SMP_FUNC_INT_EN__SHIFT 0xc 3111 #define UVD_SUVD_INT_EN__SMP_ERR_INT_EN__SHIFT 0x11 3112 #define UVD_SUVD_INT_EN__SCM_FUNC_INT_EN__SHIFT 0x12 3113 #define UVD_SUVD_INT_EN__SCM_ERR_INT_EN__SHIFT 0x17 3114 #define UVD_SUVD_INT_EN__SDB_FUNC_INT_EN__SHIFT 0x18 3115 #define UVD_SUVD_INT_EN__SDB_ERR_INT_EN__SHIFT 0x1d 3116 #define UVD_SUVD_INT_EN__FBC_ERR_INT_EN__SHIFT 0x1e 3117 #define UVD_SUVD_INT_EN__SRE_FUNC_INT_EN_MASK 0x0000001FL 3118 #define UVD_SUVD_INT_EN__SRE_ERR_INT_EN_MASK 0x00000020L 3119 #define UVD_SUVD_INT_EN__SIT_FUNC_INT_EN_MASK 0x000007C0L 3120 #define UVD_SUVD_INT_EN__SIT_ERR_INT_EN_MASK 0x00000800L 3121 #define UVD_SUVD_INT_EN__SMP_FUNC_INT_EN_MASK 0x0001F000L 3122 #define UVD_SUVD_INT_EN__SMP_ERR_INT_EN_MASK 0x00020000L 3123 #define UVD_SUVD_INT_EN__SCM_FUNC_INT_EN_MASK 0x007C0000L 3124 #define UVD_SUVD_INT_EN__SCM_ERR_INT_EN_MASK 0x00800000L 3125 #define UVD_SUVD_INT_EN__SDB_FUNC_INT_EN_MASK 0x1F000000L 3126 #define UVD_SUVD_INT_EN__SDB_ERR_INT_EN_MASK 0x20000000L 3127 #define UVD_SUVD_INT_EN__FBC_ERR_INT_EN_MASK 0x40000000L 3128 //UVD_SUVD_INT_STATUS 3129 #define UVD_SUVD_INT_STATUS__SRE_FUNC_INT__SHIFT 0x0 3130 #define UVD_SUVD_INT_STATUS__SRE_ERR_INT__SHIFT 0x5 3131 #define UVD_SUVD_INT_STATUS__SIT_FUNC_INT__SHIFT 0x6 3132 #define UVD_SUVD_INT_STATUS__SIT_ERR_INT__SHIFT 0xb 3133 #define UVD_SUVD_INT_STATUS__SMP_FUNC_INT__SHIFT 0xc 3134 #define UVD_SUVD_INT_STATUS__SMP_ERR_INT__SHIFT 0x11 3135 #define UVD_SUVD_INT_STATUS__SCM_FUNC_INT__SHIFT 0x12 3136 #define UVD_SUVD_INT_STATUS__SCM_ERR_INT__SHIFT 0x17 3137 #define UVD_SUVD_INT_STATUS__SDB_FUNC_INT__SHIFT 0x18 3138 #define UVD_SUVD_INT_STATUS__SDB_ERR_INT__SHIFT 0x1d 3139 #define UVD_SUVD_INT_STATUS__FBC_ERR_INT__SHIFT 0x1e 3140 #define UVD_SUVD_INT_STATUS__SRE_FUNC_INT_MASK 0x0000001FL 3141 #define UVD_SUVD_INT_STATUS__SRE_ERR_INT_MASK 0x00000020L 3142 #define UVD_SUVD_INT_STATUS__SIT_FUNC_INT_MASK 0x000007C0L 3143 #define UVD_SUVD_INT_STATUS__SIT_ERR_INT_MASK 0x00000800L 3144 #define UVD_SUVD_INT_STATUS__SMP_FUNC_INT_MASK 0x0001F000L 3145 #define UVD_SUVD_INT_STATUS__SMP_ERR_INT_MASK 0x00020000L 3146 #define UVD_SUVD_INT_STATUS__SCM_FUNC_INT_MASK 0x007C0000L 3147 #define UVD_SUVD_INT_STATUS__SCM_ERR_INT_MASK 0x00800000L 3148 #define UVD_SUVD_INT_STATUS__SDB_FUNC_INT_MASK 0x1F000000L 3149 #define UVD_SUVD_INT_STATUS__SDB_ERR_INT_MASK 0x20000000L 3150 #define UVD_SUVD_INT_STATUS__FBC_ERR_INT_MASK 0x40000000L 3151 //UVD_SUVD_INT_ACK 3152 #define UVD_SUVD_INT_ACK__SRE_FUNC_INT_ACK__SHIFT 0x0 3153 #define UVD_SUVD_INT_ACK__SRE_ERR_INT_ACK__SHIFT 0x5 3154 #define UVD_SUVD_INT_ACK__SIT_FUNC_INT_ACK__SHIFT 0x6 3155 #define UVD_SUVD_INT_ACK__SIT_ERR_INT_ACK__SHIFT 0xb 3156 #define UVD_SUVD_INT_ACK__SMP_FUNC_INT_ACK__SHIFT 0xc 3157 #define UVD_SUVD_INT_ACK__SMP_ERR_INT_ACK__SHIFT 0x11 3158 #define UVD_SUVD_INT_ACK__SCM_FUNC_INT_ACK__SHIFT 0x12 3159 #define UVD_SUVD_INT_ACK__SCM_ERR_INT_ACK__SHIFT 0x17 3160 #define UVD_SUVD_INT_ACK__SDB_FUNC_INT_ACK__SHIFT 0x18 3161 #define UVD_SUVD_INT_ACK__SDB_ERR_INT_ACK__SHIFT 0x1d 3162 #define UVD_SUVD_INT_ACK__FBC_ERR_INT_ACK__SHIFT 0x1e 3163 #define UVD_SUVD_INT_ACK__SRE_FUNC_INT_ACK_MASK 0x0000001FL 3164 #define UVD_SUVD_INT_ACK__SRE_ERR_INT_ACK_MASK 0x00000020L 3165 #define UVD_SUVD_INT_ACK__SIT_FUNC_INT_ACK_MASK 0x000007C0L 3166 #define UVD_SUVD_INT_ACK__SIT_ERR_INT_ACK_MASK 0x00000800L 3167 #define UVD_SUVD_INT_ACK__SMP_FUNC_INT_ACK_MASK 0x0001F000L 3168 #define UVD_SUVD_INT_ACK__SMP_ERR_INT_ACK_MASK 0x00020000L 3169 #define UVD_SUVD_INT_ACK__SCM_FUNC_INT_ACK_MASK 0x007C0000L 3170 #define UVD_SUVD_INT_ACK__SCM_ERR_INT_ACK_MASK 0x00800000L 3171 #define UVD_SUVD_INT_ACK__SDB_FUNC_INT_ACK_MASK 0x1F000000L 3172 #define UVD_SUVD_INT_ACK__SDB_ERR_INT_ACK_MASK 0x20000000L 3173 #define UVD_SUVD_INT_ACK__FBC_ERR_INT_ACK_MASK 0x40000000L 3174 //UVD_ENC_VCPU_INT_EN 3175 #define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR_EN__SHIFT 0x0 3176 #define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR2_EN__SHIFT 0x1 3177 #define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR3_EN__SHIFT 0x2 3178 #define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR_EN_MASK 0x00000001L 3179 #define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR2_EN_MASK 0x00000002L 3180 #define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR3_EN_MASK 0x00000004L 3181 //UVD_ENC_VCPU_INT_STATUS 3182 #define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR_INT__SHIFT 0x0 3183 #define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR2_INT__SHIFT 0x1 3184 #define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR3_INT__SHIFT 0x2 3185 #define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR_INT_MASK 0x00000001L 3186 #define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR2_INT_MASK 0x00000002L 3187 #define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR3_INT_MASK 0x00000004L 3188 //UVD_ENC_VCPU_INT_ACK 3189 #define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR_ACK__SHIFT 0x0 3190 #define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR2_ACK__SHIFT 0x1 3191 #define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR3_ACK__SHIFT 0x2 3192 #define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR_ACK_MASK 0x00000001L 3193 #define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR2_ACK_MASK 0x00000002L 3194 #define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR3_ACK_MASK 0x00000004L 3195 //UVD_MASTINT_EN 3196 #define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 3197 #define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x1 3198 #define UVD_MASTINT_EN__SYS_EN__SHIFT 0x2 3199 #define UVD_MASTINT_EN__INT_OVERRUN__SHIFT 0x4 3200 #define UVD_MASTINT_EN__OVERRUN_RST_MASK 0x00000001L 3201 #define UVD_MASTINT_EN__VCPU_EN_MASK 0x00000002L 3202 #define UVD_MASTINT_EN__SYS_EN_MASK 0x00000004L 3203 #define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x00FFFFF0L 3204 //UVD_SYS_INT_EN 3205 #define UVD_SYS_INT_EN__PIF_ADDR_ERR_EN__SHIFT 0x0 3206 #define UVD_SYS_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN__SHIFT 0x1 3207 #define UVD_SYS_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN__SHIFT 0x2 3208 #define UVD_SYS_INT_EN__CXW_WR_EN__SHIFT 0x3 3209 #define UVD_SYS_INT_EN__RBC_REG_PRIV_FAULT_EN__SHIFT 0x6 3210 #define UVD_SYS_INT_EN__LBSI_EN__SHIFT 0xb 3211 #define UVD_SYS_INT_EN__UDEC_EN__SHIFT 0xc 3212 #define UVD_SYS_INT_EN__LMI_AXI_UNSUPPORTED_LEN_EN__SHIFT 0xd 3213 #define UVD_SYS_INT_EN__LMI_AXI_UNSUPPORTED_ADR_ALIGN_EN__SHIFT 0xe 3214 #define UVD_SYS_INT_EN__SUVD_EN__SHIFT 0xf 3215 #define UVD_SYS_INT_EN__JOB_DONE_EN__SHIFT 0x10 3216 #define UVD_SYS_INT_EN__SEMA_WAIT_FAIL_SIG_EN__SHIFT 0x17 3217 #define UVD_SYS_INT_EN__IDCT_EN__SHIFT 0x18 3218 #define UVD_SYS_INT_EN__MPRD_EN__SHIFT 0x19 3219 #define UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN__SHIFT 0x1a 3220 #define UVD_SYS_INT_EN__CLK_SWT_EN__SHIFT 0x1b 3221 #define UVD_SYS_INT_EN__MIF_HWINT_EN__SHIFT 0x1c 3222 #define UVD_SYS_INT_EN__MPRD_ERR_EN__SHIFT 0x1d 3223 #define UVD_SYS_INT_EN__AVM_INT_EN__SHIFT 0x1f 3224 #define UVD_SYS_INT_EN__PIF_ADDR_ERR_EN_MASK 0x00000001L 3225 #define UVD_SYS_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN_MASK 0x00000002L 3226 #define UVD_SYS_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN_MASK 0x00000004L 3227 #define UVD_SYS_INT_EN__CXW_WR_EN_MASK 0x00000008L 3228 #define UVD_SYS_INT_EN__RBC_REG_PRIV_FAULT_EN_MASK 0x00000040L 3229 #define UVD_SYS_INT_EN__LBSI_EN_MASK 0x00000800L 3230 #define UVD_SYS_INT_EN__UDEC_EN_MASK 0x00001000L 3231 #define UVD_SYS_INT_EN__LMI_AXI_UNSUPPORTED_LEN_EN_MASK 0x00002000L 3232 #define UVD_SYS_INT_EN__LMI_AXI_UNSUPPORTED_ADR_ALIGN_EN_MASK 0x00004000L 3233 #define UVD_SYS_INT_EN__SUVD_EN_MASK 0x00008000L 3234 #define UVD_SYS_INT_EN__JOB_DONE_EN_MASK 0x00010000L 3235 #define UVD_SYS_INT_EN__SEMA_WAIT_FAIL_SIG_EN_MASK 0x00800000L 3236 #define UVD_SYS_INT_EN__IDCT_EN_MASK 0x01000000L 3237 #define UVD_SYS_INT_EN__MPRD_EN_MASK 0x02000000L 3238 #define UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK 0x04000000L 3239 #define UVD_SYS_INT_EN__CLK_SWT_EN_MASK 0x08000000L 3240 #define UVD_SYS_INT_EN__MIF_HWINT_EN_MASK 0x10000000L 3241 #define UVD_SYS_INT_EN__MPRD_ERR_EN_MASK 0x20000000L 3242 #define UVD_SYS_INT_EN__AVM_INT_EN_MASK 0x80000000L 3243 //UVD_SYS_INT_STATUS 3244 #define UVD_SYS_INT_STATUS__PIF_ADDR_ERR_INT__SHIFT 0x0 3245 #define UVD_SYS_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT__SHIFT 0x1 3246 #define UVD_SYS_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT__SHIFT 0x2 3247 #define UVD_SYS_INT_STATUS__CXW_WR_INT__SHIFT 0x3 3248 #define UVD_SYS_INT_STATUS__RBC_REG_PRIV_FAULT_INT__SHIFT 0x6 3249 #define UVD_SYS_INT_STATUS__LBSI_INT__SHIFT 0xb 3250 #define UVD_SYS_INT_STATUS__UDEC_INT__SHIFT 0xc 3251 #define UVD_SYS_INT_STATUS__LMI_AXI_UNSUPPORTED_LEN_INT__SHIFT 0xd 3252 #define UVD_SYS_INT_STATUS__LMI_AXI_UNSUPPORTED_ADR_ALIGN_INT__SHIFT 0xe 3253 #define UVD_SYS_INT_STATUS__SUVD_INT__SHIFT 0xf 3254 #define UVD_SYS_INT_STATUS__JOB_DONE_INT__SHIFT 0x10 3255 #define UVD_SYS_INT_STATUS__GPCOM_INT__SHIFT 0x12 3256 #define UVD_SYS_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT__SHIFT 0x17 3257 #define UVD_SYS_INT_STATUS__IDCT_INT__SHIFT 0x18 3258 #define UVD_SYS_INT_STATUS__MPRD_INT__SHIFT 0x19 3259 #define UVD_SYS_INT_STATUS__CLK_SWT_INT__SHIFT 0x1b 3260 #define UVD_SYS_INT_STATUS__MIF_HWINT__SHIFT 0x1c 3261 #define UVD_SYS_INT_STATUS__MPRD_ERR_INT__SHIFT 0x1d 3262 #define UVD_SYS_INT_STATUS__RASCNTL_VCPU_VCODEC_INT__SHIFT 0x1e 3263 #define UVD_SYS_INT_STATUS__AVM_INT__SHIFT 0x1f 3264 #define UVD_SYS_INT_STATUS__PIF_ADDR_ERR_INT_MASK 0x00000001L 3265 #define UVD_SYS_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT_MASK 0x00000002L 3266 #define UVD_SYS_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT_MASK 0x00000004L 3267 #define UVD_SYS_INT_STATUS__CXW_WR_INT_MASK 0x00000008L 3268 #define UVD_SYS_INT_STATUS__RBC_REG_PRIV_FAULT_INT_MASK 0x00000040L 3269 #define UVD_SYS_INT_STATUS__LBSI_INT_MASK 0x00000800L 3270 #define UVD_SYS_INT_STATUS__UDEC_INT_MASK 0x00001000L 3271 #define UVD_SYS_INT_STATUS__LMI_AXI_UNSUPPORTED_LEN_INT_MASK 0x00002000L 3272 #define UVD_SYS_INT_STATUS__LMI_AXI_UNSUPPORTED_ADR_ALIGN_INT_MASK 0x00004000L 3273 #define UVD_SYS_INT_STATUS__SUVD_INT_MASK 0x00008000L 3274 #define UVD_SYS_INT_STATUS__JOB_DONE_INT_MASK 0x00010000L 3275 #define UVD_SYS_INT_STATUS__GPCOM_INT_MASK 0x00040000L 3276 #define UVD_SYS_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT_MASK 0x00800000L 3277 #define UVD_SYS_INT_STATUS__IDCT_INT_MASK 0x01000000L 3278 #define UVD_SYS_INT_STATUS__MPRD_INT_MASK 0x02000000L 3279 #define UVD_SYS_INT_STATUS__CLK_SWT_INT_MASK 0x08000000L 3280 #define UVD_SYS_INT_STATUS__MIF_HWINT_MASK 0x10000000L 3281 #define UVD_SYS_INT_STATUS__MPRD_ERR_INT_MASK 0x20000000L 3282 #define UVD_SYS_INT_STATUS__RASCNTL_VCPU_VCODEC_INT_MASK 0x40000000L 3283 #define UVD_SYS_INT_STATUS__AVM_INT_MASK 0x80000000L 3284 //UVD_SYS_INT_ACK 3285 #define UVD_SYS_INT_ACK__PIF_ADDR_ERR_ACK__SHIFT 0x0 3286 #define UVD_SYS_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK__SHIFT 0x1 3287 #define UVD_SYS_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK__SHIFT 0x2 3288 #define UVD_SYS_INT_ACK__CXW_WR_ACK__SHIFT 0x3 3289 #define UVD_SYS_INT_ACK__RBC_REG_PRIV_FAULT_ACK__SHIFT 0x6 3290 #define UVD_SYS_INT_ACK__LBSI_ACK__SHIFT 0xb 3291 #define UVD_SYS_INT_ACK__UDEC_ACK__SHIFT 0xc 3292 #define UVD_SYS_INT_ACK__LMI_AXI_UNSUPPORTED_LEN_ACK__SHIFT 0xd 3293 #define UVD_SYS_INT_ACK__LMI_AXI_UNSUPPORTED_ADR_ALIGN_ACK__SHIFT 0xe 3294 #define UVD_SYS_INT_ACK__SUVD_ACK__SHIFT 0xf 3295 #define UVD_SYS_INT_ACK__JOB_DONE_ACK__SHIFT 0x10 3296 #define UVD_SYS_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK__SHIFT 0x17 3297 #define UVD_SYS_INT_ACK__IDCT_ACK__SHIFT 0x18 3298 #define UVD_SYS_INT_ACK__MPRD_ACK__SHIFT 0x19 3299 #define UVD_SYS_INT_ACK__CLK_SWT_ACK__SHIFT 0x1b 3300 #define UVD_SYS_INT_ACK__MIF_HWINT_ACK__SHIFT 0x1c 3301 #define UVD_SYS_INT_ACK__MPRD_ERR_ACK__SHIFT 0x1d 3302 #define UVD_SYS_INT_ACK__RASCNTL_VCPU_VCODEC_ACK__SHIFT 0x1e 3303 #define UVD_SYS_INT_ACK__AVM_INT_ACK__SHIFT 0x1f 3304 #define UVD_SYS_INT_ACK__PIF_ADDR_ERR_ACK_MASK 0x00000001L 3305 #define UVD_SYS_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK_MASK 0x00000002L 3306 #define UVD_SYS_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK_MASK 0x00000004L 3307 #define UVD_SYS_INT_ACK__CXW_WR_ACK_MASK 0x00000008L 3308 #define UVD_SYS_INT_ACK__RBC_REG_PRIV_FAULT_ACK_MASK 0x00000040L 3309 #define UVD_SYS_INT_ACK__LBSI_ACK_MASK 0x00000800L 3310 #define UVD_SYS_INT_ACK__UDEC_ACK_MASK 0x00001000L 3311 #define UVD_SYS_INT_ACK__LMI_AXI_UNSUPPORTED_LEN_ACK_MASK 0x00002000L 3312 #define UVD_SYS_INT_ACK__LMI_AXI_UNSUPPORTED_ADR_ALIGN_ACK_MASK 0x00004000L 3313 #define UVD_SYS_INT_ACK__SUVD_ACK_MASK 0x00008000L 3314 #define UVD_SYS_INT_ACK__JOB_DONE_ACK_MASK 0x00010000L 3315 #define UVD_SYS_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK_MASK 0x00800000L 3316 #define UVD_SYS_INT_ACK__IDCT_ACK_MASK 0x01000000L 3317 #define UVD_SYS_INT_ACK__MPRD_ACK_MASK 0x02000000L 3318 #define UVD_SYS_INT_ACK__CLK_SWT_ACK_MASK 0x08000000L 3319 #define UVD_SYS_INT_ACK__MIF_HWINT_ACK_MASK 0x10000000L 3320 #define UVD_SYS_INT_ACK__MPRD_ERR_ACK_MASK 0x20000000L 3321 #define UVD_SYS_INT_ACK__RASCNTL_VCPU_VCODEC_ACK_MASK 0x40000000L 3322 #define UVD_SYS_INT_ACK__AVM_INT_ACK_MASK 0x80000000L 3323 //UVD_JOB_DONE 3324 #define UVD_JOB_DONE__JOB_DONE__SHIFT 0x0 3325 #define UVD_JOB_DONE__JOB_DONE_MASK 0x00000003L 3326 //UVD_CBUF_ID 3327 #define UVD_CBUF_ID__CBUF_ID__SHIFT 0x0 3328 #define UVD_CBUF_ID__CBUF_ID_MASK 0xFFFFFFFFL 3329 //UVD_CONTEXT_ID 3330 #define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT 0x0 3331 #define UVD_CONTEXT_ID__CONTEXT_ID_MASK 0xFFFFFFFFL 3332 //UVD_CONTEXT_ID2 3333 #define UVD_CONTEXT_ID2__CONTEXT_ID2__SHIFT 0x0 3334 #define UVD_CONTEXT_ID2__CONTEXT_ID2_MASK 0xFFFFFFFFL 3335 //UVD_NO_OP 3336 #define UVD_NO_OP__NO_OP__SHIFT 0x0 3337 #define UVD_NO_OP__NO_OP_MASK 0xFFFFFFFFL 3338 //UVD_RB_BASE_LO 3339 #define UVD_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6 3340 #define UVD_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L 3341 //UVD_RB_BASE_HI 3342 #define UVD_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0 3343 #define UVD_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL 3344 //UVD_RB_SIZE 3345 #define UVD_RB_SIZE__RB_SIZE__SHIFT 0x4 3346 #define UVD_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L 3347 //UVD_RB_BASE_LO2 3348 #define UVD_RB_BASE_LO2__RB_BASE_LO__SHIFT 0x6 3349 #define UVD_RB_BASE_LO2__RB_BASE_LO_MASK 0xFFFFFFC0L 3350 //UVD_RB_BASE_HI2 3351 #define UVD_RB_BASE_HI2__RB_BASE_HI__SHIFT 0x0 3352 #define UVD_RB_BASE_HI2__RB_BASE_HI_MASK 0xFFFFFFFFL 3353 //UVD_RB_SIZE2 3354 #define UVD_RB_SIZE2__RB_SIZE__SHIFT 0x4 3355 #define UVD_RB_SIZE2__RB_SIZE_MASK 0x007FFFF0L 3356 //UVD_RB_BASE_LO3 3357 #define UVD_RB_BASE_LO3__RB_BASE_LO__SHIFT 0x6 3358 #define UVD_RB_BASE_LO3__RB_BASE_LO_MASK 0xFFFFFFC0L 3359 //UVD_RB_BASE_HI3 3360 #define UVD_RB_BASE_HI3__RB_BASE_HI__SHIFT 0x0 3361 #define UVD_RB_BASE_HI3__RB_BASE_HI_MASK 0xFFFFFFFFL 3362 //UVD_RB_SIZE3 3363 #define UVD_RB_SIZE3__RB_SIZE__SHIFT 0x4 3364 #define UVD_RB_SIZE3__RB_SIZE_MASK 0x007FFFF0L 3365 //UVD_RB_BASE_LO4 3366 #define UVD_RB_BASE_LO4__RB_BASE_LO__SHIFT 0x6 3367 #define UVD_RB_BASE_LO4__RB_BASE_LO_MASK 0xFFFFFFC0L 3368 //UVD_RB_BASE_HI4 3369 #define UVD_RB_BASE_HI4__RB_BASE_HI__SHIFT 0x0 3370 #define UVD_RB_BASE_HI4__RB_BASE_HI_MASK 0xFFFFFFFFL 3371 //UVD_RB_SIZE4 3372 #define UVD_RB_SIZE4__RB_SIZE__SHIFT 0x4 3373 #define UVD_RB_SIZE4__RB_SIZE_MASK 0x007FFFF0L 3374 //UVD_OUT_RB_BASE_LO 3375 #define UVD_OUT_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6 3376 #define UVD_OUT_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L 3377 //UVD_OUT_RB_BASE_HI 3378 #define UVD_OUT_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0 3379 #define UVD_OUT_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL 3380 //UVD_OUT_RB_SIZE 3381 #define UVD_OUT_RB_SIZE__RB_SIZE__SHIFT 0x4 3382 #define UVD_OUT_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L 3383 //UVD_IOV_ACTIVE_FCN_ID 3384 #define UVD_IOV_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0 3385 #define UVD_IOV_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f 3386 #define UVD_IOV_ACTIVE_FCN_ID__VF_ID_MASK 0x0000003FL 3387 #define UVD_IOV_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000L 3388 //UVD_IOV_MAILBOX 3389 #define UVD_IOV_MAILBOX__MAILBOX__SHIFT 0x0 3390 #define UVD_IOV_MAILBOX__MAILBOX_MASK 0xFFFFFFFFL 3391 //UVD_IOV_MAILBOX_RESP 3392 #define UVD_IOV_MAILBOX_RESP__RESP__SHIFT 0x0 3393 #define UVD_IOV_MAILBOX_RESP__RESP_MASK 0xFFFFFFFFL 3394 //UVD_RB_ARB_CTRL 3395 #define UVD_RB_ARB_CTRL__SRBM_DROP__SHIFT 0x0 3396 #define UVD_RB_ARB_CTRL__SRBM_DIS__SHIFT 0x1 3397 #define UVD_RB_ARB_CTRL__VCPU_DROP__SHIFT 0x2 3398 #define UVD_RB_ARB_CTRL__VCPU_DIS__SHIFT 0x3 3399 #define UVD_RB_ARB_CTRL__RBC_DROP__SHIFT 0x4 3400 #define UVD_RB_ARB_CTRL__RBC_DIS__SHIFT 0x5 3401 #define UVD_RB_ARB_CTRL__FWOFLD_DROP__SHIFT 0x6 3402 #define UVD_RB_ARB_CTRL__FWOFLD_DIS__SHIFT 0x7 3403 #define UVD_RB_ARB_CTRL__FAST_PATH_EN__SHIFT 0x8 3404 #define UVD_RB_ARB_CTRL__UVD_RB_DBG_EN__SHIFT 0x9 3405 #define UVD_RB_ARB_CTRL__SRBM_DROP_MASK 0x00000001L 3406 #define UVD_RB_ARB_CTRL__SRBM_DIS_MASK 0x00000002L 3407 #define UVD_RB_ARB_CTRL__VCPU_DROP_MASK 0x00000004L 3408 #define UVD_RB_ARB_CTRL__VCPU_DIS_MASK 0x00000008L 3409 #define UVD_RB_ARB_CTRL__RBC_DROP_MASK 0x00000010L 3410 #define UVD_RB_ARB_CTRL__RBC_DIS_MASK 0x00000020L 3411 #define UVD_RB_ARB_CTRL__FWOFLD_DROP_MASK 0x00000040L 3412 #define UVD_RB_ARB_CTRL__FWOFLD_DIS_MASK 0x00000080L 3413 #define UVD_RB_ARB_CTRL__FAST_PATH_EN_MASK 0x00000100L 3414 #define UVD_RB_ARB_CTRL__UVD_RB_DBG_EN_MASK 0x00000200L 3415 //UVD_CTX_INDEX 3416 #define UVD_CTX_INDEX__INDEX__SHIFT 0x0 3417 #define UVD_CTX_INDEX__INDEX_MASK 0x000001FFL 3418 //UVD_CTX_DATA 3419 #define UVD_CTX_DATA__DATA__SHIFT 0x0 3420 #define UVD_CTX_DATA__DATA_MASK 0xFFFFFFFFL 3421 //UVD_CXW_WR 3422 #define UVD_CXW_WR__DAT__SHIFT 0x0 3423 #define UVD_CXW_WR__STAT__SHIFT 0x1f 3424 #define UVD_CXW_WR__DAT_MASK 0x0FFFFFFFL 3425 #define UVD_CXW_WR__STAT_MASK 0x80000000L 3426 //UVD_CXW_WR_INT_ID 3427 #define UVD_CXW_WR_INT_ID__ID__SHIFT 0x0 3428 #define UVD_CXW_WR_INT_ID__ID_MASK 0x000000FFL 3429 //UVD_CXW_WR_INT_CTX_ID 3430 #define UVD_CXW_WR_INT_CTX_ID__ID__SHIFT 0x0 3431 #define UVD_CXW_WR_INT_CTX_ID__ID_MASK 0x0FFFFFFFL 3432 //UVD_CXW_INT_ID 3433 #define UVD_CXW_INT_ID__ID__SHIFT 0x0 3434 #define UVD_CXW_INT_ID__ID_MASK 0x000000FFL 3435 //UVD_MPEG2_ERROR 3436 #define UVD_MPEG2_ERROR__STATUS__SHIFT 0x0 3437 #define UVD_MPEG2_ERROR__STATUS_MASK 0xFFFFFFFFL 3438 //UVD_YBASE 3439 #define UVD_YBASE__DUM__SHIFT 0x0 3440 #define UVD_YBASE__DUM_MASK 0xFFFFFFFFL 3441 //UVD_UVBASE 3442 #define UVD_UVBASE__DUM__SHIFT 0x0 3443 #define UVD_UVBASE__DUM_MASK 0xFFFFFFFFL 3444 //UVD_PITCH 3445 #define UVD_PITCH__DUM__SHIFT 0x0 3446 #define UVD_PITCH__DUM_MASK 0xFFFFFFFFL 3447 //UVD_WIDTH 3448 #define UVD_WIDTH__DUM__SHIFT 0x0 3449 #define UVD_WIDTH__DUM_MASK 0xFFFFFFFFL 3450 //UVD_HEIGHT 3451 #define UVD_HEIGHT__DUM__SHIFT 0x0 3452 #define UVD_HEIGHT__DUM_MASK 0xFFFFFFFFL 3453 //UVD_PICCOUNT 3454 #define UVD_PICCOUNT__DUM__SHIFT 0x0 3455 #define UVD_PICCOUNT__DUM_MASK 0xFFFFFFFFL 3456 //UVD_MPRD_INITIAL_XY 3457 #define UVD_MPRD_INITIAL_XY__MPRD_SCREEN_X__SHIFT 0x0 3458 #define UVD_MPRD_INITIAL_XY__MPRD_SCREEN_Y__SHIFT 0x10 3459 #define UVD_MPRD_INITIAL_XY__MPRD_SCREEN_X_MASK 0x00000FFFL 3460 #define UVD_MPRD_INITIAL_XY__MPRD_SCREEN_Y_MASK 0x0FFF0000L 3461 //UVD_MPEG2_CTRL 3462 #define UVD_MPEG2_CTRL__EN__SHIFT 0x0 3463 #define UVD_MPEG2_CTRL__TRICK_MODE__SHIFT 0x1 3464 #define UVD_MPEG2_CTRL__NUM_MB_PER_JOB__SHIFT 0x10 3465 #define UVD_MPEG2_CTRL__EN_MASK 0x00000001L 3466 #define UVD_MPEG2_CTRL__TRICK_MODE_MASK 0x00000002L 3467 #define UVD_MPEG2_CTRL__NUM_MB_PER_JOB_MASK 0xFFFF0000L 3468 //UVD_MB_CTL_BUF_BASE 3469 #define UVD_MB_CTL_BUF_BASE__BASE__SHIFT 0x0 3470 #define UVD_MB_CTL_BUF_BASE__BASE_MASK 0xFFFFFFFFL 3471 //UVD_PIC_CTL_BUF_BASE 3472 #define UVD_PIC_CTL_BUF_BASE__BASE__SHIFT 0x0 3473 #define UVD_PIC_CTL_BUF_BASE__BASE_MASK 0xFFFFFFFFL 3474 //UVD_DXVA_BUF_SIZE 3475 #define UVD_DXVA_BUF_SIZE__PIC_SIZE__SHIFT 0x0 3476 #define UVD_DXVA_BUF_SIZE__MB_SIZE__SHIFT 0x10 3477 #define UVD_DXVA_BUF_SIZE__PIC_SIZE_MASK 0x0000FFFFL 3478 #define UVD_DXVA_BUF_SIZE__MB_SIZE_MASK 0xFFFF0000L 3479 //UVD_SCRATCH_NP 3480 #define UVD_SCRATCH_NP__DATA__SHIFT 0x0 3481 #define UVD_SCRATCH_NP__DATA_MASK 0xFFFFFFFFL 3482 //UVD_CLK_SWT_HANDSHAKE 3483 #define UVD_CLK_SWT_HANDSHAKE__CLK_SWT_TYPE__SHIFT 0x0 3484 #define UVD_CLK_SWT_HANDSHAKE__CLK_DOMAIN_SWT__SHIFT 0x8 3485 #define UVD_CLK_SWT_HANDSHAKE__CLK_SWT_TYPE_MASK 0x00000003L 3486 #define UVD_CLK_SWT_HANDSHAKE__CLK_DOMAIN_SWT_MASK 0x00000300L 3487 //UVD_GP_SCRATCH0 3488 #define UVD_GP_SCRATCH0__DATA__SHIFT 0x0 3489 #define UVD_GP_SCRATCH0__DATA_MASK 0xFFFFFFFFL 3490 //UVD_GP_SCRATCH1 3491 #define UVD_GP_SCRATCH1__DATA__SHIFT 0x0 3492 #define UVD_GP_SCRATCH1__DATA_MASK 0xFFFFFFFFL 3493 //UVD_GP_SCRATCH2 3494 #define UVD_GP_SCRATCH2__DATA__SHIFT 0x0 3495 #define UVD_GP_SCRATCH2__DATA_MASK 0xFFFFFFFFL 3496 //UVD_GP_SCRATCH3 3497 #define UVD_GP_SCRATCH3__DATA__SHIFT 0x0 3498 #define UVD_GP_SCRATCH3__DATA_MASK 0xFFFFFFFFL 3499 //UVD_GP_SCRATCH4 3500 #define UVD_GP_SCRATCH4__DATA__SHIFT 0x0 3501 #define UVD_GP_SCRATCH4__DATA_MASK 0xFFFFFFFFL 3502 //UVD_GP_SCRATCH5 3503 #define UVD_GP_SCRATCH5__DATA__SHIFT 0x0 3504 #define UVD_GP_SCRATCH5__DATA_MASK 0xFFFFFFFFL 3505 //UVD_GP_SCRATCH6 3506 #define UVD_GP_SCRATCH6__DATA__SHIFT 0x0 3507 #define UVD_GP_SCRATCH6__DATA_MASK 0xFFFFFFFFL 3508 //UVD_GP_SCRATCH7 3509 #define UVD_GP_SCRATCH7__DATA__SHIFT 0x0 3510 #define UVD_GP_SCRATCH7__DATA_MASK 0xFFFFFFFFL 3511 //UVD_GP_SCRATCH8 3512 #define UVD_GP_SCRATCH8__DATA__SHIFT 0x0 3513 #define UVD_GP_SCRATCH8__DATA_MASK 0xFFFFFFFFL 3514 //UVD_GP_SCRATCH9 3515 #define UVD_GP_SCRATCH9__DATA__SHIFT 0x0 3516 #define UVD_GP_SCRATCH9__DATA_MASK 0xFFFFFFFFL 3517 //UVD_GP_SCRATCH10 3518 #define UVD_GP_SCRATCH10__DATA__SHIFT 0x0 3519 #define UVD_GP_SCRATCH10__DATA_MASK 0xFFFFFFFFL 3520 //UVD_GP_SCRATCH11 3521 #define UVD_GP_SCRATCH11__DATA__SHIFT 0x0 3522 #define UVD_GP_SCRATCH11__DATA_MASK 0xFFFFFFFFL 3523 //UVD_GP_SCRATCH12 3524 #define UVD_GP_SCRATCH12__DATA__SHIFT 0x0 3525 #define UVD_GP_SCRATCH12__DATA_MASK 0xFFFFFFFFL 3526 //UVD_GP_SCRATCH13 3527 #define UVD_GP_SCRATCH13__DATA__SHIFT 0x0 3528 #define UVD_GP_SCRATCH13__DATA_MASK 0xFFFFFFFFL 3529 //UVD_GP_SCRATCH14 3530 #define UVD_GP_SCRATCH14__DATA__SHIFT 0x0 3531 #define UVD_GP_SCRATCH14__DATA_MASK 0xFFFFFFFFL 3532 //UVD_GP_SCRATCH15 3533 #define UVD_GP_SCRATCH15__DATA__SHIFT 0x0 3534 #define UVD_GP_SCRATCH15__DATA_MASK 0xFFFFFFFFL 3535 //UVD_GP_SCRATCH16 3536 #define UVD_GP_SCRATCH16__DATA__SHIFT 0x0 3537 #define UVD_GP_SCRATCH16__DATA_MASK 0xFFFFFFFFL 3538 //UVD_GP_SCRATCH17 3539 #define UVD_GP_SCRATCH17__DATA__SHIFT 0x0 3540 #define UVD_GP_SCRATCH17__DATA_MASK 0xFFFFFFFFL 3541 //UVD_GP_SCRATCH18 3542 #define UVD_GP_SCRATCH18__DATA__SHIFT 0x0 3543 #define UVD_GP_SCRATCH18__DATA_MASK 0xFFFFFFFFL 3544 //UVD_GP_SCRATCH19 3545 #define UVD_GP_SCRATCH19__DATA__SHIFT 0x0 3546 #define UVD_GP_SCRATCH19__DATA_MASK 0xFFFFFFFFL 3547 //UVD_GP_SCRATCH20 3548 #define UVD_GP_SCRATCH20__DATA__SHIFT 0x0 3549 #define UVD_GP_SCRATCH20__DATA_MASK 0xFFFFFFFFL 3550 //UVD_GP_SCRATCH21 3551 #define UVD_GP_SCRATCH21__DATA__SHIFT 0x0 3552 #define UVD_GP_SCRATCH21__DATA_MASK 0xFFFFFFFFL 3553 //UVD_GP_SCRATCH22 3554 #define UVD_GP_SCRATCH22__DATA__SHIFT 0x0 3555 #define UVD_GP_SCRATCH22__DATA_MASK 0xFFFFFFFFL 3556 //UVD_GP_SCRATCH23 3557 #define UVD_GP_SCRATCH23__DATA__SHIFT 0x0 3558 #define UVD_GP_SCRATCH23__DATA_MASK 0xFFFFFFFFL 3559 //UVD_AUDIO_RB_BASE_LO 3560 #define UVD_AUDIO_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6 3561 #define UVD_AUDIO_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L 3562 //UVD_AUDIO_RB_BASE_HI 3563 #define UVD_AUDIO_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0 3564 #define UVD_AUDIO_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL 3565 //UVD_AUDIO_RB_SIZE 3566 #define UVD_AUDIO_RB_SIZE__RB_SIZE__SHIFT 0x4 3567 #define UVD_AUDIO_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L 3568 //UVD_VCPU_INT_STATUS2 3569 #define UVD_VCPU_INT_STATUS2__SW_RB6_INT__SHIFT 0x0 3570 #define UVD_VCPU_INT_STATUS2__RASCNTL_VCPU_VCODEC_INT__SHIFT 0x15 3571 #define UVD_VCPU_INT_STATUS2__SW_RB6_INT_MASK 0x00000001L 3572 #define UVD_VCPU_INT_STATUS2__RASCNTL_VCPU_VCODEC_INT_MASK 0x00200000L 3573 //UVD_VCPU_INT_ACK2 3574 #define UVD_VCPU_INT_ACK2__SW_RB6_INT_ACK__SHIFT 0x0 3575 #define UVD_VCPU_INT_ACK2__RASCNTL_VCPU_VCODEC_ACK__SHIFT 0x16 3576 #define UVD_VCPU_INT_ACK2__SW_RB6_INT_ACK_MASK 0x00000001L 3577 #define UVD_VCPU_INT_ACK2__RASCNTL_VCPU_VCODEC_ACK_MASK 0x00400000L 3578 //UVD_VCPU_INT_EN2 3579 #define UVD_VCPU_INT_EN2__SW_RB6_INT_EN__SHIFT 0x0 3580 #define UVD_VCPU_INT_EN2__RASCNTL_VCPU_VCODEC_EN__SHIFT 0x1 3581 #define UVD_VCPU_INT_EN2__SW_RB6_INT_EN_MASK 0x00000001L 3582 #define UVD_VCPU_INT_EN2__RASCNTL_VCPU_VCODEC_EN_MASK 0x00000002L 3583 //UVD_SUVD_CGC_STATUS2 3584 #define UVD_SUVD_CGC_STATUS2__SMPA_VCLK__SHIFT 0x0 3585 #define UVD_SUVD_CGC_STATUS2__SMPA_DCLK__SHIFT 0x1 3586 #define UVD_SUVD_CGC_STATUS2__MPBE1_DCLK__SHIFT 0x3 3587 #define UVD_SUVD_CGC_STATUS2__SIT_AV1_DCLK__SHIFT 0x4 3588 #define UVD_SUVD_CGC_STATUS2__SDB_AV1_DCLK__SHIFT 0x5 3589 #define UVD_SUVD_CGC_STATUS2__MPC1_DCLK__SHIFT 0x6 3590 #define UVD_SUVD_CGC_STATUS2__MPC1_SCLK__SHIFT 0x7 3591 #define UVD_SUVD_CGC_STATUS2__MPC1_VCLK__SHIFT 0x8 3592 #define UVD_SUVD_CGC_STATUS2__SRE_AV1_ENC_DCLK__SHIFT 0x9 3593 #define UVD_SUVD_CGC_STATUS2__CDEFE_DCLK__SHIFT 0xa 3594 #define UVD_SUVD_CGC_STATUS2__SIT0_DCLK__SHIFT 0xb 3595 #define UVD_SUVD_CGC_STATUS2__SIT1_DCLK__SHIFT 0xc 3596 #define UVD_SUVD_CGC_STATUS2__SIT2_DCLK__SHIFT 0xd 3597 #define UVD_SUVD_CGC_STATUS2__FBC_PCLK__SHIFT 0x1c 3598 #define UVD_SUVD_CGC_STATUS2__FBC_CCLK__SHIFT 0x1d 3599 #define UVD_SUVD_CGC_STATUS2__SMPA_VCLK_MASK 0x00000001L 3600 #define UVD_SUVD_CGC_STATUS2__SMPA_DCLK_MASK 0x00000002L 3601 #define UVD_SUVD_CGC_STATUS2__MPBE1_DCLK_MASK 0x00000008L 3602 #define UVD_SUVD_CGC_STATUS2__SIT_AV1_DCLK_MASK 0x00000010L 3603 #define UVD_SUVD_CGC_STATUS2__SDB_AV1_DCLK_MASK 0x00000020L 3604 #define UVD_SUVD_CGC_STATUS2__MPC1_DCLK_MASK 0x00000040L 3605 #define UVD_SUVD_CGC_STATUS2__MPC1_SCLK_MASK 0x00000080L 3606 #define UVD_SUVD_CGC_STATUS2__MPC1_VCLK_MASK 0x00000100L 3607 #define UVD_SUVD_CGC_STATUS2__SRE_AV1_ENC_DCLK_MASK 0x00000200L 3608 #define UVD_SUVD_CGC_STATUS2__CDEFE_DCLK_MASK 0x00000400L 3609 #define UVD_SUVD_CGC_STATUS2__SIT0_DCLK_MASK 0x00000800L 3610 #define UVD_SUVD_CGC_STATUS2__SIT1_DCLK_MASK 0x00001000L 3611 #define UVD_SUVD_CGC_STATUS2__SIT2_DCLK_MASK 0x00002000L 3612 #define UVD_SUVD_CGC_STATUS2__FBC_PCLK_MASK 0x10000000L 3613 #define UVD_SUVD_CGC_STATUS2__FBC_CCLK_MASK 0x20000000L 3614 //UVD_SUVD_INT_STATUS2 3615 #define UVD_SUVD_INT_STATUS2__SMPA_FUNC_INT__SHIFT 0x0 3616 #define UVD_SUVD_INT_STATUS2__SMPA_ERR_INT__SHIFT 0x5 3617 #define UVD_SUVD_INT_STATUS2__SDB_AV1_FUNC_INT__SHIFT 0x6 3618 #define UVD_SUVD_INT_STATUS2__SDB_AV1_ERR_INT__SHIFT 0xb 3619 #define UVD_SUVD_INT_STATUS2__SMPA_FUNC_INT_MASK 0x0000001FL 3620 #define UVD_SUVD_INT_STATUS2__SMPA_ERR_INT_MASK 0x00000020L 3621 #define UVD_SUVD_INT_STATUS2__SDB_AV1_FUNC_INT_MASK 0x000007C0L 3622 #define UVD_SUVD_INT_STATUS2__SDB_AV1_ERR_INT_MASK 0x00000800L 3623 //UVD_SUVD_INT_EN2 3624 #define UVD_SUVD_INT_EN2__SMPA_FUNC_INT_EN__SHIFT 0x0 3625 #define UVD_SUVD_INT_EN2__SMPA_ERR_INT_EN__SHIFT 0x5 3626 #define UVD_SUVD_INT_EN2__SDB_AV1_FUNC_INT_EN__SHIFT 0x6 3627 #define UVD_SUVD_INT_EN2__SDB_AV1_ERR_INT_EN__SHIFT 0xb 3628 #define UVD_SUVD_INT_EN2__SMPA_FUNC_INT_EN_MASK 0x0000001FL 3629 #define UVD_SUVD_INT_EN2__SMPA_ERR_INT_EN_MASK 0x00000020L 3630 #define UVD_SUVD_INT_EN2__SDB_AV1_FUNC_INT_EN_MASK 0x000007C0L 3631 #define UVD_SUVD_INT_EN2__SDB_AV1_ERR_INT_EN_MASK 0x00000800L 3632 //UVD_SUVD_INT_ACK2 3633 #define UVD_SUVD_INT_ACK2__SMPA_FUNC_INT_ACK__SHIFT 0x0 3634 #define UVD_SUVD_INT_ACK2__SMPA_ERR_INT_ACK__SHIFT 0x5 3635 #define UVD_SUVD_INT_ACK2__SDB_AV1_FUNC_INT_ACK__SHIFT 0x6 3636 #define UVD_SUVD_INT_ACK2__SDB_AV1_ERR_INT_ACK__SHIFT 0xb 3637 #define UVD_SUVD_INT_ACK2__SMPA_FUNC_INT_ACK_MASK 0x0000001FL 3638 #define UVD_SUVD_INT_ACK2__SMPA_ERR_INT_ACK_MASK 0x00000020L 3639 #define UVD_SUVD_INT_ACK2__SDB_AV1_FUNC_INT_ACK_MASK 0x000007C0L 3640 #define UVD_SUVD_INT_ACK2__SDB_AV1_ERR_INT_ACK_MASK 0x00000800L 3641 //UVD_STATUS 3642 #define UVD_STATUS__RBC_BUSY__SHIFT 0x0 3643 #define UVD_STATUS__VCPU_REPORT__SHIFT 0x1 3644 #define UVD_STATUS__FILL_0__SHIFT 0x8 3645 #define UVD_STATUS__RBC_ACCESS_GPCOM__SHIFT 0x10 3646 #define UVD_STATUS__DRM_BUSY__SHIFT 0x11 3647 #define UVD_STATUS__FILL_1__SHIFT 0x12 3648 #define UVD_STATUS__SYS_GPCOM_REQ__SHIFT 0x1f 3649 #define UVD_STATUS__RBC_BUSY_MASK 0x00000001L 3650 #define UVD_STATUS__VCPU_REPORT_MASK 0x000000FEL 3651 #define UVD_STATUS__FILL_0_MASK 0x0000FF00L 3652 #define UVD_STATUS__RBC_ACCESS_GPCOM_MASK 0x00010000L 3653 #define UVD_STATUS__DRM_BUSY_MASK 0x00020000L 3654 #define UVD_STATUS__FILL_1_MASK 0x7FFC0000L 3655 #define UVD_STATUS__SYS_GPCOM_REQ_MASK 0x80000000L 3656 //UVD_ENC_PIPE_BUSY 3657 #define UVD_ENC_PIPE_BUSY__IME_BUSY__SHIFT 0x0 3658 #define UVD_ENC_PIPE_BUSY__SMP_BUSY__SHIFT 0x1 3659 #define UVD_ENC_PIPE_BUSY__SIT_BUSY__SHIFT 0x2 3660 #define UVD_ENC_PIPE_BUSY__SDB_BUSY__SHIFT 0x3 3661 #define UVD_ENC_PIPE_BUSY__ENT_BUSY__SHIFT 0x4 3662 #define UVD_ENC_PIPE_BUSY__ENT_HEADER_BUSY__SHIFT 0x5 3663 #define UVD_ENC_PIPE_BUSY__LCM_BUSY__SHIFT 0x6 3664 #define UVD_ENC_PIPE_BUSY__MDM_RD_CUR_BUSY__SHIFT 0x7 3665 #define UVD_ENC_PIPE_BUSY__MDM_RD_REF_BUSY__SHIFT 0x8 3666 #define UVD_ENC_PIPE_BUSY__MDM_RD_GEN_BUSY__SHIFT 0x9 3667 #define UVD_ENC_PIPE_BUSY__MDM_WR_RECON_BUSY__SHIFT 0xa 3668 #define UVD_ENC_PIPE_BUSY__MDM_WR_GEN_BUSY__SHIFT 0xb 3669 #define UVD_ENC_PIPE_BUSY__EFC_BUSY__SHIFT 0xc 3670 #define UVD_ENC_PIPE_BUSY__MDM_PPU_BUSY__SHIFT 0xd 3671 #define UVD_ENC_PIPE_BUSY__MIF_AUTODMA_BUSY__SHIFT 0xe 3672 #define UVD_ENC_PIPE_BUSY__CDEFE_BUSY__SHIFT 0xf 3673 #define UVD_ENC_PIPE_BUSY__MIF_RD_CUR_BUSY__SHIFT 0x10 3674 #define UVD_ENC_PIPE_BUSY__MIF_RD_REF0_BUSY__SHIFT 0x11 3675 #define UVD_ENC_PIPE_BUSY__MIF_WR_GEN0_BUSY__SHIFT 0x12 3676 #define UVD_ENC_PIPE_BUSY__MIF_RD_GEN0_BUSY__SHIFT 0x13 3677 #define UVD_ENC_PIPE_BUSY__MIF_WR_GEN1_BUSY__SHIFT 0x14 3678 #define UVD_ENC_PIPE_BUSY__MIF_RD_GEN1_BUSY__SHIFT 0x15 3679 #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP0_BUSY__SHIFT 0x16 3680 #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP1_BUSY__SHIFT 0x17 3681 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD0_BUSY__SHIFT 0x18 3682 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD1_BUSY__SHIFT 0x19 3683 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD2_BUSY__SHIFT 0x1a 3684 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD3_BUSY__SHIFT 0x1b 3685 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD4_BUSY__SHIFT 0x1c 3686 #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP2_BUSY__SHIFT 0x1d 3687 #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP3_BUSY__SHIFT 0x1e 3688 #define UVD_ENC_PIPE_BUSY__SAOE_BUSY__SHIFT 0x1f 3689 #define UVD_ENC_PIPE_BUSY__IME_BUSY_MASK 0x00000001L 3690 #define UVD_ENC_PIPE_BUSY__SMP_BUSY_MASK 0x00000002L 3691 #define UVD_ENC_PIPE_BUSY__SIT_BUSY_MASK 0x00000004L 3692 #define UVD_ENC_PIPE_BUSY__SDB_BUSY_MASK 0x00000008L 3693 #define UVD_ENC_PIPE_BUSY__ENT_BUSY_MASK 0x00000010L 3694 #define UVD_ENC_PIPE_BUSY__ENT_HEADER_BUSY_MASK 0x00000020L 3695 #define UVD_ENC_PIPE_BUSY__LCM_BUSY_MASK 0x00000040L 3696 #define UVD_ENC_PIPE_BUSY__MDM_RD_CUR_BUSY_MASK 0x00000080L 3697 #define UVD_ENC_PIPE_BUSY__MDM_RD_REF_BUSY_MASK 0x00000100L 3698 #define UVD_ENC_PIPE_BUSY__MDM_RD_GEN_BUSY_MASK 0x00000200L 3699 #define UVD_ENC_PIPE_BUSY__MDM_WR_RECON_BUSY_MASK 0x00000400L 3700 #define UVD_ENC_PIPE_BUSY__MDM_WR_GEN_BUSY_MASK 0x00000800L 3701 #define UVD_ENC_PIPE_BUSY__EFC_BUSY_MASK 0x00001000L 3702 #define UVD_ENC_PIPE_BUSY__MDM_PPU_BUSY_MASK 0x00002000L 3703 #define UVD_ENC_PIPE_BUSY__MIF_AUTODMA_BUSY_MASK 0x00004000L 3704 #define UVD_ENC_PIPE_BUSY__CDEFE_BUSY_MASK 0x00008000L 3705 #define UVD_ENC_PIPE_BUSY__MIF_RD_CUR_BUSY_MASK 0x00010000L 3706 #define UVD_ENC_PIPE_BUSY__MIF_RD_REF0_BUSY_MASK 0x00020000L 3707 #define UVD_ENC_PIPE_BUSY__MIF_WR_GEN0_BUSY_MASK 0x00040000L 3708 #define UVD_ENC_PIPE_BUSY__MIF_RD_GEN0_BUSY_MASK 0x00080000L 3709 #define UVD_ENC_PIPE_BUSY__MIF_WR_GEN1_BUSY_MASK 0x00100000L 3710 #define UVD_ENC_PIPE_BUSY__MIF_RD_GEN1_BUSY_MASK 0x00200000L 3711 #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP0_BUSY_MASK 0x00400000L 3712 #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP1_BUSY_MASK 0x00800000L 3713 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD0_BUSY_MASK 0x01000000L 3714 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD1_BUSY_MASK 0x02000000L 3715 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD2_BUSY_MASK 0x04000000L 3716 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD3_BUSY_MASK 0x08000000L 3717 #define UVD_ENC_PIPE_BUSY__MIF_RD_BSD4_BUSY_MASK 0x10000000L 3718 #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP2_BUSY_MASK 0x20000000L 3719 #define UVD_ENC_PIPE_BUSY__MIF_WR_BSP3_BUSY_MASK 0x40000000L 3720 #define UVD_ENC_PIPE_BUSY__SAOE_BUSY_MASK 0x80000000L 3721 //UVD_FW_POWER_STATUS 3722 #define UVD_FW_POWER_STATUS__UVDF_PWR_OFF__SHIFT 0x0 3723 #define UVD_FW_POWER_STATUS__UVDTC_PWR_OFF__SHIFT 0x1 3724 #define UVD_FW_POWER_STATUS__UVDB_PWR_OFF__SHIFT 0x2 3725 #define UVD_FW_POWER_STATUS__UVDTA_PWR_OFF__SHIFT 0x3 3726 #define UVD_FW_POWER_STATUS__UVDTD_PWR_OFF__SHIFT 0x4 3727 #define UVD_FW_POWER_STATUS__UVDTE_PWR_OFF__SHIFT 0x5 3728 #define UVD_FW_POWER_STATUS__UVDE_PWR_OFF__SHIFT 0x6 3729 #define UVD_FW_POWER_STATUS__UVDAB_PWR_OFF__SHIFT 0x7 3730 #define UVD_FW_POWER_STATUS__UVDTB_PWR_OFF__SHIFT 0x8 3731 #define UVD_FW_POWER_STATUS__UVDNA_PWR_OFF__SHIFT 0x9 3732 #define UVD_FW_POWER_STATUS__UVDNB_PWR_OFF__SHIFT 0xa 3733 #define UVD_FW_POWER_STATUS__UVDF_PWR_OFF_MASK 0x00000001L 3734 #define UVD_FW_POWER_STATUS__UVDTC_PWR_OFF_MASK 0x00000002L 3735 #define UVD_FW_POWER_STATUS__UVDB_PWR_OFF_MASK 0x00000004L 3736 #define UVD_FW_POWER_STATUS__UVDTA_PWR_OFF_MASK 0x00000008L 3737 #define UVD_FW_POWER_STATUS__UVDTD_PWR_OFF_MASK 0x00000010L 3738 #define UVD_FW_POWER_STATUS__UVDTE_PWR_OFF_MASK 0x00000020L 3739 #define UVD_FW_POWER_STATUS__UVDE_PWR_OFF_MASK 0x00000040L 3740 #define UVD_FW_POWER_STATUS__UVDAB_PWR_OFF_MASK 0x00000080L 3741 #define UVD_FW_POWER_STATUS__UVDTB_PWR_OFF_MASK 0x00000100L 3742 #define UVD_FW_POWER_STATUS__UVDNA_PWR_OFF_MASK 0x00000200L 3743 #define UVD_FW_POWER_STATUS__UVDNB_PWR_OFF_MASK 0x00000400L 3744 //UVD_CNTL 3745 #define UVD_CNTL__MIF_WR_LOW_THRESHOLD_BP__SHIFT 0x11 3746 #define UVD_CNTL__SUVD_EN__SHIFT 0x13 3747 #define UVD_CNTL__CABAC_MB_ACC__SHIFT 0x1c 3748 #define UVD_CNTL__LRBBM_SAFE_SYNC_DIS__SHIFT 0x1f 3749 #define UVD_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK 0x00020000L 3750 #define UVD_CNTL__SUVD_EN_MASK 0x00080000L 3751 #define UVD_CNTL__CABAC_MB_ACC_MASK 0x10000000L 3752 #define UVD_CNTL__LRBBM_SAFE_SYNC_DIS_MASK 0x80000000L 3753 //UVD_SOFT_RESET 3754 #define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x0 3755 #define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x1 3756 #define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0x2 3757 #define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT 0x3 3758 #define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT 0x4 3759 #define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT 0x6 3760 #define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x7 3761 #define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x8 3762 #define UVD_SOFT_RESET__EFC_SOFT_RESET__SHIFT 0x9 3763 #define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa 3764 #define UVD_SOFT_RESET__MPRD_SOFT_RESET__SHIFT 0xb 3765 #define UVD_SOFT_RESET__IDCT_SOFT_RESET__SHIFT 0xc 3766 #define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0xd 3767 #define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT 0xe 3768 #define UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0xf 3769 #define UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x10 3770 #define UVD_SOFT_RESET__SUVD_SOFT_RESET__SHIFT 0x11 3771 #define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS__SHIFT 0x12 3772 #define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS__SHIFT 0x13 3773 #define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS__SHIFT 0x14 3774 #define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS__SHIFT 0x15 3775 #define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS__SHIFT 0x16 3776 #define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS__SHIFT 0x17 3777 #define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS__SHIFT 0x18 3778 #define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS__SHIFT 0x19 3779 #define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS__SHIFT 0x1a 3780 #define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS__SHIFT 0x1b 3781 #define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS__SHIFT 0x1c 3782 #define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS__SHIFT 0x1d 3783 #define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS__SHIFT 0x1e 3784 #define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS__SHIFT 0x1f 3785 #define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK 0x00000001L 3786 #define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK 0x00000002L 3787 #define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK 0x00000004L 3788 #define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK 0x00000008L 3789 #define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK 0x00000010L 3790 #define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK 0x00000040L 3791 #define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK 0x00000080L 3792 #define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x00000100L 3793 #define UVD_SOFT_RESET__EFC_SOFT_RESET_MASK 0x00000200L 3794 #define UVD_SOFT_RESET__IH_SOFT_RESET_MASK 0x00000400L 3795 #define UVD_SOFT_RESET__MPRD_SOFT_RESET_MASK 0x00000800L 3796 #define UVD_SOFT_RESET__IDCT_SOFT_RESET_MASK 0x00001000L 3797 #define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x00002000L 3798 #define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK 0x00004000L 3799 #define UVD_SOFT_RESET__MIF_SOFT_RESET_MASK 0x00008000L 3800 #define UVD_SOFT_RESET__LCM_SOFT_RESET_MASK 0x00010000L 3801 #define UVD_SOFT_RESET__SUVD_SOFT_RESET_MASK 0x00020000L 3802 #define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS_MASK 0x00040000L 3803 #define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS_MASK 0x00080000L 3804 #define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS_MASK 0x00100000L 3805 #define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS_MASK 0x00200000L 3806 #define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS_MASK 0x00400000L 3807 #define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS_MASK 0x00800000L 3808 #define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS_MASK 0x01000000L 3809 #define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS_MASK 0x02000000L 3810 #define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS_MASK 0x04000000L 3811 #define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS_MASK 0x08000000L 3812 #define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK 0x10000000L 3813 #define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS_MASK 0x20000000L 3814 #define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS_MASK 0x40000000L 3815 #define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS_MASK 0x80000000L 3816 //UVD_SOFT_RESET2 3817 #define UVD_SOFT_RESET2__ATOMIC_SOFT_RESET__SHIFT 0x0 3818 #define UVD_SOFT_RESET2__PPU_SOFT_RESET__SHIFT 0x1 3819 #define UVD_SOFT_RESET2__MMSCH_VCLK_RESET_STATUS__SHIFT 0x10 3820 #define UVD_SOFT_RESET2__MMSCH_SCLK_RESET_STATUS__SHIFT 0x11 3821 #define UVD_SOFT_RESET2__ATOMIC_SOFT_RESET_MASK 0x00000001L 3822 #define UVD_SOFT_RESET2__PPU_SOFT_RESET_MASK 0x00000002L 3823 #define UVD_SOFT_RESET2__MMSCH_VCLK_RESET_STATUS_MASK 0x00010000L 3824 #define UVD_SOFT_RESET2__MMSCH_SCLK_RESET_STATUS_MASK 0x00020000L 3825 //UVD_MMSCH_SOFT_RESET 3826 #define UVD_MMSCH_SOFT_RESET__MMSCH_RESET__SHIFT 0x0 3827 #define UVD_MMSCH_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x1 3828 #define UVD_MMSCH_SOFT_RESET__MMSCH_LOCK__SHIFT 0x1f 3829 #define UVD_MMSCH_SOFT_RESET__MMSCH_RESET_MASK 0x00000001L 3830 #define UVD_MMSCH_SOFT_RESET__TAP_SOFT_RESET_MASK 0x00000002L 3831 #define UVD_MMSCH_SOFT_RESET__MMSCH_LOCK_MASK 0x80000000L 3832 //UVD_WIG_CTRL 3833 #define UVD_WIG_CTRL__AVM_SOFT_RESET__SHIFT 0x0 3834 #define UVD_WIG_CTRL__ACAP_SOFT_RESET__SHIFT 0x1 3835 #define UVD_WIG_CTRL__WIG_SOFT_RESET__SHIFT 0x2 3836 #define UVD_WIG_CTRL__WIG_REGCLK_FORCE_ON__SHIFT 0x3 3837 #define UVD_WIG_CTRL__AVM_REGCLK_FORCE_ON__SHIFT 0x4 3838 #define UVD_WIG_CTRL__AVM_SOFT_RESET_MASK 0x00000001L 3839 #define UVD_WIG_CTRL__ACAP_SOFT_RESET_MASK 0x00000002L 3840 #define UVD_WIG_CTRL__WIG_SOFT_RESET_MASK 0x00000004L 3841 #define UVD_WIG_CTRL__WIG_REGCLK_FORCE_ON_MASK 0x00000008L 3842 #define UVD_WIG_CTRL__AVM_REGCLK_FORCE_ON_MASK 0x00000010L 3843 //UVD_CGC_STATUS 3844 #define UVD_CGC_STATUS__SYS_SCLK__SHIFT 0x0 3845 #define UVD_CGC_STATUS__SYS_DCLK__SHIFT 0x1 3846 #define UVD_CGC_STATUS__SYS_VCLK__SHIFT 0x2 3847 #define UVD_CGC_STATUS__UDEC_SCLK__SHIFT 0x3 3848 #define UVD_CGC_STATUS__UDEC_DCLK__SHIFT 0x4 3849 #define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x5 3850 #define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT 0x6 3851 #define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT 0x7 3852 #define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT 0x8 3853 #define UVD_CGC_STATUS__REGS_SCLK__SHIFT 0x9 3854 #define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0xa 3855 #define UVD_CGC_STATUS__RBC_SCLK__SHIFT 0xb 3856 #define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT 0xc 3857 #define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT 0xd 3858 #define UVD_CGC_STATUS__IDCT_SCLK__SHIFT 0xe 3859 #define UVD_CGC_STATUS__IDCT_VCLK__SHIFT 0xf 3860 #define UVD_CGC_STATUS__MPRD_SCLK__SHIFT 0x10 3861 #define UVD_CGC_STATUS__MPRD_DCLK__SHIFT 0x11 3862 #define UVD_CGC_STATUS__MPRD_VCLK__SHIFT 0x12 3863 #define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x13 3864 #define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14 3865 #define UVD_CGC_STATUS__LBSI_SCLK__SHIFT 0x15 3866 #define UVD_CGC_STATUS__LBSI_VCLK__SHIFT 0x16 3867 #define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT 0x17 3868 #define UVD_CGC_STATUS__WCB_SCLK__SHIFT 0x18 3869 #define UVD_CGC_STATUS__VCPU_SCLK__SHIFT 0x19 3870 #define UVD_CGC_STATUS__VCPU_VCLK__SHIFT 0x1a 3871 #define UVD_CGC_STATUS__MMSCH_SCLK__SHIFT 0x1b 3872 #define UVD_CGC_STATUS__MMSCH_VCLK__SHIFT 0x1c 3873 #define UVD_CGC_STATUS__ALL_ENC_ACTIVE__SHIFT 0x1d 3874 #define UVD_CGC_STATUS__LRBBM_DCLK__SHIFT 0x1e 3875 #define UVD_CGC_STATUS__ALL_DEC_ACTIVE__SHIFT 0x1f 3876 #define UVD_CGC_STATUS__SYS_SCLK_MASK 0x00000001L 3877 #define UVD_CGC_STATUS__SYS_DCLK_MASK 0x00000002L 3878 #define UVD_CGC_STATUS__SYS_VCLK_MASK 0x00000004L 3879 #define UVD_CGC_STATUS__UDEC_SCLK_MASK 0x00000008L 3880 #define UVD_CGC_STATUS__UDEC_DCLK_MASK 0x00000010L 3881 #define UVD_CGC_STATUS__UDEC_VCLK_MASK 0x00000020L 3882 #define UVD_CGC_STATUS__MPEG2_SCLK_MASK 0x00000040L 3883 #define UVD_CGC_STATUS__MPEG2_DCLK_MASK 0x00000080L 3884 #define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x00000100L 3885 #define UVD_CGC_STATUS__REGS_SCLK_MASK 0x00000200L 3886 #define UVD_CGC_STATUS__REGS_VCLK_MASK 0x00000400L 3887 #define UVD_CGC_STATUS__RBC_SCLK_MASK 0x00000800L 3888 #define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x00001000L 3889 #define UVD_CGC_STATUS__LMI_UMC_SCLK_MASK 0x00002000L 3890 #define UVD_CGC_STATUS__IDCT_SCLK_MASK 0x00004000L 3891 #define UVD_CGC_STATUS__IDCT_VCLK_MASK 0x00008000L 3892 #define UVD_CGC_STATUS__MPRD_SCLK_MASK 0x00010000L 3893 #define UVD_CGC_STATUS__MPRD_DCLK_MASK 0x00020000L 3894 #define UVD_CGC_STATUS__MPRD_VCLK_MASK 0x00040000L 3895 #define UVD_CGC_STATUS__MPC_SCLK_MASK 0x00080000L 3896 #define UVD_CGC_STATUS__MPC_DCLK_MASK 0x00100000L 3897 #define UVD_CGC_STATUS__LBSI_SCLK_MASK 0x00200000L 3898 #define UVD_CGC_STATUS__LBSI_VCLK_MASK 0x00400000L 3899 #define UVD_CGC_STATUS__LRBBM_SCLK_MASK 0x00800000L 3900 #define UVD_CGC_STATUS__WCB_SCLK_MASK 0x01000000L 3901 #define UVD_CGC_STATUS__VCPU_SCLK_MASK 0x02000000L 3902 #define UVD_CGC_STATUS__VCPU_VCLK_MASK 0x04000000L 3903 #define UVD_CGC_STATUS__MMSCH_SCLK_MASK 0x08000000L 3904 #define UVD_CGC_STATUS__MMSCH_VCLK_MASK 0x10000000L 3905 #define UVD_CGC_STATUS__ALL_ENC_ACTIVE_MASK 0x20000000L 3906 #define UVD_CGC_STATUS__LRBBM_DCLK_MASK 0x40000000L 3907 #define UVD_CGC_STATUS__ALL_DEC_ACTIVE_MASK 0x80000000L 3908 //UVD_CGC_UDEC_STATUS 3909 #define UVD_CGC_UDEC_STATUS__RE_SCLK__SHIFT 0x0 3910 #define UVD_CGC_UDEC_STATUS__RE_DCLK__SHIFT 0x1 3911 #define UVD_CGC_UDEC_STATUS__RE_VCLK__SHIFT 0x2 3912 #define UVD_CGC_UDEC_STATUS__CM_SCLK__SHIFT 0x3 3913 #define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT 0x4 3914 #define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5 3915 #define UVD_CGC_UDEC_STATUS__IT_SCLK__SHIFT 0x6 3916 #define UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT 0x7 3917 #define UVD_CGC_UDEC_STATUS__IT_VCLK__SHIFT 0x8 3918 #define UVD_CGC_UDEC_STATUS__DB_SCLK__SHIFT 0x9 3919 #define UVD_CGC_UDEC_STATUS__DB_DCLK__SHIFT 0xa 3920 #define UVD_CGC_UDEC_STATUS__DB_VCLK__SHIFT 0xb 3921 #define UVD_CGC_UDEC_STATUS__MP_SCLK__SHIFT 0xc 3922 #define UVD_CGC_UDEC_STATUS__MP_DCLK__SHIFT 0xd 3923 #define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0xe 3924 #define UVD_CGC_UDEC_STATUS__RE_SCLK_MASK 0x00000001L 3925 #define UVD_CGC_UDEC_STATUS__RE_DCLK_MASK 0x00000002L 3926 #define UVD_CGC_UDEC_STATUS__RE_VCLK_MASK 0x00000004L 3927 #define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK 0x00000008L 3928 #define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 0x00000010L 3929 #define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x00000020L 3930 #define UVD_CGC_UDEC_STATUS__IT_SCLK_MASK 0x00000040L 3931 #define UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 0x00000080L 3932 #define UVD_CGC_UDEC_STATUS__IT_VCLK_MASK 0x00000100L 3933 #define UVD_CGC_UDEC_STATUS__DB_SCLK_MASK 0x00000200L 3934 #define UVD_CGC_UDEC_STATUS__DB_DCLK_MASK 0x00000400L 3935 #define UVD_CGC_UDEC_STATUS__DB_VCLK_MASK 0x00000800L 3936 #define UVD_CGC_UDEC_STATUS__MP_SCLK_MASK 0x00001000L 3937 #define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x00002000L 3938 #define UVD_CGC_UDEC_STATUS__MP_VCLK_MASK 0x00004000L 3939 //UVD_SUVD_CGC_STATUS 3940 #define UVD_SUVD_CGC_STATUS__SRE_VCLK__SHIFT 0x0 3941 #define UVD_SUVD_CGC_STATUS__SRE_DCLK__SHIFT 0x1 3942 #define UVD_SUVD_CGC_STATUS__SIT_DCLK__SHIFT 0x2 3943 #define UVD_SUVD_CGC_STATUS__SMP_DCLK__SHIFT 0x3 3944 #define UVD_SUVD_CGC_STATUS__SCM_DCLK__SHIFT 0x4 3945 #define UVD_SUVD_CGC_STATUS__SDB_DCLK__SHIFT 0x5 3946 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT 0x6 3947 #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK__SHIFT 0x7 3948 #define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK__SHIFT 0x8 3949 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK__SHIFT 0x9 3950 #define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK__SHIFT 0xa 3951 #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT 0xb 3952 #define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK__SHIFT 0xc 3953 #define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK__SHIFT 0xd 3954 #define UVD_SUVD_CGC_STATUS__SCLR_DCLK__SHIFT 0xe 3955 #define UVD_SUVD_CGC_STATUS__UVD_SC__SHIFT 0xf 3956 #define UVD_SUVD_CGC_STATUS__ENT_DCLK__SHIFT 0x10 3957 #define UVD_SUVD_CGC_STATUS__IME_DCLK__SHIFT 0x11 3958 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK__SHIFT 0x12 3959 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK__SHIFT 0x13 3960 #define UVD_SUVD_CGC_STATUS__SITE_DCLK__SHIFT 0x14 3961 #define UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK__SHIFT 0x15 3962 #define UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK__SHIFT 0x16 3963 #define UVD_SUVD_CGC_STATUS__SRE_VP9_VCLK__SHIFT 0x17 3964 #define UVD_SUVD_CGC_STATUS__SCM_VP9_VCLK__SHIFT 0x18 3965 #define UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK__SHIFT 0x19 3966 #define UVD_SUVD_CGC_STATUS__SDB_VP9_DCLK__SHIFT 0x1a 3967 #define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK__SHIFT 0x1b 3968 #define UVD_SUVD_CGC_STATUS__EFC_DCLK__SHIFT 0x1c 3969 #define UVD_SUVD_CGC_STATUS__SAOE_DCLK__SHIFT 0x1d 3970 #define UVD_SUVD_CGC_STATUS__SRE_AV1_VCLK__SHIFT 0x1e 3971 #define UVD_SUVD_CGC_STATUS__SCM_AV1_DCLK__SHIFT 0x1f 3972 #define UVD_SUVD_CGC_STATUS__SRE_VCLK_MASK 0x00000001L 3973 #define UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK 0x00000002L 3974 #define UVD_SUVD_CGC_STATUS__SIT_DCLK_MASK 0x00000004L 3975 #define UVD_SUVD_CGC_STATUS__SMP_DCLK_MASK 0x00000008L 3976 #define UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK 0x00000010L 3977 #define UVD_SUVD_CGC_STATUS__SDB_DCLK_MASK 0x00000020L 3978 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK 0x00000040L 3979 #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 0x00000080L 3980 #define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK_MASK 0x00000100L 3981 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK 0x00000200L 3982 #define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK_MASK 0x00000400L 3983 #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK 0x00000800L 3984 #define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK_MASK 0x00001000L 3985 #define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK_MASK 0x00002000L 3986 #define UVD_SUVD_CGC_STATUS__SCLR_DCLK_MASK 0x00004000L 3987 #define UVD_SUVD_CGC_STATUS__UVD_SC_MASK 0x00008000L 3988 #define UVD_SUVD_CGC_STATUS__ENT_DCLK_MASK 0x00010000L 3989 #define UVD_SUVD_CGC_STATUS__IME_DCLK_MASK 0x00020000L 3990 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK_MASK 0x00040000L 3991 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK_MASK 0x00080000L 3992 #define UVD_SUVD_CGC_STATUS__SITE_DCLK_MASK 0x00100000L 3993 #define UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK_MASK 0x00200000L 3994 #define UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK_MASK 0x00400000L 3995 #define UVD_SUVD_CGC_STATUS__SRE_VP9_VCLK_MASK 0x00800000L 3996 #define UVD_SUVD_CGC_STATUS__SCM_VP9_VCLK_MASK 0x01000000L 3997 #define UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK_MASK 0x02000000L 3998 #define UVD_SUVD_CGC_STATUS__SDB_VP9_DCLK_MASK 0x04000000L 3999 #define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK_MASK 0x08000000L 4000 #define UVD_SUVD_CGC_STATUS__EFC_DCLK_MASK 0x10000000L 4001 #define UVD_SUVD_CGC_STATUS__SAOE_DCLK_MASK 0x20000000L 4002 #define UVD_SUVD_CGC_STATUS__SRE_AV1_VCLK_MASK 0x40000000L 4003 #define UVD_SUVD_CGC_STATUS__SCM_AV1_DCLK_MASK 0x80000000L 4004 //UVD_GPCOM_VCPU_CMD 4005 #define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x0 4006 #define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1 4007 #define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT 0x1f 4008 #define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x00000001L 4009 #define UVD_GPCOM_VCPU_CMD__CMD_MASK 0x7FFFFFFEL 4010 #define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK 0x80000000L 4011 4012 4013 // addressBlock: aid_uvd0_ecpudec 4014 //UVD_VCPU_CACHE_OFFSET0 4015 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 4016 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x001FFFFFL 4017 //UVD_VCPU_CACHE_SIZE0 4018 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x0 4019 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x001FFFFFL 4020 //UVD_VCPU_CACHE_OFFSET1 4021 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0 4022 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x001FFFFFL 4023 //UVD_VCPU_CACHE_SIZE1 4024 #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT 0x0 4025 #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x001FFFFFL 4026 //UVD_VCPU_CACHE_OFFSET2 4027 #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0 4028 #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK 0x001FFFFFL 4029 //UVD_VCPU_CACHE_SIZE2 4030 #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x0 4031 #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x001FFFFFL 4032 //UVD_VCPU_CACHE_OFFSET3 4033 #define UVD_VCPU_CACHE_OFFSET3__CACHE_OFFSET3__SHIFT 0x0 4034 #define UVD_VCPU_CACHE_OFFSET3__CACHE_OFFSET3_MASK 0x001FFFFFL 4035 //UVD_VCPU_CACHE_SIZE3 4036 #define UVD_VCPU_CACHE_SIZE3__CACHE_SIZE3__SHIFT 0x0 4037 #define UVD_VCPU_CACHE_SIZE3__CACHE_SIZE3_MASK 0x001FFFFFL 4038 //UVD_VCPU_CACHE_OFFSET4 4039 #define UVD_VCPU_CACHE_OFFSET4__CACHE_OFFSET4__SHIFT 0x0 4040 #define UVD_VCPU_CACHE_OFFSET4__CACHE_OFFSET4_MASK 0x001FFFFFL 4041 //UVD_VCPU_CACHE_SIZE4 4042 #define UVD_VCPU_CACHE_SIZE4__CACHE_SIZE4__SHIFT 0x0 4043 #define UVD_VCPU_CACHE_SIZE4__CACHE_SIZE4_MASK 0x001FFFFFL 4044 //UVD_VCPU_CACHE_OFFSET5 4045 #define UVD_VCPU_CACHE_OFFSET5__CACHE_OFFSET5__SHIFT 0x0 4046 #define UVD_VCPU_CACHE_OFFSET5__CACHE_OFFSET5_MASK 0x001FFFFFL 4047 //UVD_VCPU_CACHE_SIZE5 4048 #define UVD_VCPU_CACHE_SIZE5__CACHE_SIZE5__SHIFT 0x0 4049 #define UVD_VCPU_CACHE_SIZE5__CACHE_SIZE5_MASK 0x001FFFFFL 4050 //UVD_VCPU_CACHE_OFFSET6 4051 #define UVD_VCPU_CACHE_OFFSET6__CACHE_OFFSET6__SHIFT 0x0 4052 #define UVD_VCPU_CACHE_OFFSET6__CACHE_OFFSET6_MASK 0x001FFFFFL 4053 //UVD_VCPU_CACHE_SIZE6 4054 #define UVD_VCPU_CACHE_SIZE6__CACHE_SIZE6__SHIFT 0x0 4055 #define UVD_VCPU_CACHE_SIZE6__CACHE_SIZE6_MASK 0x001FFFFFL 4056 //UVD_VCPU_CACHE_OFFSET7 4057 #define UVD_VCPU_CACHE_OFFSET7__CACHE_OFFSET7__SHIFT 0x0 4058 #define UVD_VCPU_CACHE_OFFSET7__CACHE_OFFSET7_MASK 0x001FFFFFL 4059 //UVD_VCPU_CACHE_SIZE7 4060 #define UVD_VCPU_CACHE_SIZE7__CACHE_SIZE7__SHIFT 0x0 4061 #define UVD_VCPU_CACHE_SIZE7__CACHE_SIZE7_MASK 0x001FFFFFL 4062 //UVD_VCPU_CACHE_OFFSET8 4063 #define UVD_VCPU_CACHE_OFFSET8__CACHE_OFFSET8__SHIFT 0x0 4064 #define UVD_VCPU_CACHE_OFFSET8__CACHE_OFFSET8_MASK 0x001FFFFFL 4065 //UVD_VCPU_CACHE_SIZE8 4066 #define UVD_VCPU_CACHE_SIZE8__CACHE_SIZE8__SHIFT 0x0 4067 #define UVD_VCPU_CACHE_SIZE8__CACHE_SIZE8_MASK 0x001FFFFFL 4068 //UVD_VCPU_NONCACHE_OFFSET0 4069 #define UVD_VCPU_NONCACHE_OFFSET0__NONCACHE_OFFSET0__SHIFT 0x0 4070 #define UVD_VCPU_NONCACHE_OFFSET0__NONCACHE_OFFSET0_MASK 0x01FFFFFFL 4071 //UVD_VCPU_NONCACHE_SIZE0 4072 #define UVD_VCPU_NONCACHE_SIZE0__NONCACHE_SIZE0__SHIFT 0x0 4073 #define UVD_VCPU_NONCACHE_SIZE0__NONCACHE_SIZE0_MASK 0x001FFFFFL 4074 //UVD_VCPU_NONCACHE_OFFSET1 4075 #define UVD_VCPU_NONCACHE_OFFSET1__NONCACHE_OFFSET1__SHIFT 0x0 4076 #define UVD_VCPU_NONCACHE_OFFSET1__NONCACHE_OFFSET1_MASK 0x01FFFFFFL 4077 //UVD_VCPU_NONCACHE_SIZE1 4078 #define UVD_VCPU_NONCACHE_SIZE1__NONCACHE_SIZE1__SHIFT 0x0 4079 #define UVD_VCPU_NONCACHE_SIZE1__NONCACHE_SIZE1_MASK 0x001FFFFFL 4080 //UVD_VCPU_CNTL 4081 #define UVD_VCPU_CNTL__IRQ_ERR__SHIFT 0x0 4082 #define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4__SHIFT 0x4 4083 #define UVD_VCPU_CNTL__PMB_ED_ENABLE__SHIFT 0x5 4084 #define UVD_VCPU_CNTL__PMB_SOFT_RESET__SHIFT 0x6 4085 #define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x7 4086 #define UVD_VCPU_CNTL__ABORT_REQ__SHIFT 0x8 4087 #define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x9 4088 #define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0xa 4089 #define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0xb 4090 #define UVD_VCPU_CNTL__DBG_MUX__SHIFT 0xd 4091 #define UVD_VCPU_CNTL__JTAG_EN__SHIFT 0x10 4092 #define UVD_VCPU_CNTL__TIMEOUT_DIS__SHIFT 0x12 4093 #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14 4094 #define UVD_VCPU_CNTL__BLK_RST__SHIFT 0x1c 4095 #define UVD_VCPU_CNTL__RUNSTALL__SHIFT 0x1d 4096 #define UVD_VCPU_CNTL__SRE_CMDIF_DRST__SHIFT 0x1e 4097 #define UVD_VCPU_CNTL__SRE_CMDIF_VRST__SHIFT 0x1f 4098 #define UVD_VCPU_CNTL__IRQ_ERR_MASK 0x0000000FL 4099 #define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4_MASK 0x00000010L 4100 #define UVD_VCPU_CNTL__PMB_ED_ENABLE_MASK 0x00000020L 4101 #define UVD_VCPU_CNTL__PMB_SOFT_RESET_MASK 0x00000040L 4102 #define UVD_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x00000080L 4103 #define UVD_VCPU_CNTL__ABORT_REQ_MASK 0x00000100L 4104 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x00000200L 4105 #define UVD_VCPU_CNTL__TRCE_EN_MASK 0x00000400L 4106 #define UVD_VCPU_CNTL__TRCE_MUX_MASK 0x00001800L 4107 #define UVD_VCPU_CNTL__DBG_MUX_MASK 0x0000E000L 4108 #define UVD_VCPU_CNTL__JTAG_EN_MASK 0x00010000L 4109 #define UVD_VCPU_CNTL__TIMEOUT_DIS_MASK 0x00040000L 4110 #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL_MASK 0x0FF00000L 4111 #define UVD_VCPU_CNTL__BLK_RST_MASK 0x10000000L 4112 #define UVD_VCPU_CNTL__RUNSTALL_MASK 0x20000000L 4113 #define UVD_VCPU_CNTL__SRE_CMDIF_DRST_MASK 0x40000000L 4114 #define UVD_VCPU_CNTL__SRE_CMDIF_VRST_MASK 0x80000000L 4115 //UVD_VCPU_PRID 4116 #define UVD_VCPU_PRID__PRID__SHIFT 0x0 4117 #define UVD_VCPU_PRID__PRID_MASK 0x0000FFFFL 4118 //UVD_VCPU_TRCE 4119 #define UVD_VCPU_TRCE__PC__SHIFT 0x0 4120 #define UVD_VCPU_TRCE__PC_MASK 0x0FFFFFFFL 4121 //UVD_VCPU_TRCE_RD 4122 #define UVD_VCPU_TRCE_RD__DATA__SHIFT 0x0 4123 #define UVD_VCPU_TRCE_RD__DATA_MASK 0xFFFFFFFFL 4124 //UVD_VCPU_IND_INDEX 4125 #define UVD_VCPU_IND_INDEX__INDEX__SHIFT 0x0 4126 #define UVD_VCPU_IND_INDEX__INDEX_MASK 0x000001FFL 4127 //UVD_VCPU_IND_DATA 4128 #define UVD_VCPU_IND_DATA__DATA__SHIFT 0x0 4129 #define UVD_VCPU_IND_DATA__DATA_MASK 0xFFFFFFFFL 4130 4131 4132 // addressBlock: aid_uvd0_uvd_mpcdec 4133 //UVD_MP_SWAP_CNTL 4134 #define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP__SHIFT 0x0 4135 #define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP__SHIFT 0x2 4136 #define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP__SHIFT 0x4 4137 #define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP__SHIFT 0x6 4138 #define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP__SHIFT 0x8 4139 #define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP__SHIFT 0xa 4140 #define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP__SHIFT 0xc 4141 #define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP__SHIFT 0xe 4142 #define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP__SHIFT 0x10 4143 #define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP__SHIFT 0x12 4144 #define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP__SHIFT 0x14 4145 #define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP__SHIFT 0x16 4146 #define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP__SHIFT 0x18 4147 #define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP__SHIFT 0x1a 4148 #define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP__SHIFT 0x1c 4149 #define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP__SHIFT 0x1e 4150 #define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP_MASK 0x00000003L 4151 #define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP_MASK 0x0000000CL 4152 #define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP_MASK 0x00000030L 4153 #define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP_MASK 0x000000C0L 4154 #define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP_MASK 0x00000300L 4155 #define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP_MASK 0x00000C00L 4156 #define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP_MASK 0x00003000L 4157 #define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP_MASK 0x0000C000L 4158 #define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP_MASK 0x00030000L 4159 #define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP_MASK 0x000C0000L 4160 #define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP_MASK 0x00300000L 4161 #define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP_MASK 0x00C00000L 4162 #define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP_MASK 0x03000000L 4163 #define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP_MASK 0x0C000000L 4164 #define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP_MASK 0x30000000L 4165 #define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP_MASK 0xC0000000L 4166 //UVD_MP_SWAP_CNTL2 4167 #define UVD_MP_SWAP_CNTL2__MP_REF16_MC_SWAP__SHIFT 0x0 4168 #define UVD_MP_SWAP_CNTL2__MP_REF16_MC_SWAP_MASK 0x00000003L 4169 //UVD_MPC_LUMA_SRCH 4170 #define UVD_MPC_LUMA_SRCH__CNTR__SHIFT 0x0 4171 #define UVD_MPC_LUMA_SRCH__CNTR_MASK 0xFFFFFFFFL 4172 //UVD_MPC_LUMA_HIT 4173 #define UVD_MPC_LUMA_HIT__CNTR__SHIFT 0x0 4174 #define UVD_MPC_LUMA_HIT__CNTR_MASK 0xFFFFFFFFL 4175 //UVD_MPC_LUMA_HITPEND 4176 #define UVD_MPC_LUMA_HITPEND__CNTR__SHIFT 0x0 4177 #define UVD_MPC_LUMA_HITPEND__CNTR_MASK 0xFFFFFFFFL 4178 //UVD_MPC_CHROMA_SRCH 4179 #define UVD_MPC_CHROMA_SRCH__CNTR__SHIFT 0x0 4180 #define UVD_MPC_CHROMA_SRCH__CNTR_MASK 0xFFFFFFFFL 4181 //UVD_MPC_CHROMA_HIT 4182 #define UVD_MPC_CHROMA_HIT__CNTR__SHIFT 0x0 4183 #define UVD_MPC_CHROMA_HIT__CNTR_MASK 0xFFFFFFFFL 4184 //UVD_MPC_CHROMA_HITPEND 4185 #define UVD_MPC_CHROMA_HITPEND__CNTR__SHIFT 0x0 4186 #define UVD_MPC_CHROMA_HITPEND__CNTR_MASK 0xFFFFFFFFL 4187 //UVD_MPC_CNTL 4188 #define UVD_MPC_CNTL__BLK_RST__SHIFT 0x0 4189 #define UVD_MPC_CNTL__REG_MPC1_PERF_SELECT__SHIFT 0x1 4190 #define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3 4191 #define UVD_MPC_CNTL__PERF_RST__SHIFT 0x6 4192 #define UVD_MPC_CNTL__REG_MPC_CNTL_BACKWARD_COMPATIBILITY__SHIFT 0x7 4193 #define UVD_MPC_CNTL__DBG_MUX__SHIFT 0x8 4194 #define UVD_MPC_CNTL__AVE_WEIGHT__SHIFT 0x10 4195 #define UVD_MPC_CNTL__URGENT_EN__SHIFT 0x12 4196 #define UVD_MPC_CNTL__SMPAT_REQ_SPEED_UP__SHIFT 0x13 4197 #define UVD_MPC_CNTL__TEST_MODE_EN__SHIFT 0x14 4198 #define UVD_MPC_CNTL__BLK_RST_MASK 0x00000001L 4199 #define UVD_MPC_CNTL__REG_MPC1_PERF_SELECT_MASK 0x00000002L 4200 #define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x00000038L 4201 #define UVD_MPC_CNTL__PERF_RST_MASK 0x00000040L 4202 #define UVD_MPC_CNTL__REG_MPC_CNTL_BACKWARD_COMPATIBILITY_MASK 0x00000080L 4203 #define UVD_MPC_CNTL__DBG_MUX_MASK 0x00000F00L 4204 #define UVD_MPC_CNTL__AVE_WEIGHT_MASK 0x00030000L 4205 #define UVD_MPC_CNTL__URGENT_EN_MASK 0x00040000L 4206 #define UVD_MPC_CNTL__SMPAT_REQ_SPEED_UP_MASK 0x00080000L 4207 #define UVD_MPC_CNTL__TEST_MODE_EN_MASK 0x00300000L 4208 //UVD_MPC_PITCH 4209 #define UVD_MPC_PITCH__LUMA_PITCH__SHIFT 0x0 4210 #define UVD_MPC_PITCH__LUMA_PITCH_MASK 0x000007FFL 4211 //UVD_MPC_SET_MUXA0 4212 #define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0 4213 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6 4214 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc 4215 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12 4216 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18 4217 #define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x0000003FL 4218 #define UVD_MPC_SET_MUXA0__VARA_1_MASK 0x00000FC0L 4219 #define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x0003F000L 4220 #define UVD_MPC_SET_MUXA0__VARA_3_MASK 0x00FC0000L 4221 #define UVD_MPC_SET_MUXA0__VARA_4_MASK 0x3F000000L 4222 //UVD_MPC_SET_MUXA1 4223 #define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0 4224 #define UVD_MPC_SET_MUXA1__VARA_6__SHIFT 0x6 4225 #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc 4226 #define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x0000003FL 4227 #define UVD_MPC_SET_MUXA1__VARA_6_MASK 0x00000FC0L 4228 #define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x0003F000L 4229 //UVD_MPC_SET_MUXB0 4230 #define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0 4231 #define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6 4232 #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc 4233 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12 4234 #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18 4235 #define UVD_MPC_SET_MUXB0__VARB_0_MASK 0x0000003FL 4236 #define UVD_MPC_SET_MUXB0__VARB_1_MASK 0x00000FC0L 4237 #define UVD_MPC_SET_MUXB0__VARB_2_MASK 0x0003F000L 4238 #define UVD_MPC_SET_MUXB0__VARB_3_MASK 0x00FC0000L 4239 #define UVD_MPC_SET_MUXB0__VARB_4_MASK 0x3F000000L 4240 //UVD_MPC_SET_MUXB1 4241 #define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x0 4242 #define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6 4243 #define UVD_MPC_SET_MUXB1__VARB_7__SHIFT 0xc 4244 #define UVD_MPC_SET_MUXB1__VARB_5_MASK 0x0000003FL 4245 #define UVD_MPC_SET_MUXB1__VARB_6_MASK 0x00000FC0L 4246 #define UVD_MPC_SET_MUXB1__VARB_7_MASK 0x0003F000L 4247 //UVD_MPC_SET_MUX 4248 #define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0 4249 #define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3 4250 #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6 4251 #define UVD_MPC_SET_MUX__SET_0_MASK 0x00000007L 4252 #define UVD_MPC_SET_MUX__SET_1_MASK 0x00000038L 4253 #define UVD_MPC_SET_MUX__SET_2_MASK 0x000001C0L 4254 //UVD_MPC_SET_ALU 4255 #define UVD_MPC_SET_ALU__FUNCT__SHIFT 0x0 4256 #define UVD_MPC_SET_ALU__OPERAND__SHIFT 0x4 4257 #define UVD_MPC_SET_ALU__FUNCT_MASK 0x00000007L 4258 #define UVD_MPC_SET_ALU__OPERAND_MASK 0x00000FF0L 4259 //UVD_MPC_PERF0 4260 #define UVD_MPC_PERF0__MAX_LAT__SHIFT 0x0 4261 #define UVD_MPC_PERF0__MAX_LAT_MASK 0x000003FFL 4262 //UVD_MPC_PERF1 4263 #define UVD_MPC_PERF1__AVE_LAT__SHIFT 0x0 4264 #define UVD_MPC_PERF1__AVE_LAT_MASK 0x000003FFL 4265 //UVD_MPC_IND_INDEX 4266 #define UVD_MPC_IND_INDEX__INDEX__SHIFT 0x0 4267 #define UVD_MPC_IND_INDEX__INDEX_MASK 0x000001FFL 4268 //UVD_MPC_IND_DATA 4269 #define UVD_MPC_IND_DATA__DATA__SHIFT 0x0 4270 #define UVD_MPC_IND_DATA__DATA_MASK 0xFFFFFFFFL 4271 4272 4273 // addressBlock: aid_uvd0_uvd_rbcdec 4274 //UVD_RBC_IB_SIZE 4275 #define UVD_RBC_IB_SIZE__IB_SIZE__SHIFT 0x4 4276 #define UVD_RBC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L 4277 //UVD_RBC_IB_SIZE_UPDATE 4278 #define UVD_RBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4 4279 #define UVD_RBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L 4280 //UVD_RBC_RB_CNTL 4281 #define UVD_RBC_RB_CNTL__RB_BUFSZ__SHIFT 0x0 4282 #define UVD_RBC_RB_CNTL__RB_BLKSZ__SHIFT 0x8 4283 #define UVD_RBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x10 4284 #define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x14 4285 #define UVD_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT 0x18 4286 #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1c 4287 #define UVD_RBC_RB_CNTL__BLK_RST__SHIFT 0x1d 4288 #define UVD_RBC_RB_CNTL__RB_BUFSZ_MASK 0x0000001FL 4289 #define UVD_RBC_RB_CNTL__RB_BLKSZ_MASK 0x00001F00L 4290 #define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x00010000L 4291 #define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK 0x00100000L 4292 #define UVD_RBC_RB_CNTL__RB_NO_UPDATE_MASK 0x01000000L 4293 #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000L 4294 #define UVD_RBC_RB_CNTL__BLK_RST_MASK 0x20000000L 4295 //UVD_RBC_RB_RPTR_ADDR 4296 #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x0 4297 #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFFL 4298 //UVD_RBC_VCPU_ACCESS 4299 #define UVD_RBC_VCPU_ACCESS__ENABLE_RBC__SHIFT 0x0 4300 #define UVD_RBC_VCPU_ACCESS__ENABLE_RBC_MASK 0x00000001L 4301 //UVD_FW_SEMAPHORE_CNTL 4302 #define UVD_FW_SEMAPHORE_CNTL__START__SHIFT 0x0 4303 #define UVD_FW_SEMAPHORE_CNTL__BUSY__SHIFT 0x8 4304 #define UVD_FW_SEMAPHORE_CNTL__PASS__SHIFT 0x9 4305 #define UVD_FW_SEMAPHORE_CNTL__START_MASK 0x00000001L 4306 #define UVD_FW_SEMAPHORE_CNTL__BUSY_MASK 0x00000100L 4307 #define UVD_FW_SEMAPHORE_CNTL__PASS_MASK 0x00000200L 4308 //UVD_RBC_READ_REQ_URGENT_CNTL 4309 #define UVD_RBC_READ_REQ_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0 4310 #define UVD_RBC_READ_REQ_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L 4311 //UVD_RBC_RB_WPTR_CNTL 4312 #define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x0 4313 #define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER_MASK 0x00007FFFL 4314 //UVD_RBC_WPTR_STATUS 4315 #define UVD_RBC_WPTR_STATUS__RB_WPTR_IN_USE__SHIFT 0x4 4316 #define UVD_RBC_WPTR_STATUS__RB_WPTR_IN_USE_MASK 0x007FFFF0L 4317 //UVD_RBC_WPTR_POLL_CNTL 4318 #define UVD_RBC_WPTR_POLL_CNTL__POLL_FREQ__SHIFT 0x0 4319 #define UVD_RBC_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 4320 #define UVD_RBC_WPTR_POLL_CNTL__POLL_FREQ_MASK 0x0000FFFFL 4321 #define UVD_RBC_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 4322 //UVD_RBC_WPTR_POLL_ADDR 4323 #define UVD_RBC_WPTR_POLL_ADDR__POLL_ADDR__SHIFT 0x2 4324 #define UVD_RBC_WPTR_POLL_ADDR__POLL_ADDR_MASK 0xFFFFFFFCL 4325 //UVD_SEMA_CMD 4326 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0 4327 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4 4328 #define UVD_SEMA_CMD__MODE__SHIFT 0x6 4329 #define UVD_SEMA_CMD__VMID_EN__SHIFT 0x7 4330 #define UVD_SEMA_CMD__VMID__SHIFT 0x8 4331 #define UVD_SEMA_CMD__REQ_CMD_MASK 0x0000000FL 4332 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x00000030L 4333 #define UVD_SEMA_CMD__MODE_MASK 0x00000040L 4334 #define UVD_SEMA_CMD__VMID_EN_MASK 0x00000080L 4335 #define UVD_SEMA_CMD__VMID_MASK 0x00000F00L 4336 //UVD_SEMA_ADDR_LOW 4337 #define UVD_SEMA_ADDR_LOW__ADDR_26_3__SHIFT 0x0 4338 #define UVD_SEMA_ADDR_LOW__ADDR_26_3_MASK 0x00FFFFFFL 4339 //UVD_SEMA_ADDR_HIGH 4340 #define UVD_SEMA_ADDR_HIGH__ADDR_47_27__SHIFT 0x0 4341 #define UVD_SEMA_ADDR_HIGH__ADDR_47_27_MASK 0x001FFFFFL 4342 //UVD_ENGINE_CNTL 4343 #define UVD_ENGINE_CNTL__ENGINE_START__SHIFT 0x0 4344 #define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x1 4345 #define UVD_ENGINE_CNTL__NJ_PF_HANDLE_DISABLE__SHIFT 0x2 4346 #define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x00000001L 4347 #define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x00000002L 4348 #define UVD_ENGINE_CNTL__NJ_PF_HANDLE_DISABLE_MASK 0x00000004L 4349 //UVD_SEMA_TIMEOUT_STATUS 4350 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x0 4351 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT__SHIFT 0x1 4352 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x2 4353 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR__SHIFT 0x3 4354 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT_MASK 0x00000001L 4355 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK 0x00000002L 4356 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT_MASK 0x00000004L 4357 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR_MASK 0x00000008L 4358 //UVD_SEMA_CNTL 4359 #define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x0 4360 #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT 0x1 4361 #define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK 0x00000001L 4362 #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK 0x00000002L 4363 //UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 4364 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN__SHIFT 0x0 4365 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT__SHIFT 0x1 4366 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 4367 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN_MASK 0x00000001L 4368 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT_MASK 0x001FFFFEL 4369 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L 4370 //UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 4371 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN__SHIFT 0x0 4372 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT__SHIFT 0x1 4373 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 4374 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN_MASK 0x00000001L 4375 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT_MASK 0x001FFFFEL 4376 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L 4377 //UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 4378 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN__SHIFT 0x0 4379 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT__SHIFT 0x1 4380 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 4381 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN_MASK 0x00000001L 4382 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT_MASK 0x001FFFFEL 4383 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L 4384 //UVD_JOB_START 4385 #define UVD_JOB_START__JOB_START__SHIFT 0x0 4386 #define UVD_JOB_START__JOB_START_MASK 0x00000001L 4387 //UVD_RBC_BUF_STATUS 4388 #define UVD_RBC_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0 4389 #define UVD_RBC_BUF_STATUS__IB_BUF_VALID__SHIFT 0x8 4390 #define UVD_RBC_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10 4391 #define UVD_RBC_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x13 4392 #define UVD_RBC_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x16 4393 #define UVD_RBC_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x19 4394 #define UVD_RBC_BUF_STATUS__RB_BUF_VALID_MASK 0x000000FFL 4395 #define UVD_RBC_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FF00L 4396 #define UVD_RBC_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x00070000L 4397 #define UVD_RBC_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x00380000L 4398 #define UVD_RBC_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x01C00000L 4399 #define UVD_RBC_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x0E000000L 4400 //UVD_RBC_SWAP_CNTL 4401 #define UVD_RBC_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 4402 #define UVD_RBC_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 4403 #define UVD_RBC_SWAP_CNTL__RB_RPTR_MC_SWAP__SHIFT 0x4 4404 #define UVD_RBC_SWAP_CNTL__RB_WR_MC_SWAP__SHIFT 0x1a 4405 #define UVD_RBC_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L 4406 #define UVD_RBC_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL 4407 #define UVD_RBC_SWAP_CNTL__RB_RPTR_MC_SWAP_MASK 0x00000030L 4408 #define UVD_RBC_SWAP_CNTL__RB_WR_MC_SWAP_MASK 0x0C000000L 4409 4410 4411 // addressBlock: aid_uvd0_lmi_adpdec 4412 //UVD_LMI_RE_64BIT_BAR_LOW 4413 #define UVD_LMI_RE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4414 #define UVD_LMI_RE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4415 //UVD_LMI_RE_64BIT_BAR_HIGH 4416 #define UVD_LMI_RE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4417 #define UVD_LMI_RE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4418 //UVD_LMI_IT_64BIT_BAR_LOW 4419 #define UVD_LMI_IT_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4420 #define UVD_LMI_IT_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4421 //UVD_LMI_IT_64BIT_BAR_HIGH 4422 #define UVD_LMI_IT_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4423 #define UVD_LMI_IT_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4424 //UVD_LMI_MP_64BIT_BAR_LOW 4425 #define UVD_LMI_MP_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4426 #define UVD_LMI_MP_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4427 //UVD_LMI_MP_64BIT_BAR_HIGH 4428 #define UVD_LMI_MP_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4429 #define UVD_LMI_MP_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4430 //UVD_LMI_CM_64BIT_BAR_LOW 4431 #define UVD_LMI_CM_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4432 #define UVD_LMI_CM_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4433 //UVD_LMI_CM_64BIT_BAR_HIGH 4434 #define UVD_LMI_CM_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4435 #define UVD_LMI_CM_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4436 //UVD_LMI_DB_64BIT_BAR_LOW 4437 #define UVD_LMI_DB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4438 #define UVD_LMI_DB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4439 //UVD_LMI_DB_64BIT_BAR_HIGH 4440 #define UVD_LMI_DB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4441 #define UVD_LMI_DB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4442 //UVD_LMI_DBW_64BIT_BAR_LOW 4443 #define UVD_LMI_DBW_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4444 #define UVD_LMI_DBW_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4445 //UVD_LMI_DBW_64BIT_BAR_HIGH 4446 #define UVD_LMI_DBW_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4447 #define UVD_LMI_DBW_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4448 //UVD_LMI_IDCT_64BIT_BAR_LOW 4449 #define UVD_LMI_IDCT_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4450 #define UVD_LMI_IDCT_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4451 //UVD_LMI_IDCT_64BIT_BAR_HIGH 4452 #define UVD_LMI_IDCT_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4453 #define UVD_LMI_IDCT_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4454 //UVD_LMI_MPRD_S0_64BIT_BAR_LOW 4455 #define UVD_LMI_MPRD_S0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4456 #define UVD_LMI_MPRD_S0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4457 //UVD_LMI_MPRD_S0_64BIT_BAR_HIGH 4458 #define UVD_LMI_MPRD_S0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4459 #define UVD_LMI_MPRD_S0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4460 //UVD_LMI_MPRD_S1_64BIT_BAR_LOW 4461 #define UVD_LMI_MPRD_S1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4462 #define UVD_LMI_MPRD_S1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4463 //UVD_LMI_MPRD_S1_64BIT_BAR_HIGH 4464 #define UVD_LMI_MPRD_S1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4465 #define UVD_LMI_MPRD_S1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4466 //UVD_LMI_MPRD_DBW_64BIT_BAR_LOW 4467 #define UVD_LMI_MPRD_DBW_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4468 #define UVD_LMI_MPRD_DBW_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4469 //UVD_LMI_MPRD_DBW_64BIT_BAR_HIGH 4470 #define UVD_LMI_MPRD_DBW_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4471 #define UVD_LMI_MPRD_DBW_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4472 //UVD_LMI_MPC_64BIT_BAR_LOW 4473 #define UVD_LMI_MPC_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4474 #define UVD_LMI_MPC_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4475 //UVD_LMI_MPC_64BIT_BAR_HIGH 4476 #define UVD_LMI_MPC_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4477 #define UVD_LMI_MPC_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4478 //UVD_LMI_RBC_RB_64BIT_BAR_LOW 4479 #define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4480 #define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4481 //UVD_LMI_RBC_RB_64BIT_BAR_HIGH 4482 #define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4483 #define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4484 //UVD_LMI_RBC_IB_64BIT_BAR_LOW 4485 #define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4486 #define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4487 //UVD_LMI_RBC_IB_64BIT_BAR_HIGH 4488 #define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4489 #define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4490 //UVD_LMI_LBSI_64BIT_BAR_LOW 4491 #define UVD_LMI_LBSI_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4492 #define UVD_LMI_LBSI_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4493 //UVD_LMI_LBSI_64BIT_BAR_HIGH 4494 #define UVD_LMI_LBSI_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4495 #define UVD_LMI_LBSI_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4496 //UVD_LMI_VCPU_NC0_64BIT_BAR_LOW 4497 #define UVD_LMI_VCPU_NC0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4498 #define UVD_LMI_VCPU_NC0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4499 //UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH 4500 #define UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4501 #define UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4502 //UVD_LMI_VCPU_NC1_64BIT_BAR_LOW 4503 #define UVD_LMI_VCPU_NC1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4504 #define UVD_LMI_VCPU_NC1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4505 //UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH 4506 #define UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4507 #define UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4508 //UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 4509 #define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4510 #define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4511 //UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH 4512 #define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4513 #define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4514 //UVD_LMI_CENC_64BIT_BAR_LOW 4515 #define UVD_LMI_CENC_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4516 #define UVD_LMI_CENC_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4517 //UVD_LMI_CENC_64BIT_BAR_HIGH 4518 #define UVD_LMI_CENC_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4519 #define UVD_LMI_CENC_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4520 //UVD_LMI_SRE_64BIT_BAR_LOW 4521 #define UVD_LMI_SRE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4522 #define UVD_LMI_SRE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4523 //UVD_LMI_SRE_64BIT_BAR_HIGH 4524 #define UVD_LMI_SRE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4525 #define UVD_LMI_SRE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4526 //UVD_LMI_MIF_GPGPU_64BIT_BAR_LOW 4527 #define UVD_LMI_MIF_GPGPU_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4528 #define UVD_LMI_MIF_GPGPU_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4529 //UVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH 4530 #define UVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4531 #define UVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4532 //UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW 4533 #define UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4534 #define UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4535 //UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH 4536 #define UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4537 #define UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4538 //UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW 4539 #define UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4540 #define UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4541 //UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH 4542 #define UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4543 #define UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4544 //UVD_LMI_MIF_REF_64BIT_BAR_LOW 4545 #define UVD_LMI_MIF_REF_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4546 #define UVD_LMI_MIF_REF_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4547 //UVD_LMI_MIF_REF_64BIT_BAR_HIGH 4548 #define UVD_LMI_MIF_REF_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4549 #define UVD_LMI_MIF_REF_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4550 //UVD_LMI_MIF_DBW_64BIT_BAR_LOW 4551 #define UVD_LMI_MIF_DBW_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4552 #define UVD_LMI_MIF_DBW_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4553 //UVD_LMI_MIF_DBW_64BIT_BAR_HIGH 4554 #define UVD_LMI_MIF_DBW_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4555 #define UVD_LMI_MIF_DBW_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4556 //UVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW 4557 #define UVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4558 #define UVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4559 //UVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH 4560 #define UVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4561 #define UVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4562 //UVD_LMI_MIF_BSP0_64BIT_BAR_LOW 4563 #define UVD_LMI_MIF_BSP0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4564 #define UVD_LMI_MIF_BSP0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4565 //UVD_LMI_MIF_BSP0_64BIT_BAR_HIGH 4566 #define UVD_LMI_MIF_BSP0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4567 #define UVD_LMI_MIF_BSP0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4568 //UVD_LMI_MIF_BSP1_64BIT_BAR_LOW 4569 #define UVD_LMI_MIF_BSP1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4570 #define UVD_LMI_MIF_BSP1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4571 //UVD_LMI_MIF_BSP1_64BIT_BAR_HIGH 4572 #define UVD_LMI_MIF_BSP1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4573 #define UVD_LMI_MIF_BSP1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4574 //UVD_LMI_MIF_BSP2_64BIT_BAR_LOW 4575 #define UVD_LMI_MIF_BSP2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4576 #define UVD_LMI_MIF_BSP2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4577 //UVD_LMI_MIF_BSP2_64BIT_BAR_HIGH 4578 #define UVD_LMI_MIF_BSP2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4579 #define UVD_LMI_MIF_BSP2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4580 //UVD_LMI_MIF_BSP3_64BIT_BAR_LOW 4581 #define UVD_LMI_MIF_BSP3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4582 #define UVD_LMI_MIF_BSP3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4583 //UVD_LMI_MIF_BSP3_64BIT_BAR_HIGH 4584 #define UVD_LMI_MIF_BSP3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4585 #define UVD_LMI_MIF_BSP3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4586 //UVD_LMI_MIF_BSD0_64BIT_BAR_LOW 4587 #define UVD_LMI_MIF_BSD0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4588 #define UVD_LMI_MIF_BSD0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4589 //UVD_LMI_MIF_BSD0_64BIT_BAR_HIGH 4590 #define UVD_LMI_MIF_BSD0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4591 #define UVD_LMI_MIF_BSD0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4592 //UVD_LMI_MIF_BSD1_64BIT_BAR_LOW 4593 #define UVD_LMI_MIF_BSD1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4594 #define UVD_LMI_MIF_BSD1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4595 //UVD_LMI_MIF_BSD1_64BIT_BAR_HIGH 4596 #define UVD_LMI_MIF_BSD1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4597 #define UVD_LMI_MIF_BSD1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4598 //UVD_LMI_MIF_BSD2_64BIT_BAR_LOW 4599 #define UVD_LMI_MIF_BSD2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4600 #define UVD_LMI_MIF_BSD2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4601 //UVD_LMI_MIF_BSD2_64BIT_BAR_HIGH 4602 #define UVD_LMI_MIF_BSD2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4603 #define UVD_LMI_MIF_BSD2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4604 //UVD_LMI_MIF_BSD3_64BIT_BAR_LOW 4605 #define UVD_LMI_MIF_BSD3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4606 #define UVD_LMI_MIF_BSD3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4607 //UVD_LMI_MIF_BSD3_64BIT_BAR_HIGH 4608 #define UVD_LMI_MIF_BSD3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4609 #define UVD_LMI_MIF_BSD3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4610 //UVD_LMI_MIF_BSD4_64BIT_BAR_LOW 4611 #define UVD_LMI_MIF_BSD4_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4612 #define UVD_LMI_MIF_BSD4_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4613 //UVD_LMI_MIF_BSD4_64BIT_BAR_HIGH 4614 #define UVD_LMI_MIF_BSD4_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4615 #define UVD_LMI_MIF_BSD4_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4616 //UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW 4617 #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4618 #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4619 //UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH 4620 #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4621 #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4622 //UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW 4623 #define UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4624 #define UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4625 //UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH 4626 #define UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4627 #define UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4628 //UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW 4629 #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4630 #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4631 //UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH 4632 #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4633 #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4634 //UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW 4635 #define UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4636 #define UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4637 //UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH 4638 #define UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4639 #define UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4640 //UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW 4641 #define UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4642 #define UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4643 //UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH 4644 #define UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4645 #define UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4646 //UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW 4647 #define UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4648 #define UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4649 //UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH 4650 #define UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4651 #define UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4652 //UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW 4653 #define UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4654 #define UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4655 //UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH 4656 #define UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4657 #define UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4658 //UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW 4659 #define UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4660 #define UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4661 //UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH 4662 #define UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4663 #define UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4664 //UVD_LMI_MIF_SCLR_64BIT_BAR_LOW 4665 #define UVD_LMI_MIF_SCLR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4666 #define UVD_LMI_MIF_SCLR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4667 //UVD_LMI_MIF_SCLR_64BIT_BAR_HIGH 4668 #define UVD_LMI_MIF_SCLR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4669 #define UVD_LMI_MIF_SCLR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4670 //UVD_LMI_MIF_SCLR2_64BIT_BAR_LOW 4671 #define UVD_LMI_MIF_SCLR2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4672 #define UVD_LMI_MIF_SCLR2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4673 //UVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH 4674 #define UVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4675 #define UVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4676 //UVD_LMI_SPH_64BIT_BAR_HIGH 4677 #define UVD_LMI_SPH_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4678 #define UVD_LMI_SPH_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4679 //UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW 4680 #define UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4681 #define UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4682 //UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH 4683 #define UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4684 #define UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4685 //UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW 4686 #define UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4687 #define UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4688 //UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH 4689 #define UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4690 #define UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4691 //UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW 4692 #define UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4693 #define UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4694 //UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH 4695 #define UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4696 #define UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4697 //UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW 4698 #define UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 4699 #define UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 4700 //UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH 4701 #define UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 4702 #define UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 4703 //UVD_ADP_ATOMIC_CONFIG 4704 #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER0_WR_CACHE__SHIFT 0x0 4705 #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER1_WR_CACHE__SHIFT 0x4 4706 #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER2_WR_CACHE__SHIFT 0x8 4707 #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER3_WR_CACHE__SHIFT 0xc 4708 #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_RD_URG__SHIFT 0x10 4709 #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER0_WR_CACHE_MASK 0x0000000FL 4710 #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER1_WR_CACHE_MASK 0x000000F0L 4711 #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER2_WR_CACHE_MASK 0x00000F00L 4712 #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER3_WR_CACHE_MASK 0x0000F000L 4713 #define UVD_ADP_ATOMIC_CONFIG__ATOMIC_RD_URG_MASK 0x000F0000L 4714 //UVD_LMI_ARB_CTRL2 4715 #define UVD_LMI_ARB_CTRL2__CENC_RD_WAIT_EN__SHIFT 0x0 4716 #define UVD_LMI_ARB_CTRL2__ATOMIC_WR_WAIT_EN__SHIFT 0x1 4717 #define UVD_LMI_ARB_CTRL2__CENC_RD_MAX_BURST__SHIFT 0x2 4718 #define UVD_LMI_ARB_CTRL2__ATOMIC_WR_MAX_BURST__SHIFT 0x6 4719 #define UVD_LMI_ARB_CTRL2__MIF_RD_REQ_RET_MAX__SHIFT 0xa 4720 #define UVD_LMI_ARB_CTRL2__MIF_WR_REQ_RET_MAX__SHIFT 0x14 4721 #define UVD_LMI_ARB_CTRL2__CENC_RD_WAIT_EN_MASK 0x00000001L 4722 #define UVD_LMI_ARB_CTRL2__ATOMIC_WR_WAIT_EN_MASK 0x00000002L 4723 #define UVD_LMI_ARB_CTRL2__CENC_RD_MAX_BURST_MASK 0x0000003CL 4724 #define UVD_LMI_ARB_CTRL2__ATOMIC_WR_MAX_BURST_MASK 0x000003C0L 4725 #define UVD_LMI_ARB_CTRL2__MIF_RD_REQ_RET_MAX_MASK 0x000FFC00L 4726 #define UVD_LMI_ARB_CTRL2__MIF_WR_REQ_RET_MAX_MASK 0xFFF00000L 4727 //UVD_LMI_VCPU_CACHE_VMIDS_MULTI 4728 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE1_VMID__SHIFT 0x0 4729 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE2_VMID__SHIFT 0x4 4730 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE3_VMID__SHIFT 0x8 4731 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE4_VMID__SHIFT 0xc 4732 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE5_VMID__SHIFT 0x10 4733 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE6_VMID__SHIFT 0x14 4734 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE7_VMID__SHIFT 0x18 4735 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE8_VMID__SHIFT 0x1c 4736 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE1_VMID_MASK 0x0000000FL 4737 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE2_VMID_MASK 0x000000F0L 4738 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE3_VMID_MASK 0x00000F00L 4739 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE4_VMID_MASK 0x0000F000L 4740 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE5_VMID_MASK 0x000F0000L 4741 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE6_VMID_MASK 0x00F00000L 4742 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE7_VMID_MASK 0x0F000000L 4743 #define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE8_VMID_MASK 0xF0000000L 4744 //UVD_LMI_VCPU_NC_VMIDS_MULTI 4745 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC2_VMID__SHIFT 0x4 4746 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC3_VMID__SHIFT 0x8 4747 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC4_VMID__SHIFT 0xc 4748 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC5_VMID__SHIFT 0x10 4749 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC6_VMID__SHIFT 0x14 4750 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC7_VMID__SHIFT 0x18 4751 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC2_VMID_MASK 0x000000F0L 4752 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC3_VMID_MASK 0x00000F00L 4753 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC4_VMID_MASK 0x0000F000L 4754 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC5_VMID_MASK 0x000F0000L 4755 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC6_VMID_MASK 0x00F00000L 4756 #define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC7_VMID_MASK 0x0F000000L 4757 //UVD_LMI_LAT_CTRL 4758 #define UVD_LMI_LAT_CTRL__SCALE__SHIFT 0x0 4759 #define UVD_LMI_LAT_CTRL__MAX_START__SHIFT 0x8 4760 #define UVD_LMI_LAT_CTRL__MIN_START__SHIFT 0x9 4761 #define UVD_LMI_LAT_CTRL__AVG_START__SHIFT 0xa 4762 #define UVD_LMI_LAT_CTRL__PERFMON_SYNC__SHIFT 0xb 4763 #define UVD_LMI_LAT_CTRL__SKIP__SHIFT 0x10 4764 #define UVD_LMI_LAT_CTRL__SCALE_MASK 0x000000FFL 4765 #define UVD_LMI_LAT_CTRL__MAX_START_MASK 0x00000100L 4766 #define UVD_LMI_LAT_CTRL__MIN_START_MASK 0x00000200L 4767 #define UVD_LMI_LAT_CTRL__AVG_START_MASK 0x00000400L 4768 #define UVD_LMI_LAT_CTRL__PERFMON_SYNC_MASK 0x00000800L 4769 #define UVD_LMI_LAT_CTRL__SKIP_MASK 0x000F0000L 4770 //UVD_LMI_LAT_CNTR 4771 #define UVD_LMI_LAT_CNTR__MAX_LAT__SHIFT 0x0 4772 #define UVD_LMI_LAT_CNTR__MIN_LAT__SHIFT 0x8 4773 #define UVD_LMI_LAT_CNTR__MAX_LAT_MASK 0x000000FFL 4774 #define UVD_LMI_LAT_CNTR__MIN_LAT_MASK 0x0000FF00L 4775 //UVD_LMI_AVG_LAT_CNTR 4776 #define UVD_LMI_AVG_LAT_CNTR__ENV_LOW__SHIFT 0x0 4777 #define UVD_LMI_AVG_LAT_CNTR__ENV_HIGH__SHIFT 0x8 4778 #define UVD_LMI_AVG_LAT_CNTR__ENV_HIT__SHIFT 0x10 4779 #define UVD_LMI_AVG_LAT_CNTR__ENV_LOW_MASK 0x000000FFL 4780 #define UVD_LMI_AVG_LAT_CNTR__ENV_HIGH_MASK 0x0000FF00L 4781 #define UVD_LMI_AVG_LAT_CNTR__ENV_HIT_MASK 0xFFFF0000L 4782 //UVD_LMI_SPH 4783 #define UVD_LMI_SPH__ADDR__SHIFT 0x0 4784 #define UVD_LMI_SPH__STS__SHIFT 0x1c 4785 #define UVD_LMI_SPH__STS_VALID__SHIFT 0x1e 4786 #define UVD_LMI_SPH__STS_OVERFLOW__SHIFT 0x1f 4787 #define UVD_LMI_SPH__ADDR_MASK 0x0FFFFFFFL 4788 #define UVD_LMI_SPH__STS_MASK 0x30000000L 4789 #define UVD_LMI_SPH__STS_VALID_MASK 0x40000000L 4790 #define UVD_LMI_SPH__STS_OVERFLOW_MASK 0x80000000L 4791 //UVD_LMI_VCPU_CACHE_VMID 4792 #define UVD_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID__SHIFT 0x0 4793 #define UVD_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID_MASK 0x0000000FL 4794 //UVD_LMI_CTRL2 4795 #define UVD_LMI_CTRL2__SPH_DIS__SHIFT 0x0 4796 #define UVD_LMI_CTRL2__STALL_ARB__SHIFT 0x1 4797 #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x2 4798 #define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x3 4799 #define UVD_LMI_CTRL2__CRC1_RESET__SHIFT 0x4 4800 #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x7 4801 #define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8 4802 #define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9 4803 #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb 4804 #define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN__SHIFT 0xd 4805 #define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN__SHIFT 0xe 4806 #define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN__SHIFT 0xf 4807 #define UVD_LMI_CTRL2__RE_OFFLOAD_EN__SHIFT 0x10 4808 #define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT 0x11 4809 #define UVD_LMI_CTRL2__CLEAR_NJ_PF_BP__SHIFT 0x19 4810 #define UVD_LMI_CTRL2__NJ_MIF_GATING__SHIFT 0x1a 4811 #define UVD_LMI_CTRL2__CRC1_SEL__SHIFT 0x1b 4812 #define UVD_LMI_CTRL2__SPH_DIS_MASK 0x00000001L 4813 #define UVD_LMI_CTRL2__STALL_ARB_MASK 0x00000002L 4814 #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x00000004L 4815 #define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x00000008L 4816 #define UVD_LMI_CTRL2__CRC1_RESET_MASK 0x00000010L 4817 #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK 0x00000080L 4818 #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x00000100L 4819 #define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x00000600L 4820 #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x00001800L 4821 #define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN_MASK 0x00002000L 4822 #define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN_MASK 0x00004000L 4823 #define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x00008000L 4824 #define UVD_LMI_CTRL2__RE_OFFLOAD_EN_MASK 0x00010000L 4825 #define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM_MASK 0x01FE0000L 4826 #define UVD_LMI_CTRL2__CLEAR_NJ_PF_BP_MASK 0x02000000L 4827 #define UVD_LMI_CTRL2__NJ_MIF_GATING_MASK 0x04000000L 4828 #define UVD_LMI_CTRL2__CRC1_SEL_MASK 0xF8000000L 4829 //UVD_LMI_URGENT_CTRL 4830 #define UVD_LMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL__SHIFT 0x0 4831 #define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_STALL__SHIFT 0x1 4832 #define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_URGENT__SHIFT 0x2 4833 #define UVD_LMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL__SHIFT 0x8 4834 #define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_STALL__SHIFT 0x9 4835 #define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_URGENT__SHIFT 0xa 4836 #define UVD_LMI_URGENT_CTRL__ENABLE_UMC_RD_URGENT_STALL__SHIFT 0x10 4837 #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_STALL__SHIFT 0x11 4838 #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_URGENT__SHIFT 0x12 4839 #define UVD_LMI_URGENT_CTRL__ENABLE_UMC_WR_URGENT_STALL__SHIFT 0x18 4840 #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_STALL__SHIFT 0x19 4841 #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_URGENT__SHIFT 0x1a 4842 #define UVD_LMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL_MASK 0x00000001L 4843 #define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_STALL_MASK 0x00000002L 4844 #define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_URGENT_MASK 0x0000003CL 4845 #define UVD_LMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL_MASK 0x00000100L 4846 #define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_STALL_MASK 0x00000200L 4847 #define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_URGENT_MASK 0x00003C00L 4848 #define UVD_LMI_URGENT_CTRL__ENABLE_UMC_RD_URGENT_STALL_MASK 0x00010000L 4849 #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_STALL_MASK 0x00020000L 4850 #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_URGENT_MASK 0x003C0000L 4851 #define UVD_LMI_URGENT_CTRL__ENABLE_UMC_WR_URGENT_STALL_MASK 0x01000000L 4852 #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_STALL_MASK 0x02000000L 4853 #define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_URGENT_MASK 0x3C000000L 4854 //UVD_LMI_CTRL 4855 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0 4856 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8 4857 #define UVD_LMI_CTRL__REQ_MODE__SHIFT 0x9 4858 #define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0xb 4859 #define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT 0xc 4860 #define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0xd 4861 #define UVD_LMI_CTRL__CRC_RESET__SHIFT 0xe 4862 #define UVD_LMI_CTRL__CRC_SEL__SHIFT 0xf 4863 #define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL__SHIFT 0x14 4864 #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15 4865 #define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT 0x16 4866 #define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT 0x17 4867 #define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT 0x18 4868 #define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT 0x19 4869 #define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN__SHIFT 0x1a 4870 #define UVD_LMI_CTRL__MIF_LESS_OUTSTANDING_RD_REQ__SHIFT 0x1b 4871 #define UVD_LMI_CTRL__MC_BLK_RST__SHIFT 0x1c 4872 #define UVD_LMI_CTRL__UMC_BLK_RST__SHIFT 0x1d 4873 #define UVD_LMI_CTRL__RFU__SHIFT 0x1e 4874 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK 0x000000FFL 4875 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x00000100L 4876 #define UVD_LMI_CTRL__REQ_MODE_MASK 0x00000200L 4877 #define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x00000800L 4878 #define UVD_LMI_CTRL__MASK_MC_URGENT_MASK 0x00001000L 4879 #define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x00002000L 4880 #define UVD_LMI_CTRL__CRC_RESET_MASK 0x00004000L 4881 #define UVD_LMI_CTRL__CRC_SEL_MASK 0x000F8000L 4882 #define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK 0x00100000L 4883 #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x00200000L 4884 #define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK 0x00400000L 4885 #define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK 0x00800000L 4886 #define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x01000000L 4887 #define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x02000000L 4888 #define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN_MASK 0x04000000L 4889 #define UVD_LMI_CTRL__MIF_LESS_OUTSTANDING_RD_REQ_MASK 0x08000000L 4890 #define UVD_LMI_CTRL__MC_BLK_RST_MASK 0x10000000L 4891 #define UVD_LMI_CTRL__UMC_BLK_RST_MASK 0x20000000L 4892 #define UVD_LMI_CTRL__RFU_MASK 0xC0000000L 4893 //UVD_LMI_STATUS 4894 #define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x0 4895 #define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x1 4896 #define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x2 4897 #define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x3 4898 #define UVD_LMI_STATUS__UMC_READ_CLEAN__SHIFT 0x4 4899 #define UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT 0x5 4900 #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT 0x6 4901 #define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE__SHIFT 0x7 4902 #define UVD_LMI_STATUS__READ_CLEAN_RAW__SHIFT 0x8 4903 #define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT 0x9 4904 #define UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT 0xa 4905 #define UVD_LMI_STATUS__UMC_AVP_IDLE__SHIFT 0xb 4906 #define UVD_LMI_STATUS__ADP_MC_READ_CLEAN__SHIFT 0xc 4907 #define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN__SHIFT 0xd 4908 #define UVD_LMI_STATUS__BSP0_WRITE_CLEAN__SHIFT 0x12 4909 #define UVD_LMI_STATUS__BSP1_WRITE_CLEAN__SHIFT 0x13 4910 #define UVD_LMI_STATUS__BSP2_WRITE_CLEAN__SHIFT 0x14 4911 #define UVD_LMI_STATUS__BSP3_WRITE_CLEAN__SHIFT 0x15 4912 #define UVD_LMI_STATUS__CENC_READ_CLEAN__SHIFT 0x16 4913 #define UVD_LMI_STATUS__READ_CLEAN_MASK 0x00000001L 4914 #define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x00000002L 4915 #define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x00000004L 4916 #define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK 0x00000008L 4917 #define UVD_LMI_STATUS__UMC_READ_CLEAN_MASK 0x00000010L 4918 #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_MASK 0x00000020L 4919 #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK 0x00000040L 4920 #define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE_MASK 0x00000080L 4921 #define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK 0x00000100L 4922 #define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x00000200L 4923 #define UVD_LMI_STATUS__UMC_UVD_IDLE_MASK 0x00000400L 4924 #define UVD_LMI_STATUS__UMC_AVP_IDLE_MASK 0x00000800L 4925 #define UVD_LMI_STATUS__ADP_MC_READ_CLEAN_MASK 0x00001000L 4926 #define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN_MASK 0x00002000L 4927 #define UVD_LMI_STATUS__BSP0_WRITE_CLEAN_MASK 0x00040000L 4928 #define UVD_LMI_STATUS__BSP1_WRITE_CLEAN_MASK 0x00080000L 4929 #define UVD_LMI_STATUS__BSP2_WRITE_CLEAN_MASK 0x00100000L 4930 #define UVD_LMI_STATUS__BSP3_WRITE_CLEAN_MASK 0x00200000L 4931 #define UVD_LMI_STATUS__CENC_READ_CLEAN_MASK 0x00400000L 4932 //UVD_LMI_PERFMON_CTRL 4933 #define UVD_LMI_PERFMON_CTRL__PERFMON_STATE__SHIFT 0x0 4934 #define UVD_LMI_PERFMON_CTRL__PERFMON_SEL__SHIFT 0x8 4935 #define UVD_LMI_PERFMON_CTRL__PERFMON_STATE_MASK 0x00000003L 4936 #define UVD_LMI_PERFMON_CTRL__PERFMON_SEL_MASK 0x00001F00L 4937 //UVD_LMI_PERFMON_COUNT_LO 4938 #define UVD_LMI_PERFMON_COUNT_LO__PERFMON_COUNT__SHIFT 0x0 4939 #define UVD_LMI_PERFMON_COUNT_LO__PERFMON_COUNT_MASK 0xFFFFFFFFL 4940 //UVD_LMI_PERFMON_COUNT_HI 4941 #define UVD_LMI_PERFMON_COUNT_HI__PERFMON_COUNT__SHIFT 0x0 4942 #define UVD_LMI_PERFMON_COUNT_HI__PERFMON_COUNT_MASK 0x0000FFFFL 4943 //UVD_LMI_ADP_SWAP_CNTL 4944 #define UVD_LMI_ADP_SWAP_CNTL__VCPU_R_MC_SWAP__SHIFT 0x6 4945 #define UVD_LMI_ADP_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x8 4946 #define UVD_LMI_ADP_SWAP_CNTL__CM_MC_SWAP__SHIFT 0xa 4947 #define UVD_LMI_ADP_SWAP_CNTL__IT_MC_SWAP__SHIFT 0xc 4948 #define UVD_LMI_ADP_SWAP_CNTL__DB_R_MC_SWAP__SHIFT 0xe 4949 #define UVD_LMI_ADP_SWAP_CNTL__DB_W_MC_SWAP__SHIFT 0x10 4950 #define UVD_LMI_ADP_SWAP_CNTL__CSM_MC_SWAP__SHIFT 0x12 4951 #define UVD_LMI_ADP_SWAP_CNTL__PREF_MC_SWAP__SHIFT 0x14 4952 #define UVD_LMI_ADP_SWAP_CNTL__DBW_MC_SWAP__SHIFT 0x18 4953 #define UVD_LMI_ADP_SWAP_CNTL__RE_MC_SWAP__SHIFT 0x1c 4954 #define UVD_LMI_ADP_SWAP_CNTL__MP_MC_SWAP__SHIFT 0x1e 4955 #define UVD_LMI_ADP_SWAP_CNTL__VCPU_R_MC_SWAP_MASK 0x000000C0L 4956 #define UVD_LMI_ADP_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x00000300L 4957 #define UVD_LMI_ADP_SWAP_CNTL__CM_MC_SWAP_MASK 0x00000C00L 4958 #define UVD_LMI_ADP_SWAP_CNTL__IT_MC_SWAP_MASK 0x00003000L 4959 #define UVD_LMI_ADP_SWAP_CNTL__DB_R_MC_SWAP_MASK 0x0000C000L 4960 #define UVD_LMI_ADP_SWAP_CNTL__DB_W_MC_SWAP_MASK 0x00030000L 4961 #define UVD_LMI_ADP_SWAP_CNTL__CSM_MC_SWAP_MASK 0x000C0000L 4962 #define UVD_LMI_ADP_SWAP_CNTL__PREF_MC_SWAP_MASK 0x00300000L 4963 #define UVD_LMI_ADP_SWAP_CNTL__DBW_MC_SWAP_MASK 0x03000000L 4964 #define UVD_LMI_ADP_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000L 4965 #define UVD_LMI_ADP_SWAP_CNTL__MP_MC_SWAP_MASK 0xC0000000L 4966 //UVD_LMI_RBC_RB_VMID 4967 #define UVD_LMI_RBC_RB_VMID__RB_VMID__SHIFT 0x0 4968 #define UVD_LMI_RBC_RB_VMID__RB_VMID_MASK 0x0000000FL 4969 //UVD_LMI_RBC_IB_VMID 4970 #define UVD_LMI_RBC_IB_VMID__IB_VMID__SHIFT 0x0 4971 #define UVD_LMI_RBC_IB_VMID__IB_VMID_MASK 0x0000000FL 4972 //UVD_LMI_MC_CREDITS 4973 #define UVD_LMI_MC_CREDITS__UVD_RD_CREDITS__SHIFT 0x0 4974 #define UVD_LMI_MC_CREDITS__UVD_WR_CREDITS__SHIFT 0x8 4975 #define UVD_LMI_MC_CREDITS__UMC_RD_CREDITS__SHIFT 0x10 4976 #define UVD_LMI_MC_CREDITS__UMC_WR_CREDITS__SHIFT 0x18 4977 #define UVD_LMI_MC_CREDITS__UVD_RD_CREDITS_MASK 0x0000003FL 4978 #define UVD_LMI_MC_CREDITS__UVD_WR_CREDITS_MASK 0x00003F00L 4979 #define UVD_LMI_MC_CREDITS__UMC_RD_CREDITS_MASK 0x003F0000L 4980 #define UVD_LMI_MC_CREDITS__UMC_WR_CREDITS_MASK 0x3F000000L 4981 //UVD_LMI_ADP_IND_INDEX 4982 #define UVD_LMI_ADP_IND_INDEX__INDEX__SHIFT 0x0 4983 #define UVD_LMI_ADP_IND_INDEX__INDEX_MASK 0x00001FFFL 4984 //UVD_LMI_ADP_IND_DATA 4985 #define UVD_LMI_ADP_IND_DATA__DATA__SHIFT 0x0 4986 #define UVD_LMI_ADP_IND_DATA__DATA_MASK 0xFFFFFFFFL 4987 //UVD_LMI_ADP_PF_EN 4988 #define UVD_LMI_ADP_PF_EN__VCPU_CACHE0_PF_EN__SHIFT 0x0 4989 #define UVD_LMI_ADP_PF_EN__VCPU_CACHE1_PF_EN__SHIFT 0x1 4990 #define UVD_LMI_ADP_PF_EN__VCPU_CACHE2_PF_EN__SHIFT 0x2 4991 #define UVD_LMI_ADP_PF_EN__VCPU_CACHE0_PF_EN_MASK 0x00000001L 4992 #define UVD_LMI_ADP_PF_EN__VCPU_CACHE1_PF_EN_MASK 0x00000002L 4993 #define UVD_LMI_ADP_PF_EN__VCPU_CACHE2_PF_EN_MASK 0x00000004L 4994 //UVD_LMI_PREF_CTRL 4995 #define UVD_LMI_PREF_CTRL__PREF_RST__SHIFT 0x0 4996 #define UVD_LMI_PREF_CTRL__PREF_BUSY_STATUS__SHIFT 0x1 4997 #define UVD_LMI_PREF_CTRL__PREF_WSTRB__SHIFT 0x2 4998 #define UVD_LMI_PREF_CTRL__PREF_WRITE_SIZE__SHIFT 0x3 4999 #define UVD_LMI_PREF_CTRL__PREF_STEP_SIZE__SHIFT 0x4 5000 #define UVD_LMI_PREF_CTRL__PREF_SIZE__SHIFT 0x13 5001 #define UVD_LMI_PREF_CTRL__PREF_RST_MASK 0x00000001L 5002 #define UVD_LMI_PREF_CTRL__PREF_BUSY_STATUS_MASK 0x00000002L 5003 #define UVD_LMI_PREF_CTRL__PREF_WSTRB_MASK 0x00000004L 5004 #define UVD_LMI_PREF_CTRL__PREF_WRITE_SIZE_MASK 0x00000008L 5005 #define UVD_LMI_PREF_CTRL__PREF_STEP_SIZE_MASK 0x00000070L 5006 #define UVD_LMI_PREF_CTRL__PREF_SIZE_MASK 0xFFF80000L 5007 //UVD_LMI_MIF_REF_LUMA_64BIT_BAR_LOW 5008 #define UVD_LMI_MIF_REF_LUMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 5009 #define UVD_LMI_MIF_REF_LUMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 5010 //UVD_LMI_MIF_REF_LUMA_64BIT_BAR_HIGH 5011 #define UVD_LMI_MIF_REF_LUMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 5012 #define UVD_LMI_MIF_REF_LUMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 5013 //VCN_RAS_CNTL 5014 #define VCN_RAS_CNTL__VCPU_VCODEC_IH_EN__SHIFT 0x0 5015 #define VCN_RAS_CNTL__VCPU_VCODEC_PMI_EN__SHIFT 0x4 5016 #define VCN_RAS_CNTL__VCPU_VCODEC_REARM__SHIFT 0x8 5017 #define VCN_RAS_CNTL__VCPU_VCODEC_STALL_EN__SHIFT 0xc 5018 #define VCN_RAS_CNTL__VCPU_VCODEC_READY__SHIFT 0x10 5019 #define VCN_RAS_CNTL__VCPU_VCODEC_IH_EN_MASK 0x00000001L 5020 #define VCN_RAS_CNTL__VCPU_VCODEC_PMI_EN_MASK 0x00000010L 5021 #define VCN_RAS_CNTL__VCPU_VCODEC_REARM_MASK 0x00000100L 5022 #define VCN_RAS_CNTL__VCPU_VCODEC_STALL_EN_MASK 0x00001000L 5023 #define VCN_RAS_CNTL__VCPU_VCODEC_READY_MASK 0x00010000L 5024 5025 5026 // addressBlock: aid_uvd0_uvd_jpeg0_jpegnpdec 5027 //UVD_JPEG_CNTL 5028 #define UVD_JPEG_CNTL__REQUEST_EN__SHIFT 0x1 5029 #define UVD_JPEG_CNTL__ERR_RST_EN__SHIFT 0x2 5030 #define UVD_JPEG_CNTL__DBG_MUX_SEL__SHIFT 0x8 5031 #define UVD_JPEG_CNTL__FORMAT_CONV_EN__SHIFT 0x10 5032 #define UVD_JPEG_CNTL__VUP_MODE__SHIFT 0x11 5033 #define UVD_JPEG_CNTL__FC_TIMEOUT_EN__SHIFT 0x12 5034 #define UVD_JPEG_CNTL__ROI_CROP_EN__SHIFT 0x18 5035 #define UVD_JPEG_CNTL__ROI_CROP_EARLY_DECODE_STOP_DIS__SHIFT 0x19 5036 #define UVD_JPEG_CNTL__REQUEST_EN_MASK 0x00000002L 5037 #define UVD_JPEG_CNTL__ERR_RST_EN_MASK 0x00000004L 5038 #define UVD_JPEG_CNTL__DBG_MUX_SEL_MASK 0x00007F00L 5039 #define UVD_JPEG_CNTL__FORMAT_CONV_EN_MASK 0x00010000L 5040 #define UVD_JPEG_CNTL__VUP_MODE_MASK 0x00020000L 5041 #define UVD_JPEG_CNTL__FC_TIMEOUT_EN_MASK 0x00040000L 5042 #define UVD_JPEG_CNTL__ROI_CROP_EN_MASK 0x01000000L 5043 #define UVD_JPEG_CNTL__ROI_CROP_EARLY_DECODE_STOP_DIS_MASK 0x02000000L 5044 //UVD_JPEG_RB_BASE 5045 #define UVD_JPEG_RB_BASE__RB_BYTE_OFF__SHIFT 0x0 5046 #define UVD_JPEG_RB_BASE__RB_BASE__SHIFT 0x6 5047 #define UVD_JPEG_RB_BASE__RB_BYTE_OFF_MASK 0x0000003FL 5048 #define UVD_JPEG_RB_BASE__RB_BASE_MASK 0xFFFFFFC0L 5049 //UVD_JPEG_RB_WPTR 5050 #define UVD_JPEG_RB_WPTR__RB_WPTR__SHIFT 0x4 5051 #define UVD_JPEG_RB_WPTR__RB_WPTR_MASK 0x3FFFFFF0L 5052 //UVD_JPEG_RB_RPTR 5053 #define UVD_JPEG_RB_RPTR__RB_RPTR__SHIFT 0x4 5054 #define UVD_JPEG_RB_RPTR__RB_RPTR_MASK 0x3FFFFFF0L 5055 //UVD_JPEG_RB_SIZE 5056 #define UVD_JPEG_RB_SIZE__RB_SIZE__SHIFT 0x4 5057 #define UVD_JPEG_RB_SIZE__RB_SIZE_MASK 0x3FFFFFF0L 5058 //UVD_JPEG_DEC_CNT 5059 #define UVD_JPEG_DEC_CNT__DECODE_COUNT__SHIFT 0x0 5060 #define UVD_JPEG_DEC_CNT__DECODE_COUNT_MASK 0xFFFFFFFFL 5061 //UVD_JPEG_SPS_INFO 5062 #define UVD_JPEG_SPS_INFO__PIC_WIDTH__SHIFT 0x0 5063 #define UVD_JPEG_SPS_INFO__PIC_HEIGHT__SHIFT 0x10 5064 #define UVD_JPEG_SPS_INFO__PIC_WIDTH_MASK 0x0000FFFFL 5065 #define UVD_JPEG_SPS_INFO__PIC_HEIGHT_MASK 0xFFFF0000L 5066 //UVD_JPEG_SPS1_INFO 5067 #define UVD_JPEG_SPS1_INFO__CHROMA_FORMAT_IDC__SHIFT 0x0 5068 #define UVD_JPEG_SPS1_INFO__YUV422_SUBFORMAT__SHIFT 0x3 5069 #define UVD_JPEG_SPS1_INFO__OUT_FMT_422__SHIFT 0x4 5070 #define UVD_JPEG_SPS1_INFO__CHROMA_FORMAT_IDC_MASK 0x00000007L 5071 #define UVD_JPEG_SPS1_INFO__YUV422_SUBFORMAT_MASK 0x00000008L 5072 #define UVD_JPEG_SPS1_INFO__OUT_FMT_422_MASK 0x00000010L 5073 //UVD_JPEG_RE_TIMER 5074 #define UVD_JPEG_RE_TIMER__TIMER_OUT__SHIFT 0x0 5075 #define UVD_JPEG_RE_TIMER__TIMER_OUT_EN__SHIFT 0x10 5076 #define UVD_JPEG_RE_TIMER__TIMER_OUT_MASK 0x000000FFL 5077 #define UVD_JPEG_RE_TIMER__TIMER_OUT_EN_MASK 0x00010000L 5078 //UVD_JPEG_DEC_SCRATCH0 5079 #define UVD_JPEG_DEC_SCRATCH0__SCRATCH0__SHIFT 0x0 5080 #define UVD_JPEG_DEC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL 5081 //UVD_JPEG_INT_EN 5082 #define UVD_JPEG_INT_EN__OUTBUF_WPTR_INC_EN__SHIFT 0x0 5083 #define UVD_JPEG_INT_EN__JOB_AVAIL_EN__SHIFT 0x1 5084 #define UVD_JPEG_INT_EN__FENCE_VAL_EN__SHIFT 0x2 5085 #define UVD_JPEG_INT_EN__FIFO_OVERFLOW_ERR_EN__SHIFT 0x6 5086 #define UVD_JPEG_INT_EN__BLK_CNT_OUT_OF_SYNC_ERR_EN__SHIFT 0x7 5087 #define UVD_JPEG_INT_EN__EOI_ERR_EN__SHIFT 0x8 5088 #define UVD_JPEG_INT_EN__HFM_ERR_EN__SHIFT 0x9 5089 #define UVD_JPEG_INT_EN__RST_ERR_EN__SHIFT 0xa 5090 #define UVD_JPEG_INT_EN__ECS_MK_ERR_EN__SHIFT 0xb 5091 #define UVD_JPEG_INT_EN__TIMEOUT_ERR_EN__SHIFT 0xc 5092 #define UVD_JPEG_INT_EN__MARKER_ERR_EN__SHIFT 0xd 5093 #define UVD_JPEG_INT_EN__FMT_ERR_EN__SHIFT 0xe 5094 #define UVD_JPEG_INT_EN__PROFILE_ERR_EN__SHIFT 0xf 5095 #define UVD_JPEG_INT_EN__FC_TIMEOUT_ERR_EN__SHIFT 0x10 5096 #define UVD_JPEG_INT_EN__FC_FMT_ERR_EN__SHIFT 0x11 5097 #define UVD_JPEG_INT_EN__FC_SRC_ERR_EN__SHIFT 0x12 5098 #define UVD_JPEG_INT_EN__CROP_SIZE_ERR_EN__SHIFT 0x13 5099 #define UVD_JPEG_INT_EN__OUTBUF_WPTR_INC_EN_MASK 0x00000001L 5100 #define UVD_JPEG_INT_EN__JOB_AVAIL_EN_MASK 0x00000002L 5101 #define UVD_JPEG_INT_EN__FENCE_VAL_EN_MASK 0x00000004L 5102 #define UVD_JPEG_INT_EN__FIFO_OVERFLOW_ERR_EN_MASK 0x00000040L 5103 #define UVD_JPEG_INT_EN__BLK_CNT_OUT_OF_SYNC_ERR_EN_MASK 0x00000080L 5104 #define UVD_JPEG_INT_EN__EOI_ERR_EN_MASK 0x00000100L 5105 #define UVD_JPEG_INT_EN__HFM_ERR_EN_MASK 0x00000200L 5106 #define UVD_JPEG_INT_EN__RST_ERR_EN_MASK 0x00000400L 5107 #define UVD_JPEG_INT_EN__ECS_MK_ERR_EN_MASK 0x00000800L 5108 #define UVD_JPEG_INT_EN__TIMEOUT_ERR_EN_MASK 0x00001000L 5109 #define UVD_JPEG_INT_EN__MARKER_ERR_EN_MASK 0x00002000L 5110 #define UVD_JPEG_INT_EN__FMT_ERR_EN_MASK 0x00004000L 5111 #define UVD_JPEG_INT_EN__PROFILE_ERR_EN_MASK 0x00008000L 5112 #define UVD_JPEG_INT_EN__FC_TIMEOUT_ERR_EN_MASK 0x00010000L 5113 #define UVD_JPEG_INT_EN__FC_FMT_ERR_EN_MASK 0x00020000L 5114 #define UVD_JPEG_INT_EN__FC_SRC_ERR_EN_MASK 0x00040000L 5115 #define UVD_JPEG_INT_EN__CROP_SIZE_ERR_EN_MASK 0x00080000L 5116 //UVD_JPEG_INT_STAT 5117 #define UVD_JPEG_INT_STAT__OUTBUF_WPTR_INC_INT__SHIFT 0x0 5118 #define UVD_JPEG_INT_STAT__JOB_AVAIL_INT__SHIFT 0x1 5119 #define UVD_JPEG_INT_STAT__FENCE_VAL_INT__SHIFT 0x2 5120 #define UVD_JPEG_INT_STAT__FIFO_OVERFLOW_ERR_INT__SHIFT 0x6 5121 #define UVD_JPEG_INT_STAT__BLK_CNT_OUT_OF_SYNC_ERR_INT__SHIFT 0x7 5122 #define UVD_JPEG_INT_STAT__EOI_ERR_INT__SHIFT 0x8 5123 #define UVD_JPEG_INT_STAT__HFM_ERR_INT__SHIFT 0x9 5124 #define UVD_JPEG_INT_STAT__RST_ERR_INT__SHIFT 0xa 5125 #define UVD_JPEG_INT_STAT__ECS_MK_ERR_INT__SHIFT 0xb 5126 #define UVD_JPEG_INT_STAT__TIMEOUT_ERR_INT__SHIFT 0xc 5127 #define UVD_JPEG_INT_STAT__MARKER_ERR_INT__SHIFT 0xd 5128 #define UVD_JPEG_INT_STAT__FMT_ERR_INT__SHIFT 0xe 5129 #define UVD_JPEG_INT_STAT__PROFILE_ERR_INT__SHIFT 0xf 5130 #define UVD_JPEG_INT_STAT__FC_TIMEOUT_ERR_INT__SHIFT 0x10 5131 #define UVD_JPEG_INT_STAT__FC_FMT_ERR_INT__SHIFT 0x11 5132 #define UVD_JPEG_INT_STAT__FC_SRC_ERR_INT__SHIFT 0x12 5133 #define UVD_JPEG_INT_STAT__CROP_SIZE_ERR_INT__SHIFT 0x13 5134 #define UVD_JPEG_INT_STAT__OUTBUF_WPTR_INC_INT_MASK 0x00000001L 5135 #define UVD_JPEG_INT_STAT__JOB_AVAIL_INT_MASK 0x00000002L 5136 #define UVD_JPEG_INT_STAT__FENCE_VAL_INT_MASK 0x00000004L 5137 #define UVD_JPEG_INT_STAT__FIFO_OVERFLOW_ERR_INT_MASK 0x00000040L 5138 #define UVD_JPEG_INT_STAT__BLK_CNT_OUT_OF_SYNC_ERR_INT_MASK 0x00000080L 5139 #define UVD_JPEG_INT_STAT__EOI_ERR_INT_MASK 0x00000100L 5140 #define UVD_JPEG_INT_STAT__HFM_ERR_INT_MASK 0x00000200L 5141 #define UVD_JPEG_INT_STAT__RST_ERR_INT_MASK 0x00000400L 5142 #define UVD_JPEG_INT_STAT__ECS_MK_ERR_INT_MASK 0x00000800L 5143 #define UVD_JPEG_INT_STAT__TIMEOUT_ERR_INT_MASK 0x00001000L 5144 #define UVD_JPEG_INT_STAT__MARKER_ERR_INT_MASK 0x00002000L 5145 #define UVD_JPEG_INT_STAT__FMT_ERR_INT_MASK 0x00004000L 5146 #define UVD_JPEG_INT_STAT__PROFILE_ERR_INT_MASK 0x00008000L 5147 #define UVD_JPEG_INT_STAT__FC_TIMEOUT_ERR_INT_MASK 0x00010000L 5148 #define UVD_JPEG_INT_STAT__FC_FMT_ERR_INT_MASK 0x00020000L 5149 #define UVD_JPEG_INT_STAT__FC_SRC_ERR_INT_MASK 0x00040000L 5150 #define UVD_JPEG_INT_STAT__CROP_SIZE_ERR_INT_MASK 0x00080000L 5151 //UVD_JPEG_TIER_CNTL0 5152 #define UVD_JPEG_TIER_CNTL0__TIER_SEL__SHIFT 0x0 5153 #define UVD_JPEG_TIER_CNTL0__Y_COMP_ID__SHIFT 0x2 5154 #define UVD_JPEG_TIER_CNTL0__U_COMP_ID__SHIFT 0x4 5155 #define UVD_JPEG_TIER_CNTL0__V_COMP_ID__SHIFT 0x6 5156 #define UVD_JPEG_TIER_CNTL0__Y_H_SAMP_FAC__SHIFT 0x8 5157 #define UVD_JPEG_TIER_CNTL0__Y_V_SAMP_FAC__SHIFT 0xb 5158 #define UVD_JPEG_TIER_CNTL0__U_H_SAMP_FAC__SHIFT 0xe 5159 #define UVD_JPEG_TIER_CNTL0__U_V_SAMP_FAC__SHIFT 0x11 5160 #define UVD_JPEG_TIER_CNTL0__V_H_SAMP_FAC__SHIFT 0x14 5161 #define UVD_JPEG_TIER_CNTL0__V_V_SAMP_FAC__SHIFT 0x17 5162 #define UVD_JPEG_TIER_CNTL0__Y_TQ__SHIFT 0x1a 5163 #define UVD_JPEG_TIER_CNTL0__U_TQ__SHIFT 0x1c 5164 #define UVD_JPEG_TIER_CNTL0__V_TQ__SHIFT 0x1e 5165 #define UVD_JPEG_TIER_CNTL0__TIER_SEL_MASK 0x00000003L 5166 #define UVD_JPEG_TIER_CNTL0__Y_COMP_ID_MASK 0x0000000CL 5167 #define UVD_JPEG_TIER_CNTL0__U_COMP_ID_MASK 0x00000030L 5168 #define UVD_JPEG_TIER_CNTL0__V_COMP_ID_MASK 0x000000C0L 5169 #define UVD_JPEG_TIER_CNTL0__Y_H_SAMP_FAC_MASK 0x00000700L 5170 #define UVD_JPEG_TIER_CNTL0__Y_V_SAMP_FAC_MASK 0x00003800L 5171 #define UVD_JPEG_TIER_CNTL0__U_H_SAMP_FAC_MASK 0x0001C000L 5172 #define UVD_JPEG_TIER_CNTL0__U_V_SAMP_FAC_MASK 0x000E0000L 5173 #define UVD_JPEG_TIER_CNTL0__V_H_SAMP_FAC_MASK 0x00700000L 5174 #define UVD_JPEG_TIER_CNTL0__V_V_SAMP_FAC_MASK 0x03800000L 5175 #define UVD_JPEG_TIER_CNTL0__Y_TQ_MASK 0x0C000000L 5176 #define UVD_JPEG_TIER_CNTL0__U_TQ_MASK 0x30000000L 5177 #define UVD_JPEG_TIER_CNTL0__V_TQ_MASK 0xC0000000L 5178 //UVD_JPEG_TIER_CNTL1 5179 #define UVD_JPEG_TIER_CNTL1__SRC_WIDTH__SHIFT 0x0 5180 #define UVD_JPEG_TIER_CNTL1__SRC_HEIGHT__SHIFT 0x10 5181 #define UVD_JPEG_TIER_CNTL1__SRC_WIDTH_MASK 0x0000FFFFL 5182 #define UVD_JPEG_TIER_CNTL1__SRC_HEIGHT_MASK 0xFFFF0000L 5183 //UVD_JPEG_TIER_CNTL2 5184 #define UVD_JPEG_TIER_CNTL2__TBL_ECS_SEL__SHIFT 0x0 5185 #define UVD_JPEG_TIER_CNTL2__TBL_TYPE__SHIFT 0x1 5186 #define UVD_JPEG_TIER_CNTL2__TQ__SHIFT 0x2 5187 #define UVD_JPEG_TIER_CNTL2__TH__SHIFT 0x4 5188 #define UVD_JPEG_TIER_CNTL2__TC__SHIFT 0x6 5189 #define UVD_JPEG_TIER_CNTL2__TD__SHIFT 0x7 5190 #define UVD_JPEG_TIER_CNTL2__TA__SHIFT 0xa 5191 #define UVD_JPEG_TIER_CNTL2__TIER2_HTBL_CNTLEN__SHIFT 0xe 5192 #define UVD_JPEG_TIER_CNTL2__DRI_VAL__SHIFT 0x10 5193 #define UVD_JPEG_TIER_CNTL2__TBL_ECS_SEL_MASK 0x00000001L 5194 #define UVD_JPEG_TIER_CNTL2__TBL_TYPE_MASK 0x00000002L 5195 #define UVD_JPEG_TIER_CNTL2__TQ_MASK 0x0000000CL 5196 #define UVD_JPEG_TIER_CNTL2__TH_MASK 0x00000030L 5197 #define UVD_JPEG_TIER_CNTL2__TC_MASK 0x00000040L 5198 #define UVD_JPEG_TIER_CNTL2__TD_MASK 0x00000380L 5199 #define UVD_JPEG_TIER_CNTL2__TA_MASK 0x00001C00L 5200 #define UVD_JPEG_TIER_CNTL2__TIER2_HTBL_CNTLEN_MASK 0x00004000L 5201 #define UVD_JPEG_TIER_CNTL2__DRI_VAL_MASK 0xFFFF0000L 5202 //UVD_JPEG_TIER_STATUS 5203 #define UVD_JPEG_TIER_STATUS__BSI_FETCH_DONE__SHIFT 0x0 5204 #define UVD_JPEG_TIER_STATUS__DECODE_DONE__SHIFT 0x1 5205 #define UVD_JPEG_TIER_STATUS__BSI_FETCH_DONE_MASK 0x00000001L 5206 #define UVD_JPEG_TIER_STATUS__DECODE_DONE_MASK 0x00000002L 5207 5208 5209 // addressBlock: aid_uvd0_uvd_jpeg_sclk0_jpegnpsclkdec 5210 //UVD_JPEG_OUTBUF_CNTL 5211 #define UVD_JPEG_OUTBUF_CNTL__OUTBUF_CNT__SHIFT 0x0 5212 #define UVD_JPEG_OUTBUF_CNTL__HGT_ALIGN__SHIFT 0x2 5213 #define UVD_JPEG_OUTBUF_CNTL__JPEG0_DECODE_DONE_FIX__SHIFT 0x6 5214 #define UVD_JPEG_OUTBUF_CNTL__JPEG0_WR_COMB_MAX_CNT__SHIFT 0x7 5215 #define UVD_JPEG_OUTBUF_CNTL__JPEG0_WR_COMB_TIMER__SHIFT 0x9 5216 #define UVD_JPEG_OUTBUF_CNTL__DIS_OBUF_AVAIL_CHECK__SHIFT 0x10 5217 #define UVD_JPEG_OUTBUF_CNTL__OUTBUF_CNT_MASK 0x00000003L 5218 #define UVD_JPEG_OUTBUF_CNTL__HGT_ALIGN_MASK 0x00000004L 5219 #define UVD_JPEG_OUTBUF_CNTL__JPEG0_DECODE_DONE_FIX_MASK 0x00000040L 5220 #define UVD_JPEG_OUTBUF_CNTL__JPEG0_WR_COMB_MAX_CNT_MASK 0x00000180L 5221 #define UVD_JPEG_OUTBUF_CNTL__JPEG0_WR_COMB_TIMER_MASK 0x00001E00L 5222 #define UVD_JPEG_OUTBUF_CNTL__DIS_OBUF_AVAIL_CHECK_MASK 0x00010000L 5223 //UVD_JPEG_OUTBUF_WPTR 5224 #define UVD_JPEG_OUTBUF_WPTR__OUTBUF_WPTR__SHIFT 0x0 5225 #define UVD_JPEG_OUTBUF_WPTR__OUTBUF_WPTR_MASK 0xFFFFFFFFL 5226 //UVD_JPEG_OUTBUF_RPTR 5227 #define UVD_JPEG_OUTBUF_RPTR__OUTBUF_RPTR__SHIFT 0x0 5228 #define UVD_JPEG_OUTBUF_RPTR__OUTBUF_RPTR_MASK 0xFFFFFFFFL 5229 //UVD_JPEG_PITCH 5230 #define UVD_JPEG_PITCH__PITCH__SHIFT 0x0 5231 #define UVD_JPEG_PITCH__PITCH_MASK 0xFFFFFFFFL 5232 //UVD_JPEG_UV_PITCH 5233 #define UVD_JPEG_UV_PITCH__UV_PITCH__SHIFT 0x0 5234 #define UVD_JPEG_UV_PITCH__UV_PITCH_MASK 0xFFFFFFFFL 5235 //JPEG_DEC_Y_GFX8_TILING_SURFACE 5236 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_WIDTH__SHIFT 0x0 5237 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_HEIGHT__SHIFT 0x2 5238 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT__SHIFT 0x4 5239 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__NUM_BANKS__SHIFT 0x6 5240 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__PIPE_CONFIG__SHIFT 0x8 5241 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__TILE_SPLIT__SHIFT 0xd 5242 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__ARRAY_MODE__SHIFT 0x10 5243 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_WIDTH_MASK 0x00000003L 5244 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_HEIGHT_MASK 0x0000000CL 5245 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT_MASK 0x00000030L 5246 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__NUM_BANKS_MASK 0x000000C0L 5247 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__PIPE_CONFIG_MASK 0x00001F00L 5248 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__TILE_SPLIT_MASK 0x0000E000L 5249 #define JPEG_DEC_Y_GFX8_TILING_SURFACE__ARRAY_MODE_MASK 0x000F0000L 5250 //JPEG_DEC_UV_GFX8_TILING_SURFACE 5251 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_WIDTH__SHIFT 0x0 5252 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_HEIGHT__SHIFT 0x2 5253 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT__SHIFT 0x4 5254 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__NUM_BANKS__SHIFT 0x6 5255 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__PIPE_CONFIG__SHIFT 0x8 5256 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__TILE_SPLIT__SHIFT 0xd 5257 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__ARRAY_MODE__SHIFT 0x10 5258 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_WIDTH_MASK 0x00000003L 5259 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_HEIGHT_MASK 0x0000000CL 5260 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT_MASK 0x00000030L 5261 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__NUM_BANKS_MASK 0x000000C0L 5262 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__PIPE_CONFIG_MASK 0x00001F00L 5263 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__TILE_SPLIT_MASK 0x0000E000L 5264 #define JPEG_DEC_UV_GFX8_TILING_SURFACE__ARRAY_MODE_MASK 0x000F0000L 5265 //JPEG_DEC_GFX8_ADDR_CONFIG 5266 #define JPEG_DEC_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 5267 #define JPEG_DEC_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L 5268 //JPEG_DEC_Y_GFX10_TILING_SURFACE 5269 #define JPEG_DEC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0 5270 #define JPEG_DEC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL 5271 //JPEG_DEC_UV_GFX10_TILING_SURFACE 5272 #define JPEG_DEC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0 5273 #define JPEG_DEC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL 5274 //JPEG_DEC_GFX10_ADDR_CONFIG 5275 #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 5276 #define JPEG_DEC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 5277 #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 5278 #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 5279 #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 5280 #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 5281 #define JPEG_DEC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 5282 #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L 5283 #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 5284 #define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 5285 //JPEG_DEC_ADDR_MODE 5286 #define JPEG_DEC_ADDR_MODE__ADDR_MODE_Y__SHIFT 0x0 5287 #define JPEG_DEC_ADDR_MODE__ADDR_MODE_UV__SHIFT 0x2 5288 #define JPEG_DEC_ADDR_MODE__ADDR_LIB_SEL__SHIFT 0xc 5289 #define JPEG_DEC_ADDR_MODE__ADDR_MODE_Y_MASK 0x00000003L 5290 #define JPEG_DEC_ADDR_MODE__ADDR_MODE_UV_MASK 0x0000000CL 5291 #define JPEG_DEC_ADDR_MODE__ADDR_LIB_SEL_MASK 0x00007000L 5292 //UVD_JPEG_OUTPUT_XY 5293 #define UVD_JPEG_OUTPUT_XY__OUTPUT_X__SHIFT 0x0 5294 #define UVD_JPEG_OUTPUT_XY__OUTPUT_Y__SHIFT 0x10 5295 #define UVD_JPEG_OUTPUT_XY__OUTPUT_X_MASK 0x00003FFFL 5296 #define UVD_JPEG_OUTPUT_XY__OUTPUT_Y_MASK 0x3FFF0000L 5297 //UVD_JPEG_GPCOM_CMD 5298 #define UVD_JPEG_GPCOM_CMD__CMD__SHIFT 0x1 5299 #define UVD_JPEG_GPCOM_CMD__CMD_MASK 0x0000000EL 5300 //UVD_JPEG_GPCOM_DATA0 5301 #define UVD_JPEG_GPCOM_DATA0__DATA0__SHIFT 0x0 5302 #define UVD_JPEG_GPCOM_DATA0__DATA0_MASK 0xFFFFFFFFL 5303 //UVD_JPEG_GPCOM_DATA1 5304 #define UVD_JPEG_GPCOM_DATA1__DATA1__SHIFT 0x0 5305 #define UVD_JPEG_GPCOM_DATA1__DATA1_MASK 0xFFFFFFFFL 5306 //UVD_JPEG_SCRATCH1 5307 #define UVD_JPEG_SCRATCH1__SCRATCH1__SHIFT 0x0 5308 #define UVD_JPEG_SCRATCH1__SCRATCH1_MASK 0xFFFFFFFFL 5309 //UVD_JPEG_DEC_SOFT_RST 5310 #define UVD_JPEG_DEC_SOFT_RST__SOFT_RESET__SHIFT 0x0 5311 #define UVD_JPEG_DEC_SOFT_RST__RESET_STATUS__SHIFT 0x10 5312 #define UVD_JPEG_DEC_SOFT_RST__SOFT_RESET_MASK 0x00000001L 5313 #define UVD_JPEG_DEC_SOFT_RST__RESET_STATUS_MASK 0x00010000L 5314 5315 // addressBlock: aid_uvd0_vcn_edcc_dec 5316 //VCN_UE_ERR_STATUS_LO_VIDD 5317 #define VCN_UE_ERR_STATUS_LO_VIDD__Err_Status_Valid_Flag__SHIFT 0x0 5318 #define VCN_UE_ERR_STATUS_LO_VIDD__Address_Valid_Flag__SHIFT 0x1 5319 #define VCN_UE_ERR_STATUS_LO_VIDD__Address__SHIFT 0x2 5320 #define VCN_UE_ERR_STATUS_LO_VIDD__Memory_id__SHIFT 0x18 5321 #define VCN_UE_ERR_STATUS_LO_VIDD__Err_Status_Valid_Flag_MASK 0x00000001L 5322 #define VCN_UE_ERR_STATUS_LO_VIDD__Address_Valid_Flag_MASK 0x00000002L 5323 #define VCN_UE_ERR_STATUS_LO_VIDD__Address_MASK 0x00FFFFFCL 5324 #define VCN_UE_ERR_STATUS_LO_VIDD__Memory_id_MASK 0xFF000000L 5325 //VCN_UE_ERR_STATUS_HI_VIDD 5326 #define VCN_UE_ERR_STATUS_HI_VIDD__ECC__SHIFT 0x0 5327 #define VCN_UE_ERR_STATUS_HI_VIDD__Parity__SHIFT 0x1 5328 #define VCN_UE_ERR_STATUS_HI_VIDD__Err_Info_Valid_Flag__SHIFT 0x2 5329 #define VCN_UE_ERR_STATUS_HI_VIDD__Err_Info__SHIFT 0x3 5330 #define VCN_UE_ERR_STATUS_HI_VIDD__UE_Cnt__SHIFT 0x17 5331 #define VCN_UE_ERR_STATUS_HI_VIDD__FED_Cnt__SHIFT 0x1a 5332 #define VCN_UE_ERR_STATUS_HI_VIDD__RESERVED__SHIFT 0x1d 5333 #define VCN_UE_ERR_STATUS_HI_VIDD__Err_clr__SHIFT 0x1f 5334 #define VCN_UE_ERR_STATUS_HI_VIDD__ECC_MASK 0x00000001L 5335 #define VCN_UE_ERR_STATUS_HI_VIDD__Parity_MASK 0x00000002L 5336 #define VCN_UE_ERR_STATUS_HI_VIDD__Err_Info_Valid_Flag_MASK 0x00000004L 5337 #define VCN_UE_ERR_STATUS_HI_VIDD__Err_Info_MASK 0x007FFFF8L 5338 #define VCN_UE_ERR_STATUS_HI_VIDD__UE_Cnt_MASK 0x03800000L 5339 #define VCN_UE_ERR_STATUS_HI_VIDD__FED_Cnt_MASK 0x1C000000L 5340 #define VCN_UE_ERR_STATUS_HI_VIDD__RESERVED_MASK 0x60000000L 5341 #define VCN_UE_ERR_STATUS_HI_VIDD__Err_clr_MASK 0x80000000L 5342 //VCN_UE_ERR_STATUS_LO_VIDV 5343 #define VCN_UE_ERR_STATUS_LO_VIDV__Err_Status_Valid_Flag__SHIFT 0x0 5344 #define VCN_UE_ERR_STATUS_LO_VIDV__Address_Valid_Flag__SHIFT 0x1 5345 #define VCN_UE_ERR_STATUS_LO_VIDV__Address__SHIFT 0x2 5346 #define VCN_UE_ERR_STATUS_LO_VIDV__Memory_id__SHIFT 0x18 5347 #define VCN_UE_ERR_STATUS_LO_VIDV__Err_Status_Valid_Flag_MASK 0x00000001L 5348 #define VCN_UE_ERR_STATUS_LO_VIDV__Address_Valid_Flag_MASK 0x00000002L 5349 #define VCN_UE_ERR_STATUS_LO_VIDV__Address_MASK 0x00FFFFFCL 5350 #define VCN_UE_ERR_STATUS_LO_VIDV__Memory_id_MASK 0xFF000000L 5351 //VCN_UE_ERR_STATUS_HI_VIDV 5352 #define VCN_UE_ERR_STATUS_HI_VIDV__ECC__SHIFT 0x0 5353 #define VCN_UE_ERR_STATUS_HI_VIDV__Parity__SHIFT 0x1 5354 #define VCN_UE_ERR_STATUS_HI_VIDV__Err_Info_Valid_Flag__SHIFT 0x2 5355 #define VCN_UE_ERR_STATUS_HI_VIDV__Err_Info__SHIFT 0x3 5356 #define VCN_UE_ERR_STATUS_HI_VIDV__UE_Cnt__SHIFT 0x17 5357 #define VCN_UE_ERR_STATUS_HI_VIDV__FED_Cnt__SHIFT 0x1a 5358 #define VCN_UE_ERR_STATUS_HI_VIDV__RESERVED__SHIFT 0x1d 5359 #define VCN_UE_ERR_STATUS_HI_VIDV__Err_clr__SHIFT 0x1f 5360 #define VCN_UE_ERR_STATUS_HI_VIDV__ECC_MASK 0x00000001L 5361 #define VCN_UE_ERR_STATUS_HI_VIDV__Parity_MASK 0x00000002L 5362 #define VCN_UE_ERR_STATUS_HI_VIDV__Err_Info_Valid_Flag_MASK 0x00000004L 5363 #define VCN_UE_ERR_STATUS_HI_VIDV__Err_Info_MASK 0x007FFFF8L 5364 #define VCN_UE_ERR_STATUS_HI_VIDV__UE_Cnt_MASK 0x03800000L 5365 #define VCN_UE_ERR_STATUS_HI_VIDV__FED_Cnt_MASK 0x1C000000L 5366 #define VCN_UE_ERR_STATUS_HI_VIDV__RESERVED_MASK 0x60000000L 5367 #define VCN_UE_ERR_STATUS_HI_VIDV__Err_clr_MASK 0x80000000L 5368 //VCN_CE_ERR_STATUS_LO_MMSCHD 5369 #define VCN_CE_ERR_STATUS_LO_MMSCHD__Err_Status_Valid_Flag__SHIFT 0x0 5370 #define VCN_CE_ERR_STATUS_LO_MMSCHD__Address_Valid_Flag__SHIFT 0x1 5371 #define VCN_CE_ERR_STATUS_LO_MMSCHD__Address__SHIFT 0x2 5372 #define VCN_CE_ERR_STATUS_LO_MMSCHD__Memory_id__SHIFT 0x18 5373 #define VCN_CE_ERR_STATUS_LO_MMSCHD__Err_Status_Valid_Flag_MASK 0x00000001L 5374 #define VCN_CE_ERR_STATUS_LO_MMSCHD__Address_Valid_Flag_MASK 0x00000002L 5375 #define VCN_CE_ERR_STATUS_LO_MMSCHD__Address_MASK 0x00FFFFFCL 5376 #define VCN_CE_ERR_STATUS_LO_MMSCHD__Memory_id_MASK 0xFF000000L 5377 //VCN_CE_ERR_STATUS_HI_MMSCHD 5378 #define VCN_CE_ERR_STATUS_HI_MMSCHD__ECC__SHIFT 0x0 5379 #define VCN_CE_ERR_STATUS_HI_MMSCHD__Other__SHIFT 0x1 5380 #define VCN_CE_ERR_STATUS_HI_MMSCHD__Err_Info_Valid_Flag__SHIFT 0x2 5381 #define VCN_CE_ERR_STATUS_HI_MMSCHD__Err_Info__SHIFT 0x3 5382 #define VCN_CE_ERR_STATUS_HI_MMSCHD__CE_Cnt__SHIFT 0x17 5383 #define VCN_CE_ERR_STATUS_HI_MMSCHD__Poison__SHIFT 0x1c 5384 #define VCN_CE_ERR_STATUS_HI_MMSCHD__RESERVED__SHIFT 0x1d 5385 #define VCN_CE_ERR_STATUS_HI_MMSCHD__Err_clr__SHIFT 0x1f 5386 #define VCN_CE_ERR_STATUS_HI_MMSCHD__ECC_MASK 0x00000001L 5387 #define VCN_CE_ERR_STATUS_HI_MMSCHD__Other_MASK 0x00000002L 5388 #define VCN_CE_ERR_STATUS_HI_MMSCHD__Err_Info_Valid_Flag_MASK 0x00000004L 5389 #define VCN_CE_ERR_STATUS_HI_MMSCHD__Err_Info_MASK 0x007FFFF8L 5390 #define VCN_CE_ERR_STATUS_HI_MMSCHD__CE_Cnt_MASK 0x03800000L 5391 #define VCN_CE_ERR_STATUS_HI_MMSCHD__Poison_MASK 0x10000000L 5392 #define VCN_CE_ERR_STATUS_HI_MMSCHD__RESERVED_MASK 0x60000000L 5393 #define VCN_CE_ERR_STATUS_HI_MMSCHD__Err_clr_MASK 0x80000000L 5394 //VCN_UE_ERR_STATUS_LO_JPEG0S 5395 #define VCN_UE_ERR_STATUS_LO_JPEG0S__Err_Status_Valid_Flag__SHIFT 0x0 5396 #define VCN_UE_ERR_STATUS_LO_JPEG0S__Address_Valid_Flag__SHIFT 0x1 5397 #define VCN_UE_ERR_STATUS_LO_JPEG0S__Address__SHIFT 0x2 5398 #define VCN_UE_ERR_STATUS_LO_JPEG0S__Memory_id__SHIFT 0x18 5399 #define VCN_UE_ERR_STATUS_LO_JPEG0S__Err_Status_Valid_Flag_MASK 0x00000001L 5400 #define VCN_UE_ERR_STATUS_LO_JPEG0S__Address_Valid_Flag_MASK 0x00000002L 5401 #define VCN_UE_ERR_STATUS_LO_JPEG0S__Address_MASK 0x00FFFFFCL 5402 #define VCN_UE_ERR_STATUS_LO_JPEG0S__Memory_id_MASK 0xFF000000L 5403 //VCN_UE_ERR_STATUS_HI_JPEG0S 5404 #define VCN_UE_ERR_STATUS_HI_JPEG0S__ECC__SHIFT 0x0 5405 #define VCN_UE_ERR_STATUS_HI_JPEG0S__Parity__SHIFT 0x1 5406 #define VCN_UE_ERR_STATUS_HI_JPEG0S__Err_Info_Valid_Flag__SHIFT 0x2 5407 #define VCN_UE_ERR_STATUS_HI_JPEG0S__Err_Info__SHIFT 0x3 5408 #define VCN_UE_ERR_STATUS_HI_JPEG0S__UE_Cnt__SHIFT 0x17 5409 #define VCN_UE_ERR_STATUS_HI_JPEG0S__FED_Cnt__SHIFT 0x1a 5410 #define VCN_UE_ERR_STATUS_HI_JPEG0S__RESERVED__SHIFT 0x1d 5411 #define VCN_UE_ERR_STATUS_HI_JPEG0S__Err_clr__SHIFT 0x1f 5412 #define VCN_UE_ERR_STATUS_HI_JPEG0S__ECC_MASK 0x00000001L 5413 #define VCN_UE_ERR_STATUS_HI_JPEG0S__Parity_MASK 0x00000002L 5414 #define VCN_UE_ERR_STATUS_HI_JPEG0S__Err_Info_Valid_Flag_MASK 0x00000004L 5415 #define VCN_UE_ERR_STATUS_HI_JPEG0S__Err_Info_MASK 0x007FFFF8L 5416 #define VCN_UE_ERR_STATUS_HI_JPEG0S__UE_Cnt_MASK 0x03800000L 5417 #define VCN_UE_ERR_STATUS_HI_JPEG0S__FED_Cnt_MASK 0x1C000000L 5418 #define VCN_UE_ERR_STATUS_HI_JPEG0S__RESERVED_MASK 0x60000000L 5419 #define VCN_UE_ERR_STATUS_HI_JPEG0S__Err_clr_MASK 0x80000000L 5420 //VCN_UE_ERR_STATUS_LO_JPEG0D 5421 #define VCN_UE_ERR_STATUS_LO_JPEG0D__Err_Status_Valid_Flag__SHIFT 0x0 5422 #define VCN_UE_ERR_STATUS_LO_JPEG0D__Address_Valid_Flag__SHIFT 0x1 5423 #define VCN_UE_ERR_STATUS_LO_JPEG0D__Address__SHIFT 0x2 5424 #define VCN_UE_ERR_STATUS_LO_JPEG0D__Memory_id__SHIFT 0x18 5425 #define VCN_UE_ERR_STATUS_LO_JPEG0D__Err_Status_Valid_Flag_MASK 0x00000001L 5426 #define VCN_UE_ERR_STATUS_LO_JPEG0D__Address_Valid_Flag_MASK 0x00000002L 5427 #define VCN_UE_ERR_STATUS_LO_JPEG0D__Address_MASK 0x00FFFFFCL 5428 #define VCN_UE_ERR_STATUS_LO_JPEG0D__Memory_id_MASK 0xFF000000L 5429 //VCN_UE_ERR_STATUS_HI_JPEG0D 5430 #define VCN_UE_ERR_STATUS_HI_JPEG0D__ECC__SHIFT 0x0 5431 #define VCN_UE_ERR_STATUS_HI_JPEG0D__Parity__SHIFT 0x1 5432 #define VCN_UE_ERR_STATUS_HI_JPEG0D__Err_Info_Valid_Flag__SHIFT 0x2 5433 #define VCN_UE_ERR_STATUS_HI_JPEG0D__Err_Info__SHIFT 0x3 5434 #define VCN_UE_ERR_STATUS_HI_JPEG0D__UE_Cnt__SHIFT 0x17 5435 #define VCN_UE_ERR_STATUS_HI_JPEG0D__FED_Cnt__SHIFT 0x1a 5436 #define VCN_UE_ERR_STATUS_HI_JPEG0D__RESERVED__SHIFT 0x1d 5437 #define VCN_UE_ERR_STATUS_HI_JPEG0D__Err_clr__SHIFT 0x1f 5438 #define VCN_UE_ERR_STATUS_HI_JPEG0D__ECC_MASK 0x00000001L 5439 #define VCN_UE_ERR_STATUS_HI_JPEG0D__Parity_MASK 0x00000002L 5440 #define VCN_UE_ERR_STATUS_HI_JPEG0D__Err_Info_Valid_Flag_MASK 0x00000004L 5441 #define VCN_UE_ERR_STATUS_HI_JPEG0D__Err_Info_MASK 0x007FFFF8L 5442 #define VCN_UE_ERR_STATUS_HI_JPEG0D__UE_Cnt_MASK 0x03800000L 5443 #define VCN_UE_ERR_STATUS_HI_JPEG0D__FED_Cnt_MASK 0x1C000000L 5444 #define VCN_UE_ERR_STATUS_HI_JPEG0D__RESERVED_MASK 0x60000000L 5445 #define VCN_UE_ERR_STATUS_HI_JPEG0D__Err_clr_MASK 0x80000000L 5446 //VCN_UE_ERR_STATUS_LO_JPEG1S 5447 #define VCN_UE_ERR_STATUS_LO_JPEG1S__Err_Status_Valid_Flag__SHIFT 0x0 5448 #define VCN_UE_ERR_STATUS_LO_JPEG1S__Address_Valid_Flag__SHIFT 0x1 5449 #define VCN_UE_ERR_STATUS_LO_JPEG1S__Address__SHIFT 0x2 5450 #define VCN_UE_ERR_STATUS_LO_JPEG1S__Memory_id__SHIFT 0x18 5451 #define VCN_UE_ERR_STATUS_LO_JPEG1S__Err_Status_Valid_Flag_MASK 0x00000001L 5452 #define VCN_UE_ERR_STATUS_LO_JPEG1S__Address_Valid_Flag_MASK 0x00000002L 5453 #define VCN_UE_ERR_STATUS_LO_JPEG1S__Address_MASK 0x00FFFFFCL 5454 #define VCN_UE_ERR_STATUS_LO_JPEG1S__Memory_id_MASK 0xFF000000L 5455 //VCN_UE_ERR_STATUS_HI_JPEG1S 5456 #define VCN_UE_ERR_STATUS_HI_JPEG1S__ECC__SHIFT 0x0 5457 #define VCN_UE_ERR_STATUS_HI_JPEG1S__Parity__SHIFT 0x1 5458 #define VCN_UE_ERR_STATUS_HI_JPEG1S__Err_Info_Valid_Flag__SHIFT 0x2 5459 #define VCN_UE_ERR_STATUS_HI_JPEG1S__Err_Info__SHIFT 0x3 5460 #define VCN_UE_ERR_STATUS_HI_JPEG1S__UE_Cnt__SHIFT 0x17 5461 #define VCN_UE_ERR_STATUS_HI_JPEG1S__FED_Cnt__SHIFT 0x1a 5462 #define VCN_UE_ERR_STATUS_HI_JPEG1S__RESERVED__SHIFT 0x1d 5463 #define VCN_UE_ERR_STATUS_HI_JPEG1S__Err_clr__SHIFT 0x1f 5464 #define VCN_UE_ERR_STATUS_HI_JPEG1S__ECC_MASK 0x00000001L 5465 #define VCN_UE_ERR_STATUS_HI_JPEG1S__Parity_MASK 0x00000002L 5466 #define VCN_UE_ERR_STATUS_HI_JPEG1S__Err_Info_Valid_Flag_MASK 0x00000004L 5467 #define VCN_UE_ERR_STATUS_HI_JPEG1S__Err_Info_MASK 0x007FFFF8L 5468 #define VCN_UE_ERR_STATUS_HI_JPEG1S__UE_Cnt_MASK 0x03800000L 5469 #define VCN_UE_ERR_STATUS_HI_JPEG1S__FED_Cnt_MASK 0x1C000000L 5470 #define VCN_UE_ERR_STATUS_HI_JPEG1S__RESERVED_MASK 0x60000000L 5471 #define VCN_UE_ERR_STATUS_HI_JPEG1S__Err_clr_MASK 0x80000000L 5472 //VCN_UE_ERR_STATUS_LO_JPEG1D 5473 #define VCN_UE_ERR_STATUS_LO_JPEG1D__Err_Status_Valid_Flag__SHIFT 0x0 5474 #define VCN_UE_ERR_STATUS_LO_JPEG1D__Address_Valid_Flag__SHIFT 0x1 5475 #define VCN_UE_ERR_STATUS_LO_JPEG1D__Address__SHIFT 0x2 5476 #define VCN_UE_ERR_STATUS_LO_JPEG1D__Memory_id__SHIFT 0x18 5477 #define VCN_UE_ERR_STATUS_LO_JPEG1D__Err_Status_Valid_Flag_MASK 0x00000001L 5478 #define VCN_UE_ERR_STATUS_LO_JPEG1D__Address_Valid_Flag_MASK 0x00000002L 5479 #define VCN_UE_ERR_STATUS_LO_JPEG1D__Address_MASK 0x00FFFFFCL 5480 #define VCN_UE_ERR_STATUS_LO_JPEG1D__Memory_id_MASK 0xFF000000L 5481 //VCN_UE_ERR_STATUS_HI_JPEG1D 5482 #define VCN_UE_ERR_STATUS_HI_JPEG1D__ECC__SHIFT 0x0 5483 #define VCN_UE_ERR_STATUS_HI_JPEG1D__Parity__SHIFT 0x1 5484 #define VCN_UE_ERR_STATUS_HI_JPEG1D__Err_Info_Valid_Flag__SHIFT 0x2 5485 #define VCN_UE_ERR_STATUS_HI_JPEG1D__Err_Info__SHIFT 0x3 5486 #define VCN_UE_ERR_STATUS_HI_JPEG1D__UE_Cnt__SHIFT 0x17 5487 #define VCN_UE_ERR_STATUS_HI_JPEG1D__FED_Cnt__SHIFT 0x1a 5488 #define VCN_UE_ERR_STATUS_HI_JPEG1D__RESERVED__SHIFT 0x1d 5489 #define VCN_UE_ERR_STATUS_HI_JPEG1D__Err_clr__SHIFT 0x1f 5490 #define VCN_UE_ERR_STATUS_HI_JPEG1D__ECC_MASK 0x00000001L 5491 #define VCN_UE_ERR_STATUS_HI_JPEG1D__Parity_MASK 0x00000002L 5492 #define VCN_UE_ERR_STATUS_HI_JPEG1D__Err_Info_Valid_Flag_MASK 0x00000004L 5493 #define VCN_UE_ERR_STATUS_HI_JPEG1D__Err_Info_MASK 0x007FFFF8L 5494 #define VCN_UE_ERR_STATUS_HI_JPEG1D__UE_Cnt_MASK 0x03800000L 5495 #define VCN_UE_ERR_STATUS_HI_JPEG1D__FED_Cnt_MASK 0x1C000000L 5496 #define VCN_UE_ERR_STATUS_HI_JPEG1D__RESERVED_MASK 0x60000000L 5497 #define VCN_UE_ERR_STATUS_HI_JPEG1D__Err_clr_MASK 0x80000000L 5498 //VCN_UE_ERR_STATUS_LO_JPEG2S 5499 #define VCN_UE_ERR_STATUS_LO_JPEG2S__Err_Status_Valid_Flag__SHIFT 0x0 5500 #define VCN_UE_ERR_STATUS_LO_JPEG2S__Address_Valid_Flag__SHIFT 0x1 5501 #define VCN_UE_ERR_STATUS_LO_JPEG2S__Address__SHIFT 0x2 5502 #define VCN_UE_ERR_STATUS_LO_JPEG2S__Memory_id__SHIFT 0x18 5503 #define VCN_UE_ERR_STATUS_LO_JPEG2S__Err_Status_Valid_Flag_MASK 0x00000001L 5504 #define VCN_UE_ERR_STATUS_LO_JPEG2S__Address_Valid_Flag_MASK 0x00000002L 5505 #define VCN_UE_ERR_STATUS_LO_JPEG2S__Address_MASK 0x00FFFFFCL 5506 #define VCN_UE_ERR_STATUS_LO_JPEG2S__Memory_id_MASK 0xFF000000L 5507 //VCN_UE_ERR_STATUS_HI_JPEG2S 5508 #define VCN_UE_ERR_STATUS_HI_JPEG2S__ECC__SHIFT 0x0 5509 #define VCN_UE_ERR_STATUS_HI_JPEG2S__Parity__SHIFT 0x1 5510 #define VCN_UE_ERR_STATUS_HI_JPEG2S__Err_Info_Valid_Flag__SHIFT 0x2 5511 #define VCN_UE_ERR_STATUS_HI_JPEG2S__Err_Info__SHIFT 0x3 5512 #define VCN_UE_ERR_STATUS_HI_JPEG2S__UE_Cnt__SHIFT 0x17 5513 #define VCN_UE_ERR_STATUS_HI_JPEG2S__FED_Cnt__SHIFT 0x1a 5514 #define VCN_UE_ERR_STATUS_HI_JPEG2S__RESERVED__SHIFT 0x1d 5515 #define VCN_UE_ERR_STATUS_HI_JPEG2S__Err_clr__SHIFT 0x1f 5516 #define VCN_UE_ERR_STATUS_HI_JPEG2S__ECC_MASK 0x00000001L 5517 #define VCN_UE_ERR_STATUS_HI_JPEG2S__Parity_MASK 0x00000002L 5518 #define VCN_UE_ERR_STATUS_HI_JPEG2S__Err_Info_Valid_Flag_MASK 0x00000004L 5519 #define VCN_UE_ERR_STATUS_HI_JPEG2S__Err_Info_MASK 0x007FFFF8L 5520 #define VCN_UE_ERR_STATUS_HI_JPEG2S__UE_Cnt_MASK 0x03800000L 5521 #define VCN_UE_ERR_STATUS_HI_JPEG2S__FED_Cnt_MASK 0x1C000000L 5522 #define VCN_UE_ERR_STATUS_HI_JPEG2S__RESERVED_MASK 0x60000000L 5523 #define VCN_UE_ERR_STATUS_HI_JPEG2S__Err_clr_MASK 0x80000000L 5524 //VCN_UE_ERR_STATUS_LO_JPEG2D 5525 #define VCN_UE_ERR_STATUS_LO_JPEG2D__Err_Status_Valid_Flag__SHIFT 0x0 5526 #define VCN_UE_ERR_STATUS_LO_JPEG2D__Address_Valid_Flag__SHIFT 0x1 5527 #define VCN_UE_ERR_STATUS_LO_JPEG2D__Address__SHIFT 0x2 5528 #define VCN_UE_ERR_STATUS_LO_JPEG2D__Memory_id__SHIFT 0x18 5529 #define VCN_UE_ERR_STATUS_LO_JPEG2D__Err_Status_Valid_Flag_MASK 0x00000001L 5530 #define VCN_UE_ERR_STATUS_LO_JPEG2D__Address_Valid_Flag_MASK 0x00000002L 5531 #define VCN_UE_ERR_STATUS_LO_JPEG2D__Address_MASK 0x00FFFFFCL 5532 #define VCN_UE_ERR_STATUS_LO_JPEG2D__Memory_id_MASK 0xFF000000L 5533 //VCN_UE_ERR_STATUS_HI_JPEG2D 5534 #define VCN_UE_ERR_STATUS_HI_JPEG2D__ECC__SHIFT 0x0 5535 #define VCN_UE_ERR_STATUS_HI_JPEG2D__Parity__SHIFT 0x1 5536 #define VCN_UE_ERR_STATUS_HI_JPEG2D__Err_Info_Valid_Flag__SHIFT 0x2 5537 #define VCN_UE_ERR_STATUS_HI_JPEG2D__Err_Info__SHIFT 0x3 5538 #define VCN_UE_ERR_STATUS_HI_JPEG2D__UE_Cnt__SHIFT 0x17 5539 #define VCN_UE_ERR_STATUS_HI_JPEG2D__FED_Cnt__SHIFT 0x1a 5540 #define VCN_UE_ERR_STATUS_HI_JPEG2D__RESERVED__SHIFT 0x1d 5541 #define VCN_UE_ERR_STATUS_HI_JPEG2D__Err_clr__SHIFT 0x1f 5542 #define VCN_UE_ERR_STATUS_HI_JPEG2D__ECC_MASK 0x00000001L 5543 #define VCN_UE_ERR_STATUS_HI_JPEG2D__Parity_MASK 0x00000002L 5544 #define VCN_UE_ERR_STATUS_HI_JPEG2D__Err_Info_Valid_Flag_MASK 0x00000004L 5545 #define VCN_UE_ERR_STATUS_HI_JPEG2D__Err_Info_MASK 0x007FFFF8L 5546 #define VCN_UE_ERR_STATUS_HI_JPEG2D__UE_Cnt_MASK 0x03800000L 5547 #define VCN_UE_ERR_STATUS_HI_JPEG2D__FED_Cnt_MASK 0x1C000000L 5548 #define VCN_UE_ERR_STATUS_HI_JPEG2D__RESERVED_MASK 0x60000000L 5549 #define VCN_UE_ERR_STATUS_HI_JPEG2D__Err_clr_MASK 0x80000000L 5550 //VCN_UE_ERR_STATUS_LO_JPEG3S 5551 #define VCN_UE_ERR_STATUS_LO_JPEG3S__Err_Status_Valid_Flag__SHIFT 0x0 5552 #define VCN_UE_ERR_STATUS_LO_JPEG3S__Address_Valid_Flag__SHIFT 0x1 5553 #define VCN_UE_ERR_STATUS_LO_JPEG3S__Address__SHIFT 0x2 5554 #define VCN_UE_ERR_STATUS_LO_JPEG3S__Memory_id__SHIFT 0x18 5555 #define VCN_UE_ERR_STATUS_LO_JPEG3S__Err_Status_Valid_Flag_MASK 0x00000001L 5556 #define VCN_UE_ERR_STATUS_LO_JPEG3S__Address_Valid_Flag_MASK 0x00000002L 5557 #define VCN_UE_ERR_STATUS_LO_JPEG3S__Address_MASK 0x00FFFFFCL 5558 #define VCN_UE_ERR_STATUS_LO_JPEG3S__Memory_id_MASK 0xFF000000L 5559 //VCN_UE_ERR_STATUS_HI_JPEG3S 5560 #define VCN_UE_ERR_STATUS_HI_JPEG3S__ECC__SHIFT 0x0 5561 #define VCN_UE_ERR_STATUS_HI_JPEG3S__Parity__SHIFT 0x1 5562 #define VCN_UE_ERR_STATUS_HI_JPEG3S__Err_Info_Valid_Flag__SHIFT 0x2 5563 #define VCN_UE_ERR_STATUS_HI_JPEG3S__Err_Info__SHIFT 0x3 5564 #define VCN_UE_ERR_STATUS_HI_JPEG3S__UE_Cnt__SHIFT 0x17 5565 #define VCN_UE_ERR_STATUS_HI_JPEG3S__FED_Cnt__SHIFT 0x1a 5566 #define VCN_UE_ERR_STATUS_HI_JPEG3S__RESERVED__SHIFT 0x1d 5567 #define VCN_UE_ERR_STATUS_HI_JPEG3S__Err_clr__SHIFT 0x1f 5568 #define VCN_UE_ERR_STATUS_HI_JPEG3S__ECC_MASK 0x00000001L 5569 #define VCN_UE_ERR_STATUS_HI_JPEG3S__Parity_MASK 0x00000002L 5570 #define VCN_UE_ERR_STATUS_HI_JPEG3S__Err_Info_Valid_Flag_MASK 0x00000004L 5571 #define VCN_UE_ERR_STATUS_HI_JPEG3S__Err_Info_MASK 0x007FFFF8L 5572 #define VCN_UE_ERR_STATUS_HI_JPEG3S__UE_Cnt_MASK 0x03800000L 5573 #define VCN_UE_ERR_STATUS_HI_JPEG3S__FED_Cnt_MASK 0x1C000000L 5574 #define VCN_UE_ERR_STATUS_HI_JPEG3S__RESERVED_MASK 0x60000000L 5575 #define VCN_UE_ERR_STATUS_HI_JPEG3S__Err_clr_MASK 0x80000000L 5576 //VCN_UE_ERR_STATUS_LO_JPEG3D 5577 #define VCN_UE_ERR_STATUS_LO_JPEG3D__Err_Status_Valid_Flag__SHIFT 0x0 5578 #define VCN_UE_ERR_STATUS_LO_JPEG3D__Address_Valid_Flag__SHIFT 0x1 5579 #define VCN_UE_ERR_STATUS_LO_JPEG3D__Address__SHIFT 0x2 5580 #define VCN_UE_ERR_STATUS_LO_JPEG3D__Memory_id__SHIFT 0x18 5581 #define VCN_UE_ERR_STATUS_LO_JPEG3D__Err_Status_Valid_Flag_MASK 0x00000001L 5582 #define VCN_UE_ERR_STATUS_LO_JPEG3D__Address_Valid_Flag_MASK 0x00000002L 5583 #define VCN_UE_ERR_STATUS_LO_JPEG3D__Address_MASK 0x00FFFFFCL 5584 #define VCN_UE_ERR_STATUS_LO_JPEG3D__Memory_id_MASK 0xFF000000L 5585 //VCN_UE_ERR_STATUS_HI_JPEG3D 5586 #define VCN_UE_ERR_STATUS_HI_JPEG3D__ECC__SHIFT 0x0 5587 #define VCN_UE_ERR_STATUS_HI_JPEG3D__Parity__SHIFT 0x1 5588 #define VCN_UE_ERR_STATUS_HI_JPEG3D__Err_Info_Valid_Flag__SHIFT 0x2 5589 #define VCN_UE_ERR_STATUS_HI_JPEG3D__Err_Info__SHIFT 0x3 5590 #define VCN_UE_ERR_STATUS_HI_JPEG3D__UE_Cnt__SHIFT 0x17 5591 #define VCN_UE_ERR_STATUS_HI_JPEG3D__FED_Cnt__SHIFT 0x1a 5592 #define VCN_UE_ERR_STATUS_HI_JPEG3D__RESERVED__SHIFT 0x1d 5593 #define VCN_UE_ERR_STATUS_HI_JPEG3D__Err_clr__SHIFT 0x1f 5594 #define VCN_UE_ERR_STATUS_HI_JPEG3D__ECC_MASK 0x00000001L 5595 #define VCN_UE_ERR_STATUS_HI_JPEG3D__Parity_MASK 0x00000002L 5596 #define VCN_UE_ERR_STATUS_HI_JPEG3D__Err_Info_Valid_Flag_MASK 0x00000004L 5597 #define VCN_UE_ERR_STATUS_HI_JPEG3D__Err_Info_MASK 0x007FFFF8L 5598 #define VCN_UE_ERR_STATUS_HI_JPEG3D__UE_Cnt_MASK 0x03800000L 5599 #define VCN_UE_ERR_STATUS_HI_JPEG3D__FED_Cnt_MASK 0x1C000000L 5600 #define VCN_UE_ERR_STATUS_HI_JPEG3D__RESERVED_MASK 0x60000000L 5601 #define VCN_UE_ERR_STATUS_HI_JPEG3D__Err_clr_MASK 0x80000000L 5602 //VCN_UE_ERR_STATUS_LO_JPEG4S 5603 #define VCN_UE_ERR_STATUS_LO_JPEG4S__Err_Status_Valid_Flag__SHIFT 0x0 5604 #define VCN_UE_ERR_STATUS_LO_JPEG4S__Address_Valid_Flag__SHIFT 0x1 5605 #define VCN_UE_ERR_STATUS_LO_JPEG4S__Address__SHIFT 0x2 5606 #define VCN_UE_ERR_STATUS_LO_JPEG4S__Memory_id__SHIFT 0x18 5607 #define VCN_UE_ERR_STATUS_LO_JPEG4S__Err_Status_Valid_Flag_MASK 0x00000001L 5608 #define VCN_UE_ERR_STATUS_LO_JPEG4S__Address_Valid_Flag_MASK 0x00000002L 5609 #define VCN_UE_ERR_STATUS_LO_JPEG4S__Address_MASK 0x00FFFFFCL 5610 #define VCN_UE_ERR_STATUS_LO_JPEG4S__Memory_id_MASK 0xFF000000L 5611 //VCN_UE_ERR_STATUS_HI_JPEG4S 5612 #define VCN_UE_ERR_STATUS_HI_JPEG4S__ECC__SHIFT 0x0 5613 #define VCN_UE_ERR_STATUS_HI_JPEG4S__Parity__SHIFT 0x1 5614 #define VCN_UE_ERR_STATUS_HI_JPEG4S__Err_Info_Valid_Flag__SHIFT 0x2 5615 #define VCN_UE_ERR_STATUS_HI_JPEG4S__Err_Info__SHIFT 0x3 5616 #define VCN_UE_ERR_STATUS_HI_JPEG4S__UE_Cnt__SHIFT 0x17 5617 #define VCN_UE_ERR_STATUS_HI_JPEG4S__FED_Cnt__SHIFT 0x1a 5618 #define VCN_UE_ERR_STATUS_HI_JPEG4S__RESERVED__SHIFT 0x1d 5619 #define VCN_UE_ERR_STATUS_HI_JPEG4S__Err_clr__SHIFT 0x1f 5620 #define VCN_UE_ERR_STATUS_HI_JPEG4S__ECC_MASK 0x00000001L 5621 #define VCN_UE_ERR_STATUS_HI_JPEG4S__Parity_MASK 0x00000002L 5622 #define VCN_UE_ERR_STATUS_HI_JPEG4S__Err_Info_Valid_Flag_MASK 0x00000004L 5623 #define VCN_UE_ERR_STATUS_HI_JPEG4S__Err_Info_MASK 0x007FFFF8L 5624 #define VCN_UE_ERR_STATUS_HI_JPEG4S__UE_Cnt_MASK 0x03800000L 5625 #define VCN_UE_ERR_STATUS_HI_JPEG4S__FED_Cnt_MASK 0x1C000000L 5626 #define VCN_UE_ERR_STATUS_HI_JPEG4S__RESERVED_MASK 0x60000000L 5627 #define VCN_UE_ERR_STATUS_HI_JPEG4S__Err_clr_MASK 0x80000000L 5628 //VCN_UE_ERR_STATUS_LO_JPEG4D 5629 #define VCN_UE_ERR_STATUS_LO_JPEG4D__Err_Status_Valid_Flag__SHIFT 0x0 5630 #define VCN_UE_ERR_STATUS_LO_JPEG4D__Address_Valid_Flag__SHIFT 0x1 5631 #define VCN_UE_ERR_STATUS_LO_JPEG4D__Address__SHIFT 0x2 5632 #define VCN_UE_ERR_STATUS_LO_JPEG4D__Memory_id__SHIFT 0x18 5633 #define VCN_UE_ERR_STATUS_LO_JPEG4D__Err_Status_Valid_Flag_MASK 0x00000001L 5634 #define VCN_UE_ERR_STATUS_LO_JPEG4D__Address_Valid_Flag_MASK 0x00000002L 5635 #define VCN_UE_ERR_STATUS_LO_JPEG4D__Address_MASK 0x00FFFFFCL 5636 #define VCN_UE_ERR_STATUS_LO_JPEG4D__Memory_id_MASK 0xFF000000L 5637 //VCN_UE_ERR_STATUS_HI_JPEG4D 5638 #define VCN_UE_ERR_STATUS_HI_JPEG4D__ECC__SHIFT 0x0 5639 #define VCN_UE_ERR_STATUS_HI_JPEG4D__Parity__SHIFT 0x1 5640 #define VCN_UE_ERR_STATUS_HI_JPEG4D__Err_Info_Valid_Flag__SHIFT 0x2 5641 #define VCN_UE_ERR_STATUS_HI_JPEG4D__Err_Info__SHIFT 0x3 5642 #define VCN_UE_ERR_STATUS_HI_JPEG4D__UE_Cnt__SHIFT 0x17 5643 #define VCN_UE_ERR_STATUS_HI_JPEG4D__FED_Cnt__SHIFT 0x1a 5644 #define VCN_UE_ERR_STATUS_HI_JPEG4D__RESERVED__SHIFT 0x1d 5645 #define VCN_UE_ERR_STATUS_HI_JPEG4D__Err_clr__SHIFT 0x1f 5646 #define VCN_UE_ERR_STATUS_HI_JPEG4D__ECC_MASK 0x00000001L 5647 #define VCN_UE_ERR_STATUS_HI_JPEG4D__Parity_MASK 0x00000002L 5648 #define VCN_UE_ERR_STATUS_HI_JPEG4D__Err_Info_Valid_Flag_MASK 0x00000004L 5649 #define VCN_UE_ERR_STATUS_HI_JPEG4D__Err_Info_MASK 0x007FFFF8L 5650 #define VCN_UE_ERR_STATUS_HI_JPEG4D__UE_Cnt_MASK 0x03800000L 5651 #define VCN_UE_ERR_STATUS_HI_JPEG4D__FED_Cnt_MASK 0x1C000000L 5652 #define VCN_UE_ERR_STATUS_HI_JPEG4D__RESERVED_MASK 0x60000000L 5653 #define VCN_UE_ERR_STATUS_HI_JPEG4D__Err_clr_MASK 0x80000000L 5654 //VCN_UE_ERR_STATUS_LO_JPEG5S 5655 #define VCN_UE_ERR_STATUS_LO_JPEG5S__Err_Status_Valid_Flag__SHIFT 0x0 5656 #define VCN_UE_ERR_STATUS_LO_JPEG5S__Address_Valid_Flag__SHIFT 0x1 5657 #define VCN_UE_ERR_STATUS_LO_JPEG5S__Address__SHIFT 0x2 5658 #define VCN_UE_ERR_STATUS_LO_JPEG5S__Memory_id__SHIFT 0x18 5659 #define VCN_UE_ERR_STATUS_LO_JPEG5S__Err_Status_Valid_Flag_MASK 0x00000001L 5660 #define VCN_UE_ERR_STATUS_LO_JPEG5S__Address_Valid_Flag_MASK 0x00000002L 5661 #define VCN_UE_ERR_STATUS_LO_JPEG5S__Address_MASK 0x00FFFFFCL 5662 #define VCN_UE_ERR_STATUS_LO_JPEG5S__Memory_id_MASK 0xFF000000L 5663 //VCN_UE_ERR_STATUS_HI_JPEG5S 5664 #define VCN_UE_ERR_STATUS_HI_JPEG5S__ECC__SHIFT 0x0 5665 #define VCN_UE_ERR_STATUS_HI_JPEG5S__Parity__SHIFT 0x1 5666 #define VCN_UE_ERR_STATUS_HI_JPEG5S__Err_Info_Valid_Flag__SHIFT 0x2 5667 #define VCN_UE_ERR_STATUS_HI_JPEG5S__Err_Info__SHIFT 0x3 5668 #define VCN_UE_ERR_STATUS_HI_JPEG5S__UE_Cnt__SHIFT 0x17 5669 #define VCN_UE_ERR_STATUS_HI_JPEG5S__FED_Cnt__SHIFT 0x1a 5670 #define VCN_UE_ERR_STATUS_HI_JPEG5S__RESERVED__SHIFT 0x1d 5671 #define VCN_UE_ERR_STATUS_HI_JPEG5S__Err_clr__SHIFT 0x1f 5672 #define VCN_UE_ERR_STATUS_HI_JPEG5S__ECC_MASK 0x00000001L 5673 #define VCN_UE_ERR_STATUS_HI_JPEG5S__Parity_MASK 0x00000002L 5674 #define VCN_UE_ERR_STATUS_HI_JPEG5S__Err_Info_Valid_Flag_MASK 0x00000004L 5675 #define VCN_UE_ERR_STATUS_HI_JPEG5S__Err_Info_MASK 0x007FFFF8L 5676 #define VCN_UE_ERR_STATUS_HI_JPEG5S__UE_Cnt_MASK 0x03800000L 5677 #define VCN_UE_ERR_STATUS_HI_JPEG5S__FED_Cnt_MASK 0x1C000000L 5678 #define VCN_UE_ERR_STATUS_HI_JPEG5S__RESERVED_MASK 0x60000000L 5679 #define VCN_UE_ERR_STATUS_HI_JPEG5S__Err_clr_MASK 0x80000000L 5680 //VCN_UE_ERR_STATUS_LO_JPEG5D 5681 #define VCN_UE_ERR_STATUS_LO_JPEG5D__Err_Status_Valid_Flag__SHIFT 0x0 5682 #define VCN_UE_ERR_STATUS_LO_JPEG5D__Address_Valid_Flag__SHIFT 0x1 5683 #define VCN_UE_ERR_STATUS_LO_JPEG5D__Address__SHIFT 0x2 5684 #define VCN_UE_ERR_STATUS_LO_JPEG5D__Memory_id__SHIFT 0x18 5685 #define VCN_UE_ERR_STATUS_LO_JPEG5D__Err_Status_Valid_Flag_MASK 0x00000001L 5686 #define VCN_UE_ERR_STATUS_LO_JPEG5D__Address_Valid_Flag_MASK 0x00000002L 5687 #define VCN_UE_ERR_STATUS_LO_JPEG5D__Address_MASK 0x00FFFFFCL 5688 #define VCN_UE_ERR_STATUS_LO_JPEG5D__Memory_id_MASK 0xFF000000L 5689 //VCN_UE_ERR_STATUS_HI_JPEG5D 5690 #define VCN_UE_ERR_STATUS_HI_JPEG5D__ECC__SHIFT 0x0 5691 #define VCN_UE_ERR_STATUS_HI_JPEG5D__Parity__SHIFT 0x1 5692 #define VCN_UE_ERR_STATUS_HI_JPEG5D__Err_Info_Valid_Flag__SHIFT 0x2 5693 #define VCN_UE_ERR_STATUS_HI_JPEG5D__Err_Info__SHIFT 0x3 5694 #define VCN_UE_ERR_STATUS_HI_JPEG5D__UE_Cnt__SHIFT 0x17 5695 #define VCN_UE_ERR_STATUS_HI_JPEG5D__FED_Cnt__SHIFT 0x1a 5696 #define VCN_UE_ERR_STATUS_HI_JPEG5D__RESERVED__SHIFT 0x1d 5697 #define VCN_UE_ERR_STATUS_HI_JPEG5D__Err_clr__SHIFT 0x1f 5698 #define VCN_UE_ERR_STATUS_HI_JPEG5D__ECC_MASK 0x00000001L 5699 #define VCN_UE_ERR_STATUS_HI_JPEG5D__Parity_MASK 0x00000002L 5700 #define VCN_UE_ERR_STATUS_HI_JPEG5D__Err_Info_Valid_Flag_MASK 0x00000004L 5701 #define VCN_UE_ERR_STATUS_HI_JPEG5D__Err_Info_MASK 0x007FFFF8L 5702 #define VCN_UE_ERR_STATUS_HI_JPEG5D__UE_Cnt_MASK 0x03800000L 5703 #define VCN_UE_ERR_STATUS_HI_JPEG5D__FED_Cnt_MASK 0x1C000000L 5704 #define VCN_UE_ERR_STATUS_HI_JPEG5D__RESERVED_MASK 0x60000000L 5705 #define VCN_UE_ERR_STATUS_HI_JPEG5D__Err_clr_MASK 0x80000000L 5706 //VCN_UE_ERR_STATUS_LO_JPEG6S 5707 #define VCN_UE_ERR_STATUS_LO_JPEG6S__Err_Status_Valid_Flag__SHIFT 0x0 5708 #define VCN_UE_ERR_STATUS_LO_JPEG6S__Address_Valid_Flag__SHIFT 0x1 5709 #define VCN_UE_ERR_STATUS_LO_JPEG6S__Address__SHIFT 0x2 5710 #define VCN_UE_ERR_STATUS_LO_JPEG6S__Memory_id__SHIFT 0x18 5711 #define VCN_UE_ERR_STATUS_LO_JPEG6S__Err_Status_Valid_Flag_MASK 0x00000001L 5712 #define VCN_UE_ERR_STATUS_LO_JPEG6S__Address_Valid_Flag_MASK 0x00000002L 5713 #define VCN_UE_ERR_STATUS_LO_JPEG6S__Address_MASK 0x00FFFFFCL 5714 #define VCN_UE_ERR_STATUS_LO_JPEG6S__Memory_id_MASK 0xFF000000L 5715 //VCN_UE_ERR_STATUS_HI_JPEG6S 5716 #define VCN_UE_ERR_STATUS_HI_JPEG6S__ECC__SHIFT 0x0 5717 #define VCN_UE_ERR_STATUS_HI_JPEG6S__Parity__SHIFT 0x1 5718 #define VCN_UE_ERR_STATUS_HI_JPEG6S__Err_Info_Valid_Flag__SHIFT 0x2 5719 #define VCN_UE_ERR_STATUS_HI_JPEG6S__Err_Info__SHIFT 0x3 5720 #define VCN_UE_ERR_STATUS_HI_JPEG6S__UE_Cnt__SHIFT 0x17 5721 #define VCN_UE_ERR_STATUS_HI_JPEG6S__FED_Cnt__SHIFT 0x1a 5722 #define VCN_UE_ERR_STATUS_HI_JPEG6S__RESERVED__SHIFT 0x1d 5723 #define VCN_UE_ERR_STATUS_HI_JPEG6S__Err_clr__SHIFT 0x1f 5724 #define VCN_UE_ERR_STATUS_HI_JPEG6S__ECC_MASK 0x00000001L 5725 #define VCN_UE_ERR_STATUS_HI_JPEG6S__Parity_MASK 0x00000002L 5726 #define VCN_UE_ERR_STATUS_HI_JPEG6S__Err_Info_Valid_Flag_MASK 0x00000004L 5727 #define VCN_UE_ERR_STATUS_HI_JPEG6S__Err_Info_MASK 0x007FFFF8L 5728 #define VCN_UE_ERR_STATUS_HI_JPEG6S__UE_Cnt_MASK 0x03800000L 5729 #define VCN_UE_ERR_STATUS_HI_JPEG6S__FED_Cnt_MASK 0x1C000000L 5730 #define VCN_UE_ERR_STATUS_HI_JPEG6S__RESERVED_MASK 0x60000000L 5731 #define VCN_UE_ERR_STATUS_HI_JPEG6S__Err_clr_MASK 0x80000000L 5732 //VCN_UE_ERR_STATUS_LO_JPEG6D 5733 #define VCN_UE_ERR_STATUS_LO_JPEG6D__Err_Status_Valid_Flag__SHIFT 0x0 5734 #define VCN_UE_ERR_STATUS_LO_JPEG6D__Address_Valid_Flag__SHIFT 0x1 5735 #define VCN_UE_ERR_STATUS_LO_JPEG6D__Address__SHIFT 0x2 5736 #define VCN_UE_ERR_STATUS_LO_JPEG6D__Memory_id__SHIFT 0x18 5737 #define VCN_UE_ERR_STATUS_LO_JPEG6D__Err_Status_Valid_Flag_MASK 0x00000001L 5738 #define VCN_UE_ERR_STATUS_LO_JPEG6D__Address_Valid_Flag_MASK 0x00000002L 5739 #define VCN_UE_ERR_STATUS_LO_JPEG6D__Address_MASK 0x00FFFFFCL 5740 #define VCN_UE_ERR_STATUS_LO_JPEG6D__Memory_id_MASK 0xFF000000L 5741 //VCN_UE_ERR_STATUS_HI_JPEG6D 5742 #define VCN_UE_ERR_STATUS_HI_JPEG6D__ECC__SHIFT 0x0 5743 #define VCN_UE_ERR_STATUS_HI_JPEG6D__Parity__SHIFT 0x1 5744 #define VCN_UE_ERR_STATUS_HI_JPEG6D__Err_Info_Valid_Flag__SHIFT 0x2 5745 #define VCN_UE_ERR_STATUS_HI_JPEG6D__Err_Info__SHIFT 0x3 5746 #define VCN_UE_ERR_STATUS_HI_JPEG6D__UE_Cnt__SHIFT 0x17 5747 #define VCN_UE_ERR_STATUS_HI_JPEG6D__FED_Cnt__SHIFT 0x1a 5748 #define VCN_UE_ERR_STATUS_HI_JPEG6D__RESERVED__SHIFT 0x1d 5749 #define VCN_UE_ERR_STATUS_HI_JPEG6D__Err_clr__SHIFT 0x1f 5750 #define VCN_UE_ERR_STATUS_HI_JPEG6D__ECC_MASK 0x00000001L 5751 #define VCN_UE_ERR_STATUS_HI_JPEG6D__Parity_MASK 0x00000002L 5752 #define VCN_UE_ERR_STATUS_HI_JPEG6D__Err_Info_Valid_Flag_MASK 0x00000004L 5753 #define VCN_UE_ERR_STATUS_HI_JPEG6D__Err_Info_MASK 0x007FFFF8L 5754 #define VCN_UE_ERR_STATUS_HI_JPEG6D__UE_Cnt_MASK 0x03800000L 5755 #define VCN_UE_ERR_STATUS_HI_JPEG6D__FED_Cnt_MASK 0x1C000000L 5756 #define VCN_UE_ERR_STATUS_HI_JPEG6D__RESERVED_MASK 0x60000000L 5757 #define VCN_UE_ERR_STATUS_HI_JPEG6D__Err_clr_MASK 0x80000000L 5758 //VCN_UE_ERR_STATUS_LO_JPEG7S 5759 #define VCN_UE_ERR_STATUS_LO_JPEG7S__Err_Status_Valid_Flag__SHIFT 0x0 5760 #define VCN_UE_ERR_STATUS_LO_JPEG7S__Address_Valid_Flag__SHIFT 0x1 5761 #define VCN_UE_ERR_STATUS_LO_JPEG7S__Address__SHIFT 0x2 5762 #define VCN_UE_ERR_STATUS_LO_JPEG7S__Memory_id__SHIFT 0x18 5763 #define VCN_UE_ERR_STATUS_LO_JPEG7S__Err_Status_Valid_Flag_MASK 0x00000001L 5764 #define VCN_UE_ERR_STATUS_LO_JPEG7S__Address_Valid_Flag_MASK 0x00000002L 5765 #define VCN_UE_ERR_STATUS_LO_JPEG7S__Address_MASK 0x00FFFFFCL 5766 #define VCN_UE_ERR_STATUS_LO_JPEG7S__Memory_id_MASK 0xFF000000L 5767 //VCN_UE_ERR_STATUS_HI_JPEG7S 5768 #define VCN_UE_ERR_STATUS_HI_JPEG7S__ECC__SHIFT 0x0 5769 #define VCN_UE_ERR_STATUS_HI_JPEG7S__Parity__SHIFT 0x1 5770 #define VCN_UE_ERR_STATUS_HI_JPEG7S__Err_Info_Valid_Flag__SHIFT 0x2 5771 #define VCN_UE_ERR_STATUS_HI_JPEG7S__Err_Info__SHIFT 0x3 5772 #define VCN_UE_ERR_STATUS_HI_JPEG7S__UE_Cnt__SHIFT 0x17 5773 #define VCN_UE_ERR_STATUS_HI_JPEG7S__FED_Cnt__SHIFT 0x1a 5774 #define VCN_UE_ERR_STATUS_HI_JPEG7S__RESERVED__SHIFT 0x1d 5775 #define VCN_UE_ERR_STATUS_HI_JPEG7S__Err_clr__SHIFT 0x1f 5776 #define VCN_UE_ERR_STATUS_HI_JPEG7S__ECC_MASK 0x00000001L 5777 #define VCN_UE_ERR_STATUS_HI_JPEG7S__Parity_MASK 0x00000002L 5778 #define VCN_UE_ERR_STATUS_HI_JPEG7S__Err_Info_Valid_Flag_MASK 0x00000004L 5779 #define VCN_UE_ERR_STATUS_HI_JPEG7S__Err_Info_MASK 0x007FFFF8L 5780 #define VCN_UE_ERR_STATUS_HI_JPEG7S__UE_Cnt_MASK 0x03800000L 5781 #define VCN_UE_ERR_STATUS_HI_JPEG7S__FED_Cnt_MASK 0x1C000000L 5782 #define VCN_UE_ERR_STATUS_HI_JPEG7S__RESERVED_MASK 0x60000000L 5783 #define VCN_UE_ERR_STATUS_HI_JPEG7S__Err_clr_MASK 0x80000000L 5784 //VCN_UE_ERR_STATUS_LO_JPEG7D 5785 #define VCN_UE_ERR_STATUS_LO_JPEG7D__Err_Status_Valid_Flag__SHIFT 0x0 5786 #define VCN_UE_ERR_STATUS_LO_JPEG7D__Address_Valid_Flag__SHIFT 0x1 5787 #define VCN_UE_ERR_STATUS_LO_JPEG7D__Address__SHIFT 0x2 5788 #define VCN_UE_ERR_STATUS_LO_JPEG7D__Memory_id__SHIFT 0x18 5789 #define VCN_UE_ERR_STATUS_LO_JPEG7D__Err_Status_Valid_Flag_MASK 0x00000001L 5790 #define VCN_UE_ERR_STATUS_LO_JPEG7D__Address_Valid_Flag_MASK 0x00000002L 5791 #define VCN_UE_ERR_STATUS_LO_JPEG7D__Address_MASK 0x00FFFFFCL 5792 #define VCN_UE_ERR_STATUS_LO_JPEG7D__Memory_id_MASK 0xFF000000L 5793 //VCN_UE_ERR_STATUS_HI_JPEG7D 5794 #define VCN_UE_ERR_STATUS_HI_JPEG7D__ECC__SHIFT 0x0 5795 #define VCN_UE_ERR_STATUS_HI_JPEG7D__Parity__SHIFT 0x1 5796 #define VCN_UE_ERR_STATUS_HI_JPEG7D__Err_Info_Valid_Flag__SHIFT 0x2 5797 #define VCN_UE_ERR_STATUS_HI_JPEG7D__Err_Info__SHIFT 0x3 5798 #define VCN_UE_ERR_STATUS_HI_JPEG7D__UE_Cnt__SHIFT 0x17 5799 #define VCN_UE_ERR_STATUS_HI_JPEG7D__FED_Cnt__SHIFT 0x1a 5800 #define VCN_UE_ERR_STATUS_HI_JPEG7D__RESERVED__SHIFT 0x1d 5801 #define VCN_UE_ERR_STATUS_HI_JPEG7D__Err_clr__SHIFT 0x1f 5802 #define VCN_UE_ERR_STATUS_HI_JPEG7D__ECC_MASK 0x00000001L 5803 #define VCN_UE_ERR_STATUS_HI_JPEG7D__Parity_MASK 0x00000002L 5804 #define VCN_UE_ERR_STATUS_HI_JPEG7D__Err_Info_Valid_Flag_MASK 0x00000004L 5805 #define VCN_UE_ERR_STATUS_HI_JPEG7D__Err_Info_MASK 0x007FFFF8L 5806 #define VCN_UE_ERR_STATUS_HI_JPEG7D__UE_Cnt_MASK 0x03800000L 5807 #define VCN_UE_ERR_STATUS_HI_JPEG7D__FED_Cnt_MASK 0x1C000000L 5808 #define VCN_UE_ERR_STATUS_HI_JPEG7D__RESERVED_MASK 0x60000000L 5809 #define VCN_UE_ERR_STATUS_HI_JPEG7D__Err_clr_MASK 0x80000000L 5810 5811 // addressBlock: aid_uvd0_uvd_jrbc0_uvd_jrbc_dec 5812 //UVD_JRBC0_UVD_JRBC_RB_WPTR 5813 #define UVD_JRBC0_UVD_JRBC_RB_WPTR__RB_WPTR__SHIFT 0x4 5814 #define UVD_JRBC0_UVD_JRBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 5815 //UVD_JRBC0_UVD_JRBC_RB_CNTL 5816 #define UVD_JRBC0_UVD_JRBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x0 5817 #define UVD_JRBC0_UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1 5818 #define UVD_JRBC0_UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x4 5819 #define UVD_JRBC0_UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK 0x00000001L 5820 #define UVD_JRBC0_UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L 5821 #define UVD_JRBC0_UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK 0x0007FFF0L 5822 //UVD_JRBC0_UVD_JRBC_IB_SIZE 5823 #define UVD_JRBC0_UVD_JRBC_IB_SIZE__IB_SIZE__SHIFT 0x4 5824 #define UVD_JRBC0_UVD_JRBC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L 5825 //UVD_JRBC0_UVD_JRBC_URGENT_CNTL 5826 #define UVD_JRBC0_UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0 5827 #define UVD_JRBC0_UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L 5828 //UVD_JRBC0_UVD_JRBC_RB_REF_DATA 5829 #define UVD_JRBC0_UVD_JRBC_RB_REF_DATA__REF_DATA__SHIFT 0x0 5830 #define UVD_JRBC0_UVD_JRBC_RB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL 5831 //UVD_JRBC0_UVD_JRBC_RB_COND_RD_TIMER 5832 #define UVD_JRBC0_UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 5833 #define UVD_JRBC0_UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 5834 #define UVD_JRBC0_UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 5835 #define UVD_JRBC0_UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 5836 #define UVD_JRBC0_UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL 5837 #define UVD_JRBC0_UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L 5838 #define UVD_JRBC0_UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L 5839 #define UVD_JRBC0_UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L 5840 //UVD_JRBC0_UVD_JRBC_SOFT_RESET 5841 #define UVD_JRBC0_UVD_JRBC_SOFT_RESET__RESET__SHIFT 0x0 5842 #define UVD_JRBC0_UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS__SHIFT 0x11 5843 #define UVD_JRBC0_UVD_JRBC_SOFT_RESET__RESET_MASK 0x00000001L 5844 #define UVD_JRBC0_UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS_MASK 0x00020000L 5845 //UVD_JRBC0_UVD_JRBC_STATUS 5846 #define UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE__SHIFT 0x0 5847 #define UVD_JRBC0_UVD_JRBC_STATUS__IB_JOB_DONE__SHIFT 0x1 5848 #define UVD_JRBC0_UVD_JRBC_STATUS__RB_ILLEGAL_CMD__SHIFT 0x2 5849 #define UVD_JRBC0_UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT__SHIFT 0x3 5850 #define UVD_JRBC0_UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT__SHIFT 0x4 5851 #define UVD_JRBC0_UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT__SHIFT 0x5 5852 #define UVD_JRBC0_UVD_JRBC_STATUS__IB_ILLEGAL_CMD__SHIFT 0x6 5853 #define UVD_JRBC0_UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT__SHIFT 0x7 5854 #define UVD_JRBC0_UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT__SHIFT 0x8 5855 #define UVD_JRBC0_UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT__SHIFT 0x9 5856 #define UVD_JRBC0_UVD_JRBC_STATUS__RB_TRAP_STATUS__SHIFT 0xa 5857 #define UVD_JRBC0_UVD_JRBC_STATUS__PREEMPT_STATUS__SHIFT 0xb 5858 #define UVD_JRBC0_UVD_JRBC_STATUS__IB_TRAP_STATUS__SHIFT 0xc 5859 #define UVD_JRBC0_UVD_JRBC_STATUS__INT_EN__SHIFT 0x10 5860 #define UVD_JRBC0_UVD_JRBC_STATUS__INT_ACK__SHIFT 0x11 5861 #define UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK 0x00000001L 5862 #define UVD_JRBC0_UVD_JRBC_STATUS__IB_JOB_DONE_MASK 0x00000002L 5863 #define UVD_JRBC0_UVD_JRBC_STATUS__RB_ILLEGAL_CMD_MASK 0x00000004L 5864 #define UVD_JRBC0_UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT_MASK 0x00000008L 5865 #define UVD_JRBC0_UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT_MASK 0x00000010L 5866 #define UVD_JRBC0_UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT_MASK 0x00000020L 5867 #define UVD_JRBC0_UVD_JRBC_STATUS__IB_ILLEGAL_CMD_MASK 0x00000040L 5868 #define UVD_JRBC0_UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT_MASK 0x00000080L 5869 #define UVD_JRBC0_UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT_MASK 0x00000100L 5870 #define UVD_JRBC0_UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT_MASK 0x00000200L 5871 #define UVD_JRBC0_UVD_JRBC_STATUS__RB_TRAP_STATUS_MASK 0x00000400L 5872 #define UVD_JRBC0_UVD_JRBC_STATUS__PREEMPT_STATUS_MASK 0x00000800L 5873 #define UVD_JRBC0_UVD_JRBC_STATUS__IB_TRAP_STATUS_MASK 0x00001000L 5874 #define UVD_JRBC0_UVD_JRBC_STATUS__INT_EN_MASK 0x00010000L 5875 #define UVD_JRBC0_UVD_JRBC_STATUS__INT_ACK_MASK 0x00020000L 5876 //UVD_JRBC0_UVD_JRBC_RB_RPTR 5877 #define UVD_JRBC0_UVD_JRBC_RB_RPTR__RB_RPTR__SHIFT 0x4 5878 #define UVD_JRBC0_UVD_JRBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 5879 //UVD_JRBC0_UVD_JRBC_RB_BUF_STATUS 5880 #define UVD_JRBC0_UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0 5881 #define UVD_JRBC0_UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10 5882 #define UVD_JRBC0_UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x18 5883 #define UVD_JRBC0_UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID_MASK 0x0000FFFFL 5884 #define UVD_JRBC0_UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x000F0000L 5885 #define UVD_JRBC0_UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x03000000L 5886 //UVD_JRBC0_UVD_JRBC_IB_BUF_STATUS 5887 #define UVD_JRBC0_UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID__SHIFT 0x0 5888 #define UVD_JRBC0_UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x10 5889 #define UVD_JRBC0_UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x18 5890 #define UVD_JRBC0_UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FFFFL 5891 #define UVD_JRBC0_UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x000F0000L 5892 #define UVD_JRBC0_UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x03000000L 5893 //UVD_JRBC0_UVD_JRBC_IB_SIZE_UPDATE 5894 #define UVD_JRBC0_UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4 5895 #define UVD_JRBC0_UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L 5896 //UVD_JRBC0_UVD_JRBC_IB_COND_RD_TIMER 5897 #define UVD_JRBC0_UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 5898 #define UVD_JRBC0_UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 5899 #define UVD_JRBC0_UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 5900 #define UVD_JRBC0_UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 5901 #define UVD_JRBC0_UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL 5902 #define UVD_JRBC0_UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L 5903 #define UVD_JRBC0_UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L 5904 #define UVD_JRBC0_UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L 5905 //UVD_JRBC0_UVD_JRBC_IB_REF_DATA 5906 #define UVD_JRBC0_UVD_JRBC_IB_REF_DATA__REF_DATA__SHIFT 0x0 5907 #define UVD_JRBC0_UVD_JRBC_IB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL 5908 //UVD_JRBC0_UVD_JPEG_PREEMPT_CMD 5909 #define UVD_JRBC0_UVD_JPEG_PREEMPT_CMD__PREEMPT_EN__SHIFT 0x0 5910 #define UVD_JRBC0_UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE__SHIFT 0x1 5911 #define UVD_JRBC0_UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD__SHIFT 0x2 5912 #define UVD_JRBC0_UVD_JPEG_PREEMPT_CMD__PREEMPT_EN_MASK 0x00000001L 5913 #define UVD_JRBC0_UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE_MASK 0x00000002L 5914 #define UVD_JRBC0_UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD_MASK 0x00000004L 5915 //UVD_JRBC0_UVD_JPEG_PREEMPT_FENCE_DATA0 5916 #define UVD_JRBC0_UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0__SHIFT 0x0 5917 #define UVD_JRBC0_UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0_MASK 0xFFFFFFFFL 5918 //UVD_JRBC0_UVD_JPEG_PREEMPT_FENCE_DATA1 5919 #define UVD_JRBC0_UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1__SHIFT 0x0 5920 #define UVD_JRBC0_UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1_MASK 0xFFFFFFFFL 5921 //UVD_JRBC0_UVD_JRBC_RB_SIZE 5922 #define UVD_JRBC0_UVD_JRBC_RB_SIZE__RB_SIZE__SHIFT 0x4 5923 #define UVD_JRBC0_UVD_JRBC_RB_SIZE__RB_SIZE_MASK 0x00FFFFF0L 5924 //UVD_JRBC0_UVD_JRBC_SCRATCH0 5925 #define UVD_JRBC0_UVD_JRBC_SCRATCH0__SCRATCH0__SHIFT 0x0 5926 #define UVD_JRBC0_UVD_JRBC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL 5927 5928 5929 // addressBlock: aid_uvd0_uvd_jmi0_uvd_jmi_dec 5930 //UVD_JMI0_UVD_JPEG_DEC_PF_CTRL 5931 #define UVD_JMI0_UVD_JPEG_DEC_PF_CTRL__DEC_PF_HANDLING_DIS__SHIFT 0x0 5932 #define UVD_JMI0_UVD_JPEG_DEC_PF_CTRL__DEC_PF_SW_GATING__SHIFT 0x1 5933 #define UVD_JMI0_UVD_JPEG_DEC_PF_CTRL__DEC_PF_HANDLING_DIS_MASK 0x00000001L 5934 #define UVD_JMI0_UVD_JPEG_DEC_PF_CTRL__DEC_PF_SW_GATING_MASK 0x00000002L 5935 //UVD_JMI0_UVD_LMI_JRBC_CTRL 5936 #define UVD_JMI0_UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 5937 #define UVD_JMI0_UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 5938 #define UVD_JMI0_UVD_LMI_JRBC_CTRL__RD_MAX_BURST__SHIFT 0x4 5939 #define UVD_JMI0_UVD_LMI_JRBC_CTRL__WR_MAX_BURST__SHIFT 0x8 5940 #define UVD_JMI0_UVD_LMI_JRBC_CTRL__RD_SWAP__SHIFT 0x14 5941 #define UVD_JMI0_UVD_LMI_JRBC_CTRL__WR_SWAP__SHIFT 0x16 5942 #define UVD_JMI0_UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 5943 #define UVD_JMI0_UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 5944 #define UVD_JMI0_UVD_LMI_JRBC_CTRL__RD_MAX_BURST_MASK 0x000000F0L 5945 #define UVD_JMI0_UVD_LMI_JRBC_CTRL__WR_MAX_BURST_MASK 0x00000F00L 5946 #define UVD_JMI0_UVD_LMI_JRBC_CTRL__RD_SWAP_MASK 0x00300000L 5947 #define UVD_JMI0_UVD_LMI_JRBC_CTRL__WR_SWAP_MASK 0x00C00000L 5948 //UVD_JMI0_UVD_LMI_JPEG_CTRL 5949 #define UVD_JMI0_UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 5950 #define UVD_JMI0_UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 5951 #define UVD_JMI0_UVD_LMI_JPEG_CTRL__RD_MAX_BURST__SHIFT 0x4 5952 #define UVD_JMI0_UVD_LMI_JPEG_CTRL__WR_MAX_BURST__SHIFT 0x8 5953 #define UVD_JMI0_UVD_LMI_JPEG_CTRL__RD_SWAP__SHIFT 0x14 5954 #define UVD_JMI0_UVD_LMI_JPEG_CTRL__WR_SWAP__SHIFT 0x16 5955 #define UVD_JMI0_UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 5956 #define UVD_JMI0_UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 5957 #define UVD_JMI0_UVD_LMI_JPEG_CTRL__RD_MAX_BURST_MASK 0x000000F0L 5958 #define UVD_JMI0_UVD_LMI_JPEG_CTRL__WR_MAX_BURST_MASK 0x00000F00L 5959 #define UVD_JMI0_UVD_LMI_JPEG_CTRL__RD_SWAP_MASK 0x00300000L 5960 #define UVD_JMI0_UVD_LMI_JPEG_CTRL__WR_SWAP_MASK 0x00C00000L 5961 //UVD_JMI0_JPEG_LMI_DROP 5962 #define UVD_JMI0_JPEG_LMI_DROP__JPEG_WR_DROP__SHIFT 0x0 5963 #define UVD_JMI0_JPEG_LMI_DROP__JRBC_WR_DROP__SHIFT 0x1 5964 #define UVD_JMI0_JPEG_LMI_DROP__JPEG_RD_DROP__SHIFT 0x2 5965 #define UVD_JMI0_JPEG_LMI_DROP__JRBC_RD_DROP__SHIFT 0x3 5966 #define UVD_JMI0_JPEG_LMI_DROP__JPEG_ATOMIC_WR_DROP__SHIFT 0x4 5967 #define UVD_JMI0_JPEG_LMI_DROP__JPEG_WR_DROP_MASK 0x00000001L 5968 #define UVD_JMI0_JPEG_LMI_DROP__JRBC_WR_DROP_MASK 0x00000002L 5969 #define UVD_JMI0_JPEG_LMI_DROP__JPEG_RD_DROP_MASK 0x00000004L 5970 #define UVD_JMI0_JPEG_LMI_DROP__JRBC_RD_DROP_MASK 0x00000008L 5971 #define UVD_JMI0_JPEG_LMI_DROP__JPEG_ATOMIC_WR_DROP_MASK 0x00000010L 5972 //UVD_JMI0_UVD_LMI_JRBC_IB_VMID 5973 #define UVD_JMI0_UVD_LMI_JRBC_IB_VMID__IB_WR_VMID__SHIFT 0x0 5974 #define UVD_JMI0_UVD_LMI_JRBC_IB_VMID__IB_RD_VMID__SHIFT 0x4 5975 #define UVD_JMI0_UVD_LMI_JRBC_IB_VMID__MEM_RD_VMID__SHIFT 0x8 5976 #define UVD_JMI0_UVD_LMI_JRBC_IB_VMID__IB_WR_VMID_MASK 0x0000000FL 5977 #define UVD_JMI0_UVD_LMI_JRBC_IB_VMID__IB_RD_VMID_MASK 0x000000F0L 5978 #define UVD_JMI0_UVD_LMI_JRBC_IB_VMID__MEM_RD_VMID_MASK 0x00000F00L 5979 //UVD_JMI0_UVD_LMI_JRBC_RB_VMID 5980 #define UVD_JMI0_UVD_LMI_JRBC_RB_VMID__RB_WR_VMID__SHIFT 0x0 5981 #define UVD_JMI0_UVD_LMI_JRBC_RB_VMID__RB_RD_VMID__SHIFT 0x4 5982 #define UVD_JMI0_UVD_LMI_JRBC_RB_VMID__MEM_RD_VMID__SHIFT 0x8 5983 #define UVD_JMI0_UVD_LMI_JRBC_RB_VMID__RB_WR_VMID_MASK 0x0000000FL 5984 #define UVD_JMI0_UVD_LMI_JRBC_RB_VMID__RB_RD_VMID_MASK 0x000000F0L 5985 #define UVD_JMI0_UVD_LMI_JRBC_RB_VMID__MEM_RD_VMID_MASK 0x00000F00L 5986 //UVD_JMI0_UVD_LMI_JPEG_VMID 5987 #define UVD_JMI0_UVD_LMI_JPEG_VMID__JPEG_RD_VMID__SHIFT 0x0 5988 #define UVD_JMI0_UVD_LMI_JPEG_VMID__JPEG_WR_VMID__SHIFT 0x4 5989 #define UVD_JMI0_UVD_LMI_JPEG_VMID__ATOMIC_USER0_WR_VMID__SHIFT 0x8 5990 #define UVD_JMI0_UVD_LMI_JPEG_VMID__JPEG_RD_VMID_MASK 0x0000000FL 5991 #define UVD_JMI0_UVD_LMI_JPEG_VMID__JPEG_WR_VMID_MASK 0x000000F0L 5992 #define UVD_JMI0_UVD_LMI_JPEG_VMID__ATOMIC_USER0_WR_VMID_MASK 0x00000F00L 5993 //UVD_JMI0_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW 5994 #define UVD_JMI0_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 5995 #define UVD_JMI0_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 5996 //UVD_JMI0_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 5997 #define UVD_JMI0_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 5998 #define UVD_JMI0_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 5999 //UVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_LOW 6000 #define UVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 6001 #define UVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 6002 //UVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH 6003 #define UVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 6004 #define UVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 6005 //UVD_JMI0_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW 6006 #define UVD_JMI0_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 6007 #define UVD_JMI0_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 6008 //UVD_JMI0_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH 6009 #define UVD_JMI0_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 6010 #define UVD_JMI0_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 6011 //UVD_JMI0_UVD_LMI_JPEG_PREEMPT_VMID 6012 #define UVD_JMI0_UVD_LMI_JPEG_PREEMPT_VMID__VMID__SHIFT 0x0 6013 #define UVD_JMI0_UVD_LMI_JPEG_PREEMPT_VMID__VMID_MASK 0x0000000FL 6014 //UVD_JMI0_UVD_JMI_DEC_SWAP_CNTL 6015 #define UVD_JMI0_UVD_JMI_DEC_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 6016 #define UVD_JMI0_UVD_JMI_DEC_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 6017 #define UVD_JMI0_UVD_JMI_DEC_SWAP_CNTL__RB_MEM_WR_MC_SWAP__SHIFT 0x4 6018 #define UVD_JMI0_UVD_JMI_DEC_SWAP_CNTL__IB_MEM_WR_MC_SWAP__SHIFT 0x6 6019 #define UVD_JMI0_UVD_JMI_DEC_SWAP_CNTL__RB_MEM_RD_MC_SWAP__SHIFT 0x8 6020 #define UVD_JMI0_UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT 0xa 6021 #define UVD_JMI0_UVD_JMI_DEC_SWAP_CNTL__PREEMPT_WR_MC_SWAP__SHIFT 0xc 6022 #define UVD_JMI0_UVD_JMI_DEC_SWAP_CNTL__JPEG_RD_MC_SWAP__SHIFT 0xe 6023 #define UVD_JMI0_UVD_JMI_DEC_SWAP_CNTL__JPEG_WR_MC_SWAP__SHIFT 0x10 6024 #define UVD_JMI0_UVD_JMI_DEC_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L 6025 #define UVD_JMI0_UVD_JMI_DEC_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL 6026 #define UVD_JMI0_UVD_JMI_DEC_SWAP_CNTL__RB_MEM_WR_MC_SWAP_MASK 0x00000030L 6027 #define UVD_JMI0_UVD_JMI_DEC_SWAP_CNTL__IB_MEM_WR_MC_SWAP_MASK 0x000000C0L 6028 #define UVD_JMI0_UVD_JMI_DEC_SWAP_CNTL__RB_MEM_RD_MC_SWAP_MASK 0x00000300L 6029 #define UVD_JMI0_UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP_MASK 0x00000C00L 6030 #define UVD_JMI0_UVD_JMI_DEC_SWAP_CNTL__PREEMPT_WR_MC_SWAP_MASK 0x00003000L 6031 #define UVD_JMI0_UVD_JMI_DEC_SWAP_CNTL__JPEG_RD_MC_SWAP_MASK 0x0000C000L 6032 #define UVD_JMI0_UVD_JMI_DEC_SWAP_CNTL__JPEG_WR_MC_SWAP_MASK 0x00030000L 6033 //UVD_JMI0_UVD_JMI_ATOMIC_CNTL 6034 #define UVD_JMI0_UVD_JMI_ATOMIC_CNTL__atomic_arb_wait_en__SHIFT 0x0 6035 #define UVD_JMI0_UVD_JMI_ATOMIC_CNTL__atomic_max_burst__SHIFT 0x1 6036 #define UVD_JMI0_UVD_JMI_ATOMIC_CNTL__atomic_wr_drop__SHIFT 0x5 6037 #define UVD_JMI0_UVD_JMI_ATOMIC_CNTL__atomic_wr_clamping_en__SHIFT 0x6 6038 #define UVD_JMI0_UVD_JMI_ATOMIC_CNTL__ATOMIC_WR_URG__SHIFT 0x7 6039 #define UVD_JMI0_UVD_JMI_ATOMIC_CNTL__ATOMIC_SW_GATE__SHIFT 0xb 6040 #define UVD_JMI0_UVD_JMI_ATOMIC_CNTL__atomic_arb_wait_en_MASK 0x00000001L 6041 #define UVD_JMI0_UVD_JMI_ATOMIC_CNTL__atomic_max_burst_MASK 0x0000001EL 6042 #define UVD_JMI0_UVD_JMI_ATOMIC_CNTL__atomic_wr_drop_MASK 0x00000020L 6043 #define UVD_JMI0_UVD_JMI_ATOMIC_CNTL__atomic_wr_clamping_en_MASK 0x00000040L 6044 #define UVD_JMI0_UVD_JMI_ATOMIC_CNTL__ATOMIC_WR_URG_MASK 0x00000780L 6045 #define UVD_JMI0_UVD_JMI_ATOMIC_CNTL__ATOMIC_SW_GATE_MASK 0x00000800L 6046 //UVD_JMI0_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW 6047 #define UVD_JMI0_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 6048 #define UVD_JMI0_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 6049 //UVD_JMI0_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH 6050 #define UVD_JMI0_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 6051 #define UVD_JMI0_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 6052 //UVD_JMI0_UVD_LMI_JPEG_READ_64BIT_BAR_LOW 6053 #define UVD_JMI0_UVD_LMI_JPEG_READ_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 6054 #define UVD_JMI0_UVD_LMI_JPEG_READ_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 6055 //UVD_JMI0_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH 6056 #define UVD_JMI0_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 6057 #define UVD_JMI0_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 6058 //UVD_JMI0_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 6059 #define UVD_JMI0_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 6060 #define UVD_JMI0_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 6061 //UVD_JMI0_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 6062 #define UVD_JMI0_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 6063 #define UVD_JMI0_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 6064 //UVD_JMI0_UVD_LMI_JRBC_IB_64BIT_BAR_LOW 6065 #define UVD_JMI0_UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 6066 #define UVD_JMI0_UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 6067 //UVD_JMI0_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH 6068 #define UVD_JMI0_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 6069 #define UVD_JMI0_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 6070 //UVD_JMI0_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW 6071 #define UVD_JMI0_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 6072 #define UVD_JMI0_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 6073 //UVD_JMI0_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH 6074 #define UVD_JMI0_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 6075 #define UVD_JMI0_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 6076 //UVD_JMI0_UVD_JMI_ATOMIC_CNTL2 6077 #define UVD_JMI0_UVD_JMI_ATOMIC_CNTL2__atomic_uvd_swap__SHIFT 0x10 6078 #define UVD_JMI0_UVD_JMI_ATOMIC_CNTL2__ATOMIC_MC_SWAP__SHIFT 0x18 6079 #define UVD_JMI0_UVD_JMI_ATOMIC_CNTL2__atomic_uvd_swap_MASK 0x00FF0000L 6080 #define UVD_JMI0_UVD_JMI_ATOMIC_CNTL2__ATOMIC_MC_SWAP_MASK 0xFF000000L 6081 6082 6083 // addressBlock: aid_uvd0_uvd_jmi_common_dec 6084 //UVD_JADP_MCIF_URGENT_CTRL 6085 #define UVD_JADP_MCIF_URGENT_CTRL__WR_WATERMARK__SHIFT 0x0 6086 #define UVD_JADP_MCIF_URGENT_CTRL__RD_WATERMARK__SHIFT 0x6 6087 #define UVD_JADP_MCIF_URGENT_CTRL__WR_RD_URGENT_TIMER__SHIFT 0xb 6088 #define UVD_JADP_MCIF_URGENT_CTRL__WR_URGENT_PROG_STEP__SHIFT 0x11 6089 #define UVD_JADP_MCIF_URGENT_CTRL__RD_URGENT_PROG_STEP__SHIFT 0x15 6090 #define UVD_JADP_MCIF_URGENT_CTRL__WR_QOS_EN__SHIFT 0x19 6091 #define UVD_JADP_MCIF_URGENT_CTRL__RD_QOS_EN__SHIFT 0x1a 6092 #define UVD_JADP_MCIF_URGENT_CTRL__WR_WATERMARK_MASK 0x0000003FL 6093 #define UVD_JADP_MCIF_URGENT_CTRL__RD_WATERMARK_MASK 0x000007C0L 6094 #define UVD_JADP_MCIF_URGENT_CTRL__WR_RD_URGENT_TIMER_MASK 0x0001F800L 6095 #define UVD_JADP_MCIF_URGENT_CTRL__WR_URGENT_PROG_STEP_MASK 0x001E0000L 6096 #define UVD_JADP_MCIF_URGENT_CTRL__RD_URGENT_PROG_STEP_MASK 0x01E00000L 6097 #define UVD_JADP_MCIF_URGENT_CTRL__WR_QOS_EN_MASK 0x02000000L 6098 #define UVD_JADP_MCIF_URGENT_CTRL__RD_QOS_EN_MASK 0x04000000L 6099 //UVD_JMI_URGENT_CTRL 6100 #define UVD_JMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL__SHIFT 0x0 6101 #define UVD_JMI_URGENT_CTRL__ASSERT_MC_RD_URGENT__SHIFT 0x4 6102 #define UVD_JMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL__SHIFT 0x10 6103 #define UVD_JMI_URGENT_CTRL__ASSERT_MC_WR_URGENT__SHIFT 0x14 6104 #define UVD_JMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL_MASK 0x00000001L 6105 #define UVD_JMI_URGENT_CTRL__ASSERT_MC_RD_URGENT_MASK 0x000000F0L 6106 #define UVD_JMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL_MASK 0x00010000L 6107 #define UVD_JMI_URGENT_CTRL__ASSERT_MC_WR_URGENT_MASK 0x00F00000L 6108 //UVD_JMI_CTRL 6109 #define UVD_JMI_CTRL__STALL_MC_ARB__SHIFT 0x0 6110 #define UVD_JMI_CTRL__MASK_MC_URGENT__SHIFT 0x1 6111 #define UVD_JMI_CTRL__ASSERT_MC_URGENT__SHIFT 0x2 6112 #define UVD_JMI_CTRL__MC_RD_ARB_WAIT_TIMER__SHIFT 0x8 6113 #define UVD_JMI_CTRL__MC_WR_ARB_WAIT_TIMER__SHIFT 0x10 6114 #define UVD_JMI_CTRL__STALL_MC_ARB_MASK 0x00000001L 6115 #define UVD_JMI_CTRL__MASK_MC_URGENT_MASK 0x00000002L 6116 #define UVD_JMI_CTRL__ASSERT_MC_URGENT_MASK 0x00000004L 6117 #define UVD_JMI_CTRL__MC_RD_ARB_WAIT_TIMER_MASK 0x0000FF00L 6118 #define UVD_JMI_CTRL__MC_WR_ARB_WAIT_TIMER_MASK 0x00FF0000L 6119 //JPEG_MEMCHECK_CLAMPING_CNTL 6120 #define JPEG_MEMCHECK_CLAMPING_CNTL__CLAMP_TO_SAFE_ADDR_EN__SHIFT 0x0 6121 #define JPEG_MEMCHECK_CLAMPING_CNTL__CLAMP_TO_SAFE_ADDR_EN_MASK 0x00000001L 6122 //JPEG_MEMCHECK_SAFE_ADDR 6123 #define JPEG_MEMCHECK_SAFE_ADDR__MEMCHECK_SAFE_ADDR__SHIFT 0x0 6124 #define JPEG_MEMCHECK_SAFE_ADDR__MEMCHECK_SAFE_ADDR_MASK 0xFFFFFFFFL 6125 //JPEG_MEMCHECK_SAFE_ADDR_64BIT 6126 #define JPEG_MEMCHECK_SAFE_ADDR_64BIT__MEMCHECK_SAFE_ADDR_64BIT__SHIFT 0x0 6127 #define JPEG_MEMCHECK_SAFE_ADDR_64BIT__MEMCHECK_SAFE_ADDR_64BIT_MASK 0xFFFFFFFFL 6128 //UVD_JMI_LAT_CTRL 6129 #define UVD_JMI_LAT_CTRL__SCALE__SHIFT 0x0 6130 #define UVD_JMI_LAT_CTRL__MAX_START__SHIFT 0x8 6131 #define UVD_JMI_LAT_CTRL__MIN_START__SHIFT 0x9 6132 #define UVD_JMI_LAT_CTRL__AVG_START__SHIFT 0xa 6133 #define UVD_JMI_LAT_CTRL__PERFMON_SYNC__SHIFT 0xb 6134 #define UVD_JMI_LAT_CTRL__SKIP__SHIFT 0x10 6135 #define UVD_JMI_LAT_CTRL__SCALE_MASK 0x000000FFL 6136 #define UVD_JMI_LAT_CTRL__MAX_START_MASK 0x00000100L 6137 #define UVD_JMI_LAT_CTRL__MIN_START_MASK 0x00000200L 6138 #define UVD_JMI_LAT_CTRL__AVG_START_MASK 0x00000400L 6139 #define UVD_JMI_LAT_CTRL__PERFMON_SYNC_MASK 0x00000800L 6140 #define UVD_JMI_LAT_CTRL__SKIP_MASK 0x000F0000L 6141 //UVD_JMI_LAT_CNTR 6142 #define UVD_JMI_LAT_CNTR__MAX_LAT__SHIFT 0x0 6143 #define UVD_JMI_LAT_CNTR__MIN_LAT__SHIFT 0x8 6144 #define UVD_JMI_LAT_CNTR__MAX_LAT_MASK 0x000000FFL 6145 #define UVD_JMI_LAT_CNTR__MIN_LAT_MASK 0x0000FF00L 6146 //UVD_JMI_AVG_LAT_CNTR 6147 #define UVD_JMI_AVG_LAT_CNTR__ENV_LOW__SHIFT 0x0 6148 #define UVD_JMI_AVG_LAT_CNTR__ENV_HIGH__SHIFT 0x8 6149 #define UVD_JMI_AVG_LAT_CNTR__ENV_HIT__SHIFT 0x10 6150 #define UVD_JMI_AVG_LAT_CNTR__ENV_LOW_MASK 0x000000FFL 6151 #define UVD_JMI_AVG_LAT_CNTR__ENV_HIGH_MASK 0x0000FF00L 6152 #define UVD_JMI_AVG_LAT_CNTR__ENV_HIT_MASK 0xFFFF0000L 6153 //UVD_JMI_PERFMON_CTRL 6154 #define UVD_JMI_PERFMON_CTRL__PERFMON_STATE__SHIFT 0x0 6155 #define UVD_JMI_PERFMON_CTRL__PERFMON_SEL__SHIFT 0x8 6156 #define UVD_JMI_PERFMON_CTRL__PERFMON_STATE_MASK 0x00000003L 6157 #define UVD_JMI_PERFMON_CTRL__PERFMON_SEL_MASK 0x00001F00L 6158 //UVD_JMI_PERFMON_COUNT_LO 6159 #define UVD_JMI_PERFMON_COUNT_LO__PERFMON_COUNT__SHIFT 0x0 6160 #define UVD_JMI_PERFMON_COUNT_LO__PERFMON_COUNT_MASK 0xFFFFFFFFL 6161 //UVD_JMI_PERFMON_COUNT_HI 6162 #define UVD_JMI_PERFMON_COUNT_HI__PERFMON_COUNT__SHIFT 0x0 6163 #define UVD_JMI_PERFMON_COUNT_HI__PERFMON_COUNT_MASK 0x0000FFFFL 6164 //UVD_JMI_CLEAN_STATUS 6165 #define UVD_JMI_CLEAN_STATUS__LMI_READ_CLEAN__SHIFT 0x0 6166 #define UVD_JMI_CLEAN_STATUS__LMI_READ_CLEAN_RAW__SHIFT 0x1 6167 #define UVD_JMI_CLEAN_STATUS__LMI_WRITE_CLEAN__SHIFT 0x2 6168 #define UVD_JMI_CLEAN_STATUS__LMI_WRITE_CLEAN_RAW__SHIFT 0x3 6169 #define UVD_JMI_CLEAN_STATUS__MC_WRITE_PENDING__SHIFT 0x4 6170 #define UVD_JMI_CLEAN_STATUS__DJPEG_CORE0_READ_CLEAN__SHIFT 0x8 6171 #define UVD_JMI_CLEAN_STATUS__DJPEG_CORE1_READ_CLEAN__SHIFT 0x9 6172 #define UVD_JMI_CLEAN_STATUS__DJPEG_CORE2_READ_CLEAN__SHIFT 0xa 6173 #define UVD_JMI_CLEAN_STATUS__DJPEG_CORE3_READ_CLEAN__SHIFT 0xb 6174 #define UVD_JMI_CLEAN_STATUS__DJPEG_CORE4_READ_CLEAN__SHIFT 0xc 6175 #define UVD_JMI_CLEAN_STATUS__DJPEG_CORE5_READ_CLEAN__SHIFT 0xd 6176 #define UVD_JMI_CLEAN_STATUS__DJPEG_CORE6_READ_CLEAN__SHIFT 0xe 6177 #define UVD_JMI_CLEAN_STATUS__DJPEG_CORE7_READ_CLEAN__SHIFT 0xf 6178 #define UVD_JMI_CLEAN_STATUS__DJPEG_CORE0_WRITE_CLEAN__SHIFT 0x10 6179 #define UVD_JMI_CLEAN_STATUS__DJPEG_CORE1_WRITE_CLEAN__SHIFT 0x11 6180 #define UVD_JMI_CLEAN_STATUS__DJPEG_CORE2_WRITE_CLEAN__SHIFT 0x12 6181 #define UVD_JMI_CLEAN_STATUS__DJPEG_CORE3_WRITE_CLEAN__SHIFT 0x13 6182 #define UVD_JMI_CLEAN_STATUS__DJPEG_CORE4_WRITE_CLEAN__SHIFT 0x14 6183 #define UVD_JMI_CLEAN_STATUS__DJPEG_CORE5_WRITE_CLEAN__SHIFT 0x15 6184 #define UVD_JMI_CLEAN_STATUS__DJPEG_CORE6_WRITE_CLEAN__SHIFT 0x16 6185 #define UVD_JMI_CLEAN_STATUS__DJPEG_CORE7_WRITE_CLEAN__SHIFT 0x17 6186 #define UVD_JMI_CLEAN_STATUS__LMI_READ_CLEAN_MASK 0x00000001L 6187 #define UVD_JMI_CLEAN_STATUS__LMI_READ_CLEAN_RAW_MASK 0x00000002L 6188 #define UVD_JMI_CLEAN_STATUS__LMI_WRITE_CLEAN_MASK 0x00000004L 6189 #define UVD_JMI_CLEAN_STATUS__LMI_WRITE_CLEAN_RAW_MASK 0x00000008L 6190 #define UVD_JMI_CLEAN_STATUS__MC_WRITE_PENDING_MASK 0x00000010L 6191 #define UVD_JMI_CLEAN_STATUS__DJPEG_CORE0_READ_CLEAN_MASK 0x00000100L 6192 #define UVD_JMI_CLEAN_STATUS__DJPEG_CORE1_READ_CLEAN_MASK 0x00000200L 6193 #define UVD_JMI_CLEAN_STATUS__DJPEG_CORE2_READ_CLEAN_MASK 0x00000400L 6194 #define UVD_JMI_CLEAN_STATUS__DJPEG_CORE3_READ_CLEAN_MASK 0x00000800L 6195 #define UVD_JMI_CLEAN_STATUS__DJPEG_CORE4_READ_CLEAN_MASK 0x00001000L 6196 #define UVD_JMI_CLEAN_STATUS__DJPEG_CORE5_READ_CLEAN_MASK 0x00002000L 6197 #define UVD_JMI_CLEAN_STATUS__DJPEG_CORE6_READ_CLEAN_MASK 0x00004000L 6198 #define UVD_JMI_CLEAN_STATUS__DJPEG_CORE7_READ_CLEAN_MASK 0x00008000L 6199 #define UVD_JMI_CLEAN_STATUS__DJPEG_CORE0_WRITE_CLEAN_MASK 0x00010000L 6200 #define UVD_JMI_CLEAN_STATUS__DJPEG_CORE1_WRITE_CLEAN_MASK 0x00020000L 6201 #define UVD_JMI_CLEAN_STATUS__DJPEG_CORE2_WRITE_CLEAN_MASK 0x00040000L 6202 #define UVD_JMI_CLEAN_STATUS__DJPEG_CORE3_WRITE_CLEAN_MASK 0x00080000L 6203 #define UVD_JMI_CLEAN_STATUS__DJPEG_CORE4_WRITE_CLEAN_MASK 0x00100000L 6204 #define UVD_JMI_CLEAN_STATUS__DJPEG_CORE5_WRITE_CLEAN_MASK 0x00200000L 6205 #define UVD_JMI_CLEAN_STATUS__DJPEG_CORE6_WRITE_CLEAN_MASK 0x00400000L 6206 #define UVD_JMI_CLEAN_STATUS__DJPEG_CORE7_WRITE_CLEAN_MASK 0x00800000L 6207 //UVD_JMI_CNTL 6208 #define UVD_JMI_CNTL__SOFT_RESET__SHIFT 0x0 6209 #define UVD_JMI_CNTL__MC_RD_REQ_RET_MAX__SHIFT 0x8 6210 #define UVD_JMI_CNTL__SOFT_RESET_MASK 0x00000001L 6211 #define UVD_JMI_CNTL__MC_RD_REQ_RET_MAX_MASK 0x0003FF00L 6212 6213 6214 // addressBlock: aid_uvd0_uvd_jpeg_common_dec 6215 //JPEG_SOFT_RESET_STATUS 6216 #define JPEG_SOFT_RESET_STATUS__JPEG0_DEC_RESET_STATUS__SHIFT 0x0 6217 #define JPEG_SOFT_RESET_STATUS__JPEG1_DEC_RESET_STATUS__SHIFT 0x1 6218 #define JPEG_SOFT_RESET_STATUS__JPEG2_DEC_RESET_STATUS__SHIFT 0x2 6219 #define JPEG_SOFT_RESET_STATUS__JPEG3_DEC_RESET_STATUS__SHIFT 0x3 6220 #define JPEG_SOFT_RESET_STATUS__JPEG4_DEC_RESET_STATUS__SHIFT 0x4 6221 #define JPEG_SOFT_RESET_STATUS__JPEG5_DEC_RESET_STATUS__SHIFT 0x5 6222 #define JPEG_SOFT_RESET_STATUS__JPEG6_DEC_RESET_STATUS__SHIFT 0x6 6223 #define JPEG_SOFT_RESET_STATUS__JPEG7_DEC_RESET_STATUS__SHIFT 0x7 6224 #define JPEG_SOFT_RESET_STATUS__DJRBC0_RESET_STATUS__SHIFT 0x8 6225 #define JPEG_SOFT_RESET_STATUS__DJRBC1_RESET_STATUS__SHIFT 0x9 6226 #define JPEG_SOFT_RESET_STATUS__DJRBC2_RESET_STATUS__SHIFT 0xa 6227 #define JPEG_SOFT_RESET_STATUS__DJRBC3_RESET_STATUS__SHIFT 0xb 6228 #define JPEG_SOFT_RESET_STATUS__DJRBC4_RESET_STATUS__SHIFT 0xc 6229 #define JPEG_SOFT_RESET_STATUS__DJRBC5_RESET_STATUS__SHIFT 0xd 6230 #define JPEG_SOFT_RESET_STATUS__DJRBC6_RESET_STATUS__SHIFT 0xe 6231 #define JPEG_SOFT_RESET_STATUS__DJRBC7_RESET_STATUS__SHIFT 0xf 6232 #define JPEG_SOFT_RESET_STATUS__JPEG_ENC_RESET_STATUS__SHIFT 0x11 6233 #define JPEG_SOFT_RESET_STATUS__EJRBC_RESET_STATUS__SHIFT 0x12 6234 #define JPEG_SOFT_RESET_STATUS__JMCIF_RESET_STATUS__SHIFT 0x18 6235 #define JPEG_SOFT_RESET_STATUS__JPEG0_DEC_RESET_STATUS_MASK 0x00000001L 6236 #define JPEG_SOFT_RESET_STATUS__JPEG1_DEC_RESET_STATUS_MASK 0x00000002L 6237 #define JPEG_SOFT_RESET_STATUS__JPEG2_DEC_RESET_STATUS_MASK 0x00000004L 6238 #define JPEG_SOFT_RESET_STATUS__JPEG3_DEC_RESET_STATUS_MASK 0x00000008L 6239 #define JPEG_SOFT_RESET_STATUS__JPEG4_DEC_RESET_STATUS_MASK 0x00000010L 6240 #define JPEG_SOFT_RESET_STATUS__JPEG5_DEC_RESET_STATUS_MASK 0x00000020L 6241 #define JPEG_SOFT_RESET_STATUS__JPEG6_DEC_RESET_STATUS_MASK 0x00000040L 6242 #define JPEG_SOFT_RESET_STATUS__JPEG7_DEC_RESET_STATUS_MASK 0x00000080L 6243 #define JPEG_SOFT_RESET_STATUS__DJRBC0_RESET_STATUS_MASK 0x00000100L 6244 #define JPEG_SOFT_RESET_STATUS__DJRBC1_RESET_STATUS_MASK 0x00000200L 6245 #define JPEG_SOFT_RESET_STATUS__DJRBC2_RESET_STATUS_MASK 0x00000400L 6246 #define JPEG_SOFT_RESET_STATUS__DJRBC3_RESET_STATUS_MASK 0x00000800L 6247 #define JPEG_SOFT_RESET_STATUS__DJRBC4_RESET_STATUS_MASK 0x00001000L 6248 #define JPEG_SOFT_RESET_STATUS__DJRBC5_RESET_STATUS_MASK 0x00002000L 6249 #define JPEG_SOFT_RESET_STATUS__DJRBC6_RESET_STATUS_MASK 0x00004000L 6250 #define JPEG_SOFT_RESET_STATUS__DJRBC7_RESET_STATUS_MASK 0x00008000L 6251 #define JPEG_SOFT_RESET_STATUS__JPEG_ENC_RESET_STATUS_MASK 0x00020000L 6252 #define JPEG_SOFT_RESET_STATUS__EJRBC_RESET_STATUS_MASK 0x00040000L 6253 #define JPEG_SOFT_RESET_STATUS__JMCIF_RESET_STATUS_MASK 0x01000000L 6254 //JPEG_SYS_INT_EN 6255 #define JPEG_SYS_INT_EN__DJPEG0_CORE__SHIFT 0x0 6256 #define JPEG_SYS_INT_EN__DJPEG1_CORE__SHIFT 0x1 6257 #define JPEG_SYS_INT_EN__DJPEG2_CORE__SHIFT 0x2 6258 #define JPEG_SYS_INT_EN__DJPEG3_CORE__SHIFT 0x3 6259 #define JPEG_SYS_INT_EN__DJPEG4_CORE__SHIFT 0x4 6260 #define JPEG_SYS_INT_EN__DJPEG5_CORE__SHIFT 0x5 6261 #define JPEG_SYS_INT_EN__DJPEG6_CORE__SHIFT 0x6 6262 #define JPEG_SYS_INT_EN__DJPEG7_CORE__SHIFT 0x7 6263 #define JPEG_SYS_INT_EN__DJRBC0__SHIFT 0x8 6264 #define JPEG_SYS_INT_EN__DJRBC1__SHIFT 0x9 6265 #define JPEG_SYS_INT_EN__DJRBC2__SHIFT 0xa 6266 #define JPEG_SYS_INT_EN__DJRBC3__SHIFT 0xb 6267 #define JPEG_SYS_INT_EN__DJRBC4__SHIFT 0xc 6268 #define JPEG_SYS_INT_EN__DJRBC5__SHIFT 0xd 6269 #define JPEG_SYS_INT_EN__DJRBC6__SHIFT 0xe 6270 #define JPEG_SYS_INT_EN__DJRBC7__SHIFT 0xf 6271 #define JPEG_SYS_INT_EN__DJPEG0_PF_RPT__SHIFT 0x10 6272 #define JPEG_SYS_INT_EN__DJPEG1_PF_RPT__SHIFT 0x11 6273 #define JPEG_SYS_INT_EN__DJPEG2_PF_RPT__SHIFT 0x12 6274 #define JPEG_SYS_INT_EN__DJPEG3_PF_RPT__SHIFT 0x13 6275 #define JPEG_SYS_INT_EN__DJPEG4_PF_RPT__SHIFT 0x14 6276 #define JPEG_SYS_INT_EN__DJPEG5_PF_RPT__SHIFT 0x15 6277 #define JPEG_SYS_INT_EN__DJPEG6_PF_RPT__SHIFT 0x16 6278 #define JPEG_SYS_INT_EN__DJPEG7_PF_RPT__SHIFT 0x17 6279 #define JPEG_SYS_INT_EN__DJPEG0_RAS_CNTL__SHIFT 0x18 6280 #define JPEG_SYS_INT_EN__DJPEG1_RAS_CNTL__SHIFT 0x19 6281 #define JPEG_SYS_INT_EN__DJPEG0_CORE_MASK 0x00000001L 6282 #define JPEG_SYS_INT_EN__DJPEG1_CORE_MASK 0x00000002L 6283 #define JPEG_SYS_INT_EN__DJPEG2_CORE_MASK 0x00000004L 6284 #define JPEG_SYS_INT_EN__DJPEG3_CORE_MASK 0x00000008L 6285 #define JPEG_SYS_INT_EN__DJPEG4_CORE_MASK 0x00000010L 6286 #define JPEG_SYS_INT_EN__DJPEG5_CORE_MASK 0x00000020L 6287 #define JPEG_SYS_INT_EN__DJPEG6_CORE_MASK 0x00000040L 6288 #define JPEG_SYS_INT_EN__DJPEG7_CORE_MASK 0x00000080L 6289 #define JPEG_SYS_INT_EN__DJRBC0_MASK 0x00000100L 6290 #define JPEG_SYS_INT_EN__DJRBC1_MASK 0x00000200L 6291 #define JPEG_SYS_INT_EN__DJRBC2_MASK 0x00000400L 6292 #define JPEG_SYS_INT_EN__DJRBC3_MASK 0x00000800L 6293 #define JPEG_SYS_INT_EN__DJRBC4_MASK 0x00001000L 6294 #define JPEG_SYS_INT_EN__DJRBC5_MASK 0x00002000L 6295 #define JPEG_SYS_INT_EN__DJRBC6_MASK 0x00004000L 6296 #define JPEG_SYS_INT_EN__DJRBC7_MASK 0x00008000L 6297 #define JPEG_SYS_INT_EN__DJPEG0_PF_RPT_MASK 0x00010000L 6298 #define JPEG_SYS_INT_EN__DJPEG1_PF_RPT_MASK 0x00020000L 6299 #define JPEG_SYS_INT_EN__DJPEG2_PF_RPT_MASK 0x00040000L 6300 #define JPEG_SYS_INT_EN__DJPEG3_PF_RPT_MASK 0x00080000L 6301 #define JPEG_SYS_INT_EN__DJPEG4_PF_RPT_MASK 0x00100000L 6302 #define JPEG_SYS_INT_EN__DJPEG5_PF_RPT_MASK 0x00200000L 6303 #define JPEG_SYS_INT_EN__DJPEG6_PF_RPT_MASK 0x00400000L 6304 #define JPEG_SYS_INT_EN__DJPEG7_PF_RPT_MASK 0x00800000L 6305 #define JPEG_SYS_INT_EN__DJPEG0_RAS_CNTL_MASK 0x01000000L 6306 #define JPEG_SYS_INT_EN__DJPEG1_RAS_CNTL_MASK 0x02000000L 6307 //JPEG_SYS_INT_EN1 6308 #define JPEG_SYS_INT_EN1__EJPEG_PF_RPT__SHIFT 0x0 6309 #define JPEG_SYS_INT_EN1__EJPEG_CORE__SHIFT 0x1 6310 #define JPEG_SYS_INT_EN1__EJRBC__SHIFT 0x2 6311 #define JPEG_SYS_INT_EN1__EJPEG_RAS_CNTL__SHIFT 0x3 6312 #define JPEG_SYS_INT_EN1__EJPEG_PF_RPT_MASK 0x00000001L 6313 #define JPEG_SYS_INT_EN1__EJPEG_CORE_MASK 0x00000002L 6314 #define JPEG_SYS_INT_EN1__EJRBC_MASK 0x00000004L 6315 #define JPEG_SYS_INT_EN1__EJPEG_RAS_CNTL_MASK 0x00000008L 6316 //JPEG_SYS_INT_STATUS 6317 #define JPEG_SYS_INT_STATUS__DJPEG0_CORE__SHIFT 0x0 6318 #define JPEG_SYS_INT_STATUS__DJPEG1_CORE__SHIFT 0x1 6319 #define JPEG_SYS_INT_STATUS__DJPEG2_CORE__SHIFT 0x2 6320 #define JPEG_SYS_INT_STATUS__DJPEG3_CORE__SHIFT 0x3 6321 #define JPEG_SYS_INT_STATUS__DJPEG4_CORE__SHIFT 0x4 6322 #define JPEG_SYS_INT_STATUS__DJPEG5_CORE__SHIFT 0x5 6323 #define JPEG_SYS_INT_STATUS__DJPEG6_CORE__SHIFT 0x6 6324 #define JPEG_SYS_INT_STATUS__DJPEG7_CORE__SHIFT 0x7 6325 #define JPEG_SYS_INT_STATUS__DJRBC0__SHIFT 0x8 6326 #define JPEG_SYS_INT_STATUS__DJRBC1__SHIFT 0x9 6327 #define JPEG_SYS_INT_STATUS__DJRBC2__SHIFT 0xa 6328 #define JPEG_SYS_INT_STATUS__DJRBC3__SHIFT 0xb 6329 #define JPEG_SYS_INT_STATUS__DJRBC4__SHIFT 0xc 6330 #define JPEG_SYS_INT_STATUS__DJRBC5__SHIFT 0xd 6331 #define JPEG_SYS_INT_STATUS__DJRBC6__SHIFT 0xe 6332 #define JPEG_SYS_INT_STATUS__DJRBC7__SHIFT 0xf 6333 #define JPEG_SYS_INT_STATUS__DJPEG0_PF_RPT__SHIFT 0x10 6334 #define JPEG_SYS_INT_STATUS__DJPEG1_PF_RPT__SHIFT 0x11 6335 #define JPEG_SYS_INT_STATUS__DJPEG2_PF_RPT__SHIFT 0x12 6336 #define JPEG_SYS_INT_STATUS__DJPEG3_PF_RPT__SHIFT 0x13 6337 #define JPEG_SYS_INT_STATUS__DJPEG4_PF_RPT__SHIFT 0x14 6338 #define JPEG_SYS_INT_STATUS__DJPEG5_PF_RPT__SHIFT 0x15 6339 #define JPEG_SYS_INT_STATUS__DJPEG6_PF_RPT__SHIFT 0x16 6340 #define JPEG_SYS_INT_STATUS__DJPEG7_PF_RPT__SHIFT 0x17 6341 #define JPEG_SYS_INT_STATUS__DJPEG0_RAS_CNTL__SHIFT 0x18 6342 #define JPEG_SYS_INT_STATUS__DJPEG1_RAS_CNTL__SHIFT 0x19 6343 #define JPEG_SYS_INT_STATUS__DJPEG0_CORE_MASK 0x00000001L 6344 #define JPEG_SYS_INT_STATUS__DJPEG1_CORE_MASK 0x00000002L 6345 #define JPEG_SYS_INT_STATUS__DJPEG2_CORE_MASK 0x00000004L 6346 #define JPEG_SYS_INT_STATUS__DJPEG3_CORE_MASK 0x00000008L 6347 #define JPEG_SYS_INT_STATUS__DJPEG4_CORE_MASK 0x00000010L 6348 #define JPEG_SYS_INT_STATUS__DJPEG5_CORE_MASK 0x00000020L 6349 #define JPEG_SYS_INT_STATUS__DJPEG6_CORE_MASK 0x00000040L 6350 #define JPEG_SYS_INT_STATUS__DJPEG7_CORE_MASK 0x00000080L 6351 #define JPEG_SYS_INT_STATUS__DJRBC0_MASK 0x00000100L 6352 #define JPEG_SYS_INT_STATUS__DJRBC1_MASK 0x00000200L 6353 #define JPEG_SYS_INT_STATUS__DJRBC2_MASK 0x00000400L 6354 #define JPEG_SYS_INT_STATUS__DJRBC3_MASK 0x00000800L 6355 #define JPEG_SYS_INT_STATUS__DJRBC4_MASK 0x00001000L 6356 #define JPEG_SYS_INT_STATUS__DJRBC5_MASK 0x00002000L 6357 #define JPEG_SYS_INT_STATUS__DJRBC6_MASK 0x00004000L 6358 #define JPEG_SYS_INT_STATUS__DJRBC7_MASK 0x00008000L 6359 #define JPEG_SYS_INT_STATUS__DJPEG0_PF_RPT_MASK 0x00010000L 6360 #define JPEG_SYS_INT_STATUS__DJPEG1_PF_RPT_MASK 0x00020000L 6361 #define JPEG_SYS_INT_STATUS__DJPEG2_PF_RPT_MASK 0x00040000L 6362 #define JPEG_SYS_INT_STATUS__DJPEG3_PF_RPT_MASK 0x00080000L 6363 #define JPEG_SYS_INT_STATUS__DJPEG4_PF_RPT_MASK 0x00100000L 6364 #define JPEG_SYS_INT_STATUS__DJPEG5_PF_RPT_MASK 0x00200000L 6365 #define JPEG_SYS_INT_STATUS__DJPEG6_PF_RPT_MASK 0x00400000L 6366 #define JPEG_SYS_INT_STATUS__DJPEG7_PF_RPT_MASK 0x00800000L 6367 #define JPEG_SYS_INT_STATUS__DJPEG0_RAS_CNTL_MASK 0x01000000L 6368 #define JPEG_SYS_INT_STATUS__DJPEG1_RAS_CNTL_MASK 0x02000000L 6369 //JPEG_SYS_INT_STATUS1 6370 #define JPEG_SYS_INT_STATUS1__EJPEG_PF_RPT__SHIFT 0x0 6371 #define JPEG_SYS_INT_STATUS1__EJPEG_CORE__SHIFT 0x1 6372 #define JPEG_SYS_INT_STATUS1__EJRBC__SHIFT 0x2 6373 #define JPEG_SYS_INT_STATUS1__EJPEG_RAS_CNTL__SHIFT 0x3 6374 #define JPEG_SYS_INT_STATUS1__EJPEG_PF_RPT_MASK 0x00000001L 6375 #define JPEG_SYS_INT_STATUS1__EJPEG_CORE_MASK 0x00000002L 6376 #define JPEG_SYS_INT_STATUS1__EJRBC_MASK 0x00000004L 6377 #define JPEG_SYS_INT_STATUS1__EJPEG_RAS_CNTL_MASK 0x00000008L 6378 //JPEG_SYS_INT_ACK 6379 #define JPEG_SYS_INT_ACK__DJPEG0_CORE__SHIFT 0x0 6380 #define JPEG_SYS_INT_ACK__DJPEG1_CORE__SHIFT 0x1 6381 #define JPEG_SYS_INT_ACK__DJPEG2_CORE__SHIFT 0x2 6382 #define JPEG_SYS_INT_ACK__DJPEG3_CORE__SHIFT 0x3 6383 #define JPEG_SYS_INT_ACK__DJPEG4_CORE__SHIFT 0x4 6384 #define JPEG_SYS_INT_ACK__DJPEG5_CORE__SHIFT 0x5 6385 #define JPEG_SYS_INT_ACK__DJPEG6_CORE__SHIFT 0x6 6386 #define JPEG_SYS_INT_ACK__DJPEG7_CORE__SHIFT 0x7 6387 #define JPEG_SYS_INT_ACK__DJRBC0__SHIFT 0x8 6388 #define JPEG_SYS_INT_ACK__DJRBC1__SHIFT 0x9 6389 #define JPEG_SYS_INT_ACK__DJRBC2__SHIFT 0xa 6390 #define JPEG_SYS_INT_ACK__DJRBC3__SHIFT 0xb 6391 #define JPEG_SYS_INT_ACK__DJRBC4__SHIFT 0xc 6392 #define JPEG_SYS_INT_ACK__DJRBC5__SHIFT 0xd 6393 #define JPEG_SYS_INT_ACK__DJRBC6__SHIFT 0xe 6394 #define JPEG_SYS_INT_ACK__DJRBC7__SHIFT 0xf 6395 #define JPEG_SYS_INT_ACK__DJPEG0_PF_RPT__SHIFT 0x10 6396 #define JPEG_SYS_INT_ACK__DJPEG1_PF_RPT__SHIFT 0x11 6397 #define JPEG_SYS_INT_ACK__DJPEG2_PF_RPT__SHIFT 0x12 6398 #define JPEG_SYS_INT_ACK__DJPEG3_PF_RPT__SHIFT 0x13 6399 #define JPEG_SYS_INT_ACK__DJPEG4_PF_RPT__SHIFT 0x14 6400 #define JPEG_SYS_INT_ACK__DJPEG5_PF_RPT__SHIFT 0x15 6401 #define JPEG_SYS_INT_ACK__DJPEG6_PF_RPT__SHIFT 0x16 6402 #define JPEG_SYS_INT_ACK__DJPEG7_PF_RPT__SHIFT 0x17 6403 #define JPEG_SYS_INT_ACK__DJPEG0_RAS_CNTL__SHIFT 0x18 6404 #define JPEG_SYS_INT_ACK__DJPEG1_RAS_CNTL__SHIFT 0x19 6405 #define JPEG_SYS_INT_ACK__DJPEG0_CORE_MASK 0x00000001L 6406 #define JPEG_SYS_INT_ACK__DJPEG1_CORE_MASK 0x00000002L 6407 #define JPEG_SYS_INT_ACK__DJPEG2_CORE_MASK 0x00000004L 6408 #define JPEG_SYS_INT_ACK__DJPEG3_CORE_MASK 0x00000008L 6409 #define JPEG_SYS_INT_ACK__DJPEG4_CORE_MASK 0x00000010L 6410 #define JPEG_SYS_INT_ACK__DJPEG5_CORE_MASK 0x00000020L 6411 #define JPEG_SYS_INT_ACK__DJPEG6_CORE_MASK 0x00000040L 6412 #define JPEG_SYS_INT_ACK__DJPEG7_CORE_MASK 0x00000080L 6413 #define JPEG_SYS_INT_ACK__DJRBC0_MASK 0x00000100L 6414 #define JPEG_SYS_INT_ACK__DJRBC1_MASK 0x00000200L 6415 #define JPEG_SYS_INT_ACK__DJRBC2_MASK 0x00000400L 6416 #define JPEG_SYS_INT_ACK__DJRBC3_MASK 0x00000800L 6417 #define JPEG_SYS_INT_ACK__DJRBC4_MASK 0x00001000L 6418 #define JPEG_SYS_INT_ACK__DJRBC5_MASK 0x00002000L 6419 #define JPEG_SYS_INT_ACK__DJRBC6_MASK 0x00004000L 6420 #define JPEG_SYS_INT_ACK__DJRBC7_MASK 0x00008000L 6421 #define JPEG_SYS_INT_ACK__DJPEG0_PF_RPT_MASK 0x00010000L 6422 #define JPEG_SYS_INT_ACK__DJPEG1_PF_RPT_MASK 0x00020000L 6423 #define JPEG_SYS_INT_ACK__DJPEG2_PF_RPT_MASK 0x00040000L 6424 #define JPEG_SYS_INT_ACK__DJPEG3_PF_RPT_MASK 0x00080000L 6425 #define JPEG_SYS_INT_ACK__DJPEG4_PF_RPT_MASK 0x00100000L 6426 #define JPEG_SYS_INT_ACK__DJPEG5_PF_RPT_MASK 0x00200000L 6427 #define JPEG_SYS_INT_ACK__DJPEG6_PF_RPT_MASK 0x00400000L 6428 #define JPEG_SYS_INT_ACK__DJPEG7_PF_RPT_MASK 0x00800000L 6429 #define JPEG_SYS_INT_ACK__DJPEG0_RAS_CNTL_MASK 0x01000000L 6430 #define JPEG_SYS_INT_ACK__DJPEG1_RAS_CNTL_MASK 0x02000000L 6431 //JPEG_SYS_INT_ACK1 6432 #define JPEG_SYS_INT_ACK1__EJPEG_PF_RPT__SHIFT 0x0 6433 #define JPEG_SYS_INT_ACK1__EJPEG_CORE__SHIFT 0x1 6434 #define JPEG_SYS_INT_ACK1__EJRBC__SHIFT 0x2 6435 #define JPEG_SYS_INT_ACK1__EJPEG_RAS_CNTL__SHIFT 0x3 6436 #define JPEG_SYS_INT_ACK1__EJPEG_PF_RPT_MASK 0x00000001L 6437 #define JPEG_SYS_INT_ACK1__EJPEG_CORE_MASK 0x00000002L 6438 #define JPEG_SYS_INT_ACK1__EJRBC_MASK 0x00000004L 6439 #define JPEG_SYS_INT_ACK1__EJPEG_RAS_CNTL_MASK 0x00000008L 6440 //JPEG_MEMCHECK_SYS_INT_EN 6441 #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC0_RD_ERR_EN__SHIFT 0x0 6442 #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC1_RD_ERR_EN__SHIFT 0x1 6443 #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC2_RD_ERR_EN__SHIFT 0x2 6444 #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC3_RD_ERR_EN__SHIFT 0x3 6445 #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC4_RD_ERR_EN__SHIFT 0x4 6446 #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC5_RD_ERR_EN__SHIFT 0x5 6447 #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC6_RD_ERR_EN__SHIFT 0x6 6448 #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC7_RD_ERR_EN__SHIFT 0x7 6449 #define JPEG_MEMCHECK_SYS_INT_EN__BSFETCH0_RD_ERR_EN__SHIFT 0x8 6450 #define JPEG_MEMCHECK_SYS_INT_EN__BSFETCH1_RD_ERR_EN__SHIFT 0x9 6451 #define JPEG_MEMCHECK_SYS_INT_EN__BSFETCH2_RD_ERR_EN__SHIFT 0xa 6452 #define JPEG_MEMCHECK_SYS_INT_EN__BSFETCH3_RD_ERR_EN__SHIFT 0xb 6453 #define JPEG_MEMCHECK_SYS_INT_EN__BSFETCH4_RD_ERR_EN__SHIFT 0xc 6454 #define JPEG_MEMCHECK_SYS_INT_EN__BSFETCH5_RD_ERR_EN__SHIFT 0xd 6455 #define JPEG_MEMCHECK_SYS_INT_EN__BSFETCH6_RD_ERR_EN__SHIFT 0xe 6456 #define JPEG_MEMCHECK_SYS_INT_EN__BSFETCH7_RD_ERR_EN__SHIFT 0xf 6457 #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC0_WR_ERR_EN__SHIFT 0x10 6458 #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC1_WR_ERR_EN__SHIFT 0x11 6459 #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC2_WR_ERR_EN__SHIFT 0x12 6460 #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC3_WR_ERR_EN__SHIFT 0x13 6461 #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC4_WR_ERR_EN__SHIFT 0x14 6462 #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC5_WR_ERR_EN__SHIFT 0x15 6463 #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC6_WR_ERR_EN__SHIFT 0x16 6464 #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC7_WR_ERR_EN__SHIFT 0x17 6465 #define JPEG_MEMCHECK_SYS_INT_EN__OBUF0_WR_ERR_EN__SHIFT 0x18 6466 #define JPEG_MEMCHECK_SYS_INT_EN__OBUF1_WR_ERR_EN__SHIFT 0x19 6467 #define JPEG_MEMCHECK_SYS_INT_EN__OBUF2_WR_ERR_EN__SHIFT 0x1a 6468 #define JPEG_MEMCHECK_SYS_INT_EN__OBUF3_WR_ERR_EN__SHIFT 0x1b 6469 #define JPEG_MEMCHECK_SYS_INT_EN__OBUF4_WR_ERR_EN__SHIFT 0x1c 6470 #define JPEG_MEMCHECK_SYS_INT_EN__OBUF5_WR_ERR_EN__SHIFT 0x1d 6471 #define JPEG_MEMCHECK_SYS_INT_EN__OBUF6_WR_ERR_EN__SHIFT 0x1e 6472 #define JPEG_MEMCHECK_SYS_INT_EN__OBUF7_WR_ERR_EN__SHIFT 0x1f 6473 #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC0_RD_ERR_EN_MASK 0x00000001L 6474 #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC1_RD_ERR_EN_MASK 0x00000002L 6475 #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC2_RD_ERR_EN_MASK 0x00000004L 6476 #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC3_RD_ERR_EN_MASK 0x00000008L 6477 #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC4_RD_ERR_EN_MASK 0x00000010L 6478 #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC5_RD_ERR_EN_MASK 0x00000020L 6479 #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC6_RD_ERR_EN_MASK 0x00000040L 6480 #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC7_RD_ERR_EN_MASK 0x00000080L 6481 #define JPEG_MEMCHECK_SYS_INT_EN__BSFETCH0_RD_ERR_EN_MASK 0x00000100L 6482 #define JPEG_MEMCHECK_SYS_INT_EN__BSFETCH1_RD_ERR_EN_MASK 0x00000200L 6483 #define JPEG_MEMCHECK_SYS_INT_EN__BSFETCH2_RD_ERR_EN_MASK 0x00000400L 6484 #define JPEG_MEMCHECK_SYS_INT_EN__BSFETCH3_RD_ERR_EN_MASK 0x00000800L 6485 #define JPEG_MEMCHECK_SYS_INT_EN__BSFETCH4_RD_ERR_EN_MASK 0x00001000L 6486 #define JPEG_MEMCHECK_SYS_INT_EN__BSFETCH5_RD_ERR_EN_MASK 0x00002000L 6487 #define JPEG_MEMCHECK_SYS_INT_EN__BSFETCH6_RD_ERR_EN_MASK 0x00004000L 6488 #define JPEG_MEMCHECK_SYS_INT_EN__BSFETCH7_RD_ERR_EN_MASK 0x00008000L 6489 #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC0_WR_ERR_EN_MASK 0x00010000L 6490 #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC1_WR_ERR_EN_MASK 0x00020000L 6491 #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC2_WR_ERR_EN_MASK 0x00040000L 6492 #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC3_WR_ERR_EN_MASK 0x00080000L 6493 #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC4_WR_ERR_EN_MASK 0x00100000L 6494 #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC5_WR_ERR_EN_MASK 0x00200000L 6495 #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC6_WR_ERR_EN_MASK 0x00400000L 6496 #define JPEG_MEMCHECK_SYS_INT_EN__DJRBC7_WR_ERR_EN_MASK 0x00800000L 6497 #define JPEG_MEMCHECK_SYS_INT_EN__OBUF0_WR_ERR_EN_MASK 0x01000000L 6498 #define JPEG_MEMCHECK_SYS_INT_EN__OBUF1_WR_ERR_EN_MASK 0x02000000L 6499 #define JPEG_MEMCHECK_SYS_INT_EN__OBUF2_WR_ERR_EN_MASK 0x04000000L 6500 #define JPEG_MEMCHECK_SYS_INT_EN__OBUF3_WR_ERR_EN_MASK 0x08000000L 6501 #define JPEG_MEMCHECK_SYS_INT_EN__OBUF4_WR_ERR_EN_MASK 0x10000000L 6502 #define JPEG_MEMCHECK_SYS_INT_EN__OBUF5_WR_ERR_EN_MASK 0x20000000L 6503 #define JPEG_MEMCHECK_SYS_INT_EN__OBUF6_WR_ERR_EN_MASK 0x40000000L 6504 #define JPEG_MEMCHECK_SYS_INT_EN__OBUF7_WR_ERR_EN_MASK 0x80000000L 6505 //JPEG_MEMCHECK_SYS_INT_EN1 6506 #define JPEG_MEMCHECK_SYS_INT_EN1__EJRBC_RD_ERR_EN__SHIFT 0x0 6507 #define JPEG_MEMCHECK_SYS_INT_EN1__PELFETCH_RD_ERR_EN__SHIFT 0x1 6508 #define JPEG_MEMCHECK_SYS_INT_EN1__SCALAR_RD_ERR_EN__SHIFT 0x2 6509 #define JPEG_MEMCHECK_SYS_INT_EN1__EJRBC_WR_ERR_EN__SHIFT 0x3 6510 #define JPEG_MEMCHECK_SYS_INT_EN1__BS_WR_ERR_EN__SHIFT 0x4 6511 #define JPEG_MEMCHECK_SYS_INT_EN1__SCALAR_WR_ERR_EN__SHIFT 0x5 6512 #define JPEG_MEMCHECK_SYS_INT_EN1__EJRBC_RD_ERR_EN_MASK 0x00000001L 6513 #define JPEG_MEMCHECK_SYS_INT_EN1__PELFETCH_RD_ERR_EN_MASK 0x00000002L 6514 #define JPEG_MEMCHECK_SYS_INT_EN1__SCALAR_RD_ERR_EN_MASK 0x00000004L 6515 #define JPEG_MEMCHECK_SYS_INT_EN1__EJRBC_WR_ERR_EN_MASK 0x00000008L 6516 #define JPEG_MEMCHECK_SYS_INT_EN1__BS_WR_ERR_EN_MASK 0x00000010L 6517 #define JPEG_MEMCHECK_SYS_INT_EN1__SCALAR_WR_ERR_EN_MASK 0x00000020L 6518 //JPEG_MEMCHECK_SYS_INT_STAT 6519 #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH0_RD_HI_ERR__SHIFT 0x0 6520 #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH1_RD_HI_ERR__SHIFT 0x1 6521 #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH2_RD_HI_ERR__SHIFT 0x2 6522 #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH3_RD_HI_ERR__SHIFT 0x3 6523 #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH4_RD_HI_ERR__SHIFT 0x4 6524 #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH5_RD_HI_ERR__SHIFT 0x5 6525 #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH6_RD_HI_ERR__SHIFT 0x6 6526 #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH7_RD_HI_ERR__SHIFT 0x7 6527 #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH0_RD_LO_ERR__SHIFT 0x8 6528 #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH1_RD_LO_ERR__SHIFT 0x9 6529 #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH2_RD_LO_ERR__SHIFT 0xa 6530 #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH3_RD_LO_ERR__SHIFT 0xb 6531 #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH4_RD_LO_ERR__SHIFT 0xc 6532 #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH5_RD_LO_ERR__SHIFT 0xd 6533 #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH6_RD_LO_ERR__SHIFT 0xe 6534 #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH7_RD_LO_ERR__SHIFT 0xf 6535 #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF0_WR_HI_ERR__SHIFT 0x10 6536 #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF1_WR_HI_ERR__SHIFT 0x11 6537 #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF2_WR_HI_ERR__SHIFT 0x12 6538 #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF3_WR_HI_ERR__SHIFT 0x13 6539 #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF4_WR_HI_ERR__SHIFT 0x14 6540 #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF5_WR_HI_ERR__SHIFT 0x15 6541 #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF6_WR_HI_ERR__SHIFT 0x16 6542 #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF7_WR_HI_ERR__SHIFT 0x17 6543 #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF0_WR_LO_ERR__SHIFT 0x18 6544 #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF1_WR_LO_ERR__SHIFT 0x19 6545 #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF2_WR_LO_ERR__SHIFT 0x1a 6546 #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF3_WR_LO_ERR__SHIFT 0x1b 6547 #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF4_WR_LO_ERR__SHIFT 0x1c 6548 #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF5_WR_LO_ERR__SHIFT 0x1d 6549 #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF6_WR_LO_ERR__SHIFT 0x1e 6550 #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF7_WR_LO_ERR__SHIFT 0x1f 6551 #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH0_RD_HI_ERR_MASK 0x00000001L 6552 #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH1_RD_HI_ERR_MASK 0x00000002L 6553 #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH2_RD_HI_ERR_MASK 0x00000004L 6554 #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH3_RD_HI_ERR_MASK 0x00000008L 6555 #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH4_RD_HI_ERR_MASK 0x00000010L 6556 #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH5_RD_HI_ERR_MASK 0x00000020L 6557 #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH6_RD_HI_ERR_MASK 0x00000040L 6558 #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH7_RD_HI_ERR_MASK 0x00000080L 6559 #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH0_RD_LO_ERR_MASK 0x00000100L 6560 #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH1_RD_LO_ERR_MASK 0x00000200L 6561 #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH2_RD_LO_ERR_MASK 0x00000400L 6562 #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH3_RD_LO_ERR_MASK 0x00000800L 6563 #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH4_RD_LO_ERR_MASK 0x00001000L 6564 #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH5_RD_LO_ERR_MASK 0x00002000L 6565 #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH6_RD_LO_ERR_MASK 0x00004000L 6566 #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH7_RD_LO_ERR_MASK 0x00008000L 6567 #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF0_WR_HI_ERR_MASK 0x00010000L 6568 #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF1_WR_HI_ERR_MASK 0x00020000L 6569 #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF2_WR_HI_ERR_MASK 0x00040000L 6570 #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF3_WR_HI_ERR_MASK 0x00080000L 6571 #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF4_WR_HI_ERR_MASK 0x00100000L 6572 #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF5_WR_HI_ERR_MASK 0x00200000L 6573 #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF6_WR_HI_ERR_MASK 0x00400000L 6574 #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF7_WR_HI_ERR_MASK 0x00800000L 6575 #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF0_WR_LO_ERR_MASK 0x01000000L 6576 #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF1_WR_LO_ERR_MASK 0x02000000L 6577 #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF2_WR_LO_ERR_MASK 0x04000000L 6578 #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF3_WR_LO_ERR_MASK 0x08000000L 6579 #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF4_WR_LO_ERR_MASK 0x10000000L 6580 #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF5_WR_LO_ERR_MASK 0x20000000L 6581 #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF6_WR_LO_ERR_MASK 0x40000000L 6582 #define JPEG_MEMCHECK_SYS_INT_STAT__OBUF7_WR_LO_ERR_MASK 0x80000000L 6583 //JPEG_MEMCHECK_SYS_INT_STAT1 6584 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC0_RD_HI_ERR__SHIFT 0x0 6585 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC1_RD_HI_ERR__SHIFT 0x1 6586 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC2_RD_HI_ERR__SHIFT 0x2 6587 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC3_RD_HI_ERR__SHIFT 0x3 6588 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC4_RD_HI_ERR__SHIFT 0x4 6589 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC5_RD_HI_ERR__SHIFT 0x5 6590 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC6_RD_HI_ERR__SHIFT 0x6 6591 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC7_RD_HI_ERR__SHIFT 0x7 6592 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC0_RD_LO_ERR__SHIFT 0x8 6593 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC1_RD_LO_ERR__SHIFT 0x9 6594 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC2_RD_LO_ERR__SHIFT 0xa 6595 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC3_RD_LO_ERR__SHIFT 0xb 6596 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC4_RD_LO_ERR__SHIFT 0xc 6597 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC5_RD_LO_ERR__SHIFT 0xd 6598 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC6_RD_LO_ERR__SHIFT 0xe 6599 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC7_RD_LO_ERR__SHIFT 0xf 6600 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC0_WR_HI_ERR__SHIFT 0x10 6601 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC1_WR_HI_ERR__SHIFT 0x11 6602 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC2_WR_HI_ERR__SHIFT 0x12 6603 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC3_WR_HI_ERR__SHIFT 0x13 6604 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC4_WR_HI_ERR__SHIFT 0x14 6605 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC5_WR_HI_ERR__SHIFT 0x15 6606 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC6_WR_HI_ERR__SHIFT 0x16 6607 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC7_WR_HI_ERR__SHIFT 0x17 6608 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC0_WR_LO_ERR__SHIFT 0x18 6609 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC1_WR_LO_ERR__SHIFT 0x19 6610 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC2_WR_LO_ERR__SHIFT 0x1a 6611 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC3_WR_LO_ERR__SHIFT 0x1b 6612 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC4_WR_LO_ERR__SHIFT 0x1c 6613 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC5_WR_LO_ERR__SHIFT 0x1d 6614 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC6_WR_LO_ERR__SHIFT 0x1e 6615 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC7_WR_LO_ERR__SHIFT 0x1f 6616 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC0_RD_HI_ERR_MASK 0x00000001L 6617 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC1_RD_HI_ERR_MASK 0x00000002L 6618 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC2_RD_HI_ERR_MASK 0x00000004L 6619 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC3_RD_HI_ERR_MASK 0x00000008L 6620 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC4_RD_HI_ERR_MASK 0x00000010L 6621 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC5_RD_HI_ERR_MASK 0x00000020L 6622 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC6_RD_HI_ERR_MASK 0x00000040L 6623 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC7_RD_HI_ERR_MASK 0x00000080L 6624 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC0_RD_LO_ERR_MASK 0x00000100L 6625 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC1_RD_LO_ERR_MASK 0x00000200L 6626 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC2_RD_LO_ERR_MASK 0x00000400L 6627 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC3_RD_LO_ERR_MASK 0x00000800L 6628 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC4_RD_LO_ERR_MASK 0x00001000L 6629 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC5_RD_LO_ERR_MASK 0x00002000L 6630 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC6_RD_LO_ERR_MASK 0x00004000L 6631 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC7_RD_LO_ERR_MASK 0x00008000L 6632 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC0_WR_HI_ERR_MASK 0x00010000L 6633 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC1_WR_HI_ERR_MASK 0x00020000L 6634 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC2_WR_HI_ERR_MASK 0x00040000L 6635 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC3_WR_HI_ERR_MASK 0x00080000L 6636 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC4_WR_HI_ERR_MASK 0x00100000L 6637 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC5_WR_HI_ERR_MASK 0x00200000L 6638 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC6_WR_HI_ERR_MASK 0x00400000L 6639 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC7_WR_HI_ERR_MASK 0x00800000L 6640 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC0_WR_LO_ERR_MASK 0x01000000L 6641 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC1_WR_LO_ERR_MASK 0x02000000L 6642 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC2_WR_LO_ERR_MASK 0x04000000L 6643 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC3_WR_LO_ERR_MASK 0x08000000L 6644 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC4_WR_LO_ERR_MASK 0x10000000L 6645 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC5_WR_LO_ERR_MASK 0x20000000L 6646 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC6_WR_LO_ERR_MASK 0x40000000L 6647 #define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC7_WR_LO_ERR_MASK 0x80000000L 6648 //JPEG_MEMCHECK_SYS_INT_STAT2 6649 #define JPEG_MEMCHECK_SYS_INT_STAT2__EJRBC_RD_HI_ERR__SHIFT 0x0 6650 #define JPEG_MEMCHECK_SYS_INT_STAT2__EJRBC_RD_LO_ERR__SHIFT 0x1 6651 #define JPEG_MEMCHECK_SYS_INT_STAT2__PELFETCH_RD_HI_ERR__SHIFT 0x2 6652 #define JPEG_MEMCHECK_SYS_INT_STAT2__PELFETCH_RD_LO_ERR__SHIFT 0x3 6653 #define JPEG_MEMCHECK_SYS_INT_STAT2__SCALAR_RD_HI_ERR__SHIFT 0x4 6654 #define JPEG_MEMCHECK_SYS_INT_STAT2__SCALAR_RD_LO_ERR__SHIFT 0x5 6655 #define JPEG_MEMCHECK_SYS_INT_STAT2__EJRBC_WR_HI_ERR__SHIFT 0x6 6656 #define JPEG_MEMCHECK_SYS_INT_STAT2__EJRBC_WR_LO_ERR__SHIFT 0x7 6657 #define JPEG_MEMCHECK_SYS_INT_STAT2__BS_WR_HI_ERR__SHIFT 0x8 6658 #define JPEG_MEMCHECK_SYS_INT_STAT2__BS_WR_LO_ERR__SHIFT 0x9 6659 #define JPEG_MEMCHECK_SYS_INT_STAT2__SCALAR_WR_HI_ERR__SHIFT 0xa 6660 #define JPEG_MEMCHECK_SYS_INT_STAT2__SCALAR_WR_LO_ERR__SHIFT 0xb 6661 #define JPEG_MEMCHECK_SYS_INT_STAT2__EJRBC_RD_HI_ERR_MASK 0x00000001L 6662 #define JPEG_MEMCHECK_SYS_INT_STAT2__EJRBC_RD_LO_ERR_MASK 0x00000002L 6663 #define JPEG_MEMCHECK_SYS_INT_STAT2__PELFETCH_RD_HI_ERR_MASK 0x00000004L 6664 #define JPEG_MEMCHECK_SYS_INT_STAT2__PELFETCH_RD_LO_ERR_MASK 0x00000008L 6665 #define JPEG_MEMCHECK_SYS_INT_STAT2__SCALAR_RD_HI_ERR_MASK 0x00000010L 6666 #define JPEG_MEMCHECK_SYS_INT_STAT2__SCALAR_RD_LO_ERR_MASK 0x00000020L 6667 #define JPEG_MEMCHECK_SYS_INT_STAT2__EJRBC_WR_HI_ERR_MASK 0x00000040L 6668 #define JPEG_MEMCHECK_SYS_INT_STAT2__EJRBC_WR_LO_ERR_MASK 0x00000080L 6669 #define JPEG_MEMCHECK_SYS_INT_STAT2__BS_WR_HI_ERR_MASK 0x00000100L 6670 #define JPEG_MEMCHECK_SYS_INT_STAT2__BS_WR_LO_ERR_MASK 0x00000200L 6671 #define JPEG_MEMCHECK_SYS_INT_STAT2__SCALAR_WR_HI_ERR_MASK 0x00000400L 6672 #define JPEG_MEMCHECK_SYS_INT_STAT2__SCALAR_WR_LO_ERR_MASK 0x00000800L 6673 //JPEG_MEMCHECK_SYS_INT_ACK 6674 #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH0_RD_HI_ERR__SHIFT 0x0 6675 #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH1_RD_HI_ERR__SHIFT 0x1 6676 #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH2_RD_HI_ERR__SHIFT 0x2 6677 #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH3_RD_HI_ERR__SHIFT 0x3 6678 #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH4_RD_HI_ERR__SHIFT 0x4 6679 #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH5_RD_HI_ERR__SHIFT 0x5 6680 #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH6_RD_HI_ERR__SHIFT 0x6 6681 #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH7_RD_HI_ERR__SHIFT 0x7 6682 #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH0_RD_LO_ERR__SHIFT 0x8 6683 #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH1_RD_LO_ERR__SHIFT 0x9 6684 #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH2_RD_LO_ERR__SHIFT 0xa 6685 #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH3_RD_LO_ERR__SHIFT 0xb 6686 #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH4_RD_LO_ERR__SHIFT 0xc 6687 #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH5_RD_LO_ERR__SHIFT 0xd 6688 #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH6_RD_LO_ERR__SHIFT 0xe 6689 #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH7_RD_LO_ERR__SHIFT 0xf 6690 #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF0_WR_HI_ERR__SHIFT 0x10 6691 #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF1_WR_HI_ERR__SHIFT 0x11 6692 #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF2_WR_HI_ERR__SHIFT 0x12 6693 #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF3_WR_HI_ERR__SHIFT 0x13 6694 #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF4_WR_HI_ERR__SHIFT 0x14 6695 #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF5_WR_HI_ERR__SHIFT 0x15 6696 #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF6_WR_HI_ERR__SHIFT 0x16 6697 #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF7_WR_HI_ERR__SHIFT 0x17 6698 #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF0_WR_LO_ERR__SHIFT 0x18 6699 #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF1_WR_LO_ERR__SHIFT 0x19 6700 #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF2_WR_LO_ERR__SHIFT 0x1a 6701 #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF3_WR_LO_ERR__SHIFT 0x1b 6702 #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF4_WR_LO_ERR__SHIFT 0x1c 6703 #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF5_WR_LO_ERR__SHIFT 0x1d 6704 #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF6_WR_LO_ERR__SHIFT 0x1e 6705 #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF7_WR_LO_ERR__SHIFT 0x1f 6706 #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH0_RD_HI_ERR_MASK 0x00000001L 6707 #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH1_RD_HI_ERR_MASK 0x00000002L 6708 #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH2_RD_HI_ERR_MASK 0x00000004L 6709 #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH3_RD_HI_ERR_MASK 0x00000008L 6710 #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH4_RD_HI_ERR_MASK 0x00000010L 6711 #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH5_RD_HI_ERR_MASK 0x00000020L 6712 #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH6_RD_HI_ERR_MASK 0x00000040L 6713 #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH7_RD_HI_ERR_MASK 0x00000080L 6714 #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH0_RD_LO_ERR_MASK 0x00000100L 6715 #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH1_RD_LO_ERR_MASK 0x00000200L 6716 #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH2_RD_LO_ERR_MASK 0x00000400L 6717 #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH3_RD_LO_ERR_MASK 0x00000800L 6718 #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH4_RD_LO_ERR_MASK 0x00001000L 6719 #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH5_RD_LO_ERR_MASK 0x00002000L 6720 #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH6_RD_LO_ERR_MASK 0x00004000L 6721 #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH7_RD_LO_ERR_MASK 0x00008000L 6722 #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF0_WR_HI_ERR_MASK 0x00010000L 6723 #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF1_WR_HI_ERR_MASK 0x00020000L 6724 #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF2_WR_HI_ERR_MASK 0x00040000L 6725 #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF3_WR_HI_ERR_MASK 0x00080000L 6726 #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF4_WR_HI_ERR_MASK 0x00100000L 6727 #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF5_WR_HI_ERR_MASK 0x00200000L 6728 #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF6_WR_HI_ERR_MASK 0x00400000L 6729 #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF7_WR_HI_ERR_MASK 0x00800000L 6730 #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF0_WR_LO_ERR_MASK 0x01000000L 6731 #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF1_WR_LO_ERR_MASK 0x02000000L 6732 #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF2_WR_LO_ERR_MASK 0x04000000L 6733 #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF3_WR_LO_ERR_MASK 0x08000000L 6734 #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF4_WR_LO_ERR_MASK 0x10000000L 6735 #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF5_WR_LO_ERR_MASK 0x20000000L 6736 #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF6_WR_LO_ERR_MASK 0x40000000L 6737 #define JPEG_MEMCHECK_SYS_INT_ACK__OBUF7_WR_LO_ERR_MASK 0x80000000L 6738 //JPEG_MEMCHECK_SYS_INT_ACK1 6739 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC0_RD_HI_ERR__SHIFT 0x0 6740 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC1_RD_HI_ERR__SHIFT 0x1 6741 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC2_RD_HI_ERR__SHIFT 0x2 6742 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC3_RD_HI_ERR__SHIFT 0x3 6743 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC4_RD_HI_ERR__SHIFT 0x4 6744 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC5_RD_HI_ERR__SHIFT 0x5 6745 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC6_RD_HI_ERR__SHIFT 0x6 6746 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC7_RD_HI_ERR__SHIFT 0x7 6747 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC0_RD_LO_ERR__SHIFT 0x8 6748 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC1_RD_LO_ERR__SHIFT 0x9 6749 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC2_RD_LO_ERR__SHIFT 0xa 6750 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC3_RD_LO_ERR__SHIFT 0xb 6751 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC4_RD_LO_ERR__SHIFT 0xc 6752 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC5_RD_LO_ERR__SHIFT 0xd 6753 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC6_RD_LO_ERR__SHIFT 0xe 6754 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC7_RD_LO_ERR__SHIFT 0xf 6755 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC0_WR_HI_ERR__SHIFT 0x10 6756 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC1_WR_HI_ERR__SHIFT 0x11 6757 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC2_WR_HI_ERR__SHIFT 0x12 6758 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC3_WR_HI_ERR__SHIFT 0x13 6759 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC4_WR_HI_ERR__SHIFT 0x14 6760 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC5_WR_HI_ERR__SHIFT 0x15 6761 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC6_WR_HI_ERR__SHIFT 0x16 6762 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC7_WR_HI_ERR__SHIFT 0x17 6763 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC0_WR_LO_ERR__SHIFT 0x18 6764 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC1_WR_LO_ERR__SHIFT 0x19 6765 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC2_WR_LO_ERR__SHIFT 0x1a 6766 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC3_WR_LO_ERR__SHIFT 0x1b 6767 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC4_WR_LO_ERR__SHIFT 0x1c 6768 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC5_WR_LO_ERR__SHIFT 0x1d 6769 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC6_WR_LO_ERR__SHIFT 0x1e 6770 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC7_WR_LO_ERR__SHIFT 0x1f 6771 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC0_RD_HI_ERR_MASK 0x00000001L 6772 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC1_RD_HI_ERR_MASK 0x00000002L 6773 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC2_RD_HI_ERR_MASK 0x00000004L 6774 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC3_RD_HI_ERR_MASK 0x00000008L 6775 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC4_RD_HI_ERR_MASK 0x00000010L 6776 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC5_RD_HI_ERR_MASK 0x00000020L 6777 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC6_RD_HI_ERR_MASK 0x00000040L 6778 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC7_RD_HI_ERR_MASK 0x00000080L 6779 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC0_RD_LO_ERR_MASK 0x00000100L 6780 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC1_RD_LO_ERR_MASK 0x00000200L 6781 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC2_RD_LO_ERR_MASK 0x00000400L 6782 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC3_RD_LO_ERR_MASK 0x00000800L 6783 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC4_RD_LO_ERR_MASK 0x00001000L 6784 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC5_RD_LO_ERR_MASK 0x00002000L 6785 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC6_RD_LO_ERR_MASK 0x00004000L 6786 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC7_RD_LO_ERR_MASK 0x00008000L 6787 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC0_WR_HI_ERR_MASK 0x00010000L 6788 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC1_WR_HI_ERR_MASK 0x00020000L 6789 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC2_WR_HI_ERR_MASK 0x00040000L 6790 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC3_WR_HI_ERR_MASK 0x00080000L 6791 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC4_WR_HI_ERR_MASK 0x00100000L 6792 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC5_WR_HI_ERR_MASK 0x00200000L 6793 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC6_WR_HI_ERR_MASK 0x00400000L 6794 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC7_WR_HI_ERR_MASK 0x00800000L 6795 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC0_WR_LO_ERR_MASK 0x01000000L 6796 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC1_WR_LO_ERR_MASK 0x02000000L 6797 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC2_WR_LO_ERR_MASK 0x04000000L 6798 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC3_WR_LO_ERR_MASK 0x08000000L 6799 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC4_WR_LO_ERR_MASK 0x10000000L 6800 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC5_WR_LO_ERR_MASK 0x20000000L 6801 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC6_WR_LO_ERR_MASK 0x40000000L 6802 #define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC7_WR_LO_ERR_MASK 0x80000000L 6803 //JPEG_MEMCHECK_SYS_INT_ACK2 6804 #define JPEG_MEMCHECK_SYS_INT_ACK2__EJRBC_RD_HI_ERR__SHIFT 0x0 6805 #define JPEG_MEMCHECK_SYS_INT_ACK2__EJRBC_RD_LO_ERR__SHIFT 0x1 6806 #define JPEG_MEMCHECK_SYS_INT_ACK2__PELFETCH_RD_HI_ERR__SHIFT 0x2 6807 #define JPEG_MEMCHECK_SYS_INT_ACK2__PELFETCH_RD_LO_ERR__SHIFT 0x3 6808 #define JPEG_MEMCHECK_SYS_INT_ACK2__SCALAR_RD_HI_ERR__SHIFT 0x4 6809 #define JPEG_MEMCHECK_SYS_INT_ACK2__SCALAR_RD_LO_ERR__SHIFT 0x5 6810 #define JPEG_MEMCHECK_SYS_INT_ACK2__EJRBC_WR_HI_ERR__SHIFT 0x6 6811 #define JPEG_MEMCHECK_SYS_INT_ACK2__EJRBC_WR_LO_ERR__SHIFT 0x7 6812 #define JPEG_MEMCHECK_SYS_INT_ACK2__BS_WR_HI_ERR__SHIFT 0x8 6813 #define JPEG_MEMCHECK_SYS_INT_ACK2__BS_WR_LO_ERR__SHIFT 0x9 6814 #define JPEG_MEMCHECK_SYS_INT_ACK2__SCALAR_WR_HI_ERR__SHIFT 0xa 6815 #define JPEG_MEMCHECK_SYS_INT_ACK2__SCALAR_WR_LO_ERR__SHIFT 0xb 6816 #define JPEG_MEMCHECK_SYS_INT_ACK2__EJRBC_RD_HI_ERR_MASK 0x00000001L 6817 #define JPEG_MEMCHECK_SYS_INT_ACK2__EJRBC_RD_LO_ERR_MASK 0x00000002L 6818 #define JPEG_MEMCHECK_SYS_INT_ACK2__PELFETCH_RD_HI_ERR_MASK 0x00000004L 6819 #define JPEG_MEMCHECK_SYS_INT_ACK2__PELFETCH_RD_LO_ERR_MASK 0x00000008L 6820 #define JPEG_MEMCHECK_SYS_INT_ACK2__SCALAR_RD_HI_ERR_MASK 0x00000010L 6821 #define JPEG_MEMCHECK_SYS_INT_ACK2__SCALAR_RD_LO_ERR_MASK 0x00000020L 6822 #define JPEG_MEMCHECK_SYS_INT_ACK2__EJRBC_WR_HI_ERR_MASK 0x00000040L 6823 #define JPEG_MEMCHECK_SYS_INT_ACK2__EJRBC_WR_LO_ERR_MASK 0x00000080L 6824 #define JPEG_MEMCHECK_SYS_INT_ACK2__BS_WR_HI_ERR_MASK 0x00000100L 6825 #define JPEG_MEMCHECK_SYS_INT_ACK2__BS_WR_LO_ERR_MASK 0x00000200L 6826 #define JPEG_MEMCHECK_SYS_INT_ACK2__SCALAR_WR_HI_ERR_MASK 0x00000400L 6827 #define JPEG_MEMCHECK_SYS_INT_ACK2__SCALAR_WR_LO_ERR_MASK 0x00000800L 6828 //JPEG_MASTINT_EN 6829 #define JPEG_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 6830 #define JPEG_MASTINT_EN__INT_OVERRUN__SHIFT 0x4 6831 #define JPEG_MASTINT_EN__OVERRUN_RST_MASK 0x00000001L 6832 #define JPEG_MASTINT_EN__INT_OVERRUN_MASK 0x007FFFF0L 6833 //JPEG_IH_CTRL 6834 #define JPEG_IH_CTRL__IH_SOFT_RESET__SHIFT 0x0 6835 #define JPEG_IH_CTRL__IH_STALL_EN__SHIFT 0x1 6836 #define JPEG_IH_CTRL__IH_STATUS_CLEAN__SHIFT 0x2 6837 #define JPEG_IH_CTRL__IH_VMID__SHIFT 0x3 6838 #define JPEG_IH_CTRL__IH_USER_DATA__SHIFT 0x7 6839 #define JPEG_IH_CTRL__IH_RINGID__SHIFT 0x13 6840 #define JPEG_IH_CTRL__IH_SOFT_RESET_MASK 0x00000001L 6841 #define JPEG_IH_CTRL__IH_STALL_EN_MASK 0x00000002L 6842 #define JPEG_IH_CTRL__IH_STATUS_CLEAN_MASK 0x00000004L 6843 #define JPEG_IH_CTRL__IH_VMID_MASK 0x00000078L 6844 #define JPEG_IH_CTRL__IH_USER_DATA_MASK 0x0007FF80L 6845 #define JPEG_IH_CTRL__IH_RINGID_MASK 0x07F80000L 6846 //JRBBM_ARB_CTRL 6847 #define JRBBM_ARB_CTRL__DJRBC0_DROP__SHIFT 0x0 6848 #define JRBBM_ARB_CTRL__DJRBC1_DROP__SHIFT 0x1 6849 #define JRBBM_ARB_CTRL__DJRBC2_DROP__SHIFT 0x2 6850 #define JRBBM_ARB_CTRL__DJRBC3_DROP__SHIFT 0x3 6851 #define JRBBM_ARB_CTRL__DJRBC4_DROP__SHIFT 0x4 6852 #define JRBBM_ARB_CTRL__DJRBC5_DROP__SHIFT 0x5 6853 #define JRBBM_ARB_CTRL__DJRBC6_DROP__SHIFT 0x6 6854 #define JRBBM_ARB_CTRL__DJRBC7_DROP__SHIFT 0x7 6855 #define JRBBM_ARB_CTRL__EJRBC_DROP__SHIFT 0x8 6856 #define JRBBM_ARB_CTRL__SRBM_DROP__SHIFT 0x9 6857 #define JRBBM_ARB_CTRL__DJRBC0_DROP_MASK 0x00000001L 6858 #define JRBBM_ARB_CTRL__DJRBC1_DROP_MASK 0x00000002L 6859 #define JRBBM_ARB_CTRL__DJRBC2_DROP_MASK 0x00000004L 6860 #define JRBBM_ARB_CTRL__DJRBC3_DROP_MASK 0x00000008L 6861 #define JRBBM_ARB_CTRL__DJRBC4_DROP_MASK 0x00000010L 6862 #define JRBBM_ARB_CTRL__DJRBC5_DROP_MASK 0x00000020L 6863 #define JRBBM_ARB_CTRL__DJRBC6_DROP_MASK 0x00000040L 6864 #define JRBBM_ARB_CTRL__DJRBC7_DROP_MASK 0x00000080L 6865 #define JRBBM_ARB_CTRL__EJRBC_DROP_MASK 0x00000100L 6866 #define JRBBM_ARB_CTRL__SRBM_DROP_MASK 0x00000200L 6867 6868 6869 // addressBlock: aid_uvd0_uvd_jpeg_common_sclk_dec 6870 //JPEG_CGC_GATE 6871 #define JPEG_CGC_GATE__JPEG0_DEC__SHIFT 0x0 6872 #define JPEG_CGC_GATE__JPEG1_DEC__SHIFT 0x1 6873 #define JPEG_CGC_GATE__JPEG2_DEC__SHIFT 0x2 6874 #define JPEG_CGC_GATE__JPEG3_DEC__SHIFT 0x3 6875 #define JPEG_CGC_GATE__JPEG4_DEC__SHIFT 0x4 6876 #define JPEG_CGC_GATE__JPEG5_DEC__SHIFT 0x5 6877 #define JPEG_CGC_GATE__JPEG6_DEC__SHIFT 0x6 6878 #define JPEG_CGC_GATE__JPEG7_DEC__SHIFT 0x7 6879 #define JPEG_CGC_GATE__JPEG_ENC__SHIFT 0x8 6880 #define JPEG_CGC_GATE__JMCIF__SHIFT 0x9 6881 #define JPEG_CGC_GATE__JRBBM__SHIFT 0xa 6882 #define JPEG_CGC_GATE__JPEG0_DEC_MASK 0x00000001L 6883 #define JPEG_CGC_GATE__JPEG1_DEC_MASK 0x00000002L 6884 #define JPEG_CGC_GATE__JPEG2_DEC_MASK 0x00000004L 6885 #define JPEG_CGC_GATE__JPEG3_DEC_MASK 0x00000008L 6886 #define JPEG_CGC_GATE__JPEG4_DEC_MASK 0x00000010L 6887 #define JPEG_CGC_GATE__JPEG5_DEC_MASK 0x00000020L 6888 #define JPEG_CGC_GATE__JPEG6_DEC_MASK 0x00000040L 6889 #define JPEG_CGC_GATE__JPEG7_DEC_MASK 0x00000080L 6890 #define JPEG_CGC_GATE__JPEG_ENC_MASK 0x00000100L 6891 #define JPEG_CGC_GATE__JMCIF_MASK 0x00000200L 6892 #define JPEG_CGC_GATE__JRBBM_MASK 0x00000400L 6893 //JPEG_CGC_CTRL 6894 #define JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 6895 #define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x1 6896 #define JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x5 6897 #define JPEG_CGC_CTRL__JPEG0_DEC_MODE__SHIFT 0x10 6898 #define JPEG_CGC_CTRL__JPEG1_DEC_MODE__SHIFT 0x11 6899 #define JPEG_CGC_CTRL__JPEG2_DEC_MODE__SHIFT 0x12 6900 #define JPEG_CGC_CTRL__JPEG3_DEC_MODE__SHIFT 0x13 6901 #define JPEG_CGC_CTRL__JPEG4_DEC_MODE__SHIFT 0x14 6902 #define JPEG_CGC_CTRL__JPEG5_DEC_MODE__SHIFT 0x15 6903 #define JPEG_CGC_CTRL__JPEG6_DEC_MODE__SHIFT 0x16 6904 #define JPEG_CGC_CTRL__JPEG7_DEC_MODE__SHIFT 0x17 6905 #define JPEG_CGC_CTRL__JPEG_ENC_MODE__SHIFT 0x18 6906 #define JPEG_CGC_CTRL__JMCIF_MODE__SHIFT 0x19 6907 #define JPEG_CGC_CTRL__JRBBM_MODE__SHIFT 0x1a 6908 #define JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L 6909 #define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000001EL 6910 #define JPEG_CGC_CTRL__CLK_OFF_DELAY_MASK 0x00001FE0L 6911 #define JPEG_CGC_CTRL__JPEG0_DEC_MODE_MASK 0x00010000L 6912 #define JPEG_CGC_CTRL__JPEG1_DEC_MODE_MASK 0x00020000L 6913 #define JPEG_CGC_CTRL__JPEG2_DEC_MODE_MASK 0x00040000L 6914 #define JPEG_CGC_CTRL__JPEG3_DEC_MODE_MASK 0x00080000L 6915 #define JPEG_CGC_CTRL__JPEG4_DEC_MODE_MASK 0x00100000L 6916 #define JPEG_CGC_CTRL__JPEG5_DEC_MODE_MASK 0x00200000L 6917 #define JPEG_CGC_CTRL__JPEG6_DEC_MODE_MASK 0x00400000L 6918 #define JPEG_CGC_CTRL__JPEG7_DEC_MODE_MASK 0x00800000L 6919 #define JPEG_CGC_CTRL__JPEG_ENC_MODE_MASK 0x01000000L 6920 #define JPEG_CGC_CTRL__JMCIF_MODE_MASK 0x02000000L 6921 #define JPEG_CGC_CTRL__JRBBM_MODE_MASK 0x04000000L 6922 //JPEG_CGC_STATUS 6923 #define JPEG_CGC_STATUS__JPEG0_DEC_VCLK_ACTIVE__SHIFT 0x0 6924 #define JPEG_CGC_STATUS__JPEG0_DEC_SCLK_ACTIVE__SHIFT 0x1 6925 #define JPEG_CGC_STATUS__JPEG1_DEC_VCLK_ACTIVE__SHIFT 0x2 6926 #define JPEG_CGC_STATUS__JPEG1_DEC_SCLK_ACTIVE__SHIFT 0x3 6927 #define JPEG_CGC_STATUS__JPEG2_DEC_VCLK_ACTIVE__SHIFT 0x4 6928 #define JPEG_CGC_STATUS__JPEG2_DEC_SCLK_ACTIVE__SHIFT 0x5 6929 #define JPEG_CGC_STATUS__JPEG3_DEC_VCLK_ACTIVE__SHIFT 0x6 6930 #define JPEG_CGC_STATUS__JPEG3_DEC_SCLK_ACTIVE__SHIFT 0x7 6931 #define JPEG_CGC_STATUS__JPEG4_DEC_VCLK_ACTIVE__SHIFT 0x8 6932 #define JPEG_CGC_STATUS__JPEG4_DEC_SCLK_ACTIVE__SHIFT 0x9 6933 #define JPEG_CGC_STATUS__JPEG5_DEC_VCLK_ACTIVE__SHIFT 0xa 6934 #define JPEG_CGC_STATUS__JPEG5_DEC_SCLK_ACTIVE__SHIFT 0xb 6935 #define JPEG_CGC_STATUS__JPEG6_DEC_VCLK_ACTIVE__SHIFT 0xc 6936 #define JPEG_CGC_STATUS__JPEG6_DEC_SCLK_ACTIVE__SHIFT 0xd 6937 #define JPEG_CGC_STATUS__JPEG7_DEC_VCLK_ACTIVE__SHIFT 0xe 6938 #define JPEG_CGC_STATUS__JPEG7_DEC_SCLK_ACTIVE__SHIFT 0xf 6939 #define JPEG_CGC_STATUS__JPEG_ENC_VCLK_ACTIVE__SHIFT 0x10 6940 #define JPEG_CGC_STATUS__JPEG_ENC_SCLK_ACTIVE__SHIFT 0x11 6941 #define JPEG_CGC_STATUS__JMCIF_SCLK_ACTIVE__SHIFT 0x12 6942 #define JPEG_CGC_STATUS__JRBBM_VCLK_ACTIVE__SHIFT 0x13 6943 #define JPEG_CGC_STATUS__JRBBM_SCLK_ACTIVE__SHIFT 0x14 6944 #define JPEG_CGC_STATUS__JPEG0_DEC_VCLK_ACTIVE_MASK 0x00000001L 6945 #define JPEG_CGC_STATUS__JPEG0_DEC_SCLK_ACTIVE_MASK 0x00000002L 6946 #define JPEG_CGC_STATUS__JPEG1_DEC_VCLK_ACTIVE_MASK 0x00000004L 6947 #define JPEG_CGC_STATUS__JPEG1_DEC_SCLK_ACTIVE_MASK 0x00000008L 6948 #define JPEG_CGC_STATUS__JPEG2_DEC_VCLK_ACTIVE_MASK 0x00000010L 6949 #define JPEG_CGC_STATUS__JPEG2_DEC_SCLK_ACTIVE_MASK 0x00000020L 6950 #define JPEG_CGC_STATUS__JPEG3_DEC_VCLK_ACTIVE_MASK 0x00000040L 6951 #define JPEG_CGC_STATUS__JPEG3_DEC_SCLK_ACTIVE_MASK 0x00000080L 6952 #define JPEG_CGC_STATUS__JPEG4_DEC_VCLK_ACTIVE_MASK 0x00000100L 6953 #define JPEG_CGC_STATUS__JPEG4_DEC_SCLK_ACTIVE_MASK 0x00000200L 6954 #define JPEG_CGC_STATUS__JPEG5_DEC_VCLK_ACTIVE_MASK 0x00000400L 6955 #define JPEG_CGC_STATUS__JPEG5_DEC_SCLK_ACTIVE_MASK 0x00000800L 6956 #define JPEG_CGC_STATUS__JPEG6_DEC_VCLK_ACTIVE_MASK 0x00001000L 6957 #define JPEG_CGC_STATUS__JPEG6_DEC_SCLK_ACTIVE_MASK 0x00002000L 6958 #define JPEG_CGC_STATUS__JPEG7_DEC_VCLK_ACTIVE_MASK 0x00004000L 6959 #define JPEG_CGC_STATUS__JPEG7_DEC_SCLK_ACTIVE_MASK 0x00008000L 6960 #define JPEG_CGC_STATUS__JPEG_ENC_VCLK_ACTIVE_MASK 0x00010000L 6961 #define JPEG_CGC_STATUS__JPEG_ENC_SCLK_ACTIVE_MASK 0x00020000L 6962 #define JPEG_CGC_STATUS__JMCIF_SCLK_ACTIVE_MASK 0x00040000L 6963 #define JPEG_CGC_STATUS__JRBBM_VCLK_ACTIVE_MASK 0x00080000L 6964 #define JPEG_CGC_STATUS__JRBBM_SCLK_ACTIVE_MASK 0x00100000L 6965 //JPEG_COMN_CGC_MEM_CTRL 6966 #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_LS_EN__SHIFT 0x0 6967 #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_DS_EN__SHIFT 0x1 6968 #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_SD_EN__SHIFT 0x2 6969 #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_LS_SW_EN__SHIFT 0x3 6970 #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_LS_EN_MASK 0x00000001L 6971 #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_DS_EN_MASK 0x00000002L 6972 #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_SD_EN_MASK 0x00000004L 6973 #define JPEG_COMN_CGC_MEM_CTRL__JMCIF_LS_SW_EN_MASK 0x00000008L 6974 //JPEG_DEC_CGC_MEM_CTRL 6975 #define JPEG_DEC_CGC_MEM_CTRL__JPEG0_DEC_LS_EN__SHIFT 0x0 6976 #define JPEG_DEC_CGC_MEM_CTRL__JPEG0_DEC_DS_EN__SHIFT 0x1 6977 #define JPEG_DEC_CGC_MEM_CTRL__JPEG0_DEC_SD_EN__SHIFT 0x2 6978 #define JPEG_DEC_CGC_MEM_CTRL__JPEG0_DEC_LS_SW_EN__SHIFT 0x3 6979 #define JPEG_DEC_CGC_MEM_CTRL__JPEG1_DEC_LS_EN__SHIFT 0x4 6980 #define JPEG_DEC_CGC_MEM_CTRL__JPEG1_DEC_DS_EN__SHIFT 0x5 6981 #define JPEG_DEC_CGC_MEM_CTRL__JPEG1_DEC_SD_EN__SHIFT 0x6 6982 #define JPEG_DEC_CGC_MEM_CTRL__JPEG1_DEC_LS_SW_EN__SHIFT 0x7 6983 #define JPEG_DEC_CGC_MEM_CTRL__JPEG2_DEC_LS_EN__SHIFT 0x8 6984 #define JPEG_DEC_CGC_MEM_CTRL__JPEG2_DEC_DS_EN__SHIFT 0x9 6985 #define JPEG_DEC_CGC_MEM_CTRL__JPEG2_DEC_SD_EN__SHIFT 0xa 6986 #define JPEG_DEC_CGC_MEM_CTRL__JPEG2_DEC_LS_SW_EN__SHIFT 0xb 6987 #define JPEG_DEC_CGC_MEM_CTRL__JPEG3_DEC_LS_EN__SHIFT 0xc 6988 #define JPEG_DEC_CGC_MEM_CTRL__JPEG3_DEC_DS_EN__SHIFT 0xd 6989 #define JPEG_DEC_CGC_MEM_CTRL__JPEG3_DEC_SD_EN__SHIFT 0xe 6990 #define JPEG_DEC_CGC_MEM_CTRL__JPEG3_DEC_LS_SW_EN__SHIFT 0xf 6991 #define JPEG_DEC_CGC_MEM_CTRL__JPEG4_DEC_LS_EN__SHIFT 0x10 6992 #define JPEG_DEC_CGC_MEM_CTRL__JPEG4_DEC_DS_EN__SHIFT 0x11 6993 #define JPEG_DEC_CGC_MEM_CTRL__JPEG4_DEC_SD_EN__SHIFT 0x12 6994 #define JPEG_DEC_CGC_MEM_CTRL__JPEG4_DEC_LS_SW_EN__SHIFT 0x13 6995 #define JPEG_DEC_CGC_MEM_CTRL__JPEG5_DEC_LS_EN__SHIFT 0x14 6996 #define JPEG_DEC_CGC_MEM_CTRL__JPEG5_DEC_DS_EN__SHIFT 0x15 6997 #define JPEG_DEC_CGC_MEM_CTRL__JPEG5_DEC_SD_EN__SHIFT 0x16 6998 #define JPEG_DEC_CGC_MEM_CTRL__JPEG5_DEC_LS_SW_EN__SHIFT 0x17 6999 #define JPEG_DEC_CGC_MEM_CTRL__JPEG6_DEC_LS_EN__SHIFT 0x18 7000 #define JPEG_DEC_CGC_MEM_CTRL__JPEG6_DEC_DS_EN__SHIFT 0x19 7001 #define JPEG_DEC_CGC_MEM_CTRL__JPEG6_DEC_SD_EN__SHIFT 0x1a 7002 #define JPEG_DEC_CGC_MEM_CTRL__JPEG6_DEC_LS_SW_EN__SHIFT 0x1b 7003 #define JPEG_DEC_CGC_MEM_CTRL__JPEG7_DEC_LS_EN__SHIFT 0x1c 7004 #define JPEG_DEC_CGC_MEM_CTRL__JPEG7_DEC_DS_EN__SHIFT 0x1d 7005 #define JPEG_DEC_CGC_MEM_CTRL__JPEG7_DEC_SD_EN__SHIFT 0x1e 7006 #define JPEG_DEC_CGC_MEM_CTRL__JPEG7_DEC_LS_SW_EN__SHIFT 0x1f 7007 #define JPEG_DEC_CGC_MEM_CTRL__JPEG0_DEC_LS_EN_MASK 0x00000001L 7008 #define JPEG_DEC_CGC_MEM_CTRL__JPEG0_DEC_DS_EN_MASK 0x00000002L 7009 #define JPEG_DEC_CGC_MEM_CTRL__JPEG0_DEC_SD_EN_MASK 0x00000004L 7010 #define JPEG_DEC_CGC_MEM_CTRL__JPEG0_DEC_LS_SW_EN_MASK 0x00000008L 7011 #define JPEG_DEC_CGC_MEM_CTRL__JPEG1_DEC_LS_EN_MASK 0x00000010L 7012 #define JPEG_DEC_CGC_MEM_CTRL__JPEG1_DEC_DS_EN_MASK 0x00000020L 7013 #define JPEG_DEC_CGC_MEM_CTRL__JPEG1_DEC_SD_EN_MASK 0x00000040L 7014 #define JPEG_DEC_CGC_MEM_CTRL__JPEG1_DEC_LS_SW_EN_MASK 0x00000080L 7015 #define JPEG_DEC_CGC_MEM_CTRL__JPEG2_DEC_LS_EN_MASK 0x00000100L 7016 #define JPEG_DEC_CGC_MEM_CTRL__JPEG2_DEC_DS_EN_MASK 0x00000200L 7017 #define JPEG_DEC_CGC_MEM_CTRL__JPEG2_DEC_SD_EN_MASK 0x00000400L 7018 #define JPEG_DEC_CGC_MEM_CTRL__JPEG2_DEC_LS_SW_EN_MASK 0x00000800L 7019 #define JPEG_DEC_CGC_MEM_CTRL__JPEG3_DEC_LS_EN_MASK 0x00001000L 7020 #define JPEG_DEC_CGC_MEM_CTRL__JPEG3_DEC_DS_EN_MASK 0x00002000L 7021 #define JPEG_DEC_CGC_MEM_CTRL__JPEG3_DEC_SD_EN_MASK 0x00004000L 7022 #define JPEG_DEC_CGC_MEM_CTRL__JPEG3_DEC_LS_SW_EN_MASK 0x00008000L 7023 #define JPEG_DEC_CGC_MEM_CTRL__JPEG4_DEC_LS_EN_MASK 0x00010000L 7024 #define JPEG_DEC_CGC_MEM_CTRL__JPEG4_DEC_DS_EN_MASK 0x00020000L 7025 #define JPEG_DEC_CGC_MEM_CTRL__JPEG4_DEC_SD_EN_MASK 0x00040000L 7026 #define JPEG_DEC_CGC_MEM_CTRL__JPEG4_DEC_LS_SW_EN_MASK 0x00080000L 7027 #define JPEG_DEC_CGC_MEM_CTRL__JPEG5_DEC_LS_EN_MASK 0x00100000L 7028 #define JPEG_DEC_CGC_MEM_CTRL__JPEG5_DEC_DS_EN_MASK 0x00200000L 7029 #define JPEG_DEC_CGC_MEM_CTRL__JPEG5_DEC_SD_EN_MASK 0x00400000L 7030 #define JPEG_DEC_CGC_MEM_CTRL__JPEG5_DEC_LS_SW_EN_MASK 0x00800000L 7031 #define JPEG_DEC_CGC_MEM_CTRL__JPEG6_DEC_LS_EN_MASK 0x01000000L 7032 #define JPEG_DEC_CGC_MEM_CTRL__JPEG6_DEC_DS_EN_MASK 0x02000000L 7033 #define JPEG_DEC_CGC_MEM_CTRL__JPEG6_DEC_SD_EN_MASK 0x04000000L 7034 #define JPEG_DEC_CGC_MEM_CTRL__JPEG6_DEC_LS_SW_EN_MASK 0x08000000L 7035 #define JPEG_DEC_CGC_MEM_CTRL__JPEG7_DEC_LS_EN_MASK 0x10000000L 7036 #define JPEG_DEC_CGC_MEM_CTRL__JPEG7_DEC_DS_EN_MASK 0x20000000L 7037 #define JPEG_DEC_CGC_MEM_CTRL__JPEG7_DEC_SD_EN_MASK 0x40000000L 7038 #define JPEG_DEC_CGC_MEM_CTRL__JPEG7_DEC_LS_SW_EN_MASK 0x80000000L 7039 //JPEG_ENC_CGC_MEM_CTRL 7040 #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_LS_EN__SHIFT 0x0 7041 #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_DS_EN__SHIFT 0x1 7042 #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_SD_EN__SHIFT 0x2 7043 #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_LS_SW_EN__SHIFT 0x3 7044 #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_LS_EN_MASK 0x00000001L 7045 #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_DS_EN_MASK 0x00000002L 7046 #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_SD_EN_MASK 0x00000004L 7047 #define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_LS_SW_EN_MASK 0x00000008L 7048 //JPEG_PERF_BANK_CONF 7049 #define JPEG_PERF_BANK_CONF__RESET__SHIFT 0x0 7050 #define JPEG_PERF_BANK_CONF__PEEK__SHIFT 0x8 7051 #define JPEG_PERF_BANK_CONF__CONCATENATE__SHIFT 0x10 7052 #define JPEG_PERF_BANK_CONF__CORE_SEL__SHIFT 0x15 7053 #define JPEG_PERF_BANK_CONF__RESET_MASK 0x0000000FL 7054 #define JPEG_PERF_BANK_CONF__PEEK_MASK 0x00000F00L 7055 #define JPEG_PERF_BANK_CONF__CONCATENATE_MASK 0x00030000L 7056 #define JPEG_PERF_BANK_CONF__CORE_SEL_MASK 0x00E00000L 7057 //JPEG_PERF_BANK_EVENT_SEL 7058 #define JPEG_PERF_BANK_EVENT_SEL__SEL0__SHIFT 0x0 7059 #define JPEG_PERF_BANK_EVENT_SEL__SEL1__SHIFT 0x8 7060 #define JPEG_PERF_BANK_EVENT_SEL__SEL2__SHIFT 0x10 7061 #define JPEG_PERF_BANK_EVENT_SEL__SEL3__SHIFT 0x18 7062 #define JPEG_PERF_BANK_EVENT_SEL__SEL0_MASK 0x000000FFL 7063 #define JPEG_PERF_BANK_EVENT_SEL__SEL1_MASK 0x0000FF00L 7064 #define JPEG_PERF_BANK_EVENT_SEL__SEL2_MASK 0x00FF0000L 7065 #define JPEG_PERF_BANK_EVENT_SEL__SEL3_MASK 0xFF000000L 7066 //JPEG_PERF_BANK_COUNT0 7067 #define JPEG_PERF_BANK_COUNT0__COUNT__SHIFT 0x0 7068 #define JPEG_PERF_BANK_COUNT0__COUNT_MASK 0xFFFFFFFFL 7069 //JPEG_PERF_BANK_COUNT1 7070 #define JPEG_PERF_BANK_COUNT1__COUNT__SHIFT 0x0 7071 #define JPEG_PERF_BANK_COUNT1__COUNT_MASK 0xFFFFFFFFL 7072 //JPEG_PERF_BANK_COUNT2 7073 #define JPEG_PERF_BANK_COUNT2__COUNT__SHIFT 0x0 7074 #define JPEG_PERF_BANK_COUNT2__COUNT_MASK 0xFFFFFFFFL 7075 //JPEG_PERF_BANK_COUNT3 7076 #define JPEG_PERF_BANK_COUNT3__COUNT__SHIFT 0x0 7077 #define JPEG_PERF_BANK_COUNT3__COUNT_MASK 0xFFFFFFFFL 7078 7079 7080 // addressBlock: aid_uvd0_uvd_pg_dec 7081 //UVD_PGFSM_CONFIG 7082 #define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 0x0 7083 #define UVD_PGFSM_CONFIG__UVDS_PWR_CONFIG__SHIFT 0x2 7084 #define UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 0x4 7085 #define UVD_PGFSM_CONFIG__UVDTC_PWR_CONFIG__SHIFT 0x6 7086 #define UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 0x8 7087 #define UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG__SHIFT 0xa 7088 #define UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 0xc 7089 #define UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 0xe 7090 #define UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 0x10 7091 #define UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 0x12 7092 #define UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 0x14 7093 #define UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT 0x16 7094 #define UVD_PGFSM_CONFIG__UVDTB_PWR_CONFIG__SHIFT 0x18 7095 #define UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 0x1a 7096 #define UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT 0x1c 7097 #define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG_MASK 0x00000003L 7098 #define UVD_PGFSM_CONFIG__UVDS_PWR_CONFIG_MASK 0x0000000CL 7099 #define UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG_MASK 0x00000030L 7100 #define UVD_PGFSM_CONFIG__UVDTC_PWR_CONFIG_MASK 0x000000C0L 7101 #define UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG_MASK 0x00000300L 7102 #define UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG_MASK 0x00000C00L 7103 #define UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG_MASK 0x00003000L 7104 #define UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG_MASK 0x0000C000L 7105 #define UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG_MASK 0x00030000L 7106 #define UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG_MASK 0x000C0000L 7107 #define UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG_MASK 0x00300000L 7108 #define UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG_MASK 0x00C00000L 7109 #define UVD_PGFSM_CONFIG__UVDTB_PWR_CONFIG_MASK 0x03000000L 7110 #define UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG_MASK 0x0C000000L 7111 #define UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG_MASK 0x30000000L 7112 //UVD_PGFSM_STATUS 7113 #define UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 0x0 7114 #define UVD_PGFSM_STATUS__UVDS_PWR_STATUS__SHIFT 0x2 7115 #define UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 0x4 7116 #define UVD_PGFSM_STATUS__UVDTC_PWR_STATUS__SHIFT 0x6 7117 #define UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 0x8 7118 #define UVD_PGFSM_STATUS__UVDTA_PWR_STATUS__SHIFT 0xa 7119 #define UVD_PGFSM_STATUS__UVDLM_PWR_STATUS__SHIFT 0xc 7120 #define UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 0xe 7121 #define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 0x10 7122 #define UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 0x12 7123 #define UVD_PGFSM_STATUS__UVDAB_PWR_STATUS__SHIFT 0x14 7124 #define UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT 0x16 7125 #define UVD_PGFSM_STATUS__UVDTB_PWR_STATUS__SHIFT 0x18 7126 #define UVD_PGFSM_STATUS__UVDNA_PWR_STATUS__SHIFT 0x1a 7127 #define UVD_PGFSM_STATUS__UVDNB_PWR_STATUS__SHIFT 0x1c 7128 #define UVD_PGFSM_STATUS__UVDM_PWR_STATUS_MASK 0x00000003L 7129 #define UVD_PGFSM_STATUS__UVDS_PWR_STATUS_MASK 0x0000000CL 7130 #define UVD_PGFSM_STATUS__UVDF_PWR_STATUS_MASK 0x00000030L 7131 #define UVD_PGFSM_STATUS__UVDTC_PWR_STATUS_MASK 0x000000C0L 7132 #define UVD_PGFSM_STATUS__UVDB_PWR_STATUS_MASK 0x00000300L 7133 #define UVD_PGFSM_STATUS__UVDTA_PWR_STATUS_MASK 0x00000C00L 7134 #define UVD_PGFSM_STATUS__UVDLM_PWR_STATUS_MASK 0x00003000L 7135 #define UVD_PGFSM_STATUS__UVDTD_PWR_STATUS_MASK 0x0000C000L 7136 #define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS_MASK 0x00030000L 7137 #define UVD_PGFSM_STATUS__UVDE_PWR_STATUS_MASK 0x000C0000L 7138 #define UVD_PGFSM_STATUS__UVDAB_PWR_STATUS_MASK 0x00300000L 7139 #define UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK 0x00C00000L 7140 #define UVD_PGFSM_STATUS__UVDTB_PWR_STATUS_MASK 0x03000000L 7141 #define UVD_PGFSM_STATUS__UVDNA_PWR_STATUS_MASK 0x0C000000L 7142 #define UVD_PGFSM_STATUS__UVDNB_PWR_STATUS_MASK 0x30000000L 7143 //UVD_POWER_STATUS 7144 #define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT 0x0 7145 #define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT 0x2 7146 #define UVD_POWER_STATUS__UVD_CG_MODE__SHIFT 0x4 7147 #define UVD_POWER_STATUS__UVD_PG_EN__SHIFT 0x8 7148 #define UVD_POWER_STATUS__RBC_SNOOP_DIS__SHIFT 0x9 7149 #define UVD_POWER_STATUS__SW_RB_SNOOP_DIS__SHIFT 0xb 7150 #define UVD_POWER_STATUS__STALL_DPG_POWER_UP__SHIFT 0x1f 7151 #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x00000003L 7152 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x00000004L 7153 #define UVD_POWER_STATUS__UVD_CG_MODE_MASK 0x00000030L 7154 #define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x00000100L 7155 #define UVD_POWER_STATUS__RBC_SNOOP_DIS_MASK 0x00000200L 7156 #define UVD_POWER_STATUS__SW_RB_SNOOP_DIS_MASK 0x00000800L 7157 #define UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK 0x80000000L 7158 //UVD_JPEG_POWER_STATUS 7159 #define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS__SHIFT 0x0 7160 #define UVD_JPEG_POWER_STATUS__JPEG_PG_MODE__SHIFT 0x4 7161 #define UVD_JPEG_POWER_STATUS__JRBC_DEC_SNOOP_DIS__SHIFT 0x8 7162 #define UVD_JPEG_POWER_STATUS__JRBC_ENC_SNOOP_DIS__SHIFT 0x9 7163 #define UVD_JPEG_POWER_STATUS__STALL_JDPG_POWER_UP__SHIFT 0x1f 7164 #define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK 0x00000001L 7165 #define UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK 0x00000010L 7166 #define UVD_JPEG_POWER_STATUS__JRBC_DEC_SNOOP_DIS_MASK 0x00000100L 7167 #define UVD_JPEG_POWER_STATUS__JRBC_ENC_SNOOP_DIS_MASK 0x00000200L 7168 #define UVD_JPEG_POWER_STATUS__STALL_JDPG_POWER_UP_MASK 0x80000000L 7169 //UVD_MC_DJPEG_RD_SPACE 7170 #define UVD_MC_DJPEG_RD_SPACE__DJPEG_RD_SPACE__SHIFT 0x0 7171 #define UVD_MC_DJPEG_RD_SPACE__DJPEG_RD_SPACE_MASK 0x0003FFFFL 7172 //UVD_MC_DJPEG_WR_SPACE 7173 #define UVD_MC_DJPEG_WR_SPACE__DJPEG_WR_SPACE__SHIFT 0x0 7174 #define UVD_MC_DJPEG_WR_SPACE__DJPEG_WR_SPACE_MASK 0x0003FFFFL 7175 //UVD_MC_EJPEG_RD_SPACE 7176 #define UVD_MC_EJPEG_RD_SPACE__EJPEG_RD_SPACE__SHIFT 0x0 7177 #define UVD_MC_EJPEG_RD_SPACE__EJPEG_RD_SPACE_MASK 0x0003FFFFL 7178 //UVD_MC_EJPEG_WR_SPACE 7179 #define UVD_MC_EJPEG_WR_SPACE__EJPEG_WR_SPACE__SHIFT 0x0 7180 #define UVD_MC_EJPEG_WR_SPACE__EJPEG_WR_SPACE_MASK 0x0003FFFFL 7181 //UVD_PG_IND_INDEX 7182 #define UVD_PG_IND_INDEX__INDEX__SHIFT 0x0 7183 #define UVD_PG_IND_INDEX__INDEX_MASK 0x0000003FL 7184 //UVD_PG_IND_DATA 7185 #define UVD_PG_IND_DATA__DATA__SHIFT 0x0 7186 #define UVD_PG_IND_DATA__DATA_MASK 0xFFFFFFFFL 7187 //CC_UVD_HARVESTING 7188 #define CC_UVD_HARVESTING__MMSCH_DISABLE__SHIFT 0x0 7189 #define CC_UVD_HARVESTING__UVD_DISABLE__SHIFT 0x1 7190 #define CC_UVD_HARVESTING__MMSCH_DISABLE_MASK 0x00000001L 7191 #define CC_UVD_HARVESTING__UVD_DISABLE_MASK 0x00000002L 7192 //UVD_DPG_LMA_CTL 7193 #define UVD_DPG_LMA_CTL__READ_WRITE__SHIFT 0x0 7194 #define UVD_DPG_LMA_CTL__MASK_EN__SHIFT 0x1 7195 #define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT__SHIFT 0x2 7196 #define UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT 0x4 7197 #define UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT 0x10 7198 #define UVD_DPG_LMA_CTL__READ_WRITE_MASK 0x00000001L 7199 #define UVD_DPG_LMA_CTL__MASK_EN_MASK 0x00000002L 7200 #define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT_MASK 0x00000004L 7201 #define UVD_DPG_LMA_CTL__SRAM_SEL_MASK 0x00000010L 7202 #define UVD_DPG_LMA_CTL__READ_WRITE_ADDR_MASK 0xFFFF0000L 7203 //UVD_DPG_LMA_DATA 7204 #define UVD_DPG_LMA_DATA__LMA_DATA__SHIFT 0x0 7205 #define UVD_DPG_LMA_DATA__LMA_DATA_MASK 0xFFFFFFFFL 7206 //UVD_DPG_LMA_MASK 7207 #define UVD_DPG_LMA_MASK__LMA_MASK__SHIFT 0x0 7208 #define UVD_DPG_LMA_MASK__LMA_MASK_MASK 0xFFFFFFFFL 7209 //UVD_DPG_PAUSE 7210 #define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ__SHIFT 0x0 7211 #define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK__SHIFT 0x1 7212 #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ__SHIFT 0x2 7213 #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK__SHIFT 0x3 7214 #define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK 0x00000001L 7215 #define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK 0x00000002L 7216 #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK 0x00000004L 7217 #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK 0x00000008L 7218 //UVD_SCRATCH1 7219 #define UVD_SCRATCH1__SCRATCH1_DATA__SHIFT 0x0 7220 #define UVD_SCRATCH1__SCRATCH1_DATA_MASK 0xFFFFFFFFL 7221 //UVD_SCRATCH2 7222 #define UVD_SCRATCH2__SCRATCH2_DATA__SHIFT 0x0 7223 #define UVD_SCRATCH2__SCRATCH2_DATA_MASK 0xFFFFFFFFL 7224 //UVD_SCRATCH3 7225 #define UVD_SCRATCH3__SCRATCH3_DATA__SHIFT 0x0 7226 #define UVD_SCRATCH3__SCRATCH3_DATA_MASK 0xFFFFFFFFL 7227 //UVD_SCRATCH4 7228 #define UVD_SCRATCH4__SCRATCH4_DATA__SHIFT 0x0 7229 #define UVD_SCRATCH4__SCRATCH4_DATA_MASK 0xFFFFFFFFL 7230 //UVD_SCRATCH5 7231 #define UVD_SCRATCH5__SCRATCH5_DATA__SHIFT 0x0 7232 #define UVD_SCRATCH5__SCRATCH5_DATA_MASK 0xFFFFFFFFL 7233 //UVD_SCRATCH6 7234 #define UVD_SCRATCH6__SCRATCH6_DATA__SHIFT 0x0 7235 #define UVD_SCRATCH6__SCRATCH6_DATA_MASK 0xFFFFFFFFL 7236 //UVD_SCRATCH7 7237 #define UVD_SCRATCH7__SCRATCH7_DATA__SHIFT 0x0 7238 #define UVD_SCRATCH7__SCRATCH7_DATA_MASK 0xFFFFFFFFL 7239 //UVD_SCRATCH8 7240 #define UVD_SCRATCH8__SCRATCH8_DATA__SHIFT 0x0 7241 #define UVD_SCRATCH8__SCRATCH8_DATA_MASK 0xFFFFFFFFL 7242 //UVD_SCRATCH9 7243 #define UVD_SCRATCH9__SCRATCH9_DATA__SHIFT 0x0 7244 #define UVD_SCRATCH9__SCRATCH9_DATA_MASK 0xFFFFFFFFL 7245 //UVD_SCRATCH10 7246 #define UVD_SCRATCH10__SCRATCH10_DATA__SHIFT 0x0 7247 #define UVD_SCRATCH10__SCRATCH10_DATA_MASK 0xFFFFFFFFL 7248 //UVD_SCRATCH11 7249 #define UVD_SCRATCH11__SCRATCH11_DATA__SHIFT 0x0 7250 #define UVD_SCRATCH11__SCRATCH11_DATA_MASK 0xFFFFFFFFL 7251 //UVD_SCRATCH12 7252 #define UVD_SCRATCH12__SCRATCH12_DATA__SHIFT 0x0 7253 #define UVD_SCRATCH12__SCRATCH12_DATA_MASK 0xFFFFFFFFL 7254 //UVD_SCRATCH13 7255 #define UVD_SCRATCH13__SCRATCH13_DATA__SHIFT 0x0 7256 #define UVD_SCRATCH13__SCRATCH13_DATA_MASK 0xFFFFFFFFL 7257 //UVD_SCRATCH14 7258 #define UVD_SCRATCH14__SCRATCH14_DATA__SHIFT 0x0 7259 #define UVD_SCRATCH14__SCRATCH14_DATA_MASK 0xFFFFFFFFL 7260 //UVD_FREE_COUNTER_REG 7261 #define UVD_FREE_COUNTER_REG__FREE_COUNTER__SHIFT 0x0 7262 #define UVD_FREE_COUNTER_REG__FREE_COUNTER_MASK 0xFFFFFFFFL 7263 //UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW 7264 #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 7265 #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 7266 //UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH 7267 #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 7268 #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 7269 //UVD_DPG_VCPU_CACHE_OFFSET0 7270 #define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 7271 #define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x01FFFFFFL 7272 //UVD_DPG_LMI_VCPU_CACHE_VMID 7273 #define UVD_DPG_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID__SHIFT 0x0 7274 #define UVD_DPG_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID_MASK 0x0000000FL 7275 //UVD_REG_FILTER_EN 7276 #define UVD_REG_FILTER_EN__UVD_REG_FILTER_EN__SHIFT 0x0 7277 #define UVD_REG_FILTER_EN__MMSCH_HI_PRIV__SHIFT 0x1 7278 #define UVD_REG_FILTER_EN__VIDEO_PRIV_EN__SHIFT 0x2 7279 #define UVD_REG_FILTER_EN__JPEG_PRIV_EN__SHIFT 0x3 7280 #define UVD_REG_FILTER_EN__UVD_REG_FILTER_EN_MASK 0x00000001L 7281 #define UVD_REG_FILTER_EN__MMSCH_HI_PRIV_MASK 0x00000002L 7282 #define UVD_REG_FILTER_EN__VIDEO_PRIV_EN_MASK 0x00000004L 7283 #define UVD_REG_FILTER_EN__JPEG_PRIV_EN_MASK 0x00000008L 7284 //UVD_SECURITY_REG_VIO_REPORT 7285 #define UVD_SECURITY_REG_VIO_REPORT__HOST_REG_VIO__SHIFT 0x0 7286 #define UVD_SECURITY_REG_VIO_REPORT__VCPU_REG_VIO__SHIFT 0x1 7287 #define UVD_SECURITY_REG_VIO_REPORT__VIDEO_REG_VIO__SHIFT 0x2 7288 #define UVD_SECURITY_REG_VIO_REPORT__DPG_REG_VIO__SHIFT 0x3 7289 #define UVD_SECURITY_REG_VIO_REPORT__JPEG_REG_VIO__SHIFT 0x4 7290 #define UVD_SECURITY_REG_VIO_REPORT__JDPG_REG_VIO__SHIFT 0x5 7291 #define UVD_SECURITY_REG_VIO_REPORT__HOST_REG_VIO_MASK 0x00000001L 7292 #define UVD_SECURITY_REG_VIO_REPORT__VCPU_REG_VIO_MASK 0x00000002L 7293 #define UVD_SECURITY_REG_VIO_REPORT__VIDEO_REG_VIO_MASK 0x00000004L 7294 #define UVD_SECURITY_REG_VIO_REPORT__DPG_REG_VIO_MASK 0x00000008L 7295 #define UVD_SECURITY_REG_VIO_REPORT__JPEG_REG_VIO_MASK 0x00000010L 7296 #define UVD_SECURITY_REG_VIO_REPORT__JDPG_REG_VIO_MASK 0x00000020L 7297 //UVD_FW_VERSION 7298 #define UVD_FW_VERSION__FW_VERSION__SHIFT 0x0 7299 #define UVD_FW_VERSION__FW_VERSION_MASK 0xFFFFFFFFL 7300 //UVD_PF_STATUS 7301 #define UVD_PF_STATUS__JPEG_PF_OCCURED__SHIFT 0x0 7302 #define UVD_PF_STATUS__NJ_PF_OCCURED__SHIFT 0x1 7303 #define UVD_PF_STATUS__ENCODER0_PF_OCCURED__SHIFT 0x2 7304 #define UVD_PF_STATUS__ENCODER1_PF_OCCURED__SHIFT 0x3 7305 #define UVD_PF_STATUS__ENCODER2_PF_OCCURED__SHIFT 0x4 7306 #define UVD_PF_STATUS__ENCODER3_PF_OCCURED__SHIFT 0x5 7307 #define UVD_PF_STATUS__ENCODER4_PF_OCCURED__SHIFT 0x6 7308 #define UVD_PF_STATUS__EJPEG_PF_OCCURED__SHIFT 0x7 7309 #define UVD_PF_STATUS__JPEG_PF_CLEAR__SHIFT 0x8 7310 #define UVD_PF_STATUS__NJ_PF_CLEAR__SHIFT 0x9 7311 #define UVD_PF_STATUS__ENCODER0_PF_CLEAR__SHIFT 0xa 7312 #define UVD_PF_STATUS__ENCODER1_PF_CLEAR__SHIFT 0xb 7313 #define UVD_PF_STATUS__ENCODER2_PF_CLEAR__SHIFT 0xc 7314 #define UVD_PF_STATUS__ENCODER3_PF_CLEAR__SHIFT 0xd 7315 #define UVD_PF_STATUS__ENCODER4_PF_CLEAR__SHIFT 0xe 7316 #define UVD_PF_STATUS__EJPEG_PF_CLEAR__SHIFT 0xf 7317 #define UVD_PF_STATUS__NJ_ATM_PF_OCCURED__SHIFT 0x10 7318 #define UVD_PF_STATUS__DJ_ATM_PF_OCCURED__SHIFT 0x11 7319 #define UVD_PF_STATUS__EJ_ATM_PF_OCCURED__SHIFT 0x12 7320 #define UVD_PF_STATUS__JPEG2_PF_OCCURED__SHIFT 0x13 7321 #define UVD_PF_STATUS__DJ2_ATM_PF_OCCURED__SHIFT 0x14 7322 #define UVD_PF_STATUS__JPEG2_PF_CLEAR__SHIFT 0x15 7323 #define UVD_PF_STATUS__ENCODER5_PF_OCCURED__SHIFT 0x16 7324 #define UVD_PF_STATUS__ENCODER5_PF_CLEAR__SHIFT 0x17 7325 #define UVD_PF_STATUS__JPEG_PF_OCCURED_MASK 0x00000001L 7326 #define UVD_PF_STATUS__NJ_PF_OCCURED_MASK 0x00000002L 7327 #define UVD_PF_STATUS__ENCODER0_PF_OCCURED_MASK 0x00000004L 7328 #define UVD_PF_STATUS__ENCODER1_PF_OCCURED_MASK 0x00000008L 7329 #define UVD_PF_STATUS__ENCODER2_PF_OCCURED_MASK 0x00000010L 7330 #define UVD_PF_STATUS__ENCODER3_PF_OCCURED_MASK 0x00000020L 7331 #define UVD_PF_STATUS__ENCODER4_PF_OCCURED_MASK 0x00000040L 7332 #define UVD_PF_STATUS__EJPEG_PF_OCCURED_MASK 0x00000080L 7333 #define UVD_PF_STATUS__JPEG_PF_CLEAR_MASK 0x00000100L 7334 #define UVD_PF_STATUS__NJ_PF_CLEAR_MASK 0x00000200L 7335 #define UVD_PF_STATUS__ENCODER0_PF_CLEAR_MASK 0x00000400L 7336 #define UVD_PF_STATUS__ENCODER1_PF_CLEAR_MASK 0x00000800L 7337 #define UVD_PF_STATUS__ENCODER2_PF_CLEAR_MASK 0x00001000L 7338 #define UVD_PF_STATUS__ENCODER3_PF_CLEAR_MASK 0x00002000L 7339 #define UVD_PF_STATUS__ENCODER4_PF_CLEAR_MASK 0x00004000L 7340 #define UVD_PF_STATUS__EJPEG_PF_CLEAR_MASK 0x00008000L 7341 #define UVD_PF_STATUS__NJ_ATM_PF_OCCURED_MASK 0x00010000L 7342 #define UVD_PF_STATUS__DJ_ATM_PF_OCCURED_MASK 0x00020000L 7343 #define UVD_PF_STATUS__EJ_ATM_PF_OCCURED_MASK 0x00040000L 7344 #define UVD_PF_STATUS__JPEG2_PF_OCCURED_MASK 0x00080000L 7345 #define UVD_PF_STATUS__DJ2_ATM_PF_OCCURED_MASK 0x00100000L 7346 #define UVD_PF_STATUS__JPEG2_PF_CLEAR_MASK 0x00200000L 7347 #define UVD_PF_STATUS__ENCODER5_PF_OCCURED_MASK 0x00400000L 7348 #define UVD_PF_STATUS__ENCODER5_PF_CLEAR_MASK 0x00800000L 7349 //UVD_DPG_CLK_EN_VCPU_REPORT 7350 #define UVD_DPG_CLK_EN_VCPU_REPORT__CLK_EN__SHIFT 0x0 7351 #define UVD_DPG_CLK_EN_VCPU_REPORT__VCPU_REPORT__SHIFT 0x1 7352 #define UVD_DPG_CLK_EN_VCPU_REPORT__CLK_EN_MASK 0x00000001L 7353 #define UVD_DPG_CLK_EN_VCPU_REPORT__VCPU_REPORT_MASK 0x000000FEL 7354 //CC_UVD_VCPU_ERR_DETECT_BOT_LO 7355 #define CC_UVD_VCPU_ERR_DETECT_BOT_LO__UVD_VCPU_ERR_DETECT_BOT_LO__SHIFT 0xc 7356 #define CC_UVD_VCPU_ERR_DETECT_BOT_LO__UVD_VCPU_ERR_DETECT_BOT_LO_MASK 0xFFFFF000L 7357 //CC_UVD_VCPU_ERR_DETECT_BOT_HI 7358 #define CC_UVD_VCPU_ERR_DETECT_BOT_HI__UVD_VCPU_ERR_DETECT_BOT_HI__SHIFT 0x0 7359 #define CC_UVD_VCPU_ERR_DETECT_BOT_HI__UVD_VCPU_ERR_DETECT_BOT_HI_MASK 0x0000FFFFL 7360 //CC_UVD_VCPU_ERR_DETECT_TOP_LO 7361 #define CC_UVD_VCPU_ERR_DETECT_TOP_LO__UVD_VCPU_ERR_DETECT_TOP_LO__SHIFT 0xc 7362 #define CC_UVD_VCPU_ERR_DETECT_TOP_LO__UVD_VCPU_ERR_DETECT_TOP_LO_MASK 0xFFFFF000L 7363 //CC_UVD_VCPU_ERR_DETECT_TOP_HI 7364 #define CC_UVD_VCPU_ERR_DETECT_TOP_HI__UVD_VCPU_ERR_DETECT_TOP_HI__SHIFT 0x0 7365 #define CC_UVD_VCPU_ERR_DETECT_TOP_HI__UVD_VCPU_ERR_DETECT_TOP_HI_MASK 0x0000FFFFL 7366 //CC_UVD_VCPU_ERR 7367 #define CC_UVD_VCPU_ERR__UVD_VCPU_ERR_STATUS__SHIFT 0x0 7368 #define CC_UVD_VCPU_ERR__UVD_VCPU_ERR_CLEAR__SHIFT 0x1 7369 #define CC_UVD_VCPU_ERR__UVD_VCPU_ERR_DETECT_EN__SHIFT 0x2 7370 #define CC_UVD_VCPU_ERR__UVD_TMZ_DBG_DIS__SHIFT 0x3 7371 #define CC_UVD_VCPU_ERR__RESET_ON_FAULT__SHIFT 0x4 7372 #define CC_UVD_VCPU_ERR__UVD_VCPU_ERR_STATUS_MASK 0x00000001L 7373 #define CC_UVD_VCPU_ERR__UVD_VCPU_ERR_CLEAR_MASK 0x00000002L 7374 #define CC_UVD_VCPU_ERR__UVD_VCPU_ERR_DETECT_EN_MASK 0x00000004L 7375 #define CC_UVD_VCPU_ERR__UVD_TMZ_DBG_DIS_MASK 0x00000008L 7376 #define CC_UVD_VCPU_ERR__RESET_ON_FAULT_MASK 0x00000010L 7377 //CC_UVD_VCPU_ERR_INST_ADDR_LO 7378 #define CC_UVD_VCPU_ERR_INST_ADDR_LO__UVD_VCPU_ERR_INST_ADDR_LO__SHIFT 0x0 7379 #define CC_UVD_VCPU_ERR_INST_ADDR_LO__UVD_VCPU_ERR_INST_ADDR_LO_MASK 0xFFFFFFFFL 7380 //CC_UVD_VCPU_ERR_INST_ADDR_HI 7381 #define CC_UVD_VCPU_ERR_INST_ADDR_HI__UVD_VCPU_ERR_INST_ADDR_HI__SHIFT 0x0 7382 #define CC_UVD_VCPU_ERR_INST_ADDR_HI__UVD_VCPU_ERR_INST_ADDR_HI_MASK 0x0000FFFFL 7383 //UVD_LMI_MMSCH_NC_SPACE 7384 #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC0_SPACE__SHIFT 0x0 7385 #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC1_SPACE__SHIFT 0x3 7386 #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC2_SPACE__SHIFT 0x6 7387 #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC3_SPACE__SHIFT 0x9 7388 #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC4_SPACE__SHIFT 0xc 7389 #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC5_SPACE__SHIFT 0xf 7390 #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC6_SPACE__SHIFT 0x12 7391 #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC7_SPACE__SHIFT 0x15 7392 #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC0_SPACE_MASK 0x00000007L 7393 #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC1_SPACE_MASK 0x00000038L 7394 #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC2_SPACE_MASK 0x000001C0L 7395 #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC3_SPACE_MASK 0x00000E00L 7396 #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC4_SPACE_MASK 0x00007000L 7397 #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC5_SPACE_MASK 0x00038000L 7398 #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC6_SPACE_MASK 0x001C0000L 7399 #define UVD_LMI_MMSCH_NC_SPACE__MMSCH_NC7_SPACE_MASK 0x00E00000L 7400 //UVD_LMI_ATOMIC_SPACE 7401 #define UVD_LMI_ATOMIC_SPACE__ATOMIC_USER0_SPACE__SHIFT 0x0 7402 #define UVD_LMI_ATOMIC_SPACE__ATOMIC_USER1_SPACE__SHIFT 0x3 7403 #define UVD_LMI_ATOMIC_SPACE__ATOMIC_USER2_SPACE__SHIFT 0x6 7404 #define UVD_LMI_ATOMIC_SPACE__ATOMIC_USER3_SPACE__SHIFT 0x9 7405 #define UVD_LMI_ATOMIC_SPACE__ATOMIC_USER0_SPACE_MASK 0x00000007L 7406 #define UVD_LMI_ATOMIC_SPACE__ATOMIC_USER1_SPACE_MASK 0x00000038L 7407 #define UVD_LMI_ATOMIC_SPACE__ATOMIC_USER2_SPACE_MASK 0x000001C0L 7408 #define UVD_LMI_ATOMIC_SPACE__ATOMIC_USER3_SPACE_MASK 0x00000E00L 7409 //UVD_GFX8_ADDR_CONFIG 7410 #define UVD_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 7411 #define UVD_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L 7412 //UVD_GFX10_ADDR_CONFIG 7413 #define UVD_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 7414 #define UVD_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 7415 #define UVD_GFX10_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 7416 #define UVD_GFX10_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 7417 #define UVD_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 7418 #define UVD_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 7419 #define UVD_GFX10_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 7420 #define UVD_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 7421 #define UVD_GFX10_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L 7422 #define UVD_GFX10_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L 7423 #define UVD_GFX10_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 7424 #define UVD_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 7425 //UVD_GPCNT2_CNTL 7426 #define UVD_GPCNT2_CNTL__CLR__SHIFT 0x0 7427 #define UVD_GPCNT2_CNTL__START__SHIFT 0x1 7428 #define UVD_GPCNT2_CNTL__COUNTUP__SHIFT 0x2 7429 #define UVD_GPCNT2_CNTL__CLR_MASK 0x00000001L 7430 #define UVD_GPCNT2_CNTL__START_MASK 0x00000002L 7431 #define UVD_GPCNT2_CNTL__COUNTUP_MASK 0x00000004L 7432 //UVD_GPCNT2_TARGET_LOWER 7433 #define UVD_GPCNT2_TARGET_LOWER__TARGET__SHIFT 0x0 7434 #define UVD_GPCNT2_TARGET_LOWER__TARGET_MASK 0xFFFFFFFFL 7435 //UVD_GPCNT2_STATUS_LOWER 7436 #define UVD_GPCNT2_STATUS_LOWER__COUNT__SHIFT 0x0 7437 #define UVD_GPCNT2_STATUS_LOWER__COUNT_MASK 0xFFFFFFFFL 7438 //UVD_GPCNT2_TARGET_UPPER 7439 #define UVD_GPCNT2_TARGET_UPPER__TARGET__SHIFT 0x0 7440 #define UVD_GPCNT2_TARGET_UPPER__TARGET_MASK 0x0000FFFFL 7441 //UVD_GPCNT2_STATUS_UPPER 7442 #define UVD_GPCNT2_STATUS_UPPER__COUNT__SHIFT 0x0 7443 #define UVD_GPCNT2_STATUS_UPPER__COUNT_MASK 0x0000FFFFL 7444 //UVD_GPCNT3_CNTL 7445 #define UVD_GPCNT3_CNTL__CLR__SHIFT 0x0 7446 #define UVD_GPCNT3_CNTL__START__SHIFT 0x1 7447 #define UVD_GPCNT3_CNTL__COUNTUP__SHIFT 0x2 7448 #define UVD_GPCNT3_CNTL__FREQ__SHIFT 0x3 7449 #define UVD_GPCNT3_CNTL__DIV__SHIFT 0xa 7450 #define UVD_GPCNT3_CNTL__CLR_MASK 0x00000001L 7451 #define UVD_GPCNT3_CNTL__START_MASK 0x00000002L 7452 #define UVD_GPCNT3_CNTL__COUNTUP_MASK 0x00000004L 7453 #define UVD_GPCNT3_CNTL__FREQ_MASK 0x000003F8L 7454 #define UVD_GPCNT3_CNTL__DIV_MASK 0x0001FC00L 7455 //UVD_GPCNT3_TARGET_LOWER 7456 #define UVD_GPCNT3_TARGET_LOWER__TARGET__SHIFT 0x0 7457 #define UVD_GPCNT3_TARGET_LOWER__TARGET_MASK 0xFFFFFFFFL 7458 //UVD_GPCNT3_STATUS_LOWER 7459 #define UVD_GPCNT3_STATUS_LOWER__COUNT__SHIFT 0x0 7460 #define UVD_GPCNT3_STATUS_LOWER__COUNT_MASK 0xFFFFFFFFL 7461 //UVD_GPCNT3_TARGET_UPPER 7462 #define UVD_GPCNT3_TARGET_UPPER__TARGET__SHIFT 0x0 7463 #define UVD_GPCNT3_TARGET_UPPER__TARGET_MASK 0x0000FFFFL 7464 //UVD_GPCNT3_STATUS_UPPER 7465 #define UVD_GPCNT3_STATUS_UPPER__COUNT__SHIFT 0x0 7466 #define UVD_GPCNT3_STATUS_UPPER__COUNT_MASK 0x0000FFFFL 7467 //UVD_VCLK_DS_CNTL 7468 #define UVD_VCLK_DS_CNTL__VCLK_DS_EN__SHIFT 0x0 7469 #define UVD_VCLK_DS_CNTL__VCLK_DS_STATUS__SHIFT 0x4 7470 #define UVD_VCLK_DS_CNTL__VCLK_DS_HYSTERESIS_CNT__SHIFT 0x10 7471 #define UVD_VCLK_DS_CNTL__VCLK_DS_EN_MASK 0x00000001L 7472 #define UVD_VCLK_DS_CNTL__VCLK_DS_STATUS_MASK 0x00000010L 7473 #define UVD_VCLK_DS_CNTL__VCLK_DS_HYSTERESIS_CNT_MASK 0xFFFF0000L 7474 //UVD_DCLK_DS_CNTL 7475 #define UVD_DCLK_DS_CNTL__DCLK_DS_EN__SHIFT 0x0 7476 #define UVD_DCLK_DS_CNTL__DCLK_DS_STATUS__SHIFT 0x4 7477 #define UVD_DCLK_DS_CNTL__DCLK_DS_HYSTERESIS_CNT__SHIFT 0x10 7478 #define UVD_DCLK_DS_CNTL__DCLK_DS_EN_MASK 0x00000001L 7479 #define UVD_DCLK_DS_CNTL__DCLK_DS_STATUS_MASK 0x00000010L 7480 #define UVD_DCLK_DS_CNTL__DCLK_DS_HYSTERESIS_CNT_MASK 0xFFFF0000L 7481 //UVD_TSC_LOWER 7482 #define UVD_TSC_LOWER__COUNT__SHIFT 0x0 7483 #define UVD_TSC_LOWER__COUNT_MASK 0xFFFFFFFFL 7484 //UVD_TSC_UPPER 7485 #define UVD_TSC_UPPER__COUNT__SHIFT 0x0 7486 #define UVD_TSC_UPPER__COUNT_MASK 0x00FFFFFFL 7487 //VCN_FEATURES 7488 #define VCN_FEATURES__HAS_VIDEO_DEC__SHIFT 0x0 7489 #define VCN_FEATURES__HAS_VIDEO_ENC__SHIFT 0x1 7490 #define VCN_FEATURES__HAS_MJPEG_DEC__SHIFT 0x2 7491 #define VCN_FEATURES__HAS_MJPEG_ENC__SHIFT 0x3 7492 #define VCN_FEATURES__HAS_VIDEO_VIRT__SHIFT 0x4 7493 #define VCN_FEATURES__HAS_H264_LEGACY_DEC__SHIFT 0x5 7494 #define VCN_FEATURES__HAS_UDEC_DEC__SHIFT 0x6 7495 #define VCN_FEATURES__HAS_MJPEG2_IDCT_DEC__SHIFT 0x7 7496 #define VCN_FEATURES__HAS_SCLR_DEC__SHIFT 0x8 7497 #define VCN_FEATURES__HAS_VP9_DEC__SHIFT 0x9 7498 #define VCN_FEATURES__HAS_AV1_DEC__SHIFT 0xa 7499 #define VCN_FEATURES__HAS_EFC_ENC__SHIFT 0xb 7500 #define VCN_FEATURES__HAS_EFC_HDR2SDR_ENC__SHIFT 0xc 7501 #define VCN_FEATURES__HAS_DUAL_MJPEG_DEC__SHIFT 0xd 7502 #define VCN_FEATURES__HAS_AV1_ENC__SHIFT 0xe 7503 #define VCN_FEATURES__INSTANCE_ID__SHIFT 0x1c 7504 #define VCN_FEATURES__HAS_VIDEO_DEC_MASK 0x00000001L 7505 #define VCN_FEATURES__HAS_VIDEO_ENC_MASK 0x00000002L 7506 #define VCN_FEATURES__HAS_MJPEG_DEC_MASK 0x00000004L 7507 #define VCN_FEATURES__HAS_MJPEG_ENC_MASK 0x00000008L 7508 #define VCN_FEATURES__HAS_VIDEO_VIRT_MASK 0x00000010L 7509 #define VCN_FEATURES__HAS_H264_LEGACY_DEC_MASK 0x00000020L 7510 #define VCN_FEATURES__HAS_UDEC_DEC_MASK 0x00000040L 7511 #define VCN_FEATURES__HAS_MJPEG2_IDCT_DEC_MASK 0x00000080L 7512 #define VCN_FEATURES__HAS_SCLR_DEC_MASK 0x00000100L 7513 #define VCN_FEATURES__HAS_VP9_DEC_MASK 0x00000200L 7514 #define VCN_FEATURES__HAS_AV1_DEC_MASK 0x00000400L 7515 #define VCN_FEATURES__HAS_EFC_ENC_MASK 0x00000800L 7516 #define VCN_FEATURES__HAS_EFC_HDR2SDR_ENC_MASK 0x00001000L 7517 #define VCN_FEATURES__HAS_DUAL_MJPEG_DEC_MASK 0x00002000L 7518 #define VCN_FEATURES__HAS_AV1_ENC_MASK 0x00004000L 7519 #define VCN_FEATURES__INSTANCE_ID_MASK 0xF0000000L 7520 //UVD_GPUIOV_STATUS 7521 #define UVD_GPUIOV_STATUS__UVD_GPUIOV_STATUS_VF_ENABLE__SHIFT 0x0 7522 #define UVD_GPUIOV_STATUS__UVD_GPUIOV_STATUS_VF_ENABLE_MASK 0x00000001L 7523 //UVD_RAS_VCPU_VCODEC_STATUS 7524 #define UVD_RAS_VCPU_VCODEC_STATUS__POISONED_VF__SHIFT 0x0 7525 #define UVD_RAS_VCPU_VCODEC_STATUS__POISONED_PF__SHIFT 0x1f 7526 #define UVD_RAS_VCPU_VCODEC_STATUS__POISONED_VF_MASK 0x7FFFFFFFL 7527 #define UVD_RAS_VCPU_VCODEC_STATUS__POISONED_PF_MASK 0x80000000L 7528 //UVD_RAS_MMSCH_FATAL_ERROR 7529 #define UVD_RAS_MMSCH_FATAL_ERROR__POISONED_VF__SHIFT 0x0 7530 #define UVD_RAS_MMSCH_FATAL_ERROR__POISONED_PF__SHIFT 0x1f 7531 #define UVD_RAS_MMSCH_FATAL_ERROR__POISONED_VF_MASK 0x7FFFFFFFL 7532 #define UVD_RAS_MMSCH_FATAL_ERROR__POISONED_PF_MASK 0x80000000L 7533 //UVD_RAS_JPEG0_STATUS 7534 #define UVD_RAS_JPEG0_STATUS__POISONED_VF__SHIFT 0x0 7535 #define UVD_RAS_JPEG0_STATUS__POISONED_PF__SHIFT 0x1f 7536 #define UVD_RAS_JPEG0_STATUS__POISONED_VF_MASK 0x7FFFFFFFL 7537 #define UVD_RAS_JPEG0_STATUS__POISONED_PF_MASK 0x80000000L 7538 //UVD_RAS_JPEG1_STATUS 7539 #define UVD_RAS_JPEG1_STATUS__POISONED_VF__SHIFT 0x0 7540 #define UVD_RAS_JPEG1_STATUS__POISONED_PF__SHIFT 0x1f 7541 #define UVD_RAS_JPEG1_STATUS__POISONED_VF_MASK 0x7FFFFFFFL 7542 #define UVD_RAS_JPEG1_STATUS__POISONED_PF_MASK 0x80000000L 7543 //UVD_RAS_CNTL_PMI_ARB 7544 #define UVD_RAS_CNTL_PMI_ARB__STAT_VCPU_VCODEC__SHIFT 0x0 7545 #define UVD_RAS_CNTL_PMI_ARB__ACK_VCPU_VCODEC__SHIFT 0x1 7546 #define UVD_RAS_CNTL_PMI_ARB__STAT_MMSCH__SHIFT 0x2 7547 #define UVD_RAS_CNTL_PMI_ARB__ACK_MMSCH__SHIFT 0x3 7548 #define UVD_RAS_CNTL_PMI_ARB__STAT_JPEG0__SHIFT 0x4 7549 #define UVD_RAS_CNTL_PMI_ARB__ACK_JPEG0__SHIFT 0x5 7550 #define UVD_RAS_CNTL_PMI_ARB__STAT_JPEG1__SHIFT 0x6 7551 #define UVD_RAS_CNTL_PMI_ARB__ACK_JPEG1__SHIFT 0x7 7552 #define UVD_RAS_CNTL_PMI_ARB__STAT_VCPU_VCODEC_MASK 0x00000001L 7553 #define UVD_RAS_CNTL_PMI_ARB__ACK_VCPU_VCODEC_MASK 0x00000002L 7554 #define UVD_RAS_CNTL_PMI_ARB__STAT_MMSCH_MASK 0x00000004L 7555 #define UVD_RAS_CNTL_PMI_ARB__ACK_MMSCH_MASK 0x00000008L 7556 #define UVD_RAS_CNTL_PMI_ARB__STAT_JPEG0_MASK 0x00000010L 7557 #define UVD_RAS_CNTL_PMI_ARB__ACK_JPEG0_MASK 0x00000020L 7558 #define UVD_RAS_CNTL_PMI_ARB__STAT_JPEG1_MASK 0x00000040L 7559 #define UVD_RAS_CNTL_PMI_ARB__ACK_JPEG1_MASK 0x00000080L 7560 //UVD_SCRATCH15 7561 #define UVD_SCRATCH15__SCRATCH15_DATA__SHIFT 0x0 7562 #define UVD_SCRATCH15__SCRATCH15_DATA_MASK 0xFFFFFFFFL 7563 //VCN_JPEG_DB_CTRL1 7564 #define VCN_JPEG_DB_CTRL1__OFFSET__SHIFT 0x2 7565 #define VCN_JPEG_DB_CTRL1__EN__SHIFT 0x1e 7566 #define VCN_JPEG_DB_CTRL1__HIT__SHIFT 0x1f 7567 #define VCN_JPEG_DB_CTRL1__OFFSET_MASK 0x0FFFFFFCL 7568 #define VCN_JPEG_DB_CTRL1__EN_MASK 0x40000000L 7569 #define VCN_JPEG_DB_CTRL1__HIT_MASK 0x80000000L 7570 //VCN_JPEG_DB_CTRL2 7571 #define VCN_JPEG_DB_CTRL2__OFFSET__SHIFT 0x2 7572 #define VCN_JPEG_DB_CTRL2__EN__SHIFT 0x1e 7573 #define VCN_JPEG_DB_CTRL2__HIT__SHIFT 0x1f 7574 #define VCN_JPEG_DB_CTRL2__OFFSET_MASK 0x0FFFFFFCL 7575 #define VCN_JPEG_DB_CTRL2__EN_MASK 0x40000000L 7576 #define VCN_JPEG_DB_CTRL2__HIT_MASK 0x80000000L 7577 //VCN_JPEG_DB_CTRL3 7578 #define VCN_JPEG_DB_CTRL3__OFFSET__SHIFT 0x2 7579 #define VCN_JPEG_DB_CTRL3__EN__SHIFT 0x1e 7580 #define VCN_JPEG_DB_CTRL3__HIT__SHIFT 0x1f 7581 #define VCN_JPEG_DB_CTRL3__OFFSET_MASK 0x0FFFFFFCL 7582 #define VCN_JPEG_DB_CTRL3__EN_MASK 0x40000000L 7583 #define VCN_JPEG_DB_CTRL3__HIT_MASK 0x80000000L 7584 //VCN_JPEG_DB_CTRL4 7585 #define VCN_JPEG_DB_CTRL4__OFFSET__SHIFT 0x2 7586 #define VCN_JPEG_DB_CTRL4__EN__SHIFT 0x1e 7587 #define VCN_JPEG_DB_CTRL4__HIT__SHIFT 0x1f 7588 #define VCN_JPEG_DB_CTRL4__OFFSET_MASK 0x0FFFFFFCL 7589 #define VCN_JPEG_DB_CTRL4__EN_MASK 0x40000000L 7590 #define VCN_JPEG_DB_CTRL4__HIT_MASK 0x80000000L 7591 //VCN_JPEG_DB_CTRL5 7592 #define VCN_JPEG_DB_CTRL5__OFFSET__SHIFT 0x2 7593 #define VCN_JPEG_DB_CTRL5__EN__SHIFT 0x1e 7594 #define VCN_JPEG_DB_CTRL5__HIT__SHIFT 0x1f 7595 #define VCN_JPEG_DB_CTRL5__OFFSET_MASK 0x0FFFFFFCL 7596 #define VCN_JPEG_DB_CTRL5__EN_MASK 0x40000000L 7597 #define VCN_JPEG_DB_CTRL5__HIT_MASK 0x80000000L 7598 //VCN_JPEG_DB_CTRL6 7599 #define VCN_JPEG_DB_CTRL6__OFFSET__SHIFT 0x2 7600 #define VCN_JPEG_DB_CTRL6__EN__SHIFT 0x1e 7601 #define VCN_JPEG_DB_CTRL6__HIT__SHIFT 0x1f 7602 #define VCN_JPEG_DB_CTRL6__OFFSET_MASK 0x0FFFFFFCL 7603 #define VCN_JPEG_DB_CTRL6__EN_MASK 0x40000000L 7604 #define VCN_JPEG_DB_CTRL6__HIT_MASK 0x80000000L 7605 //VCN_JPEG_DB_CTRL7 7606 #define VCN_JPEG_DB_CTRL7__OFFSET__SHIFT 0x2 7607 #define VCN_JPEG_DB_CTRL7__EN__SHIFT 0x1e 7608 #define VCN_JPEG_DB_CTRL7__HIT__SHIFT 0x1f 7609 #define VCN_JPEG_DB_CTRL7__OFFSET_MASK 0x0FFFFFFCL 7610 #define VCN_JPEG_DB_CTRL7__EN_MASK 0x40000000L 7611 #define VCN_JPEG_DB_CTRL7__HIT_MASK 0x80000000L 7612 //UVD_SCRATCH32 7613 #define UVD_SCRATCH32__SCRATCH32_DATA__SHIFT 0x0 7614 #define UVD_SCRATCH32__SCRATCH32_DATA_MASK 0xFFFFFFFFL 7615 //UVD_VERSION 7616 #define UVD_VERSION__VARIANT_TYPE__SHIFT 0x0 7617 #define UVD_VERSION__MINOR_VERSION__SHIFT 0x8 7618 #define UVD_VERSION__MAJOR_VERSION__SHIFT 0x10 7619 #define UVD_VERSION__INSTANCE_ID__SHIFT 0x1c 7620 #define UVD_VERSION__VARIANT_TYPE_MASK 0x000000FFL 7621 #define UVD_VERSION__MINOR_VERSION_MASK 0x0000FF00L 7622 #define UVD_VERSION__MAJOR_VERSION_MASK 0x0FFF0000L 7623 #define UVD_VERSION__INSTANCE_ID_MASK 0xF0000000L 7624 //VCN_RB_DB_CTRL 7625 #define VCN_RB_DB_CTRL__OFFSET__SHIFT 0x2 7626 #define VCN_RB_DB_CTRL__EN__SHIFT 0x1e 7627 #define VCN_RB_DB_CTRL__HIT__SHIFT 0x1f 7628 #define VCN_RB_DB_CTRL__OFFSET_MASK 0x0FFFFFFCL 7629 #define VCN_RB_DB_CTRL__EN_MASK 0x40000000L 7630 #define VCN_RB_DB_CTRL__HIT_MASK 0x80000000L 7631 //VCN_JPEG_DB_CTRL 7632 #define VCN_JPEG_DB_CTRL__OFFSET__SHIFT 0x2 7633 #define VCN_JPEG_DB_CTRL__EN__SHIFT 0x1e 7634 #define VCN_JPEG_DB_CTRL__HIT__SHIFT 0x1f 7635 #define VCN_JPEG_DB_CTRL__OFFSET_MASK 0x0FFFFFFCL 7636 #define VCN_JPEG_DB_CTRL__EN_MASK 0x40000000L 7637 #define VCN_JPEG_DB_CTRL__HIT_MASK 0x80000000L 7638 //VCN_RB1_DB_CTRL 7639 #define VCN_RB1_DB_CTRL__OFFSET__SHIFT 0x2 7640 #define VCN_RB1_DB_CTRL__EN__SHIFT 0x1e 7641 #define VCN_RB1_DB_CTRL__HIT__SHIFT 0x1f 7642 #define VCN_RB1_DB_CTRL__OFFSET_MASK 0x0FFFFFFCL 7643 #define VCN_RB1_DB_CTRL__EN_MASK 0x40000000L 7644 #define VCN_RB1_DB_CTRL__HIT_MASK 0x80000000L 7645 //VCN_RB2_DB_CTRL 7646 #define VCN_RB2_DB_CTRL__OFFSET__SHIFT 0x2 7647 #define VCN_RB2_DB_CTRL__EN__SHIFT 0x1e 7648 #define VCN_RB2_DB_CTRL__HIT__SHIFT 0x1f 7649 #define VCN_RB2_DB_CTRL__OFFSET_MASK 0x0FFFFFFCL 7650 #define VCN_RB2_DB_CTRL__EN_MASK 0x40000000L 7651 #define VCN_RB2_DB_CTRL__HIT_MASK 0x80000000L 7652 //VCN_RB3_DB_CTRL 7653 #define VCN_RB3_DB_CTRL__OFFSET__SHIFT 0x2 7654 #define VCN_RB3_DB_CTRL__EN__SHIFT 0x1e 7655 #define VCN_RB3_DB_CTRL__HIT__SHIFT 0x1f 7656 #define VCN_RB3_DB_CTRL__OFFSET_MASK 0x0FFFFFFCL 7657 #define VCN_RB3_DB_CTRL__EN_MASK 0x40000000L 7658 #define VCN_RB3_DB_CTRL__HIT_MASK 0x80000000L 7659 //VCN_RB4_DB_CTRL 7660 #define VCN_RB4_DB_CTRL__OFFSET__SHIFT 0x2 7661 #define VCN_RB4_DB_CTRL__EN__SHIFT 0x1e 7662 #define VCN_RB4_DB_CTRL__HIT__SHIFT 0x1f 7663 #define VCN_RB4_DB_CTRL__OFFSET_MASK 0x0FFFFFFCL 7664 #define VCN_RB4_DB_CTRL__EN_MASK 0x40000000L 7665 #define VCN_RB4_DB_CTRL__HIT_MASK 0x80000000L 7666 //VCN_RB_ENABLE 7667 #define VCN_RB_ENABLE__RB_EN__SHIFT 0x0 7668 #define VCN_RB_ENABLE__JPEG_RB_EN__SHIFT 0x1 7669 #define VCN_RB_ENABLE__RB1_EN__SHIFT 0x2 7670 #define VCN_RB_ENABLE__RB2_EN__SHIFT 0x3 7671 #define VCN_RB_ENABLE__RB3_EN__SHIFT 0x4 7672 #define VCN_RB_ENABLE__RB4_EN__SHIFT 0x5 7673 #define VCN_RB_ENABLE__UMSCH_RB_EN__SHIFT 0x6 7674 #define VCN_RB_ENABLE__EJPEG_RB_EN__SHIFT 0x7 7675 #define VCN_RB_ENABLE__AUDIO_RB_EN__SHIFT 0x8 7676 #define VCN_RB_ENABLE__RB_EN_MASK 0x00000001L 7677 #define VCN_RB_ENABLE__JPEG_RB_EN_MASK 0x00000002L 7678 #define VCN_RB_ENABLE__RB1_EN_MASK 0x00000004L 7679 #define VCN_RB_ENABLE__RB2_EN_MASK 0x00000008L 7680 #define VCN_RB_ENABLE__RB3_EN_MASK 0x00000010L 7681 #define VCN_RB_ENABLE__RB4_EN_MASK 0x00000020L 7682 #define VCN_RB_ENABLE__UMSCH_RB_EN_MASK 0x00000040L 7683 #define VCN_RB_ENABLE__EJPEG_RB_EN_MASK 0x00000080L 7684 #define VCN_RB_ENABLE__AUDIO_RB_EN_MASK 0x00000100L 7685 //VCN_RB_WPTR_CTRL 7686 #define VCN_RB_WPTR_CTRL__RB_CS_EN__SHIFT 0x0 7687 #define VCN_RB_WPTR_CTRL__JPEG_CS_EN__SHIFT 0x1 7688 #define VCN_RB_WPTR_CTRL__RB1_CS_EN__SHIFT 0x2 7689 #define VCN_RB_WPTR_CTRL__RB2_CS_EN__SHIFT 0x3 7690 #define VCN_RB_WPTR_CTRL__RB3_CS_EN__SHIFT 0x4 7691 #define VCN_RB_WPTR_CTRL__RB4_CS_EN__SHIFT 0x5 7692 #define VCN_RB_WPTR_CTRL__UMSCH_RB_CS_EN__SHIFT 0x6 7693 #define VCN_RB_WPTR_CTRL__EJPEG_RB_CS_EN__SHIFT 0x7 7694 #define VCN_RB_WPTR_CTRL__AUDIO_RB_CS_EN__SHIFT 0x8 7695 #define VCN_RB_WPTR_CTRL__RB_CS_EN_MASK 0x00000001L 7696 #define VCN_RB_WPTR_CTRL__JPEG_CS_EN_MASK 0x00000002L 7697 #define VCN_RB_WPTR_CTRL__RB1_CS_EN_MASK 0x00000004L 7698 #define VCN_RB_WPTR_CTRL__RB2_CS_EN_MASK 0x00000008L 7699 #define VCN_RB_WPTR_CTRL__RB3_CS_EN_MASK 0x00000010L 7700 #define VCN_RB_WPTR_CTRL__RB4_CS_EN_MASK 0x00000020L 7701 #define VCN_RB_WPTR_CTRL__UMSCH_RB_CS_EN_MASK 0x00000040L 7702 #define VCN_RB_WPTR_CTRL__EJPEG_RB_CS_EN_MASK 0x00000080L 7703 #define VCN_RB_WPTR_CTRL__AUDIO_RB_CS_EN_MASK 0x00000100L 7704 //UVD_RB_RPTR 7705 #define UVD_RB_RPTR__RB_RPTR__SHIFT 0x4 7706 #define UVD_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 7707 //UVD_RB_WPTR 7708 #define UVD_RB_WPTR__RB_WPTR__SHIFT 0x4 7709 #define UVD_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 7710 //UVD_RB_RPTR2 7711 #define UVD_RB_RPTR2__RB_RPTR__SHIFT 0x4 7712 #define UVD_RB_RPTR2__RB_RPTR_MASK 0x007FFFF0L 7713 //UVD_RB_WPTR2 7714 #define UVD_RB_WPTR2__RB_WPTR__SHIFT 0x4 7715 #define UVD_RB_WPTR2__RB_WPTR_MASK 0x007FFFF0L 7716 //UVD_RB_RPTR3 7717 #define UVD_RB_RPTR3__RB_RPTR__SHIFT 0x4 7718 #define UVD_RB_RPTR3__RB_RPTR_MASK 0x007FFFF0L 7719 //UVD_RB_WPTR3 7720 #define UVD_RB_WPTR3__RB_WPTR__SHIFT 0x4 7721 #define UVD_RB_WPTR3__RB_WPTR_MASK 0x007FFFF0L 7722 //UVD_RB_RPTR4 7723 #define UVD_RB_RPTR4__RB_RPTR__SHIFT 0x4 7724 #define UVD_RB_RPTR4__RB_RPTR_MASK 0x007FFFF0L 7725 //UVD_RB_WPTR4 7726 #define UVD_RB_WPTR4__RB_WPTR__SHIFT 0x4 7727 #define UVD_RB_WPTR4__RB_WPTR_MASK 0x007FFFF0L 7728 //UVD_OUT_RB_RPTR 7729 #define UVD_OUT_RB_RPTR__RB_RPTR__SHIFT 0x4 7730 #define UVD_OUT_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 7731 //UVD_OUT_RB_WPTR 7732 #define UVD_OUT_RB_WPTR__RB_WPTR__SHIFT 0x4 7733 #define UVD_OUT_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 7734 //UVD_AUDIO_RB_RPTR 7735 #define UVD_AUDIO_RB_RPTR__RB_RPTR__SHIFT 0x4 7736 #define UVD_AUDIO_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 7737 //UVD_AUDIO_RB_WPTR 7738 #define UVD_AUDIO_RB_WPTR__RB_WPTR__SHIFT 0x4 7739 #define UVD_AUDIO_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 7740 //UVD_RBC_RB_RPTR 7741 #define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT 0x4 7742 #define UVD_RBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 7743 //UVD_RBC_RB_WPTR 7744 #define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT 0x4 7745 #define UVD_RBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 7746 //UVD_DPG_LMA_CTL2 7747 #define UVD_DPG_LMA_CTL2__DIRECT_ACCESS_SRAM_SEL__SHIFT 0x0 7748 #define UVD_DPG_LMA_CTL2__FIFO_DIRECT_ACCESS_EN__SHIFT 0x1 7749 #define UVD_DPG_LMA_CTL2__VID_WRITE_PTR__SHIFT 0x2 7750 #define UVD_DPG_LMA_CTL2__JPEG_WRITE_PTR__SHIFT 0x9 7751 #define UVD_DPG_LMA_CTL2__DIRECT_ACCESS_SRAM_SEL_MASK 0x00000001L 7752 #define UVD_DPG_LMA_CTL2__FIFO_DIRECT_ACCESS_EN_MASK 0x00000002L 7753 #define UVD_DPG_LMA_CTL2__VID_WRITE_PTR_MASK 0x000001FCL 7754 #define UVD_DPG_LMA_CTL2__JPEG_WRITE_PTR_MASK 0x0000FE00L 7755 7756 7757 // addressBlock: aid_uvd0_mmsch_dec 7758 //MMSCH_UCODE_ADDR 7759 #define MMSCH_UCODE_ADDR__UCODE_ADDR__SHIFT 0x2 7760 #define MMSCH_UCODE_ADDR__UCODE_LOCK__SHIFT 0x1f 7761 #define MMSCH_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFCL 7762 #define MMSCH_UCODE_ADDR__UCODE_LOCK_MASK 0x80000000L 7763 //MMSCH_UCODE_DATA 7764 #define MMSCH_UCODE_DATA__UCODE_DATA__SHIFT 0x0 7765 #define MMSCH_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL 7766 //MMSCH_SRAM_ADDR 7767 #define MMSCH_SRAM_ADDR__SRAM_ADDR__SHIFT 0x2 7768 #define MMSCH_SRAM_ADDR__SRAM_LOCK__SHIFT 0x1f 7769 #define MMSCH_SRAM_ADDR__SRAM_ADDR_MASK 0x00001FFCL 7770 #define MMSCH_SRAM_ADDR__SRAM_LOCK_MASK 0x80000000L 7771 //MMSCH_SRAM_DATA 7772 #define MMSCH_SRAM_DATA__SRAM_DATA__SHIFT 0x0 7773 #define MMSCH_SRAM_DATA__SRAM_DATA_MASK 0xFFFFFFFFL 7774 //MMSCH_VF_SRAM_OFFSET 7775 #define MMSCH_VF_SRAM_OFFSET__VF_SRAM_OFFSET__SHIFT 0x2 7776 #define MMSCH_VF_SRAM_OFFSET__VF_SRAM_NUM_DW_PER_VF__SHIFT 0x10 7777 #define MMSCH_VF_SRAM_OFFSET__VF_SRAM_OFFSET_MASK 0x00001FFCL 7778 #define MMSCH_VF_SRAM_OFFSET__VF_SRAM_NUM_DW_PER_VF_MASK 0x00FF0000L 7779 //MMSCH_DB_SRAM_OFFSET 7780 #define MMSCH_DB_SRAM_OFFSET__DB_SRAM_OFFSET__SHIFT 0x2 7781 #define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_ENG__SHIFT 0x10 7782 #define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_RING_PER_ENG__SHIFT 0x18 7783 #define MMSCH_DB_SRAM_OFFSET__DB_SRAM_OFFSET_MASK 0x00001FFCL 7784 #define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_ENG_MASK 0x00FF0000L 7785 #define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_RING_PER_ENG_MASK 0xFF000000L 7786 //MMSCH_CTX_SRAM_OFFSET 7787 #define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_OFFSET__SHIFT 0x2 7788 #define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_SIZE__SHIFT 0x10 7789 #define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_OFFSET_MASK 0x00001FFCL 7790 #define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_SIZE_MASK 0xFFFF0000L 7791 //MMSCH_CTL 7792 #define MMSCH_CTL__P_RUNSTALL__SHIFT 0x0 7793 #define MMSCH_CTL__P_RESET__SHIFT 0x1 7794 #define MMSCH_CTL__VFID_FIFO_EN__SHIFT 0x4 7795 #define MMSCH_CTL__P_LOCK__SHIFT 0x1f 7796 #define MMSCH_CTL__P_RUNSTALL_MASK 0x00000001L 7797 #define MMSCH_CTL__P_RESET_MASK 0x00000002L 7798 #define MMSCH_CTL__VFID_FIFO_EN_MASK 0x00000010L 7799 #define MMSCH_CTL__P_LOCK_MASK 0x80000000L 7800 //MMSCH_INTR 7801 #define MMSCH_INTR__INTR__SHIFT 0x0 7802 #define MMSCH_INTR__INTR_MASK 0x00001FFFL 7803 //MMSCH_INTR_ACK 7804 #define MMSCH_INTR_ACK__INTR__SHIFT 0x0 7805 #define MMSCH_INTR_ACK__INTR_MASK 0x00001FFFL 7806 //MMSCH_INTR_STATUS 7807 #define MMSCH_INTR_STATUS__INTR__SHIFT 0x0 7808 #define MMSCH_INTR_STATUS__INTR_MASK 0x00001FFFL 7809 //MMSCH_VF_VMID 7810 #define MMSCH_VF_VMID__VF_CTX_VMID__SHIFT 0x0 7811 #define MMSCH_VF_VMID__VF_GPCOM_VMID__SHIFT 0x5 7812 #define MMSCH_VF_VMID__VF_CTX_VMID_MASK 0x0000001FL 7813 #define MMSCH_VF_VMID__VF_GPCOM_VMID_MASK 0x000003E0L 7814 //MMSCH_VF_CTX_ADDR_LO 7815 #define MMSCH_VF_CTX_ADDR_LO__VF_CTX_ADDR_LO__SHIFT 0x6 7816 #define MMSCH_VF_CTX_ADDR_LO__VF_CTX_ADDR_LO_MASK 0xFFFFFFC0L 7817 //MMSCH_VF_CTX_ADDR_HI 7818 #define MMSCH_VF_CTX_ADDR_HI__VF_CTX_ADDR_HI__SHIFT 0x0 7819 #define MMSCH_VF_CTX_ADDR_HI__VF_CTX_ADDR_HI_MASK 0xFFFFFFFFL 7820 //MMSCH_VF_CTX_SIZE 7821 #define MMSCH_VF_CTX_SIZE__VF_CTX_SIZE__SHIFT 0x0 7822 #define MMSCH_VF_CTX_SIZE__VF_CTX_SIZE_MASK 0xFFFFFFFFL 7823 //MMSCH_VF_GPCOM_ADDR_LO 7824 #define MMSCH_VF_GPCOM_ADDR_LO__VF_GPCOM_ADDR_LO__SHIFT 0x6 7825 #define MMSCH_VF_GPCOM_ADDR_LO__VF_GPCOM_ADDR_LO_MASK 0xFFFFFFC0L 7826 //MMSCH_VF_GPCOM_ADDR_HI 7827 #define MMSCH_VF_GPCOM_ADDR_HI__VF_GPCOM_ADDR_HI__SHIFT 0x0 7828 #define MMSCH_VF_GPCOM_ADDR_HI__VF_GPCOM_ADDR_HI_MASK 0xFFFFFFFFL 7829 //MMSCH_VF_GPCOM_SIZE 7830 #define MMSCH_VF_GPCOM_SIZE__VF_GPCOM_SIZE__SHIFT 0x0 7831 #define MMSCH_VF_GPCOM_SIZE__VF_GPCOM_SIZE_MASK 0xFFFFFFFFL 7832 //MMSCH_VF_MAILBOX_HOST 7833 #define MMSCH_VF_MAILBOX_HOST__DATA__SHIFT 0x0 7834 #define MMSCH_VF_MAILBOX_HOST__DATA_MASK 0xFFFFFFFFL 7835 //MMSCH_VF_MAILBOX_RESP 7836 #define MMSCH_VF_MAILBOX_RESP__RESP__SHIFT 0x0 7837 #define MMSCH_VF_MAILBOX_RESP__RESP_MASK 0xFFFFFFFFL 7838 //MMSCH_VF_MAILBOX_0 7839 #define MMSCH_VF_MAILBOX_0__DATA__SHIFT 0x0 7840 #define MMSCH_VF_MAILBOX_0__DATA_MASK 0xFFFFFFFFL 7841 //MMSCH_VF_MAILBOX_0_RESP 7842 #define MMSCH_VF_MAILBOX_0_RESP__RESP__SHIFT 0x0 7843 #define MMSCH_VF_MAILBOX_0_RESP__RESP_MASK 0xFFFFFFFFL 7844 //MMSCH_VF_MAILBOX_1 7845 #define MMSCH_VF_MAILBOX_1__DATA__SHIFT 0x0 7846 #define MMSCH_VF_MAILBOX_1__DATA_MASK 0xFFFFFFFFL 7847 //MMSCH_VF_MAILBOX_1_RESP 7848 #define MMSCH_VF_MAILBOX_1_RESP__RESP__SHIFT 0x0 7849 #define MMSCH_VF_MAILBOX_1_RESP__RESP_MASK 0xFFFFFFFFL 7850 //MMSCH_CNTL 7851 #define MMSCH_CNTL__CLK_EN__SHIFT 0x0 7852 #define MMSCH_CNTL__ED_ENABLE__SHIFT 0x1 7853 #define MMSCH_CNTL__AXI_MAX_BRST_SIZE_IS_4__SHIFT 0x2 7854 #define MMSCH_CNTL__AXI_40BIT_PIF_ADDR_FIX_EN__SHIFT 0x3 7855 #define MMSCH_CNTL__PDEBUG_ENABLE__SHIFT 0x4 7856 #define MMSCH_CNTL__MMSCH_IRQ_ERR__SHIFT 0x5 7857 #define MMSCH_CNTL__MMSCH_NACK_INTR_EN__SHIFT 0x9 7858 #define MMSCH_CNTL__MMSCH_DB_BUSY_INTR_EN__SHIFT 0xa 7859 #define MMSCH_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14 7860 #define MMSCH_CNTL__TIMEOUT_DIS__SHIFT 0x1c 7861 #define MMSCH_CNTL__MMSCH_IDLE__SHIFT 0x1d 7862 #define MMSCH_CNTL__CLK_EN_MASK 0x00000001L 7863 #define MMSCH_CNTL__ED_ENABLE_MASK 0x00000002L 7864 #define MMSCH_CNTL__AXI_MAX_BRST_SIZE_IS_4_MASK 0x00000004L 7865 #define MMSCH_CNTL__AXI_40BIT_PIF_ADDR_FIX_EN_MASK 0x00000008L 7866 #define MMSCH_CNTL__PDEBUG_ENABLE_MASK 0x00000010L 7867 #define MMSCH_CNTL__MMSCH_IRQ_ERR_MASK 0x000001E0L 7868 #define MMSCH_CNTL__MMSCH_NACK_INTR_EN_MASK 0x00000200L 7869 #define MMSCH_CNTL__MMSCH_DB_BUSY_INTR_EN_MASK 0x00000400L 7870 #define MMSCH_CNTL__PRB_TIMEOUT_VAL_MASK 0x0FF00000L 7871 #define MMSCH_CNTL__TIMEOUT_DIS_MASK 0x10000000L 7872 #define MMSCH_CNTL__MMSCH_IDLE_MASK 0x20000000L 7873 //MMSCH_NONCACHE_OFFSET0 7874 #define MMSCH_NONCACHE_OFFSET0__OFFSET__SHIFT 0x0 7875 #define MMSCH_NONCACHE_OFFSET0__OFFSET_MASK 0x0FFFFFFFL 7876 //MMSCH_NONCACHE_SIZE0 7877 #define MMSCH_NONCACHE_SIZE0__SIZE__SHIFT 0x0 7878 #define MMSCH_NONCACHE_SIZE0__SIZE_MASK 0x00FFFFFFL 7879 //MMSCH_NONCACHE_OFFSET1 7880 #define MMSCH_NONCACHE_OFFSET1__OFFSET__SHIFT 0x0 7881 #define MMSCH_NONCACHE_OFFSET1__OFFSET_MASK 0x0FFFFFFFL 7882 //MMSCH_NONCACHE_SIZE1 7883 #define MMSCH_NONCACHE_SIZE1__SIZE__SHIFT 0x0 7884 #define MMSCH_NONCACHE_SIZE1__SIZE_MASK 0x00FFFFFFL 7885 //MMSCH_PROC_STATE1 7886 #define MMSCH_PROC_STATE1__PC__SHIFT 0x0 7887 #define MMSCH_PROC_STATE1__PC_MASK 0xFFFFFFFFL 7888 //MMSCH_LAST_MC_ADDR 7889 #define MMSCH_LAST_MC_ADDR__MC_ADDR__SHIFT 0x0 7890 #define MMSCH_LAST_MC_ADDR__RW__SHIFT 0x1f 7891 #define MMSCH_LAST_MC_ADDR__MC_ADDR_MASK 0x0FFFFFFFL 7892 #define MMSCH_LAST_MC_ADDR__RW_MASK 0x80000000L 7893 //MMSCH_LAST_MEM_ACCESS_HI 7894 #define MMSCH_LAST_MEM_ACCESS_HI__PROC_CMD__SHIFT 0x0 7895 #define MMSCH_LAST_MEM_ACCESS_HI__FIFO_RPTR__SHIFT 0x8 7896 #define MMSCH_LAST_MEM_ACCESS_HI__FIFO_WPTR__SHIFT 0xc 7897 #define MMSCH_LAST_MEM_ACCESS_HI__PROC_CMD_MASK 0x00000007L 7898 #define MMSCH_LAST_MEM_ACCESS_HI__FIFO_RPTR_MASK 0x00000700L 7899 #define MMSCH_LAST_MEM_ACCESS_HI__FIFO_WPTR_MASK 0x00007000L 7900 //MMSCH_LAST_MEM_ACCESS_LO 7901 #define MMSCH_LAST_MEM_ACCESS_LO__PROC_ADDR__SHIFT 0x0 7902 #define MMSCH_LAST_MEM_ACCESS_LO__PROC_ADDR_MASK 0xFFFFFFFFL 7903 //MMSCH_IOV_ACTIVE_FCN_ID 7904 #define MMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_VF_ID__SHIFT 0x0 7905 #define MMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_PF_VF__SHIFT 0x1f 7906 #define MMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_VF_ID_MASK 0x0000001FL 7907 #define MMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_PF_VF_MASK 0x80000000L 7908 //MMSCH_SCRATCH_0 7909 #define MMSCH_SCRATCH_0__SCRATCH_0__SHIFT 0x0 7910 #define MMSCH_SCRATCH_0__SCRATCH_0_MASK 0xFFFFFFFFL 7911 //MMSCH_SCRATCH_1 7912 #define MMSCH_SCRATCH_1__SCRATCH_1__SHIFT 0x0 7913 #define MMSCH_SCRATCH_1__SCRATCH_1_MASK 0xFFFFFFFFL 7914 //MMSCH_GPUIOV_SCH_BLOCK_0 7915 #define MMSCH_GPUIOV_SCH_BLOCK_0__ID__SHIFT 0x0 7916 #define MMSCH_GPUIOV_SCH_BLOCK_0__VERSION__SHIFT 0x4 7917 #define MMSCH_GPUIOV_SCH_BLOCK_0__SIZE__SHIFT 0x8 7918 #define MMSCH_GPUIOV_SCH_BLOCK_0__ID_MASK 0x0000000FL 7919 #define MMSCH_GPUIOV_SCH_BLOCK_0__VERSION_MASK 0x000000F0L 7920 #define MMSCH_GPUIOV_SCH_BLOCK_0__SIZE_MASK 0x0000FF00L 7921 //MMSCH_GPUIOV_CMD_CONTROL_0 7922 #define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_TYPE__SHIFT 0x0 7923 #define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE__SHIFT 0x4 7924 #define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE_INTR_EN__SHIFT 0x5 7925 #define MMSCH_GPUIOV_CMD_CONTROL_0__VM_BUSY_INTR_EN__SHIFT 0x6 7926 #define MMSCH_GPUIOV_CMD_CONTROL_0__FUNCTINO_ID__SHIFT 0x8 7927 #define MMSCH_GPUIOV_CMD_CONTROL_0__NEXT_FUNCTINO_ID__SHIFT 0x10 7928 #define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_TYPE_MASK 0x0000000FL 7929 #define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE_MASK 0x00000010L 7930 #define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE_INTR_EN_MASK 0x00000020L 7931 #define MMSCH_GPUIOV_CMD_CONTROL_0__VM_BUSY_INTR_EN_MASK 0x00000040L 7932 #define MMSCH_GPUIOV_CMD_CONTROL_0__FUNCTINO_ID_MASK 0x0000FF00L 7933 #define MMSCH_GPUIOV_CMD_CONTROL_0__NEXT_FUNCTINO_ID_MASK 0x00FF0000L 7934 //MMSCH_GPUIOV_CMD_STATUS_0 7935 #define MMSCH_GPUIOV_CMD_STATUS_0__CMD_STATUS__SHIFT 0x0 7936 #define MMSCH_GPUIOV_CMD_STATUS_0__CMD_STATUS_MASK 0x0000000FL 7937 //MMSCH_GPUIOV_VM_BUSY_STATUS_0 7938 #define MMSCH_GPUIOV_VM_BUSY_STATUS_0__BUSY__SHIFT 0x0 7939 #define MMSCH_GPUIOV_VM_BUSY_STATUS_0__BUSY_MASK 0xFFFFFFFFL 7940 //MMSCH_GPUIOV_ACTIVE_FCNS_0 7941 #define MMSCH_GPUIOV_ACTIVE_FCNS_0__ACTIVE_FCNS__SHIFT 0x0 7942 #define MMSCH_GPUIOV_ACTIVE_FCNS_0__ACTIVE_FCNS_MASK 0xFFFFFFFFL 7943 //MMSCH_GPUIOV_ACTIVE_FCN_ID_0 7944 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID__SHIFT 0x0 7945 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID_STATUS__SHIFT 0x8 7946 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID_MASK 0x000000FFL 7947 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID_STATUS_MASK 0x00000F00L 7948 //MMSCH_GPUIOV_DW6_0 7949 #define MMSCH_GPUIOV_DW6_0__DATA__SHIFT 0x0 7950 #define MMSCH_GPUIOV_DW6_0__DATA_MASK 0xFFFFFFFFL 7951 //MMSCH_GPUIOV_DW7_0 7952 #define MMSCH_GPUIOV_DW7_0__DATA__SHIFT 0x0 7953 #define MMSCH_GPUIOV_DW7_0__DATA_MASK 0xFFFFFFFFL 7954 //MMSCH_GPUIOV_DW8_0 7955 #define MMSCH_GPUIOV_DW8_0__DATA__SHIFT 0x0 7956 #define MMSCH_GPUIOV_DW8_0__DATA_MASK 0xFFFFFFFFL 7957 //MMSCH_GPUIOV_SCH_BLOCK_1 7958 #define MMSCH_GPUIOV_SCH_BLOCK_1__ID__SHIFT 0x0 7959 #define MMSCH_GPUIOV_SCH_BLOCK_1__VERSION__SHIFT 0x4 7960 #define MMSCH_GPUIOV_SCH_BLOCK_1__SIZE__SHIFT 0x8 7961 #define MMSCH_GPUIOV_SCH_BLOCK_1__ID_MASK 0x0000000FL 7962 #define MMSCH_GPUIOV_SCH_BLOCK_1__VERSION_MASK 0x000000F0L 7963 #define MMSCH_GPUIOV_SCH_BLOCK_1__SIZE_MASK 0x0000FF00L 7964 //MMSCH_GPUIOV_CMD_CONTROL_1 7965 #define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_TYPE__SHIFT 0x0 7966 #define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE__SHIFT 0x4 7967 #define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE_INTR_EN__SHIFT 0x5 7968 #define MMSCH_GPUIOV_CMD_CONTROL_1__VM_BUSY_INTR_EN__SHIFT 0x6 7969 #define MMSCH_GPUIOV_CMD_CONTROL_1__FUNCTINO_ID__SHIFT 0x8 7970 #define MMSCH_GPUIOV_CMD_CONTROL_1__NEXT_FUNCTINO_ID__SHIFT 0x10 7971 #define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_TYPE_MASK 0x0000000FL 7972 #define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE_MASK 0x00000010L 7973 #define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE_INTR_EN_MASK 0x00000020L 7974 #define MMSCH_GPUIOV_CMD_CONTROL_1__VM_BUSY_INTR_EN_MASK 0x00000040L 7975 #define MMSCH_GPUIOV_CMD_CONTROL_1__FUNCTINO_ID_MASK 0x0000FF00L 7976 #define MMSCH_GPUIOV_CMD_CONTROL_1__NEXT_FUNCTINO_ID_MASK 0x00FF0000L 7977 //MMSCH_GPUIOV_CMD_STATUS_1 7978 #define MMSCH_GPUIOV_CMD_STATUS_1__CMD_STATUS__SHIFT 0x0 7979 #define MMSCH_GPUIOV_CMD_STATUS_1__CMD_STATUS_MASK 0x0000000FL 7980 //MMSCH_GPUIOV_VM_BUSY_STATUS_1 7981 #define MMSCH_GPUIOV_VM_BUSY_STATUS_1__BUSY__SHIFT 0x0 7982 #define MMSCH_GPUIOV_VM_BUSY_STATUS_1__BUSY_MASK 0xFFFFFFFFL 7983 //MMSCH_GPUIOV_ACTIVE_FCNS_1 7984 #define MMSCH_GPUIOV_ACTIVE_FCNS_1__ACTIVE_FCNS__SHIFT 0x0 7985 #define MMSCH_GPUIOV_ACTIVE_FCNS_1__ACTIVE_FCNS_MASK 0xFFFFFFFFL 7986 //MMSCH_GPUIOV_ACTIVE_FCN_ID_1 7987 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID__SHIFT 0x0 7988 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID_STATUS__SHIFT 0x8 7989 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID_MASK 0x000000FFL 7990 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID_STATUS_MASK 0x00000F00L 7991 //MMSCH_GPUIOV_DW6_1 7992 #define MMSCH_GPUIOV_DW6_1__DATA__SHIFT 0x0 7993 #define MMSCH_GPUIOV_DW6_1__DATA_MASK 0xFFFFFFFFL 7994 //MMSCH_GPUIOV_DW7_1 7995 #define MMSCH_GPUIOV_DW7_1__DATA__SHIFT 0x0 7996 #define MMSCH_GPUIOV_DW7_1__DATA_MASK 0xFFFFFFFFL 7997 //MMSCH_GPUIOV_DW8_1 7998 #define MMSCH_GPUIOV_DW8_1__DATA__SHIFT 0x0 7999 #define MMSCH_GPUIOV_DW8_1__DATA_MASK 0xFFFFFFFFL 8000 //MMSCH_GPUIOV_CNTXT 8001 #define MMSCH_GPUIOV_CNTXT__CNTXT_SIZE__SHIFT 0x0 8002 #define MMSCH_GPUIOV_CNTXT__CNTXT_LOCATION__SHIFT 0x7 8003 #define MMSCH_GPUIOV_CNTXT__CNTXT_OFFSET__SHIFT 0xa 8004 #define MMSCH_GPUIOV_CNTXT__CNTXT_SIZE_MASK 0x0000007FL 8005 #define MMSCH_GPUIOV_CNTXT__CNTXT_LOCATION_MASK 0x00000080L 8006 #define MMSCH_GPUIOV_CNTXT__CNTXT_OFFSET_MASK 0xFFFFFC00L 8007 //MMSCH_SCRATCH_2 8008 #define MMSCH_SCRATCH_2__SCRATCH_2__SHIFT 0x0 8009 #define MMSCH_SCRATCH_2__SCRATCH_2_MASK 0xFFFFFFFFL 8010 //MMSCH_SCRATCH_3 8011 #define MMSCH_SCRATCH_3__SCRATCH_3__SHIFT 0x0 8012 #define MMSCH_SCRATCH_3__SCRATCH_3_MASK 0xFFFFFFFFL 8013 //MMSCH_SCRATCH_4 8014 #define MMSCH_SCRATCH_4__SCRATCH_4__SHIFT 0x0 8015 #define MMSCH_SCRATCH_4__SCRATCH_4_MASK 0xFFFFFFFFL 8016 //MMSCH_SCRATCH_5 8017 #define MMSCH_SCRATCH_5__SCRATCH_5__SHIFT 0x0 8018 #define MMSCH_SCRATCH_5__SCRATCH_5_MASK 0xFFFFFFFFL 8019 //MMSCH_SCRATCH_6 8020 #define MMSCH_SCRATCH_6__SCRATCH_6__SHIFT 0x0 8021 #define MMSCH_SCRATCH_6__SCRATCH_6_MASK 0xFFFFFFFFL 8022 //MMSCH_SCRATCH_7 8023 #define MMSCH_SCRATCH_7__SCRATCH_7__SHIFT 0x0 8024 #define MMSCH_SCRATCH_7__SCRATCH_7_MASK 0xFFFFFFFFL 8025 //MMSCH_VFID_FIFO_HEAD_0 8026 #define MMSCH_VFID_FIFO_HEAD_0__HEAD__SHIFT 0x0 8027 #define MMSCH_VFID_FIFO_HEAD_0__HEAD_MASK 0x0000003FL 8028 //MMSCH_VFID_FIFO_TAIL_0 8029 #define MMSCH_VFID_FIFO_TAIL_0__TAIL__SHIFT 0x0 8030 #define MMSCH_VFID_FIFO_TAIL_0__TAIL_MASK 0x0000003FL 8031 //MMSCH_VFID_FIFO_HEAD_1 8032 #define MMSCH_VFID_FIFO_HEAD_1__HEAD__SHIFT 0x0 8033 #define MMSCH_VFID_FIFO_HEAD_1__HEAD_MASK 0x0000003FL 8034 //MMSCH_VFID_FIFO_TAIL_1 8035 #define MMSCH_VFID_FIFO_TAIL_1__TAIL__SHIFT 0x0 8036 #define MMSCH_VFID_FIFO_TAIL_1__TAIL_MASK 0x0000003FL 8037 //MMSCH_NACK_STATUS 8038 #define MMSCH_NACK_STATUS__WR_NACK_STATUS__SHIFT 0x0 8039 #define MMSCH_NACK_STATUS__RD_NACK_STATUS__SHIFT 0x2 8040 #define MMSCH_NACK_STATUS__WR_NACK_STATUS_MASK 0x00000003L 8041 #define MMSCH_NACK_STATUS__RD_NACK_STATUS_MASK 0x0000000CL 8042 //MMSCH_VF_MAILBOX0_DATA 8043 #define MMSCH_VF_MAILBOX0_DATA__DATA__SHIFT 0x0 8044 #define MMSCH_VF_MAILBOX0_DATA__DATA_MASK 0xFFFFFFFFL 8045 //MMSCH_VF_MAILBOX1_DATA 8046 #define MMSCH_VF_MAILBOX1_DATA__DATA__SHIFT 0x0 8047 #define MMSCH_VF_MAILBOX1_DATA__DATA_MASK 0xFFFFFFFFL 8048 //MMSCH_GPUIOV_SCH_BLOCK_IP_0 8049 #define MMSCH_GPUIOV_SCH_BLOCK_IP_0__ID__SHIFT 0x0 8050 #define MMSCH_GPUIOV_SCH_BLOCK_IP_0__VERSION__SHIFT 0x4 8051 #define MMSCH_GPUIOV_SCH_BLOCK_IP_0__SIZE__SHIFT 0x8 8052 #define MMSCH_GPUIOV_SCH_BLOCK_IP_0__ID_MASK 0x0000000FL 8053 #define MMSCH_GPUIOV_SCH_BLOCK_IP_0__VERSION_MASK 0x000000F0L 8054 #define MMSCH_GPUIOV_SCH_BLOCK_IP_0__SIZE_MASK 0x0000FF00L 8055 //MMSCH_GPUIOV_CMD_STATUS_IP_0 8056 #define MMSCH_GPUIOV_CMD_STATUS_IP_0__CMD_STATUS__SHIFT 0x0 8057 #define MMSCH_GPUIOV_CMD_STATUS_IP_0__CMD_STATUS_MASK 0x0000000FL 8058 //MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0 8059 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID__SHIFT 0x0 8060 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID_STATUS__SHIFT 0x8 8061 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID_MASK 0x000000FFL 8062 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID_STATUS_MASK 0x00000F00L 8063 //MMSCH_GPUIOV_SCH_BLOCK_IP_1 8064 #define MMSCH_GPUIOV_SCH_BLOCK_IP_1__ID__SHIFT 0x0 8065 #define MMSCH_GPUIOV_SCH_BLOCK_IP_1__VERSION__SHIFT 0x4 8066 #define MMSCH_GPUIOV_SCH_BLOCK_IP_1__SIZE__SHIFT 0x8 8067 #define MMSCH_GPUIOV_SCH_BLOCK_IP_1__ID_MASK 0x0000000FL 8068 #define MMSCH_GPUIOV_SCH_BLOCK_IP_1__VERSION_MASK 0x000000F0L 8069 #define MMSCH_GPUIOV_SCH_BLOCK_IP_1__SIZE_MASK 0x0000FF00L 8070 //MMSCH_GPUIOV_CMD_STATUS_IP_1 8071 #define MMSCH_GPUIOV_CMD_STATUS_IP_1__CMD_STATUS__SHIFT 0x0 8072 #define MMSCH_GPUIOV_CMD_STATUS_IP_1__CMD_STATUS_MASK 0x0000000FL 8073 //MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1 8074 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID__SHIFT 0x0 8075 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID_STATUS__SHIFT 0x8 8076 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID_MASK 0x000000FFL 8077 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID_STATUS_MASK 0x00000F00L 8078 //MMSCH_GPUIOV_CNTXT_IP 8079 #define MMSCH_GPUIOV_CNTXT_IP__CNTXT_SIZE__SHIFT 0x0 8080 #define MMSCH_GPUIOV_CNTXT_IP__CNTXT_LOCATION__SHIFT 0x7 8081 #define MMSCH_GPUIOV_CNTXT_IP__CNTXT_SIZE_MASK 0x0000007FL 8082 #define MMSCH_GPUIOV_CNTXT_IP__CNTXT_LOCATION_MASK 0x00000080L 8083 //MMSCH_GPUIOV_SCH_BLOCK_2 8084 #define MMSCH_GPUIOV_SCH_BLOCK_2__ID__SHIFT 0x0 8085 #define MMSCH_GPUIOV_SCH_BLOCK_2__VERSION__SHIFT 0x4 8086 #define MMSCH_GPUIOV_SCH_BLOCK_2__SIZE__SHIFT 0x8 8087 #define MMSCH_GPUIOV_SCH_BLOCK_2__ID_MASK 0x0000000FL 8088 #define MMSCH_GPUIOV_SCH_BLOCK_2__VERSION_MASK 0x000000F0L 8089 #define MMSCH_GPUIOV_SCH_BLOCK_2__SIZE_MASK 0x0000FF00L 8090 //MMSCH_GPUIOV_CMD_CONTROL_2 8091 #define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_TYPE__SHIFT 0x0 8092 #define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE__SHIFT 0x4 8093 #define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE_INTR_EN__SHIFT 0x5 8094 #define MMSCH_GPUIOV_CMD_CONTROL_2__VM_BUSY_INTR_EN__SHIFT 0x6 8095 #define MMSCH_GPUIOV_CMD_CONTROL_2__FUNCTINO_ID__SHIFT 0x8 8096 #define MMSCH_GPUIOV_CMD_CONTROL_2__NEXT_FUNCTINO_ID__SHIFT 0x10 8097 #define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_TYPE_MASK 0x0000000FL 8098 #define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE_MASK 0x00000010L 8099 #define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE_INTR_EN_MASK 0x00000020L 8100 #define MMSCH_GPUIOV_CMD_CONTROL_2__VM_BUSY_INTR_EN_MASK 0x00000040L 8101 #define MMSCH_GPUIOV_CMD_CONTROL_2__FUNCTINO_ID_MASK 0x0000FF00L 8102 #define MMSCH_GPUIOV_CMD_CONTROL_2__NEXT_FUNCTINO_ID_MASK 0x00FF0000L 8103 //MMSCH_GPUIOV_CMD_STATUS_2 8104 #define MMSCH_GPUIOV_CMD_STATUS_2__CMD_STATUS__SHIFT 0x0 8105 #define MMSCH_GPUIOV_CMD_STATUS_2__CMD_STATUS_MASK 0x0000000FL 8106 //MMSCH_GPUIOV_VM_BUSY_STATUS_2 8107 #define MMSCH_GPUIOV_VM_BUSY_STATUS_2__BUSY__SHIFT 0x0 8108 #define MMSCH_GPUIOV_VM_BUSY_STATUS_2__BUSY_MASK 0xFFFFFFFFL 8109 //MMSCH_GPUIOV_ACTIVE_FCNS_2 8110 #define MMSCH_GPUIOV_ACTIVE_FCNS_2__ACTIVE_FCNS__SHIFT 0x0 8111 #define MMSCH_GPUIOV_ACTIVE_FCNS_2__ACTIVE_FCNS_MASK 0xFFFFFFFFL 8112 //MMSCH_GPUIOV_ACTIVE_FCN_ID_2 8113 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID__SHIFT 0x0 8114 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID_STATUS__SHIFT 0x8 8115 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID_MASK 0x000000FFL 8116 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID_STATUS_MASK 0x00000F00L 8117 //MMSCH_GPUIOV_DW6_2 8118 #define MMSCH_GPUIOV_DW6_2__DATA__SHIFT 0x0 8119 #define MMSCH_GPUIOV_DW6_2__DATA_MASK 0xFFFFFFFFL 8120 //MMSCH_GPUIOV_DW7_2 8121 #define MMSCH_GPUIOV_DW7_2__DATA__SHIFT 0x0 8122 #define MMSCH_GPUIOV_DW7_2__DATA_MASK 0xFFFFFFFFL 8123 //MMSCH_GPUIOV_DW8_2 8124 #define MMSCH_GPUIOV_DW8_2__DATA__SHIFT 0x0 8125 #define MMSCH_GPUIOV_DW8_2__DATA_MASK 0xFFFFFFFFL 8126 //MMSCH_GPUIOV_SCH_BLOCK_IP_2 8127 #define MMSCH_GPUIOV_SCH_BLOCK_IP_2__ID__SHIFT 0x0 8128 #define MMSCH_GPUIOV_SCH_BLOCK_IP_2__VERSION__SHIFT 0x4 8129 #define MMSCH_GPUIOV_SCH_BLOCK_IP_2__SIZE__SHIFT 0x8 8130 #define MMSCH_GPUIOV_SCH_BLOCK_IP_2__ID_MASK 0x0000000FL 8131 #define MMSCH_GPUIOV_SCH_BLOCK_IP_2__VERSION_MASK 0x000000F0L 8132 #define MMSCH_GPUIOV_SCH_BLOCK_IP_2__SIZE_MASK 0x0000FF00L 8133 //MMSCH_GPUIOV_CMD_STATUS_IP_2 8134 #define MMSCH_GPUIOV_CMD_STATUS_IP_2__CMD_STATUS__SHIFT 0x0 8135 #define MMSCH_GPUIOV_CMD_STATUS_IP_2__CMD_STATUS_MASK 0x0000000FL 8136 //MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2 8137 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID__SHIFT 0x0 8138 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID_STATUS__SHIFT 0x8 8139 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID_MASK 0x000000FFL 8140 #define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID_STATUS_MASK 0x00000F00L 8141 //MMSCH_VFID_FIFO_HEAD_2 8142 #define MMSCH_VFID_FIFO_HEAD_2__HEAD__SHIFT 0x0 8143 #define MMSCH_VFID_FIFO_HEAD_2__HEAD_MASK 0x0000003FL 8144 //MMSCH_VFID_FIFO_TAIL_2 8145 #define MMSCH_VFID_FIFO_TAIL_2__TAIL__SHIFT 0x0 8146 #define MMSCH_VFID_FIFO_TAIL_2__TAIL_MASK 0x0000003FL 8147 //MMSCH_VM_BUSY_STATUS_0 8148 #define MMSCH_VM_BUSY_STATUS_0__BUSY__SHIFT 0x0 8149 #define MMSCH_VM_BUSY_STATUS_0__BUSY_MASK 0xFFFFFFFFL 8150 //MMSCH_VM_BUSY_STATUS_1 8151 #define MMSCH_VM_BUSY_STATUS_1__BUSY__SHIFT 0x0 8152 #define MMSCH_VM_BUSY_STATUS_1__BUSY_MASK 0xFFFFFFFFL 8153 //MMSCH_VM_BUSY_STATUS_2 8154 #define MMSCH_VM_BUSY_STATUS_2__BUSY__SHIFT 0x0 8155 #define MMSCH_VM_BUSY_STATUS_2__BUSY_MASK 0xFFFFFFFFL 8156 8157 8158 // addressBlock: aid_uvd0_slmi_adpdec 8159 //UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW 8160 #define UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 8161 #define UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 8162 //UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH 8163 #define UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 8164 #define UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 8165 //UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW 8166 #define UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 8167 #define UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 8168 //UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH 8169 #define UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 8170 #define UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 8171 //UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW 8172 #define UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 8173 #define UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 8174 //UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH 8175 #define UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 8176 #define UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 8177 //UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW 8178 #define UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 8179 #define UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 8180 //UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH 8181 #define UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 8182 #define UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 8183 //UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW 8184 #define UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 8185 #define UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 8186 //UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH 8187 #define UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 8188 #define UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 8189 //UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW 8190 #define UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 8191 #define UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 8192 //UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH 8193 #define UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 8194 #define UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 8195 //UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW 8196 #define UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 8197 #define UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 8198 //UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH 8199 #define UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 8200 #define UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 8201 //UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW 8202 #define UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 8203 #define UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 8204 //UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH 8205 #define UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 8206 #define UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 8207 //UVD_LMI_MMSCH_NC_VMID 8208 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC0_VMID__SHIFT 0x0 8209 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC1_VMID__SHIFT 0x4 8210 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC2_VMID__SHIFT 0x8 8211 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC3_VMID__SHIFT 0xc 8212 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC4_VMID__SHIFT 0x10 8213 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC5_VMID__SHIFT 0x14 8214 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC6_VMID__SHIFT 0x18 8215 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC7_VMID__SHIFT 0x1c 8216 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC0_VMID_MASK 0x0000000FL 8217 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC1_VMID_MASK 0x000000F0L 8218 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC2_VMID_MASK 0x00000F00L 8219 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC3_VMID_MASK 0x0000F000L 8220 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC4_VMID_MASK 0x000F0000L 8221 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC5_VMID_MASK 0x00F00000L 8222 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC6_VMID_MASK 0x0F000000L 8223 #define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC7_VMID_MASK 0xF0000000L 8224 //UVD_LMI_MMSCH_CTRL 8225 #define UVD_LMI_MMSCH_CTRL__MMSCH_DATA_COHERENCY_EN__SHIFT 0x0 8226 #define UVD_LMI_MMSCH_CTRL__MMSCH_VM__SHIFT 0x1 8227 #define UVD_LMI_MMSCH_CTRL__PRIV_CLIENT_MMSCH__SHIFT 0x2 8228 #define UVD_LMI_MMSCH_CTRL__MMSCH_R_MC_SWAP__SHIFT 0x3 8229 #define UVD_LMI_MMSCH_CTRL__MMSCH_W_MC_SWAP__SHIFT 0x5 8230 #define UVD_LMI_MMSCH_CTRL__MMSCH_RD__SHIFT 0x7 8231 #define UVD_LMI_MMSCH_CTRL__MMSCH_WR__SHIFT 0x9 8232 #define UVD_LMI_MMSCH_CTRL__MMSCH_RD_DROP__SHIFT 0xb 8233 #define UVD_LMI_MMSCH_CTRL__MMSCH_WR_DROP__SHIFT 0xc 8234 #define UVD_LMI_MMSCH_CTRL__MMSCH_DATA_COHERENCY_EN_MASK 0x00000001L 8235 #define UVD_LMI_MMSCH_CTRL__MMSCH_VM_MASK 0x00000002L 8236 #define UVD_LMI_MMSCH_CTRL__PRIV_CLIENT_MMSCH_MASK 0x00000004L 8237 #define UVD_LMI_MMSCH_CTRL__MMSCH_R_MC_SWAP_MASK 0x00000018L 8238 #define UVD_LMI_MMSCH_CTRL__MMSCH_W_MC_SWAP_MASK 0x00000060L 8239 #define UVD_LMI_MMSCH_CTRL__MMSCH_RD_MASK 0x00000180L 8240 #define UVD_LMI_MMSCH_CTRL__MMSCH_WR_MASK 0x00000600L 8241 #define UVD_LMI_MMSCH_CTRL__MMSCH_RD_DROP_MASK 0x00000800L 8242 #define UVD_LMI_MMSCH_CTRL__MMSCH_WR_DROP_MASK 0x00001000L 8243 //UVD_MMSCH_LMI_STATUS 8244 #define UVD_MMSCH_LMI_STATUS__LMI_AXI_MMSCH_UNSUPPORTED_LEN_INT__SHIFT 0x0 8245 #define UVD_MMSCH_LMI_STATUS__LMI_AXI_MMSCH_UNSUPPORTED_ADR_ALIGN_INT__SHIFT 0x1 8246 #define UVD_MMSCH_LMI_STATUS__MMSCH_LMI_WRITE_CLEAN__SHIFT 0x2 8247 #define UVD_MMSCH_LMI_STATUS__AXI_MMSCH_ERR_LEN__SHIFT 0x4 8248 #define UVD_MMSCH_LMI_STATUS__AXI_MMSCH_ERR_ADDR_LSBS__SHIFT 0x8 8249 #define UVD_MMSCH_LMI_STATUS__AXI_MMSCH_ERR_AWRITE__SHIFT 0xc 8250 #define UVD_MMSCH_LMI_STATUS__MMSCH_RD_CLEAN__SHIFT 0xd 8251 #define UVD_MMSCH_LMI_STATUS__MMSCH_WR_CLEAN__SHIFT 0xe 8252 #define UVD_MMSCH_LMI_STATUS__LMI_AXI_MMSCH_UNSUPPORTED_LEN_INT_MASK 0x00000001L 8253 #define UVD_MMSCH_LMI_STATUS__LMI_AXI_MMSCH_UNSUPPORTED_ADR_ALIGN_INT_MASK 0x00000002L 8254 #define UVD_MMSCH_LMI_STATUS__MMSCH_LMI_WRITE_CLEAN_MASK 0x00000004L 8255 #define UVD_MMSCH_LMI_STATUS__AXI_MMSCH_ERR_LEN_MASK 0x000000F0L 8256 #define UVD_MMSCH_LMI_STATUS__AXI_MMSCH_ERR_ADDR_LSBS_MASK 0x00000700L 8257 #define UVD_MMSCH_LMI_STATUS__AXI_MMSCH_ERR_AWRITE_MASK 0x00001000L 8258 #define UVD_MMSCH_LMI_STATUS__MMSCH_RD_CLEAN_MASK 0x00002000L 8259 #define UVD_MMSCH_LMI_STATUS__MMSCH_WR_CLEAN_MASK 0x00004000L 8260 //VCN_RAS_CNTL_MMSCH 8261 #define VCN_RAS_CNTL_MMSCH__MMSCH_FATAL_ERROR_EN__SHIFT 0x1 8262 #define VCN_RAS_CNTL_MMSCH__MMSCH_PMI_EN__SHIFT 0x5 8263 #define VCN_RAS_CNTL_MMSCH__MMSCH_REARM__SHIFT 0x9 8264 #define VCN_RAS_CNTL_MMSCH__MMSCH_READY__SHIFT 0x11 8265 #define VCN_RAS_CNTL_MMSCH__MMSCH_FATAL_ERROR_EN_MASK 0x00000002L 8266 #define VCN_RAS_CNTL_MMSCH__MMSCH_PMI_EN_MASK 0x00000020L 8267 #define VCN_RAS_CNTL_MMSCH__MMSCH_REARM_MASK 0x00000200L 8268 #define VCN_RAS_CNTL_MMSCH__MMSCH_READY_MASK 0x00020000L 8269 8270 8271 // addressBlock: aid_uvd0_uvd_jrbc1_uvd_jrbc_dec 8272 //UVD_JRBC1_UVD_JRBC_RB_WPTR 8273 #define UVD_JRBC1_UVD_JRBC_RB_WPTR__RB_WPTR__SHIFT 0x4 8274 #define UVD_JRBC1_UVD_JRBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 8275 //UVD_JRBC1_UVD_JRBC_RB_CNTL 8276 #define UVD_JRBC1_UVD_JRBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x0 8277 #define UVD_JRBC1_UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1 8278 #define UVD_JRBC1_UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x4 8279 #define UVD_JRBC1_UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK 0x00000001L 8280 #define UVD_JRBC1_UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L 8281 #define UVD_JRBC1_UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK 0x0007FFF0L 8282 //UVD_JRBC1_UVD_JRBC_IB_SIZE 8283 #define UVD_JRBC1_UVD_JRBC_IB_SIZE__IB_SIZE__SHIFT 0x4 8284 #define UVD_JRBC1_UVD_JRBC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L 8285 //UVD_JRBC1_UVD_JRBC_URGENT_CNTL 8286 #define UVD_JRBC1_UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0 8287 #define UVD_JRBC1_UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L 8288 //UVD_JRBC1_UVD_JRBC_RB_REF_DATA 8289 #define UVD_JRBC1_UVD_JRBC_RB_REF_DATA__REF_DATA__SHIFT 0x0 8290 #define UVD_JRBC1_UVD_JRBC_RB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL 8291 //UVD_JRBC1_UVD_JRBC_RB_COND_RD_TIMER 8292 #define UVD_JRBC1_UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 8293 #define UVD_JRBC1_UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 8294 #define UVD_JRBC1_UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 8295 #define UVD_JRBC1_UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 8296 #define UVD_JRBC1_UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL 8297 #define UVD_JRBC1_UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L 8298 #define UVD_JRBC1_UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L 8299 #define UVD_JRBC1_UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L 8300 //UVD_JRBC1_UVD_JRBC_SOFT_RESET 8301 #define UVD_JRBC1_UVD_JRBC_SOFT_RESET__RESET__SHIFT 0x0 8302 #define UVD_JRBC1_UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS__SHIFT 0x11 8303 #define UVD_JRBC1_UVD_JRBC_SOFT_RESET__RESET_MASK 0x00000001L 8304 #define UVD_JRBC1_UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS_MASK 0x00020000L 8305 //UVD_JRBC1_UVD_JRBC_STATUS 8306 #define UVD_JRBC1_UVD_JRBC_STATUS__RB_JOB_DONE__SHIFT 0x0 8307 #define UVD_JRBC1_UVD_JRBC_STATUS__IB_JOB_DONE__SHIFT 0x1 8308 #define UVD_JRBC1_UVD_JRBC_STATUS__RB_ILLEGAL_CMD__SHIFT 0x2 8309 #define UVD_JRBC1_UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT__SHIFT 0x3 8310 #define UVD_JRBC1_UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT__SHIFT 0x4 8311 #define UVD_JRBC1_UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT__SHIFT 0x5 8312 #define UVD_JRBC1_UVD_JRBC_STATUS__IB_ILLEGAL_CMD__SHIFT 0x6 8313 #define UVD_JRBC1_UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT__SHIFT 0x7 8314 #define UVD_JRBC1_UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT__SHIFT 0x8 8315 #define UVD_JRBC1_UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT__SHIFT 0x9 8316 #define UVD_JRBC1_UVD_JRBC_STATUS__RB_TRAP_STATUS__SHIFT 0xa 8317 #define UVD_JRBC1_UVD_JRBC_STATUS__PREEMPT_STATUS__SHIFT 0xb 8318 #define UVD_JRBC1_UVD_JRBC_STATUS__IB_TRAP_STATUS__SHIFT 0xc 8319 #define UVD_JRBC1_UVD_JRBC_STATUS__INT_EN__SHIFT 0x10 8320 #define UVD_JRBC1_UVD_JRBC_STATUS__INT_ACK__SHIFT 0x11 8321 #define UVD_JRBC1_UVD_JRBC_STATUS__RB_JOB_DONE_MASK 0x00000001L 8322 #define UVD_JRBC1_UVD_JRBC_STATUS__IB_JOB_DONE_MASK 0x00000002L 8323 #define UVD_JRBC1_UVD_JRBC_STATUS__RB_ILLEGAL_CMD_MASK 0x00000004L 8324 #define UVD_JRBC1_UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT_MASK 0x00000008L 8325 #define UVD_JRBC1_UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT_MASK 0x00000010L 8326 #define UVD_JRBC1_UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT_MASK 0x00000020L 8327 #define UVD_JRBC1_UVD_JRBC_STATUS__IB_ILLEGAL_CMD_MASK 0x00000040L 8328 #define UVD_JRBC1_UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT_MASK 0x00000080L 8329 #define UVD_JRBC1_UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT_MASK 0x00000100L 8330 #define UVD_JRBC1_UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT_MASK 0x00000200L 8331 #define UVD_JRBC1_UVD_JRBC_STATUS__RB_TRAP_STATUS_MASK 0x00000400L 8332 #define UVD_JRBC1_UVD_JRBC_STATUS__PREEMPT_STATUS_MASK 0x00000800L 8333 #define UVD_JRBC1_UVD_JRBC_STATUS__IB_TRAP_STATUS_MASK 0x00001000L 8334 #define UVD_JRBC1_UVD_JRBC_STATUS__INT_EN_MASK 0x00010000L 8335 #define UVD_JRBC1_UVD_JRBC_STATUS__INT_ACK_MASK 0x00020000L 8336 //UVD_JRBC1_UVD_JRBC_RB_RPTR 8337 #define UVD_JRBC1_UVD_JRBC_RB_RPTR__RB_RPTR__SHIFT 0x4 8338 #define UVD_JRBC1_UVD_JRBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 8339 //UVD_JRBC1_UVD_JRBC_RB_BUF_STATUS 8340 #define UVD_JRBC1_UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0 8341 #define UVD_JRBC1_UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10 8342 #define UVD_JRBC1_UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x18 8343 #define UVD_JRBC1_UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID_MASK 0x0000FFFFL 8344 #define UVD_JRBC1_UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x000F0000L 8345 #define UVD_JRBC1_UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x03000000L 8346 //UVD_JRBC1_UVD_JRBC_IB_BUF_STATUS 8347 #define UVD_JRBC1_UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID__SHIFT 0x0 8348 #define UVD_JRBC1_UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x10 8349 #define UVD_JRBC1_UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x18 8350 #define UVD_JRBC1_UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FFFFL 8351 #define UVD_JRBC1_UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x000F0000L 8352 #define UVD_JRBC1_UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x03000000L 8353 //UVD_JRBC1_UVD_JRBC_IB_SIZE_UPDATE 8354 #define UVD_JRBC1_UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4 8355 #define UVD_JRBC1_UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L 8356 //UVD_JRBC1_UVD_JRBC_IB_COND_RD_TIMER 8357 #define UVD_JRBC1_UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 8358 #define UVD_JRBC1_UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 8359 #define UVD_JRBC1_UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 8360 #define UVD_JRBC1_UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 8361 #define UVD_JRBC1_UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL 8362 #define UVD_JRBC1_UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L 8363 #define UVD_JRBC1_UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L 8364 #define UVD_JRBC1_UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L 8365 //UVD_JRBC1_UVD_JRBC_IB_REF_DATA 8366 #define UVD_JRBC1_UVD_JRBC_IB_REF_DATA__REF_DATA__SHIFT 0x0 8367 #define UVD_JRBC1_UVD_JRBC_IB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL 8368 //UVD_JRBC1_UVD_JPEG_PREEMPT_CMD 8369 #define UVD_JRBC1_UVD_JPEG_PREEMPT_CMD__PREEMPT_EN__SHIFT 0x0 8370 #define UVD_JRBC1_UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE__SHIFT 0x1 8371 #define UVD_JRBC1_UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD__SHIFT 0x2 8372 #define UVD_JRBC1_UVD_JPEG_PREEMPT_CMD__PREEMPT_EN_MASK 0x00000001L 8373 #define UVD_JRBC1_UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE_MASK 0x00000002L 8374 #define UVD_JRBC1_UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD_MASK 0x00000004L 8375 //UVD_JRBC1_UVD_JPEG_PREEMPT_FENCE_DATA0 8376 #define UVD_JRBC1_UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0__SHIFT 0x0 8377 #define UVD_JRBC1_UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0_MASK 0xFFFFFFFFL 8378 //UVD_JRBC1_UVD_JPEG_PREEMPT_FENCE_DATA1 8379 #define UVD_JRBC1_UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1__SHIFT 0x0 8380 #define UVD_JRBC1_UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1_MASK 0xFFFFFFFFL 8381 //UVD_JRBC1_UVD_JRBC_RB_SIZE 8382 #define UVD_JRBC1_UVD_JRBC_RB_SIZE__RB_SIZE__SHIFT 0x4 8383 #define UVD_JRBC1_UVD_JRBC_RB_SIZE__RB_SIZE_MASK 0x00FFFFF0L 8384 //UVD_JRBC1_UVD_JRBC_SCRATCH0 8385 #define UVD_JRBC1_UVD_JRBC_SCRATCH0__SCRATCH0__SHIFT 0x0 8386 #define UVD_JRBC1_UVD_JRBC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL 8387 8388 8389 // addressBlock: aid_uvd0_uvd_jrbc2_uvd_jrbc_dec 8390 //UVD_JRBC2_UVD_JRBC_RB_WPTR 8391 #define UVD_JRBC2_UVD_JRBC_RB_WPTR__RB_WPTR__SHIFT 0x4 8392 #define UVD_JRBC2_UVD_JRBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 8393 //UVD_JRBC2_UVD_JRBC_RB_CNTL 8394 #define UVD_JRBC2_UVD_JRBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x0 8395 #define UVD_JRBC2_UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1 8396 #define UVD_JRBC2_UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x4 8397 #define UVD_JRBC2_UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK 0x00000001L 8398 #define UVD_JRBC2_UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L 8399 #define UVD_JRBC2_UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK 0x0007FFF0L 8400 //UVD_JRBC2_UVD_JRBC_IB_SIZE 8401 #define UVD_JRBC2_UVD_JRBC_IB_SIZE__IB_SIZE__SHIFT 0x4 8402 #define UVD_JRBC2_UVD_JRBC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L 8403 //UVD_JRBC2_UVD_JRBC_URGENT_CNTL 8404 #define UVD_JRBC2_UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0 8405 #define UVD_JRBC2_UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L 8406 //UVD_JRBC2_UVD_JRBC_RB_REF_DATA 8407 #define UVD_JRBC2_UVD_JRBC_RB_REF_DATA__REF_DATA__SHIFT 0x0 8408 #define UVD_JRBC2_UVD_JRBC_RB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL 8409 //UVD_JRBC2_UVD_JRBC_RB_COND_RD_TIMER 8410 #define UVD_JRBC2_UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 8411 #define UVD_JRBC2_UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 8412 #define UVD_JRBC2_UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 8413 #define UVD_JRBC2_UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 8414 #define UVD_JRBC2_UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL 8415 #define UVD_JRBC2_UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L 8416 #define UVD_JRBC2_UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L 8417 #define UVD_JRBC2_UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L 8418 //UVD_JRBC2_UVD_JRBC_SOFT_RESET 8419 #define UVD_JRBC2_UVD_JRBC_SOFT_RESET__RESET__SHIFT 0x0 8420 #define UVD_JRBC2_UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS__SHIFT 0x11 8421 #define UVD_JRBC2_UVD_JRBC_SOFT_RESET__RESET_MASK 0x00000001L 8422 #define UVD_JRBC2_UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS_MASK 0x00020000L 8423 //UVD_JRBC2_UVD_JRBC_STATUS 8424 #define UVD_JRBC2_UVD_JRBC_STATUS__RB_JOB_DONE__SHIFT 0x0 8425 #define UVD_JRBC2_UVD_JRBC_STATUS__IB_JOB_DONE__SHIFT 0x1 8426 #define UVD_JRBC2_UVD_JRBC_STATUS__RB_ILLEGAL_CMD__SHIFT 0x2 8427 #define UVD_JRBC2_UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT__SHIFT 0x3 8428 #define UVD_JRBC2_UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT__SHIFT 0x4 8429 #define UVD_JRBC2_UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT__SHIFT 0x5 8430 #define UVD_JRBC2_UVD_JRBC_STATUS__IB_ILLEGAL_CMD__SHIFT 0x6 8431 #define UVD_JRBC2_UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT__SHIFT 0x7 8432 #define UVD_JRBC2_UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT__SHIFT 0x8 8433 #define UVD_JRBC2_UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT__SHIFT 0x9 8434 #define UVD_JRBC2_UVD_JRBC_STATUS__RB_TRAP_STATUS__SHIFT 0xa 8435 #define UVD_JRBC2_UVD_JRBC_STATUS__PREEMPT_STATUS__SHIFT 0xb 8436 #define UVD_JRBC2_UVD_JRBC_STATUS__IB_TRAP_STATUS__SHIFT 0xc 8437 #define UVD_JRBC2_UVD_JRBC_STATUS__INT_EN__SHIFT 0x10 8438 #define UVD_JRBC2_UVD_JRBC_STATUS__INT_ACK__SHIFT 0x11 8439 #define UVD_JRBC2_UVD_JRBC_STATUS__RB_JOB_DONE_MASK 0x00000001L 8440 #define UVD_JRBC2_UVD_JRBC_STATUS__IB_JOB_DONE_MASK 0x00000002L 8441 #define UVD_JRBC2_UVD_JRBC_STATUS__RB_ILLEGAL_CMD_MASK 0x00000004L 8442 #define UVD_JRBC2_UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT_MASK 0x00000008L 8443 #define UVD_JRBC2_UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT_MASK 0x00000010L 8444 #define UVD_JRBC2_UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT_MASK 0x00000020L 8445 #define UVD_JRBC2_UVD_JRBC_STATUS__IB_ILLEGAL_CMD_MASK 0x00000040L 8446 #define UVD_JRBC2_UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT_MASK 0x00000080L 8447 #define UVD_JRBC2_UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT_MASK 0x00000100L 8448 #define UVD_JRBC2_UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT_MASK 0x00000200L 8449 #define UVD_JRBC2_UVD_JRBC_STATUS__RB_TRAP_STATUS_MASK 0x00000400L 8450 #define UVD_JRBC2_UVD_JRBC_STATUS__PREEMPT_STATUS_MASK 0x00000800L 8451 #define UVD_JRBC2_UVD_JRBC_STATUS__IB_TRAP_STATUS_MASK 0x00001000L 8452 #define UVD_JRBC2_UVD_JRBC_STATUS__INT_EN_MASK 0x00010000L 8453 #define UVD_JRBC2_UVD_JRBC_STATUS__INT_ACK_MASK 0x00020000L 8454 //UVD_JRBC2_UVD_JRBC_RB_RPTR 8455 #define UVD_JRBC2_UVD_JRBC_RB_RPTR__RB_RPTR__SHIFT 0x4 8456 #define UVD_JRBC2_UVD_JRBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 8457 //UVD_JRBC2_UVD_JRBC_RB_BUF_STATUS 8458 #define UVD_JRBC2_UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0 8459 #define UVD_JRBC2_UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10 8460 #define UVD_JRBC2_UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x18 8461 #define UVD_JRBC2_UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID_MASK 0x0000FFFFL 8462 #define UVD_JRBC2_UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x000F0000L 8463 #define UVD_JRBC2_UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x03000000L 8464 //UVD_JRBC2_UVD_JRBC_IB_BUF_STATUS 8465 #define UVD_JRBC2_UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID__SHIFT 0x0 8466 #define UVD_JRBC2_UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x10 8467 #define UVD_JRBC2_UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x18 8468 #define UVD_JRBC2_UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FFFFL 8469 #define UVD_JRBC2_UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x000F0000L 8470 #define UVD_JRBC2_UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x03000000L 8471 //UVD_JRBC2_UVD_JRBC_IB_SIZE_UPDATE 8472 #define UVD_JRBC2_UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4 8473 #define UVD_JRBC2_UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L 8474 //UVD_JRBC2_UVD_JRBC_IB_COND_RD_TIMER 8475 #define UVD_JRBC2_UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 8476 #define UVD_JRBC2_UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 8477 #define UVD_JRBC2_UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 8478 #define UVD_JRBC2_UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 8479 #define UVD_JRBC2_UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL 8480 #define UVD_JRBC2_UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L 8481 #define UVD_JRBC2_UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L 8482 #define UVD_JRBC2_UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L 8483 //UVD_JRBC2_UVD_JRBC_IB_REF_DATA 8484 #define UVD_JRBC2_UVD_JRBC_IB_REF_DATA__REF_DATA__SHIFT 0x0 8485 #define UVD_JRBC2_UVD_JRBC_IB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL 8486 //UVD_JRBC2_UVD_JPEG_PREEMPT_CMD 8487 #define UVD_JRBC2_UVD_JPEG_PREEMPT_CMD__PREEMPT_EN__SHIFT 0x0 8488 #define UVD_JRBC2_UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE__SHIFT 0x1 8489 #define UVD_JRBC2_UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD__SHIFT 0x2 8490 #define UVD_JRBC2_UVD_JPEG_PREEMPT_CMD__PREEMPT_EN_MASK 0x00000001L 8491 #define UVD_JRBC2_UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE_MASK 0x00000002L 8492 #define UVD_JRBC2_UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD_MASK 0x00000004L 8493 //UVD_JRBC2_UVD_JPEG_PREEMPT_FENCE_DATA0 8494 #define UVD_JRBC2_UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0__SHIFT 0x0 8495 #define UVD_JRBC2_UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0_MASK 0xFFFFFFFFL 8496 //UVD_JRBC2_UVD_JPEG_PREEMPT_FENCE_DATA1 8497 #define UVD_JRBC2_UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1__SHIFT 0x0 8498 #define UVD_JRBC2_UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1_MASK 0xFFFFFFFFL 8499 //UVD_JRBC2_UVD_JRBC_RB_SIZE 8500 #define UVD_JRBC2_UVD_JRBC_RB_SIZE__RB_SIZE__SHIFT 0x4 8501 #define UVD_JRBC2_UVD_JRBC_RB_SIZE__RB_SIZE_MASK 0x00FFFFF0L 8502 //UVD_JRBC2_UVD_JRBC_SCRATCH0 8503 #define UVD_JRBC2_UVD_JRBC_SCRATCH0__SCRATCH0__SHIFT 0x0 8504 #define UVD_JRBC2_UVD_JRBC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL 8505 8506 8507 // addressBlock: aid_uvd0_uvd_jrbc3_uvd_jrbc_dec 8508 //UVD_JRBC3_UVD_JRBC_RB_WPTR 8509 #define UVD_JRBC3_UVD_JRBC_RB_WPTR__RB_WPTR__SHIFT 0x4 8510 #define UVD_JRBC3_UVD_JRBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 8511 //UVD_JRBC3_UVD_JRBC_RB_CNTL 8512 #define UVD_JRBC3_UVD_JRBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x0 8513 #define UVD_JRBC3_UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1 8514 #define UVD_JRBC3_UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x4 8515 #define UVD_JRBC3_UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK 0x00000001L 8516 #define UVD_JRBC3_UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L 8517 #define UVD_JRBC3_UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK 0x0007FFF0L 8518 //UVD_JRBC3_UVD_JRBC_IB_SIZE 8519 #define UVD_JRBC3_UVD_JRBC_IB_SIZE__IB_SIZE__SHIFT 0x4 8520 #define UVD_JRBC3_UVD_JRBC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L 8521 //UVD_JRBC3_UVD_JRBC_URGENT_CNTL 8522 #define UVD_JRBC3_UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0 8523 #define UVD_JRBC3_UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L 8524 //UVD_JRBC3_UVD_JRBC_RB_REF_DATA 8525 #define UVD_JRBC3_UVD_JRBC_RB_REF_DATA__REF_DATA__SHIFT 0x0 8526 #define UVD_JRBC3_UVD_JRBC_RB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL 8527 //UVD_JRBC3_UVD_JRBC_RB_COND_RD_TIMER 8528 #define UVD_JRBC3_UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 8529 #define UVD_JRBC3_UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 8530 #define UVD_JRBC3_UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 8531 #define UVD_JRBC3_UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 8532 #define UVD_JRBC3_UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL 8533 #define UVD_JRBC3_UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L 8534 #define UVD_JRBC3_UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L 8535 #define UVD_JRBC3_UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L 8536 //UVD_JRBC3_UVD_JRBC_SOFT_RESET 8537 #define UVD_JRBC3_UVD_JRBC_SOFT_RESET__RESET__SHIFT 0x0 8538 #define UVD_JRBC3_UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS__SHIFT 0x11 8539 #define UVD_JRBC3_UVD_JRBC_SOFT_RESET__RESET_MASK 0x00000001L 8540 #define UVD_JRBC3_UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS_MASK 0x00020000L 8541 //UVD_JRBC3_UVD_JRBC_STATUS 8542 #define UVD_JRBC3_UVD_JRBC_STATUS__RB_JOB_DONE__SHIFT 0x0 8543 #define UVD_JRBC3_UVD_JRBC_STATUS__IB_JOB_DONE__SHIFT 0x1 8544 #define UVD_JRBC3_UVD_JRBC_STATUS__RB_ILLEGAL_CMD__SHIFT 0x2 8545 #define UVD_JRBC3_UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT__SHIFT 0x3 8546 #define UVD_JRBC3_UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT__SHIFT 0x4 8547 #define UVD_JRBC3_UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT__SHIFT 0x5 8548 #define UVD_JRBC3_UVD_JRBC_STATUS__IB_ILLEGAL_CMD__SHIFT 0x6 8549 #define UVD_JRBC3_UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT__SHIFT 0x7 8550 #define UVD_JRBC3_UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT__SHIFT 0x8 8551 #define UVD_JRBC3_UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT__SHIFT 0x9 8552 #define UVD_JRBC3_UVD_JRBC_STATUS__RB_TRAP_STATUS__SHIFT 0xa 8553 #define UVD_JRBC3_UVD_JRBC_STATUS__PREEMPT_STATUS__SHIFT 0xb 8554 #define UVD_JRBC3_UVD_JRBC_STATUS__IB_TRAP_STATUS__SHIFT 0xc 8555 #define UVD_JRBC3_UVD_JRBC_STATUS__INT_EN__SHIFT 0x10 8556 #define UVD_JRBC3_UVD_JRBC_STATUS__INT_ACK__SHIFT 0x11 8557 #define UVD_JRBC3_UVD_JRBC_STATUS__RB_JOB_DONE_MASK 0x00000001L 8558 #define UVD_JRBC3_UVD_JRBC_STATUS__IB_JOB_DONE_MASK 0x00000002L 8559 #define UVD_JRBC3_UVD_JRBC_STATUS__RB_ILLEGAL_CMD_MASK 0x00000004L 8560 #define UVD_JRBC3_UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT_MASK 0x00000008L 8561 #define UVD_JRBC3_UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT_MASK 0x00000010L 8562 #define UVD_JRBC3_UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT_MASK 0x00000020L 8563 #define UVD_JRBC3_UVD_JRBC_STATUS__IB_ILLEGAL_CMD_MASK 0x00000040L 8564 #define UVD_JRBC3_UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT_MASK 0x00000080L 8565 #define UVD_JRBC3_UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT_MASK 0x00000100L 8566 #define UVD_JRBC3_UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT_MASK 0x00000200L 8567 #define UVD_JRBC3_UVD_JRBC_STATUS__RB_TRAP_STATUS_MASK 0x00000400L 8568 #define UVD_JRBC3_UVD_JRBC_STATUS__PREEMPT_STATUS_MASK 0x00000800L 8569 #define UVD_JRBC3_UVD_JRBC_STATUS__IB_TRAP_STATUS_MASK 0x00001000L 8570 #define UVD_JRBC3_UVD_JRBC_STATUS__INT_EN_MASK 0x00010000L 8571 #define UVD_JRBC3_UVD_JRBC_STATUS__INT_ACK_MASK 0x00020000L 8572 //UVD_JRBC3_UVD_JRBC_RB_RPTR 8573 #define UVD_JRBC3_UVD_JRBC_RB_RPTR__RB_RPTR__SHIFT 0x4 8574 #define UVD_JRBC3_UVD_JRBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 8575 //UVD_JRBC3_UVD_JRBC_RB_BUF_STATUS 8576 #define UVD_JRBC3_UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0 8577 #define UVD_JRBC3_UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10 8578 #define UVD_JRBC3_UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x18 8579 #define UVD_JRBC3_UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID_MASK 0x0000FFFFL 8580 #define UVD_JRBC3_UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x000F0000L 8581 #define UVD_JRBC3_UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x03000000L 8582 //UVD_JRBC3_UVD_JRBC_IB_BUF_STATUS 8583 #define UVD_JRBC3_UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID__SHIFT 0x0 8584 #define UVD_JRBC3_UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x10 8585 #define UVD_JRBC3_UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x18 8586 #define UVD_JRBC3_UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FFFFL 8587 #define UVD_JRBC3_UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x000F0000L 8588 #define UVD_JRBC3_UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x03000000L 8589 //UVD_JRBC3_UVD_JRBC_IB_SIZE_UPDATE 8590 #define UVD_JRBC3_UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4 8591 #define UVD_JRBC3_UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L 8592 //UVD_JRBC3_UVD_JRBC_IB_COND_RD_TIMER 8593 #define UVD_JRBC3_UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 8594 #define UVD_JRBC3_UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 8595 #define UVD_JRBC3_UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 8596 #define UVD_JRBC3_UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 8597 #define UVD_JRBC3_UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL 8598 #define UVD_JRBC3_UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L 8599 #define UVD_JRBC3_UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L 8600 #define UVD_JRBC3_UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L 8601 //UVD_JRBC3_UVD_JRBC_IB_REF_DATA 8602 #define UVD_JRBC3_UVD_JRBC_IB_REF_DATA__REF_DATA__SHIFT 0x0 8603 #define UVD_JRBC3_UVD_JRBC_IB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL 8604 //UVD_JRBC3_UVD_JPEG_PREEMPT_CMD 8605 #define UVD_JRBC3_UVD_JPEG_PREEMPT_CMD__PREEMPT_EN__SHIFT 0x0 8606 #define UVD_JRBC3_UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE__SHIFT 0x1 8607 #define UVD_JRBC3_UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD__SHIFT 0x2 8608 #define UVD_JRBC3_UVD_JPEG_PREEMPT_CMD__PREEMPT_EN_MASK 0x00000001L 8609 #define UVD_JRBC3_UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE_MASK 0x00000002L 8610 #define UVD_JRBC3_UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD_MASK 0x00000004L 8611 //UVD_JRBC3_UVD_JPEG_PREEMPT_FENCE_DATA0 8612 #define UVD_JRBC3_UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0__SHIFT 0x0 8613 #define UVD_JRBC3_UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0_MASK 0xFFFFFFFFL 8614 //UVD_JRBC3_UVD_JPEG_PREEMPT_FENCE_DATA1 8615 #define UVD_JRBC3_UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1__SHIFT 0x0 8616 #define UVD_JRBC3_UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1_MASK 0xFFFFFFFFL 8617 //UVD_JRBC3_UVD_JRBC_RB_SIZE 8618 #define UVD_JRBC3_UVD_JRBC_RB_SIZE__RB_SIZE__SHIFT 0x4 8619 #define UVD_JRBC3_UVD_JRBC_RB_SIZE__RB_SIZE_MASK 0x00FFFFF0L 8620 //UVD_JRBC3_UVD_JRBC_SCRATCH0 8621 #define UVD_JRBC3_UVD_JRBC_SCRATCH0__SCRATCH0__SHIFT 0x0 8622 #define UVD_JRBC3_UVD_JRBC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL 8623 8624 8625 // addressBlock: aid_uvd0_uvd_jrbc4_uvd_jrbc_dec 8626 //UVD_JRBC4_UVD_JRBC_RB_WPTR 8627 #define UVD_JRBC4_UVD_JRBC_RB_WPTR__RB_WPTR__SHIFT 0x4 8628 #define UVD_JRBC4_UVD_JRBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 8629 //UVD_JRBC4_UVD_JRBC_RB_CNTL 8630 #define UVD_JRBC4_UVD_JRBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x0 8631 #define UVD_JRBC4_UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1 8632 #define UVD_JRBC4_UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x4 8633 #define UVD_JRBC4_UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK 0x00000001L 8634 #define UVD_JRBC4_UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L 8635 #define UVD_JRBC4_UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK 0x0007FFF0L 8636 //UVD_JRBC4_UVD_JRBC_IB_SIZE 8637 #define UVD_JRBC4_UVD_JRBC_IB_SIZE__IB_SIZE__SHIFT 0x4 8638 #define UVD_JRBC4_UVD_JRBC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L 8639 //UVD_JRBC4_UVD_JRBC_URGENT_CNTL 8640 #define UVD_JRBC4_UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0 8641 #define UVD_JRBC4_UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L 8642 //UVD_JRBC4_UVD_JRBC_RB_REF_DATA 8643 #define UVD_JRBC4_UVD_JRBC_RB_REF_DATA__REF_DATA__SHIFT 0x0 8644 #define UVD_JRBC4_UVD_JRBC_RB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL 8645 //UVD_JRBC4_UVD_JRBC_RB_COND_RD_TIMER 8646 #define UVD_JRBC4_UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 8647 #define UVD_JRBC4_UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 8648 #define UVD_JRBC4_UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 8649 #define UVD_JRBC4_UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 8650 #define UVD_JRBC4_UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL 8651 #define UVD_JRBC4_UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L 8652 #define UVD_JRBC4_UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L 8653 #define UVD_JRBC4_UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L 8654 //UVD_JRBC4_UVD_JRBC_SOFT_RESET 8655 #define UVD_JRBC4_UVD_JRBC_SOFT_RESET__RESET__SHIFT 0x0 8656 #define UVD_JRBC4_UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS__SHIFT 0x11 8657 #define UVD_JRBC4_UVD_JRBC_SOFT_RESET__RESET_MASK 0x00000001L 8658 #define UVD_JRBC4_UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS_MASK 0x00020000L 8659 //UVD_JRBC4_UVD_JRBC_STATUS 8660 #define UVD_JRBC4_UVD_JRBC_STATUS__RB_JOB_DONE__SHIFT 0x0 8661 #define UVD_JRBC4_UVD_JRBC_STATUS__IB_JOB_DONE__SHIFT 0x1 8662 #define UVD_JRBC4_UVD_JRBC_STATUS__RB_ILLEGAL_CMD__SHIFT 0x2 8663 #define UVD_JRBC4_UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT__SHIFT 0x3 8664 #define UVD_JRBC4_UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT__SHIFT 0x4 8665 #define UVD_JRBC4_UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT__SHIFT 0x5 8666 #define UVD_JRBC4_UVD_JRBC_STATUS__IB_ILLEGAL_CMD__SHIFT 0x6 8667 #define UVD_JRBC4_UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT__SHIFT 0x7 8668 #define UVD_JRBC4_UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT__SHIFT 0x8 8669 #define UVD_JRBC4_UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT__SHIFT 0x9 8670 #define UVD_JRBC4_UVD_JRBC_STATUS__RB_TRAP_STATUS__SHIFT 0xa 8671 #define UVD_JRBC4_UVD_JRBC_STATUS__PREEMPT_STATUS__SHIFT 0xb 8672 #define UVD_JRBC4_UVD_JRBC_STATUS__IB_TRAP_STATUS__SHIFT 0xc 8673 #define UVD_JRBC4_UVD_JRBC_STATUS__INT_EN__SHIFT 0x10 8674 #define UVD_JRBC4_UVD_JRBC_STATUS__INT_ACK__SHIFT 0x11 8675 #define UVD_JRBC4_UVD_JRBC_STATUS__RB_JOB_DONE_MASK 0x00000001L 8676 #define UVD_JRBC4_UVD_JRBC_STATUS__IB_JOB_DONE_MASK 0x00000002L 8677 #define UVD_JRBC4_UVD_JRBC_STATUS__RB_ILLEGAL_CMD_MASK 0x00000004L 8678 #define UVD_JRBC4_UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT_MASK 0x00000008L 8679 #define UVD_JRBC4_UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT_MASK 0x00000010L 8680 #define UVD_JRBC4_UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT_MASK 0x00000020L 8681 #define UVD_JRBC4_UVD_JRBC_STATUS__IB_ILLEGAL_CMD_MASK 0x00000040L 8682 #define UVD_JRBC4_UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT_MASK 0x00000080L 8683 #define UVD_JRBC4_UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT_MASK 0x00000100L 8684 #define UVD_JRBC4_UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT_MASK 0x00000200L 8685 #define UVD_JRBC4_UVD_JRBC_STATUS__RB_TRAP_STATUS_MASK 0x00000400L 8686 #define UVD_JRBC4_UVD_JRBC_STATUS__PREEMPT_STATUS_MASK 0x00000800L 8687 #define UVD_JRBC4_UVD_JRBC_STATUS__IB_TRAP_STATUS_MASK 0x00001000L 8688 #define UVD_JRBC4_UVD_JRBC_STATUS__INT_EN_MASK 0x00010000L 8689 #define UVD_JRBC4_UVD_JRBC_STATUS__INT_ACK_MASK 0x00020000L 8690 //UVD_JRBC4_UVD_JRBC_RB_RPTR 8691 #define UVD_JRBC4_UVD_JRBC_RB_RPTR__RB_RPTR__SHIFT 0x4 8692 #define UVD_JRBC4_UVD_JRBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 8693 //UVD_JRBC4_UVD_JRBC_RB_BUF_STATUS 8694 #define UVD_JRBC4_UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0 8695 #define UVD_JRBC4_UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10 8696 #define UVD_JRBC4_UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x18 8697 #define UVD_JRBC4_UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID_MASK 0x0000FFFFL 8698 #define UVD_JRBC4_UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x000F0000L 8699 #define UVD_JRBC4_UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x03000000L 8700 //UVD_JRBC4_UVD_JRBC_IB_BUF_STATUS 8701 #define UVD_JRBC4_UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID__SHIFT 0x0 8702 #define UVD_JRBC4_UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x10 8703 #define UVD_JRBC4_UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x18 8704 #define UVD_JRBC4_UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FFFFL 8705 #define UVD_JRBC4_UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x000F0000L 8706 #define UVD_JRBC4_UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x03000000L 8707 //UVD_JRBC4_UVD_JRBC_IB_SIZE_UPDATE 8708 #define UVD_JRBC4_UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4 8709 #define UVD_JRBC4_UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L 8710 //UVD_JRBC4_UVD_JRBC_IB_COND_RD_TIMER 8711 #define UVD_JRBC4_UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 8712 #define UVD_JRBC4_UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 8713 #define UVD_JRBC4_UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 8714 #define UVD_JRBC4_UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 8715 #define UVD_JRBC4_UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL 8716 #define UVD_JRBC4_UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L 8717 #define UVD_JRBC4_UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L 8718 #define UVD_JRBC4_UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L 8719 //UVD_JRBC4_UVD_JRBC_IB_REF_DATA 8720 #define UVD_JRBC4_UVD_JRBC_IB_REF_DATA__REF_DATA__SHIFT 0x0 8721 #define UVD_JRBC4_UVD_JRBC_IB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL 8722 //UVD_JRBC4_UVD_JPEG_PREEMPT_CMD 8723 #define UVD_JRBC4_UVD_JPEG_PREEMPT_CMD__PREEMPT_EN__SHIFT 0x0 8724 #define UVD_JRBC4_UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE__SHIFT 0x1 8725 #define UVD_JRBC4_UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD__SHIFT 0x2 8726 #define UVD_JRBC4_UVD_JPEG_PREEMPT_CMD__PREEMPT_EN_MASK 0x00000001L 8727 #define UVD_JRBC4_UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE_MASK 0x00000002L 8728 #define UVD_JRBC4_UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD_MASK 0x00000004L 8729 //UVD_JRBC4_UVD_JPEG_PREEMPT_FENCE_DATA0 8730 #define UVD_JRBC4_UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0__SHIFT 0x0 8731 #define UVD_JRBC4_UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0_MASK 0xFFFFFFFFL 8732 //UVD_JRBC4_UVD_JPEG_PREEMPT_FENCE_DATA1 8733 #define UVD_JRBC4_UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1__SHIFT 0x0 8734 #define UVD_JRBC4_UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1_MASK 0xFFFFFFFFL 8735 //UVD_JRBC4_UVD_JRBC_RB_SIZE 8736 #define UVD_JRBC4_UVD_JRBC_RB_SIZE__RB_SIZE__SHIFT 0x4 8737 #define UVD_JRBC4_UVD_JRBC_RB_SIZE__RB_SIZE_MASK 0x00FFFFF0L 8738 //UVD_JRBC4_UVD_JRBC_SCRATCH0 8739 #define UVD_JRBC4_UVD_JRBC_SCRATCH0__SCRATCH0__SHIFT 0x0 8740 #define UVD_JRBC4_UVD_JRBC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL 8741 8742 8743 // addressBlock: aid_uvd0_uvd_jrbc5_uvd_jrbc_dec 8744 //UVD_JRBC5_UVD_JRBC_RB_WPTR 8745 #define UVD_JRBC5_UVD_JRBC_RB_WPTR__RB_WPTR__SHIFT 0x4 8746 #define UVD_JRBC5_UVD_JRBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 8747 //UVD_JRBC5_UVD_JRBC_RB_CNTL 8748 #define UVD_JRBC5_UVD_JRBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x0 8749 #define UVD_JRBC5_UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1 8750 #define UVD_JRBC5_UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x4 8751 #define UVD_JRBC5_UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK 0x00000001L 8752 #define UVD_JRBC5_UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L 8753 #define UVD_JRBC5_UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK 0x0007FFF0L 8754 //UVD_JRBC5_UVD_JRBC_IB_SIZE 8755 #define UVD_JRBC5_UVD_JRBC_IB_SIZE__IB_SIZE__SHIFT 0x4 8756 #define UVD_JRBC5_UVD_JRBC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L 8757 //UVD_JRBC5_UVD_JRBC_URGENT_CNTL 8758 #define UVD_JRBC5_UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0 8759 #define UVD_JRBC5_UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L 8760 //UVD_JRBC5_UVD_JRBC_RB_REF_DATA 8761 #define UVD_JRBC5_UVD_JRBC_RB_REF_DATA__REF_DATA__SHIFT 0x0 8762 #define UVD_JRBC5_UVD_JRBC_RB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL 8763 //UVD_JRBC5_UVD_JRBC_RB_COND_RD_TIMER 8764 #define UVD_JRBC5_UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 8765 #define UVD_JRBC5_UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 8766 #define UVD_JRBC5_UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 8767 #define UVD_JRBC5_UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 8768 #define UVD_JRBC5_UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL 8769 #define UVD_JRBC5_UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L 8770 #define UVD_JRBC5_UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L 8771 #define UVD_JRBC5_UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L 8772 //UVD_JRBC5_UVD_JRBC_SOFT_RESET 8773 #define UVD_JRBC5_UVD_JRBC_SOFT_RESET__RESET__SHIFT 0x0 8774 #define UVD_JRBC5_UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS__SHIFT 0x11 8775 #define UVD_JRBC5_UVD_JRBC_SOFT_RESET__RESET_MASK 0x00000001L 8776 #define UVD_JRBC5_UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS_MASK 0x00020000L 8777 //UVD_JRBC5_UVD_JRBC_STATUS 8778 #define UVD_JRBC5_UVD_JRBC_STATUS__RB_JOB_DONE__SHIFT 0x0 8779 #define UVD_JRBC5_UVD_JRBC_STATUS__IB_JOB_DONE__SHIFT 0x1 8780 #define UVD_JRBC5_UVD_JRBC_STATUS__RB_ILLEGAL_CMD__SHIFT 0x2 8781 #define UVD_JRBC5_UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT__SHIFT 0x3 8782 #define UVD_JRBC5_UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT__SHIFT 0x4 8783 #define UVD_JRBC5_UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT__SHIFT 0x5 8784 #define UVD_JRBC5_UVD_JRBC_STATUS__IB_ILLEGAL_CMD__SHIFT 0x6 8785 #define UVD_JRBC5_UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT__SHIFT 0x7 8786 #define UVD_JRBC5_UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT__SHIFT 0x8 8787 #define UVD_JRBC5_UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT__SHIFT 0x9 8788 #define UVD_JRBC5_UVD_JRBC_STATUS__RB_TRAP_STATUS__SHIFT 0xa 8789 #define UVD_JRBC5_UVD_JRBC_STATUS__PREEMPT_STATUS__SHIFT 0xb 8790 #define UVD_JRBC5_UVD_JRBC_STATUS__IB_TRAP_STATUS__SHIFT 0xc 8791 #define UVD_JRBC5_UVD_JRBC_STATUS__INT_EN__SHIFT 0x10 8792 #define UVD_JRBC5_UVD_JRBC_STATUS__INT_ACK__SHIFT 0x11 8793 #define UVD_JRBC5_UVD_JRBC_STATUS__RB_JOB_DONE_MASK 0x00000001L 8794 #define UVD_JRBC5_UVD_JRBC_STATUS__IB_JOB_DONE_MASK 0x00000002L 8795 #define UVD_JRBC5_UVD_JRBC_STATUS__RB_ILLEGAL_CMD_MASK 0x00000004L 8796 #define UVD_JRBC5_UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT_MASK 0x00000008L 8797 #define UVD_JRBC5_UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT_MASK 0x00000010L 8798 #define UVD_JRBC5_UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT_MASK 0x00000020L 8799 #define UVD_JRBC5_UVD_JRBC_STATUS__IB_ILLEGAL_CMD_MASK 0x00000040L 8800 #define UVD_JRBC5_UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT_MASK 0x00000080L 8801 #define UVD_JRBC5_UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT_MASK 0x00000100L 8802 #define UVD_JRBC5_UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT_MASK 0x00000200L 8803 #define UVD_JRBC5_UVD_JRBC_STATUS__RB_TRAP_STATUS_MASK 0x00000400L 8804 #define UVD_JRBC5_UVD_JRBC_STATUS__PREEMPT_STATUS_MASK 0x00000800L 8805 #define UVD_JRBC5_UVD_JRBC_STATUS__IB_TRAP_STATUS_MASK 0x00001000L 8806 #define UVD_JRBC5_UVD_JRBC_STATUS__INT_EN_MASK 0x00010000L 8807 #define UVD_JRBC5_UVD_JRBC_STATUS__INT_ACK_MASK 0x00020000L 8808 //UVD_JRBC5_UVD_JRBC_RB_RPTR 8809 #define UVD_JRBC5_UVD_JRBC_RB_RPTR__RB_RPTR__SHIFT 0x4 8810 #define UVD_JRBC5_UVD_JRBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 8811 //UVD_JRBC5_UVD_JRBC_RB_BUF_STATUS 8812 #define UVD_JRBC5_UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0 8813 #define UVD_JRBC5_UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10 8814 #define UVD_JRBC5_UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x18 8815 #define UVD_JRBC5_UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID_MASK 0x0000FFFFL 8816 #define UVD_JRBC5_UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x000F0000L 8817 #define UVD_JRBC5_UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x03000000L 8818 //UVD_JRBC5_UVD_JRBC_IB_BUF_STATUS 8819 #define UVD_JRBC5_UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID__SHIFT 0x0 8820 #define UVD_JRBC5_UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x10 8821 #define UVD_JRBC5_UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x18 8822 #define UVD_JRBC5_UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FFFFL 8823 #define UVD_JRBC5_UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x000F0000L 8824 #define UVD_JRBC5_UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x03000000L 8825 //UVD_JRBC5_UVD_JRBC_IB_SIZE_UPDATE 8826 #define UVD_JRBC5_UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4 8827 #define UVD_JRBC5_UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L 8828 //UVD_JRBC5_UVD_JRBC_IB_COND_RD_TIMER 8829 #define UVD_JRBC5_UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 8830 #define UVD_JRBC5_UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 8831 #define UVD_JRBC5_UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 8832 #define UVD_JRBC5_UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 8833 #define UVD_JRBC5_UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL 8834 #define UVD_JRBC5_UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L 8835 #define UVD_JRBC5_UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L 8836 #define UVD_JRBC5_UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L 8837 //UVD_JRBC5_UVD_JRBC_IB_REF_DATA 8838 #define UVD_JRBC5_UVD_JRBC_IB_REF_DATA__REF_DATA__SHIFT 0x0 8839 #define UVD_JRBC5_UVD_JRBC_IB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL 8840 //UVD_JRBC5_UVD_JPEG_PREEMPT_CMD 8841 #define UVD_JRBC5_UVD_JPEG_PREEMPT_CMD__PREEMPT_EN__SHIFT 0x0 8842 #define UVD_JRBC5_UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE__SHIFT 0x1 8843 #define UVD_JRBC5_UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD__SHIFT 0x2 8844 #define UVD_JRBC5_UVD_JPEG_PREEMPT_CMD__PREEMPT_EN_MASK 0x00000001L 8845 #define UVD_JRBC5_UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE_MASK 0x00000002L 8846 #define UVD_JRBC5_UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD_MASK 0x00000004L 8847 //UVD_JRBC5_UVD_JPEG_PREEMPT_FENCE_DATA0 8848 #define UVD_JRBC5_UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0__SHIFT 0x0 8849 #define UVD_JRBC5_UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0_MASK 0xFFFFFFFFL 8850 //UVD_JRBC5_UVD_JPEG_PREEMPT_FENCE_DATA1 8851 #define UVD_JRBC5_UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1__SHIFT 0x0 8852 #define UVD_JRBC5_UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1_MASK 0xFFFFFFFFL 8853 //UVD_JRBC5_UVD_JRBC_RB_SIZE 8854 #define UVD_JRBC5_UVD_JRBC_RB_SIZE__RB_SIZE__SHIFT 0x4 8855 #define UVD_JRBC5_UVD_JRBC_RB_SIZE__RB_SIZE_MASK 0x00FFFFF0L 8856 //UVD_JRBC5_UVD_JRBC_SCRATCH0 8857 #define UVD_JRBC5_UVD_JRBC_SCRATCH0__SCRATCH0__SHIFT 0x0 8858 #define UVD_JRBC5_UVD_JRBC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL 8859 8860 8861 // addressBlock: aid_uvd0_uvd_jrbc6_uvd_jrbc_dec 8862 //UVD_JRBC6_UVD_JRBC_RB_WPTR 8863 #define UVD_JRBC6_UVD_JRBC_RB_WPTR__RB_WPTR__SHIFT 0x4 8864 #define UVD_JRBC6_UVD_JRBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 8865 //UVD_JRBC6_UVD_JRBC_RB_CNTL 8866 #define UVD_JRBC6_UVD_JRBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x0 8867 #define UVD_JRBC6_UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1 8868 #define UVD_JRBC6_UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x4 8869 #define UVD_JRBC6_UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK 0x00000001L 8870 #define UVD_JRBC6_UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L 8871 #define UVD_JRBC6_UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK 0x0007FFF0L 8872 //UVD_JRBC6_UVD_JRBC_IB_SIZE 8873 #define UVD_JRBC6_UVD_JRBC_IB_SIZE__IB_SIZE__SHIFT 0x4 8874 #define UVD_JRBC6_UVD_JRBC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L 8875 //UVD_JRBC6_UVD_JRBC_URGENT_CNTL 8876 #define UVD_JRBC6_UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0 8877 #define UVD_JRBC6_UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L 8878 //UVD_JRBC6_UVD_JRBC_RB_REF_DATA 8879 #define UVD_JRBC6_UVD_JRBC_RB_REF_DATA__REF_DATA__SHIFT 0x0 8880 #define UVD_JRBC6_UVD_JRBC_RB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL 8881 //UVD_JRBC6_UVD_JRBC_RB_COND_RD_TIMER 8882 #define UVD_JRBC6_UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 8883 #define UVD_JRBC6_UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 8884 #define UVD_JRBC6_UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 8885 #define UVD_JRBC6_UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 8886 #define UVD_JRBC6_UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL 8887 #define UVD_JRBC6_UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L 8888 #define UVD_JRBC6_UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L 8889 #define UVD_JRBC6_UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L 8890 //UVD_JRBC6_UVD_JRBC_SOFT_RESET 8891 #define UVD_JRBC6_UVD_JRBC_SOFT_RESET__RESET__SHIFT 0x0 8892 #define UVD_JRBC6_UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS__SHIFT 0x11 8893 #define UVD_JRBC6_UVD_JRBC_SOFT_RESET__RESET_MASK 0x00000001L 8894 #define UVD_JRBC6_UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS_MASK 0x00020000L 8895 //UVD_JRBC6_UVD_JRBC_STATUS 8896 #define UVD_JRBC6_UVD_JRBC_STATUS__RB_JOB_DONE__SHIFT 0x0 8897 #define UVD_JRBC6_UVD_JRBC_STATUS__IB_JOB_DONE__SHIFT 0x1 8898 #define UVD_JRBC6_UVD_JRBC_STATUS__RB_ILLEGAL_CMD__SHIFT 0x2 8899 #define UVD_JRBC6_UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT__SHIFT 0x3 8900 #define UVD_JRBC6_UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT__SHIFT 0x4 8901 #define UVD_JRBC6_UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT__SHIFT 0x5 8902 #define UVD_JRBC6_UVD_JRBC_STATUS__IB_ILLEGAL_CMD__SHIFT 0x6 8903 #define UVD_JRBC6_UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT__SHIFT 0x7 8904 #define UVD_JRBC6_UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT__SHIFT 0x8 8905 #define UVD_JRBC6_UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT__SHIFT 0x9 8906 #define UVD_JRBC6_UVD_JRBC_STATUS__RB_TRAP_STATUS__SHIFT 0xa 8907 #define UVD_JRBC6_UVD_JRBC_STATUS__PREEMPT_STATUS__SHIFT 0xb 8908 #define UVD_JRBC6_UVD_JRBC_STATUS__IB_TRAP_STATUS__SHIFT 0xc 8909 #define UVD_JRBC6_UVD_JRBC_STATUS__INT_EN__SHIFT 0x10 8910 #define UVD_JRBC6_UVD_JRBC_STATUS__INT_ACK__SHIFT 0x11 8911 #define UVD_JRBC6_UVD_JRBC_STATUS__RB_JOB_DONE_MASK 0x00000001L 8912 #define UVD_JRBC6_UVD_JRBC_STATUS__IB_JOB_DONE_MASK 0x00000002L 8913 #define UVD_JRBC6_UVD_JRBC_STATUS__RB_ILLEGAL_CMD_MASK 0x00000004L 8914 #define UVD_JRBC6_UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT_MASK 0x00000008L 8915 #define UVD_JRBC6_UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT_MASK 0x00000010L 8916 #define UVD_JRBC6_UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT_MASK 0x00000020L 8917 #define UVD_JRBC6_UVD_JRBC_STATUS__IB_ILLEGAL_CMD_MASK 0x00000040L 8918 #define UVD_JRBC6_UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT_MASK 0x00000080L 8919 #define UVD_JRBC6_UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT_MASK 0x00000100L 8920 #define UVD_JRBC6_UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT_MASK 0x00000200L 8921 #define UVD_JRBC6_UVD_JRBC_STATUS__RB_TRAP_STATUS_MASK 0x00000400L 8922 #define UVD_JRBC6_UVD_JRBC_STATUS__PREEMPT_STATUS_MASK 0x00000800L 8923 #define UVD_JRBC6_UVD_JRBC_STATUS__IB_TRAP_STATUS_MASK 0x00001000L 8924 #define UVD_JRBC6_UVD_JRBC_STATUS__INT_EN_MASK 0x00010000L 8925 #define UVD_JRBC6_UVD_JRBC_STATUS__INT_ACK_MASK 0x00020000L 8926 //UVD_JRBC6_UVD_JRBC_RB_RPTR 8927 #define UVD_JRBC6_UVD_JRBC_RB_RPTR__RB_RPTR__SHIFT 0x4 8928 #define UVD_JRBC6_UVD_JRBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 8929 //UVD_JRBC6_UVD_JRBC_RB_BUF_STATUS 8930 #define UVD_JRBC6_UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0 8931 #define UVD_JRBC6_UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10 8932 #define UVD_JRBC6_UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x18 8933 #define UVD_JRBC6_UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID_MASK 0x0000FFFFL 8934 #define UVD_JRBC6_UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x000F0000L 8935 #define UVD_JRBC6_UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x03000000L 8936 //UVD_JRBC6_UVD_JRBC_IB_BUF_STATUS 8937 #define UVD_JRBC6_UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID__SHIFT 0x0 8938 #define UVD_JRBC6_UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x10 8939 #define UVD_JRBC6_UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x18 8940 #define UVD_JRBC6_UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FFFFL 8941 #define UVD_JRBC6_UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x000F0000L 8942 #define UVD_JRBC6_UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x03000000L 8943 //UVD_JRBC6_UVD_JRBC_IB_SIZE_UPDATE 8944 #define UVD_JRBC6_UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4 8945 #define UVD_JRBC6_UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L 8946 //UVD_JRBC6_UVD_JRBC_IB_COND_RD_TIMER 8947 #define UVD_JRBC6_UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 8948 #define UVD_JRBC6_UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 8949 #define UVD_JRBC6_UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 8950 #define UVD_JRBC6_UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 8951 #define UVD_JRBC6_UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL 8952 #define UVD_JRBC6_UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L 8953 #define UVD_JRBC6_UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L 8954 #define UVD_JRBC6_UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L 8955 //UVD_JRBC6_UVD_JRBC_IB_REF_DATA 8956 #define UVD_JRBC6_UVD_JRBC_IB_REF_DATA__REF_DATA__SHIFT 0x0 8957 #define UVD_JRBC6_UVD_JRBC_IB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL 8958 //UVD_JRBC6_UVD_JPEG_PREEMPT_CMD 8959 #define UVD_JRBC6_UVD_JPEG_PREEMPT_CMD__PREEMPT_EN__SHIFT 0x0 8960 #define UVD_JRBC6_UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE__SHIFT 0x1 8961 #define UVD_JRBC6_UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD__SHIFT 0x2 8962 #define UVD_JRBC6_UVD_JPEG_PREEMPT_CMD__PREEMPT_EN_MASK 0x00000001L 8963 #define UVD_JRBC6_UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE_MASK 0x00000002L 8964 #define UVD_JRBC6_UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD_MASK 0x00000004L 8965 //UVD_JRBC6_UVD_JPEG_PREEMPT_FENCE_DATA0 8966 #define UVD_JRBC6_UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0__SHIFT 0x0 8967 #define UVD_JRBC6_UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0_MASK 0xFFFFFFFFL 8968 //UVD_JRBC6_UVD_JPEG_PREEMPT_FENCE_DATA1 8969 #define UVD_JRBC6_UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1__SHIFT 0x0 8970 #define UVD_JRBC6_UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1_MASK 0xFFFFFFFFL 8971 //UVD_JRBC6_UVD_JRBC_RB_SIZE 8972 #define UVD_JRBC6_UVD_JRBC_RB_SIZE__RB_SIZE__SHIFT 0x4 8973 #define UVD_JRBC6_UVD_JRBC_RB_SIZE__RB_SIZE_MASK 0x00FFFFF0L 8974 //UVD_JRBC6_UVD_JRBC_SCRATCH0 8975 #define UVD_JRBC6_UVD_JRBC_SCRATCH0__SCRATCH0__SHIFT 0x0 8976 #define UVD_JRBC6_UVD_JRBC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL 8977 8978 8979 // addressBlock: aid_uvd0_uvd_jrbc7_uvd_jrbc_dec 8980 //UVD_JRBC7_UVD_JRBC_RB_WPTR 8981 #define UVD_JRBC7_UVD_JRBC_RB_WPTR__RB_WPTR__SHIFT 0x4 8982 #define UVD_JRBC7_UVD_JRBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 8983 //UVD_JRBC7_UVD_JRBC_RB_CNTL 8984 #define UVD_JRBC7_UVD_JRBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x0 8985 #define UVD_JRBC7_UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1 8986 #define UVD_JRBC7_UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x4 8987 #define UVD_JRBC7_UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK 0x00000001L 8988 #define UVD_JRBC7_UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L 8989 #define UVD_JRBC7_UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK 0x0007FFF0L 8990 //UVD_JRBC7_UVD_JRBC_IB_SIZE 8991 #define UVD_JRBC7_UVD_JRBC_IB_SIZE__IB_SIZE__SHIFT 0x4 8992 #define UVD_JRBC7_UVD_JRBC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L 8993 //UVD_JRBC7_UVD_JRBC_URGENT_CNTL 8994 #define UVD_JRBC7_UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0 8995 #define UVD_JRBC7_UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L 8996 //UVD_JRBC7_UVD_JRBC_RB_REF_DATA 8997 #define UVD_JRBC7_UVD_JRBC_RB_REF_DATA__REF_DATA__SHIFT 0x0 8998 #define UVD_JRBC7_UVD_JRBC_RB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL 8999 //UVD_JRBC7_UVD_JRBC_RB_COND_RD_TIMER 9000 #define UVD_JRBC7_UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 9001 #define UVD_JRBC7_UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 9002 #define UVD_JRBC7_UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 9003 #define UVD_JRBC7_UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 9004 #define UVD_JRBC7_UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL 9005 #define UVD_JRBC7_UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L 9006 #define UVD_JRBC7_UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L 9007 #define UVD_JRBC7_UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L 9008 //UVD_JRBC7_UVD_JRBC_SOFT_RESET 9009 #define UVD_JRBC7_UVD_JRBC_SOFT_RESET__RESET__SHIFT 0x0 9010 #define UVD_JRBC7_UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS__SHIFT 0x11 9011 #define UVD_JRBC7_UVD_JRBC_SOFT_RESET__RESET_MASK 0x00000001L 9012 #define UVD_JRBC7_UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS_MASK 0x00020000L 9013 //UVD_JRBC7_UVD_JRBC_STATUS 9014 #define UVD_JRBC7_UVD_JRBC_STATUS__RB_JOB_DONE__SHIFT 0x0 9015 #define UVD_JRBC7_UVD_JRBC_STATUS__IB_JOB_DONE__SHIFT 0x1 9016 #define UVD_JRBC7_UVD_JRBC_STATUS__RB_ILLEGAL_CMD__SHIFT 0x2 9017 #define UVD_JRBC7_UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT__SHIFT 0x3 9018 #define UVD_JRBC7_UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT__SHIFT 0x4 9019 #define UVD_JRBC7_UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT__SHIFT 0x5 9020 #define UVD_JRBC7_UVD_JRBC_STATUS__IB_ILLEGAL_CMD__SHIFT 0x6 9021 #define UVD_JRBC7_UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT__SHIFT 0x7 9022 #define UVD_JRBC7_UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT__SHIFT 0x8 9023 #define UVD_JRBC7_UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT__SHIFT 0x9 9024 #define UVD_JRBC7_UVD_JRBC_STATUS__RB_TRAP_STATUS__SHIFT 0xa 9025 #define UVD_JRBC7_UVD_JRBC_STATUS__PREEMPT_STATUS__SHIFT 0xb 9026 #define UVD_JRBC7_UVD_JRBC_STATUS__IB_TRAP_STATUS__SHIFT 0xc 9027 #define UVD_JRBC7_UVD_JRBC_STATUS__INT_EN__SHIFT 0x10 9028 #define UVD_JRBC7_UVD_JRBC_STATUS__INT_ACK__SHIFT 0x11 9029 #define UVD_JRBC7_UVD_JRBC_STATUS__RB_JOB_DONE_MASK 0x00000001L 9030 #define UVD_JRBC7_UVD_JRBC_STATUS__IB_JOB_DONE_MASK 0x00000002L 9031 #define UVD_JRBC7_UVD_JRBC_STATUS__RB_ILLEGAL_CMD_MASK 0x00000004L 9032 #define UVD_JRBC7_UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT_MASK 0x00000008L 9033 #define UVD_JRBC7_UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT_MASK 0x00000010L 9034 #define UVD_JRBC7_UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT_MASK 0x00000020L 9035 #define UVD_JRBC7_UVD_JRBC_STATUS__IB_ILLEGAL_CMD_MASK 0x00000040L 9036 #define UVD_JRBC7_UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT_MASK 0x00000080L 9037 #define UVD_JRBC7_UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT_MASK 0x00000100L 9038 #define UVD_JRBC7_UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT_MASK 0x00000200L 9039 #define UVD_JRBC7_UVD_JRBC_STATUS__RB_TRAP_STATUS_MASK 0x00000400L 9040 #define UVD_JRBC7_UVD_JRBC_STATUS__PREEMPT_STATUS_MASK 0x00000800L 9041 #define UVD_JRBC7_UVD_JRBC_STATUS__IB_TRAP_STATUS_MASK 0x00001000L 9042 #define UVD_JRBC7_UVD_JRBC_STATUS__INT_EN_MASK 0x00010000L 9043 #define UVD_JRBC7_UVD_JRBC_STATUS__INT_ACK_MASK 0x00020000L 9044 //UVD_JRBC7_UVD_JRBC_RB_RPTR 9045 #define UVD_JRBC7_UVD_JRBC_RB_RPTR__RB_RPTR__SHIFT 0x4 9046 #define UVD_JRBC7_UVD_JRBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 9047 //UVD_JRBC7_UVD_JRBC_RB_BUF_STATUS 9048 #define UVD_JRBC7_UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0 9049 #define UVD_JRBC7_UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10 9050 #define UVD_JRBC7_UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x18 9051 #define UVD_JRBC7_UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID_MASK 0x0000FFFFL 9052 #define UVD_JRBC7_UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x000F0000L 9053 #define UVD_JRBC7_UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x03000000L 9054 //UVD_JRBC7_UVD_JRBC_IB_BUF_STATUS 9055 #define UVD_JRBC7_UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID__SHIFT 0x0 9056 #define UVD_JRBC7_UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x10 9057 #define UVD_JRBC7_UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x18 9058 #define UVD_JRBC7_UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FFFFL 9059 #define UVD_JRBC7_UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x000F0000L 9060 #define UVD_JRBC7_UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x03000000L 9061 //UVD_JRBC7_UVD_JRBC_IB_SIZE_UPDATE 9062 #define UVD_JRBC7_UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4 9063 #define UVD_JRBC7_UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L 9064 //UVD_JRBC7_UVD_JRBC_IB_COND_RD_TIMER 9065 #define UVD_JRBC7_UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 9066 #define UVD_JRBC7_UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 9067 #define UVD_JRBC7_UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 9068 #define UVD_JRBC7_UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 9069 #define UVD_JRBC7_UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL 9070 #define UVD_JRBC7_UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L 9071 #define UVD_JRBC7_UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L 9072 #define UVD_JRBC7_UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L 9073 //UVD_JRBC7_UVD_JRBC_IB_REF_DATA 9074 #define UVD_JRBC7_UVD_JRBC_IB_REF_DATA__REF_DATA__SHIFT 0x0 9075 #define UVD_JRBC7_UVD_JRBC_IB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL 9076 //UVD_JRBC7_UVD_JPEG_PREEMPT_CMD 9077 #define UVD_JRBC7_UVD_JPEG_PREEMPT_CMD__PREEMPT_EN__SHIFT 0x0 9078 #define UVD_JRBC7_UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE__SHIFT 0x1 9079 #define UVD_JRBC7_UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD__SHIFT 0x2 9080 #define UVD_JRBC7_UVD_JPEG_PREEMPT_CMD__PREEMPT_EN_MASK 0x00000001L 9081 #define UVD_JRBC7_UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE_MASK 0x00000002L 9082 #define UVD_JRBC7_UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD_MASK 0x00000004L 9083 //UVD_JRBC7_UVD_JPEG_PREEMPT_FENCE_DATA0 9084 #define UVD_JRBC7_UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0__SHIFT 0x0 9085 #define UVD_JRBC7_UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0_MASK 0xFFFFFFFFL 9086 //UVD_JRBC7_UVD_JPEG_PREEMPT_FENCE_DATA1 9087 #define UVD_JRBC7_UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1__SHIFT 0x0 9088 #define UVD_JRBC7_UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1_MASK 0xFFFFFFFFL 9089 //UVD_JRBC7_UVD_JRBC_RB_SIZE 9090 #define UVD_JRBC7_UVD_JRBC_RB_SIZE__RB_SIZE__SHIFT 0x4 9091 #define UVD_JRBC7_UVD_JRBC_RB_SIZE__RB_SIZE_MASK 0x00FFFFF0L 9092 //UVD_JRBC7_UVD_JRBC_SCRATCH0 9093 #define UVD_JRBC7_UVD_JRBC_SCRATCH0__SCRATCH0__SHIFT 0x0 9094 #define UVD_JRBC7_UVD_JRBC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL 9095 9096 9097 // addressBlock: aid_uvd0_uvd_jmi1_uvd_jmi_dec 9098 //UVD_JMI1_UVD_JPEG_DEC_PF_CTRL 9099 #define UVD_JMI1_UVD_JPEG_DEC_PF_CTRL__DEC_PF_HANDLING_DIS__SHIFT 0x0 9100 #define UVD_JMI1_UVD_JPEG_DEC_PF_CTRL__DEC_PF_SW_GATING__SHIFT 0x1 9101 #define UVD_JMI1_UVD_JPEG_DEC_PF_CTRL__DEC_PF_HANDLING_DIS_MASK 0x00000001L 9102 #define UVD_JMI1_UVD_JPEG_DEC_PF_CTRL__DEC_PF_SW_GATING_MASK 0x00000002L 9103 //UVD_JMI1_UVD_LMI_JRBC_CTRL 9104 #define UVD_JMI1_UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 9105 #define UVD_JMI1_UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 9106 #define UVD_JMI1_UVD_LMI_JRBC_CTRL__RD_MAX_BURST__SHIFT 0x4 9107 #define UVD_JMI1_UVD_LMI_JRBC_CTRL__WR_MAX_BURST__SHIFT 0x8 9108 #define UVD_JMI1_UVD_LMI_JRBC_CTRL__RD_SWAP__SHIFT 0x14 9109 #define UVD_JMI1_UVD_LMI_JRBC_CTRL__WR_SWAP__SHIFT 0x16 9110 #define UVD_JMI1_UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 9111 #define UVD_JMI1_UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 9112 #define UVD_JMI1_UVD_LMI_JRBC_CTRL__RD_MAX_BURST_MASK 0x000000F0L 9113 #define UVD_JMI1_UVD_LMI_JRBC_CTRL__WR_MAX_BURST_MASK 0x00000F00L 9114 #define UVD_JMI1_UVD_LMI_JRBC_CTRL__RD_SWAP_MASK 0x00300000L 9115 #define UVD_JMI1_UVD_LMI_JRBC_CTRL__WR_SWAP_MASK 0x00C00000L 9116 //UVD_JMI1_UVD_LMI_JPEG_CTRL 9117 #define UVD_JMI1_UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 9118 #define UVD_JMI1_UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 9119 #define UVD_JMI1_UVD_LMI_JPEG_CTRL__RD_MAX_BURST__SHIFT 0x4 9120 #define UVD_JMI1_UVD_LMI_JPEG_CTRL__WR_MAX_BURST__SHIFT 0x8 9121 #define UVD_JMI1_UVD_LMI_JPEG_CTRL__RD_SWAP__SHIFT 0x14 9122 #define UVD_JMI1_UVD_LMI_JPEG_CTRL__WR_SWAP__SHIFT 0x16 9123 #define UVD_JMI1_UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 9124 #define UVD_JMI1_UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 9125 #define UVD_JMI1_UVD_LMI_JPEG_CTRL__RD_MAX_BURST_MASK 0x000000F0L 9126 #define UVD_JMI1_UVD_LMI_JPEG_CTRL__WR_MAX_BURST_MASK 0x00000F00L 9127 #define UVD_JMI1_UVD_LMI_JPEG_CTRL__RD_SWAP_MASK 0x00300000L 9128 #define UVD_JMI1_UVD_LMI_JPEG_CTRL__WR_SWAP_MASK 0x00C00000L 9129 //UVD_JMI1_JPEG_LMI_DROP 9130 #define UVD_JMI1_JPEG_LMI_DROP__JPEG_WR_DROP__SHIFT 0x0 9131 #define UVD_JMI1_JPEG_LMI_DROP__JRBC_WR_DROP__SHIFT 0x1 9132 #define UVD_JMI1_JPEG_LMI_DROP__JPEG_RD_DROP__SHIFT 0x2 9133 #define UVD_JMI1_JPEG_LMI_DROP__JRBC_RD_DROP__SHIFT 0x3 9134 #define UVD_JMI1_JPEG_LMI_DROP__JPEG_ATOMIC_WR_DROP__SHIFT 0x4 9135 #define UVD_JMI1_JPEG_LMI_DROP__JPEG_WR_DROP_MASK 0x00000001L 9136 #define UVD_JMI1_JPEG_LMI_DROP__JRBC_WR_DROP_MASK 0x00000002L 9137 #define UVD_JMI1_JPEG_LMI_DROP__JPEG_RD_DROP_MASK 0x00000004L 9138 #define UVD_JMI1_JPEG_LMI_DROP__JRBC_RD_DROP_MASK 0x00000008L 9139 #define UVD_JMI1_JPEG_LMI_DROP__JPEG_ATOMIC_WR_DROP_MASK 0x00000010L 9140 //UVD_JMI1_UVD_LMI_JRBC_IB_VMID 9141 #define UVD_JMI1_UVD_LMI_JRBC_IB_VMID__IB_WR_VMID__SHIFT 0x0 9142 #define UVD_JMI1_UVD_LMI_JRBC_IB_VMID__IB_RD_VMID__SHIFT 0x4 9143 #define UVD_JMI1_UVD_LMI_JRBC_IB_VMID__MEM_RD_VMID__SHIFT 0x8 9144 #define UVD_JMI1_UVD_LMI_JRBC_IB_VMID__IB_WR_VMID_MASK 0x0000000FL 9145 #define UVD_JMI1_UVD_LMI_JRBC_IB_VMID__IB_RD_VMID_MASK 0x000000F0L 9146 #define UVD_JMI1_UVD_LMI_JRBC_IB_VMID__MEM_RD_VMID_MASK 0x00000F00L 9147 //UVD_JMI1_UVD_LMI_JRBC_RB_VMID 9148 #define UVD_JMI1_UVD_LMI_JRBC_RB_VMID__RB_WR_VMID__SHIFT 0x0 9149 #define UVD_JMI1_UVD_LMI_JRBC_RB_VMID__RB_RD_VMID__SHIFT 0x4 9150 #define UVD_JMI1_UVD_LMI_JRBC_RB_VMID__MEM_RD_VMID__SHIFT 0x8 9151 #define UVD_JMI1_UVD_LMI_JRBC_RB_VMID__RB_WR_VMID_MASK 0x0000000FL 9152 #define UVD_JMI1_UVD_LMI_JRBC_RB_VMID__RB_RD_VMID_MASK 0x000000F0L 9153 #define UVD_JMI1_UVD_LMI_JRBC_RB_VMID__MEM_RD_VMID_MASK 0x00000F00L 9154 //UVD_JMI1_UVD_LMI_JPEG_VMID 9155 #define UVD_JMI1_UVD_LMI_JPEG_VMID__JPEG_RD_VMID__SHIFT 0x0 9156 #define UVD_JMI1_UVD_LMI_JPEG_VMID__JPEG_WR_VMID__SHIFT 0x4 9157 #define UVD_JMI1_UVD_LMI_JPEG_VMID__ATOMIC_USER0_WR_VMID__SHIFT 0x8 9158 #define UVD_JMI1_UVD_LMI_JPEG_VMID__JPEG_RD_VMID_MASK 0x0000000FL 9159 #define UVD_JMI1_UVD_LMI_JPEG_VMID__JPEG_WR_VMID_MASK 0x000000F0L 9160 #define UVD_JMI1_UVD_LMI_JPEG_VMID__ATOMIC_USER0_WR_VMID_MASK 0x00000F00L 9161 //UVD_JMI1_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW 9162 #define UVD_JMI1_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 9163 #define UVD_JMI1_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 9164 //UVD_JMI1_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 9165 #define UVD_JMI1_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 9166 #define UVD_JMI1_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 9167 //UVD_JMI1_UVD_LMI_JRBC_RB_64BIT_BAR_LOW 9168 #define UVD_JMI1_UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 9169 #define UVD_JMI1_UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 9170 //UVD_JMI1_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH 9171 #define UVD_JMI1_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 9172 #define UVD_JMI1_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 9173 //UVD_JMI1_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW 9174 #define UVD_JMI1_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 9175 #define UVD_JMI1_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 9176 //UVD_JMI1_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH 9177 #define UVD_JMI1_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 9178 #define UVD_JMI1_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 9179 //UVD_JMI1_UVD_LMI_JPEG_PREEMPT_VMID 9180 #define UVD_JMI1_UVD_LMI_JPEG_PREEMPT_VMID__VMID__SHIFT 0x0 9181 #define UVD_JMI1_UVD_LMI_JPEG_PREEMPT_VMID__VMID_MASK 0x0000000FL 9182 //UVD_JMI1_UVD_JMI_DEC_SWAP_CNTL 9183 #define UVD_JMI1_UVD_JMI_DEC_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 9184 #define UVD_JMI1_UVD_JMI_DEC_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 9185 #define UVD_JMI1_UVD_JMI_DEC_SWAP_CNTL__RB_MEM_WR_MC_SWAP__SHIFT 0x4 9186 #define UVD_JMI1_UVD_JMI_DEC_SWAP_CNTL__IB_MEM_WR_MC_SWAP__SHIFT 0x6 9187 #define UVD_JMI1_UVD_JMI_DEC_SWAP_CNTL__RB_MEM_RD_MC_SWAP__SHIFT 0x8 9188 #define UVD_JMI1_UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT 0xa 9189 #define UVD_JMI1_UVD_JMI_DEC_SWAP_CNTL__PREEMPT_WR_MC_SWAP__SHIFT 0xc 9190 #define UVD_JMI1_UVD_JMI_DEC_SWAP_CNTL__JPEG_RD_MC_SWAP__SHIFT 0xe 9191 #define UVD_JMI1_UVD_JMI_DEC_SWAP_CNTL__JPEG_WR_MC_SWAP__SHIFT 0x10 9192 #define UVD_JMI1_UVD_JMI_DEC_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L 9193 #define UVD_JMI1_UVD_JMI_DEC_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL 9194 #define UVD_JMI1_UVD_JMI_DEC_SWAP_CNTL__RB_MEM_WR_MC_SWAP_MASK 0x00000030L 9195 #define UVD_JMI1_UVD_JMI_DEC_SWAP_CNTL__IB_MEM_WR_MC_SWAP_MASK 0x000000C0L 9196 #define UVD_JMI1_UVD_JMI_DEC_SWAP_CNTL__RB_MEM_RD_MC_SWAP_MASK 0x00000300L 9197 #define UVD_JMI1_UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP_MASK 0x00000C00L 9198 #define UVD_JMI1_UVD_JMI_DEC_SWAP_CNTL__PREEMPT_WR_MC_SWAP_MASK 0x00003000L 9199 #define UVD_JMI1_UVD_JMI_DEC_SWAP_CNTL__JPEG_RD_MC_SWAP_MASK 0x0000C000L 9200 #define UVD_JMI1_UVD_JMI_DEC_SWAP_CNTL__JPEG_WR_MC_SWAP_MASK 0x00030000L 9201 //UVD_JMI1_UVD_JMI_ATOMIC_CNTL 9202 #define UVD_JMI1_UVD_JMI_ATOMIC_CNTL__atomic_arb_wait_en__SHIFT 0x0 9203 #define UVD_JMI1_UVD_JMI_ATOMIC_CNTL__atomic_max_burst__SHIFT 0x1 9204 #define UVD_JMI1_UVD_JMI_ATOMIC_CNTL__atomic_wr_drop__SHIFT 0x5 9205 #define UVD_JMI1_UVD_JMI_ATOMIC_CNTL__atomic_wr_clamping_en__SHIFT 0x6 9206 #define UVD_JMI1_UVD_JMI_ATOMIC_CNTL__ATOMIC_WR_URG__SHIFT 0x7 9207 #define UVD_JMI1_UVD_JMI_ATOMIC_CNTL__ATOMIC_SW_GATE__SHIFT 0xb 9208 #define UVD_JMI1_UVD_JMI_ATOMIC_CNTL__atomic_arb_wait_en_MASK 0x00000001L 9209 #define UVD_JMI1_UVD_JMI_ATOMIC_CNTL__atomic_max_burst_MASK 0x0000001EL 9210 #define UVD_JMI1_UVD_JMI_ATOMIC_CNTL__atomic_wr_drop_MASK 0x00000020L 9211 #define UVD_JMI1_UVD_JMI_ATOMIC_CNTL__atomic_wr_clamping_en_MASK 0x00000040L 9212 #define UVD_JMI1_UVD_JMI_ATOMIC_CNTL__ATOMIC_WR_URG_MASK 0x00000780L 9213 #define UVD_JMI1_UVD_JMI_ATOMIC_CNTL__ATOMIC_SW_GATE_MASK 0x00000800L 9214 //UVD_JMI1_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW 9215 #define UVD_JMI1_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 9216 #define UVD_JMI1_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 9217 //UVD_JMI1_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH 9218 #define UVD_JMI1_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 9219 #define UVD_JMI1_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 9220 //UVD_JMI1_UVD_LMI_JPEG_READ_64BIT_BAR_LOW 9221 #define UVD_JMI1_UVD_LMI_JPEG_READ_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 9222 #define UVD_JMI1_UVD_LMI_JPEG_READ_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 9223 //UVD_JMI1_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH 9224 #define UVD_JMI1_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 9225 #define UVD_JMI1_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 9226 //UVD_JMI1_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 9227 #define UVD_JMI1_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 9228 #define UVD_JMI1_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 9229 //UVD_JMI1_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 9230 #define UVD_JMI1_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 9231 #define UVD_JMI1_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 9232 //UVD_JMI1_UVD_LMI_JRBC_IB_64BIT_BAR_LOW 9233 #define UVD_JMI1_UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 9234 #define UVD_JMI1_UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 9235 //UVD_JMI1_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH 9236 #define UVD_JMI1_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 9237 #define UVD_JMI1_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 9238 //UVD_JMI1_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW 9239 #define UVD_JMI1_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 9240 #define UVD_JMI1_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 9241 //UVD_JMI1_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH 9242 #define UVD_JMI1_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 9243 #define UVD_JMI1_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 9244 //UVD_JMI1_UVD_JMI_ATOMIC_CNTL2 9245 #define UVD_JMI1_UVD_JMI_ATOMIC_CNTL2__atomic_uvd_swap__SHIFT 0x10 9246 #define UVD_JMI1_UVD_JMI_ATOMIC_CNTL2__ATOMIC_MC_SWAP__SHIFT 0x18 9247 #define UVD_JMI1_UVD_JMI_ATOMIC_CNTL2__atomic_uvd_swap_MASK 0x00FF0000L 9248 #define UVD_JMI1_UVD_JMI_ATOMIC_CNTL2__ATOMIC_MC_SWAP_MASK 0xFF000000L 9249 9250 9251 // addressBlock: aid_uvd0_uvd_jmi2_uvd_jmi_dec 9252 //UVD_JMI2_UVD_JPEG_DEC_PF_CTRL 9253 #define UVD_JMI2_UVD_JPEG_DEC_PF_CTRL__DEC_PF_HANDLING_DIS__SHIFT 0x0 9254 #define UVD_JMI2_UVD_JPEG_DEC_PF_CTRL__DEC_PF_SW_GATING__SHIFT 0x1 9255 #define UVD_JMI2_UVD_JPEG_DEC_PF_CTRL__DEC_PF_HANDLING_DIS_MASK 0x00000001L 9256 #define UVD_JMI2_UVD_JPEG_DEC_PF_CTRL__DEC_PF_SW_GATING_MASK 0x00000002L 9257 //UVD_JMI2_UVD_LMI_JRBC_CTRL 9258 #define UVD_JMI2_UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 9259 #define UVD_JMI2_UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 9260 #define UVD_JMI2_UVD_LMI_JRBC_CTRL__RD_MAX_BURST__SHIFT 0x4 9261 #define UVD_JMI2_UVD_LMI_JRBC_CTRL__WR_MAX_BURST__SHIFT 0x8 9262 #define UVD_JMI2_UVD_LMI_JRBC_CTRL__RD_SWAP__SHIFT 0x14 9263 #define UVD_JMI2_UVD_LMI_JRBC_CTRL__WR_SWAP__SHIFT 0x16 9264 #define UVD_JMI2_UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 9265 #define UVD_JMI2_UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 9266 #define UVD_JMI2_UVD_LMI_JRBC_CTRL__RD_MAX_BURST_MASK 0x000000F0L 9267 #define UVD_JMI2_UVD_LMI_JRBC_CTRL__WR_MAX_BURST_MASK 0x00000F00L 9268 #define UVD_JMI2_UVD_LMI_JRBC_CTRL__RD_SWAP_MASK 0x00300000L 9269 #define UVD_JMI2_UVD_LMI_JRBC_CTRL__WR_SWAP_MASK 0x00C00000L 9270 //UVD_JMI2_UVD_LMI_JPEG_CTRL 9271 #define UVD_JMI2_UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 9272 #define UVD_JMI2_UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 9273 #define UVD_JMI2_UVD_LMI_JPEG_CTRL__RD_MAX_BURST__SHIFT 0x4 9274 #define UVD_JMI2_UVD_LMI_JPEG_CTRL__WR_MAX_BURST__SHIFT 0x8 9275 #define UVD_JMI2_UVD_LMI_JPEG_CTRL__RD_SWAP__SHIFT 0x14 9276 #define UVD_JMI2_UVD_LMI_JPEG_CTRL__WR_SWAP__SHIFT 0x16 9277 #define UVD_JMI2_UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 9278 #define UVD_JMI2_UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 9279 #define UVD_JMI2_UVD_LMI_JPEG_CTRL__RD_MAX_BURST_MASK 0x000000F0L 9280 #define UVD_JMI2_UVD_LMI_JPEG_CTRL__WR_MAX_BURST_MASK 0x00000F00L 9281 #define UVD_JMI2_UVD_LMI_JPEG_CTRL__RD_SWAP_MASK 0x00300000L 9282 #define UVD_JMI2_UVD_LMI_JPEG_CTRL__WR_SWAP_MASK 0x00C00000L 9283 //UVD_JMI2_JPEG_LMI_DROP 9284 #define UVD_JMI2_JPEG_LMI_DROP__JPEG_WR_DROP__SHIFT 0x0 9285 #define UVD_JMI2_JPEG_LMI_DROP__JRBC_WR_DROP__SHIFT 0x1 9286 #define UVD_JMI2_JPEG_LMI_DROP__JPEG_RD_DROP__SHIFT 0x2 9287 #define UVD_JMI2_JPEG_LMI_DROP__JRBC_RD_DROP__SHIFT 0x3 9288 #define UVD_JMI2_JPEG_LMI_DROP__JPEG_ATOMIC_WR_DROP__SHIFT 0x4 9289 #define UVD_JMI2_JPEG_LMI_DROP__JPEG_WR_DROP_MASK 0x00000001L 9290 #define UVD_JMI2_JPEG_LMI_DROP__JRBC_WR_DROP_MASK 0x00000002L 9291 #define UVD_JMI2_JPEG_LMI_DROP__JPEG_RD_DROP_MASK 0x00000004L 9292 #define UVD_JMI2_JPEG_LMI_DROP__JRBC_RD_DROP_MASK 0x00000008L 9293 #define UVD_JMI2_JPEG_LMI_DROP__JPEG_ATOMIC_WR_DROP_MASK 0x00000010L 9294 //UVD_JMI2_UVD_LMI_JRBC_IB_VMID 9295 #define UVD_JMI2_UVD_LMI_JRBC_IB_VMID__IB_WR_VMID__SHIFT 0x0 9296 #define UVD_JMI2_UVD_LMI_JRBC_IB_VMID__IB_RD_VMID__SHIFT 0x4 9297 #define UVD_JMI2_UVD_LMI_JRBC_IB_VMID__MEM_RD_VMID__SHIFT 0x8 9298 #define UVD_JMI2_UVD_LMI_JRBC_IB_VMID__IB_WR_VMID_MASK 0x0000000FL 9299 #define UVD_JMI2_UVD_LMI_JRBC_IB_VMID__IB_RD_VMID_MASK 0x000000F0L 9300 #define UVD_JMI2_UVD_LMI_JRBC_IB_VMID__MEM_RD_VMID_MASK 0x00000F00L 9301 //UVD_JMI2_UVD_LMI_JRBC_RB_VMID 9302 #define UVD_JMI2_UVD_LMI_JRBC_RB_VMID__RB_WR_VMID__SHIFT 0x0 9303 #define UVD_JMI2_UVD_LMI_JRBC_RB_VMID__RB_RD_VMID__SHIFT 0x4 9304 #define UVD_JMI2_UVD_LMI_JRBC_RB_VMID__MEM_RD_VMID__SHIFT 0x8 9305 #define UVD_JMI2_UVD_LMI_JRBC_RB_VMID__RB_WR_VMID_MASK 0x0000000FL 9306 #define UVD_JMI2_UVD_LMI_JRBC_RB_VMID__RB_RD_VMID_MASK 0x000000F0L 9307 #define UVD_JMI2_UVD_LMI_JRBC_RB_VMID__MEM_RD_VMID_MASK 0x00000F00L 9308 //UVD_JMI2_UVD_LMI_JPEG_VMID 9309 #define UVD_JMI2_UVD_LMI_JPEG_VMID__JPEG_RD_VMID__SHIFT 0x0 9310 #define UVD_JMI2_UVD_LMI_JPEG_VMID__JPEG_WR_VMID__SHIFT 0x4 9311 #define UVD_JMI2_UVD_LMI_JPEG_VMID__ATOMIC_USER0_WR_VMID__SHIFT 0x8 9312 #define UVD_JMI2_UVD_LMI_JPEG_VMID__JPEG_RD_VMID_MASK 0x0000000FL 9313 #define UVD_JMI2_UVD_LMI_JPEG_VMID__JPEG_WR_VMID_MASK 0x000000F0L 9314 #define UVD_JMI2_UVD_LMI_JPEG_VMID__ATOMIC_USER0_WR_VMID_MASK 0x00000F00L 9315 //UVD_JMI2_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW 9316 #define UVD_JMI2_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 9317 #define UVD_JMI2_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 9318 //UVD_JMI2_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 9319 #define UVD_JMI2_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 9320 #define UVD_JMI2_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 9321 //UVD_JMI2_UVD_LMI_JRBC_RB_64BIT_BAR_LOW 9322 #define UVD_JMI2_UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 9323 #define UVD_JMI2_UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 9324 //UVD_JMI2_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH 9325 #define UVD_JMI2_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 9326 #define UVD_JMI2_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 9327 //UVD_JMI2_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW 9328 #define UVD_JMI2_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 9329 #define UVD_JMI2_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 9330 //UVD_JMI2_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH 9331 #define UVD_JMI2_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 9332 #define UVD_JMI2_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 9333 //UVD_JMI2_UVD_LMI_JPEG_PREEMPT_VMID 9334 #define UVD_JMI2_UVD_LMI_JPEG_PREEMPT_VMID__VMID__SHIFT 0x0 9335 #define UVD_JMI2_UVD_LMI_JPEG_PREEMPT_VMID__VMID_MASK 0x0000000FL 9336 //UVD_JMI2_UVD_JMI_DEC_SWAP_CNTL 9337 #define UVD_JMI2_UVD_JMI_DEC_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 9338 #define UVD_JMI2_UVD_JMI_DEC_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 9339 #define UVD_JMI2_UVD_JMI_DEC_SWAP_CNTL__RB_MEM_WR_MC_SWAP__SHIFT 0x4 9340 #define UVD_JMI2_UVD_JMI_DEC_SWAP_CNTL__IB_MEM_WR_MC_SWAP__SHIFT 0x6 9341 #define UVD_JMI2_UVD_JMI_DEC_SWAP_CNTL__RB_MEM_RD_MC_SWAP__SHIFT 0x8 9342 #define UVD_JMI2_UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT 0xa 9343 #define UVD_JMI2_UVD_JMI_DEC_SWAP_CNTL__PREEMPT_WR_MC_SWAP__SHIFT 0xc 9344 #define UVD_JMI2_UVD_JMI_DEC_SWAP_CNTL__JPEG_RD_MC_SWAP__SHIFT 0xe 9345 #define UVD_JMI2_UVD_JMI_DEC_SWAP_CNTL__JPEG_WR_MC_SWAP__SHIFT 0x10 9346 #define UVD_JMI2_UVD_JMI_DEC_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L 9347 #define UVD_JMI2_UVD_JMI_DEC_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL 9348 #define UVD_JMI2_UVD_JMI_DEC_SWAP_CNTL__RB_MEM_WR_MC_SWAP_MASK 0x00000030L 9349 #define UVD_JMI2_UVD_JMI_DEC_SWAP_CNTL__IB_MEM_WR_MC_SWAP_MASK 0x000000C0L 9350 #define UVD_JMI2_UVD_JMI_DEC_SWAP_CNTL__RB_MEM_RD_MC_SWAP_MASK 0x00000300L 9351 #define UVD_JMI2_UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP_MASK 0x00000C00L 9352 #define UVD_JMI2_UVD_JMI_DEC_SWAP_CNTL__PREEMPT_WR_MC_SWAP_MASK 0x00003000L 9353 #define UVD_JMI2_UVD_JMI_DEC_SWAP_CNTL__JPEG_RD_MC_SWAP_MASK 0x0000C000L 9354 #define UVD_JMI2_UVD_JMI_DEC_SWAP_CNTL__JPEG_WR_MC_SWAP_MASK 0x00030000L 9355 //UVD_JMI2_UVD_JMI_ATOMIC_CNTL 9356 #define UVD_JMI2_UVD_JMI_ATOMIC_CNTL__atomic_arb_wait_en__SHIFT 0x0 9357 #define UVD_JMI2_UVD_JMI_ATOMIC_CNTL__atomic_max_burst__SHIFT 0x1 9358 #define UVD_JMI2_UVD_JMI_ATOMIC_CNTL__atomic_wr_drop__SHIFT 0x5 9359 #define UVD_JMI2_UVD_JMI_ATOMIC_CNTL__atomic_wr_clamping_en__SHIFT 0x6 9360 #define UVD_JMI2_UVD_JMI_ATOMIC_CNTL__ATOMIC_WR_URG__SHIFT 0x7 9361 #define UVD_JMI2_UVD_JMI_ATOMIC_CNTL__ATOMIC_SW_GATE__SHIFT 0xb 9362 #define UVD_JMI2_UVD_JMI_ATOMIC_CNTL__atomic_arb_wait_en_MASK 0x00000001L 9363 #define UVD_JMI2_UVD_JMI_ATOMIC_CNTL__atomic_max_burst_MASK 0x0000001EL 9364 #define UVD_JMI2_UVD_JMI_ATOMIC_CNTL__atomic_wr_drop_MASK 0x00000020L 9365 #define UVD_JMI2_UVD_JMI_ATOMIC_CNTL__atomic_wr_clamping_en_MASK 0x00000040L 9366 #define UVD_JMI2_UVD_JMI_ATOMIC_CNTL__ATOMIC_WR_URG_MASK 0x00000780L 9367 #define UVD_JMI2_UVD_JMI_ATOMIC_CNTL__ATOMIC_SW_GATE_MASK 0x00000800L 9368 //UVD_JMI2_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW 9369 #define UVD_JMI2_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 9370 #define UVD_JMI2_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 9371 //UVD_JMI2_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH 9372 #define UVD_JMI2_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 9373 #define UVD_JMI2_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 9374 //UVD_JMI2_UVD_LMI_JPEG_READ_64BIT_BAR_LOW 9375 #define UVD_JMI2_UVD_LMI_JPEG_READ_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 9376 #define UVD_JMI2_UVD_LMI_JPEG_READ_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 9377 //UVD_JMI2_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH 9378 #define UVD_JMI2_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 9379 #define UVD_JMI2_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 9380 //UVD_JMI2_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 9381 #define UVD_JMI2_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 9382 #define UVD_JMI2_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 9383 //UVD_JMI2_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 9384 #define UVD_JMI2_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 9385 #define UVD_JMI2_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 9386 //UVD_JMI2_UVD_LMI_JRBC_IB_64BIT_BAR_LOW 9387 #define UVD_JMI2_UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 9388 #define UVD_JMI2_UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 9389 //UVD_JMI2_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH 9390 #define UVD_JMI2_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 9391 #define UVD_JMI2_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 9392 //UVD_JMI2_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW 9393 #define UVD_JMI2_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 9394 #define UVD_JMI2_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 9395 //UVD_JMI2_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH 9396 #define UVD_JMI2_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 9397 #define UVD_JMI2_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 9398 //UVD_JMI2_UVD_JMI_ATOMIC_CNTL2 9399 #define UVD_JMI2_UVD_JMI_ATOMIC_CNTL2__atomic_uvd_swap__SHIFT 0x10 9400 #define UVD_JMI2_UVD_JMI_ATOMIC_CNTL2__ATOMIC_MC_SWAP__SHIFT 0x18 9401 #define UVD_JMI2_UVD_JMI_ATOMIC_CNTL2__atomic_uvd_swap_MASK 0x00FF0000L 9402 #define UVD_JMI2_UVD_JMI_ATOMIC_CNTL2__ATOMIC_MC_SWAP_MASK 0xFF000000L 9403 9404 9405 // addressBlock: aid_uvd0_uvd_jmi3_uvd_jmi_dec 9406 //UVD_JMI3_UVD_JPEG_DEC_PF_CTRL 9407 #define UVD_JMI3_UVD_JPEG_DEC_PF_CTRL__DEC_PF_HANDLING_DIS__SHIFT 0x0 9408 #define UVD_JMI3_UVD_JPEG_DEC_PF_CTRL__DEC_PF_SW_GATING__SHIFT 0x1 9409 #define UVD_JMI3_UVD_JPEG_DEC_PF_CTRL__DEC_PF_HANDLING_DIS_MASK 0x00000001L 9410 #define UVD_JMI3_UVD_JPEG_DEC_PF_CTRL__DEC_PF_SW_GATING_MASK 0x00000002L 9411 //UVD_JMI3_UVD_LMI_JRBC_CTRL 9412 #define UVD_JMI3_UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 9413 #define UVD_JMI3_UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 9414 #define UVD_JMI3_UVD_LMI_JRBC_CTRL__RD_MAX_BURST__SHIFT 0x4 9415 #define UVD_JMI3_UVD_LMI_JRBC_CTRL__WR_MAX_BURST__SHIFT 0x8 9416 #define UVD_JMI3_UVD_LMI_JRBC_CTRL__RD_SWAP__SHIFT 0x14 9417 #define UVD_JMI3_UVD_LMI_JRBC_CTRL__WR_SWAP__SHIFT 0x16 9418 #define UVD_JMI3_UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 9419 #define UVD_JMI3_UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 9420 #define UVD_JMI3_UVD_LMI_JRBC_CTRL__RD_MAX_BURST_MASK 0x000000F0L 9421 #define UVD_JMI3_UVD_LMI_JRBC_CTRL__WR_MAX_BURST_MASK 0x00000F00L 9422 #define UVD_JMI3_UVD_LMI_JRBC_CTRL__RD_SWAP_MASK 0x00300000L 9423 #define UVD_JMI3_UVD_LMI_JRBC_CTRL__WR_SWAP_MASK 0x00C00000L 9424 //UVD_JMI3_UVD_LMI_JPEG_CTRL 9425 #define UVD_JMI3_UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 9426 #define UVD_JMI3_UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 9427 #define UVD_JMI3_UVD_LMI_JPEG_CTRL__RD_MAX_BURST__SHIFT 0x4 9428 #define UVD_JMI3_UVD_LMI_JPEG_CTRL__WR_MAX_BURST__SHIFT 0x8 9429 #define UVD_JMI3_UVD_LMI_JPEG_CTRL__RD_SWAP__SHIFT 0x14 9430 #define UVD_JMI3_UVD_LMI_JPEG_CTRL__WR_SWAP__SHIFT 0x16 9431 #define UVD_JMI3_UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 9432 #define UVD_JMI3_UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 9433 #define UVD_JMI3_UVD_LMI_JPEG_CTRL__RD_MAX_BURST_MASK 0x000000F0L 9434 #define UVD_JMI3_UVD_LMI_JPEG_CTRL__WR_MAX_BURST_MASK 0x00000F00L 9435 #define UVD_JMI3_UVD_LMI_JPEG_CTRL__RD_SWAP_MASK 0x00300000L 9436 #define UVD_JMI3_UVD_LMI_JPEG_CTRL__WR_SWAP_MASK 0x00C00000L 9437 //UVD_JMI3_JPEG_LMI_DROP 9438 #define UVD_JMI3_JPEG_LMI_DROP__JPEG_WR_DROP__SHIFT 0x0 9439 #define UVD_JMI3_JPEG_LMI_DROP__JRBC_WR_DROP__SHIFT 0x1 9440 #define UVD_JMI3_JPEG_LMI_DROP__JPEG_RD_DROP__SHIFT 0x2 9441 #define UVD_JMI3_JPEG_LMI_DROP__JRBC_RD_DROP__SHIFT 0x3 9442 #define UVD_JMI3_JPEG_LMI_DROP__JPEG_ATOMIC_WR_DROP__SHIFT 0x4 9443 #define UVD_JMI3_JPEG_LMI_DROP__JPEG_WR_DROP_MASK 0x00000001L 9444 #define UVD_JMI3_JPEG_LMI_DROP__JRBC_WR_DROP_MASK 0x00000002L 9445 #define UVD_JMI3_JPEG_LMI_DROP__JPEG_RD_DROP_MASK 0x00000004L 9446 #define UVD_JMI3_JPEG_LMI_DROP__JRBC_RD_DROP_MASK 0x00000008L 9447 #define UVD_JMI3_JPEG_LMI_DROP__JPEG_ATOMIC_WR_DROP_MASK 0x00000010L 9448 //UVD_JMI3_UVD_LMI_JRBC_IB_VMID 9449 #define UVD_JMI3_UVD_LMI_JRBC_IB_VMID__IB_WR_VMID__SHIFT 0x0 9450 #define UVD_JMI3_UVD_LMI_JRBC_IB_VMID__IB_RD_VMID__SHIFT 0x4 9451 #define UVD_JMI3_UVD_LMI_JRBC_IB_VMID__MEM_RD_VMID__SHIFT 0x8 9452 #define UVD_JMI3_UVD_LMI_JRBC_IB_VMID__IB_WR_VMID_MASK 0x0000000FL 9453 #define UVD_JMI3_UVD_LMI_JRBC_IB_VMID__IB_RD_VMID_MASK 0x000000F0L 9454 #define UVD_JMI3_UVD_LMI_JRBC_IB_VMID__MEM_RD_VMID_MASK 0x00000F00L 9455 //UVD_JMI3_UVD_LMI_JRBC_RB_VMID 9456 #define UVD_JMI3_UVD_LMI_JRBC_RB_VMID__RB_WR_VMID__SHIFT 0x0 9457 #define UVD_JMI3_UVD_LMI_JRBC_RB_VMID__RB_RD_VMID__SHIFT 0x4 9458 #define UVD_JMI3_UVD_LMI_JRBC_RB_VMID__MEM_RD_VMID__SHIFT 0x8 9459 #define UVD_JMI3_UVD_LMI_JRBC_RB_VMID__RB_WR_VMID_MASK 0x0000000FL 9460 #define UVD_JMI3_UVD_LMI_JRBC_RB_VMID__RB_RD_VMID_MASK 0x000000F0L 9461 #define UVD_JMI3_UVD_LMI_JRBC_RB_VMID__MEM_RD_VMID_MASK 0x00000F00L 9462 //UVD_JMI3_UVD_LMI_JPEG_VMID 9463 #define UVD_JMI3_UVD_LMI_JPEG_VMID__JPEG_RD_VMID__SHIFT 0x0 9464 #define UVD_JMI3_UVD_LMI_JPEG_VMID__JPEG_WR_VMID__SHIFT 0x4 9465 #define UVD_JMI3_UVD_LMI_JPEG_VMID__ATOMIC_USER0_WR_VMID__SHIFT 0x8 9466 #define UVD_JMI3_UVD_LMI_JPEG_VMID__JPEG_RD_VMID_MASK 0x0000000FL 9467 #define UVD_JMI3_UVD_LMI_JPEG_VMID__JPEG_WR_VMID_MASK 0x000000F0L 9468 #define UVD_JMI3_UVD_LMI_JPEG_VMID__ATOMIC_USER0_WR_VMID_MASK 0x00000F00L 9469 //UVD_JMI3_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW 9470 #define UVD_JMI3_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 9471 #define UVD_JMI3_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 9472 //UVD_JMI3_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 9473 #define UVD_JMI3_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 9474 #define UVD_JMI3_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 9475 //UVD_JMI3_UVD_LMI_JRBC_RB_64BIT_BAR_LOW 9476 #define UVD_JMI3_UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 9477 #define UVD_JMI3_UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 9478 //UVD_JMI3_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH 9479 #define UVD_JMI3_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 9480 #define UVD_JMI3_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 9481 //UVD_JMI3_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW 9482 #define UVD_JMI3_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 9483 #define UVD_JMI3_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 9484 //UVD_JMI3_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH 9485 #define UVD_JMI3_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 9486 #define UVD_JMI3_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 9487 //UVD_JMI3_UVD_LMI_JPEG_PREEMPT_VMID 9488 #define UVD_JMI3_UVD_LMI_JPEG_PREEMPT_VMID__VMID__SHIFT 0x0 9489 #define UVD_JMI3_UVD_LMI_JPEG_PREEMPT_VMID__VMID_MASK 0x0000000FL 9490 //UVD_JMI3_UVD_JMI_DEC_SWAP_CNTL 9491 #define UVD_JMI3_UVD_JMI_DEC_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 9492 #define UVD_JMI3_UVD_JMI_DEC_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 9493 #define UVD_JMI3_UVD_JMI_DEC_SWAP_CNTL__RB_MEM_WR_MC_SWAP__SHIFT 0x4 9494 #define UVD_JMI3_UVD_JMI_DEC_SWAP_CNTL__IB_MEM_WR_MC_SWAP__SHIFT 0x6 9495 #define UVD_JMI3_UVD_JMI_DEC_SWAP_CNTL__RB_MEM_RD_MC_SWAP__SHIFT 0x8 9496 #define UVD_JMI3_UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT 0xa 9497 #define UVD_JMI3_UVD_JMI_DEC_SWAP_CNTL__PREEMPT_WR_MC_SWAP__SHIFT 0xc 9498 #define UVD_JMI3_UVD_JMI_DEC_SWAP_CNTL__JPEG_RD_MC_SWAP__SHIFT 0xe 9499 #define UVD_JMI3_UVD_JMI_DEC_SWAP_CNTL__JPEG_WR_MC_SWAP__SHIFT 0x10 9500 #define UVD_JMI3_UVD_JMI_DEC_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L 9501 #define UVD_JMI3_UVD_JMI_DEC_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL 9502 #define UVD_JMI3_UVD_JMI_DEC_SWAP_CNTL__RB_MEM_WR_MC_SWAP_MASK 0x00000030L 9503 #define UVD_JMI3_UVD_JMI_DEC_SWAP_CNTL__IB_MEM_WR_MC_SWAP_MASK 0x000000C0L 9504 #define UVD_JMI3_UVD_JMI_DEC_SWAP_CNTL__RB_MEM_RD_MC_SWAP_MASK 0x00000300L 9505 #define UVD_JMI3_UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP_MASK 0x00000C00L 9506 #define UVD_JMI3_UVD_JMI_DEC_SWAP_CNTL__PREEMPT_WR_MC_SWAP_MASK 0x00003000L 9507 #define UVD_JMI3_UVD_JMI_DEC_SWAP_CNTL__JPEG_RD_MC_SWAP_MASK 0x0000C000L 9508 #define UVD_JMI3_UVD_JMI_DEC_SWAP_CNTL__JPEG_WR_MC_SWAP_MASK 0x00030000L 9509 //UVD_JMI3_UVD_JMI_ATOMIC_CNTL 9510 #define UVD_JMI3_UVD_JMI_ATOMIC_CNTL__atomic_arb_wait_en__SHIFT 0x0 9511 #define UVD_JMI3_UVD_JMI_ATOMIC_CNTL__atomic_max_burst__SHIFT 0x1 9512 #define UVD_JMI3_UVD_JMI_ATOMIC_CNTL__atomic_wr_drop__SHIFT 0x5 9513 #define UVD_JMI3_UVD_JMI_ATOMIC_CNTL__atomic_wr_clamping_en__SHIFT 0x6 9514 #define UVD_JMI3_UVD_JMI_ATOMIC_CNTL__ATOMIC_WR_URG__SHIFT 0x7 9515 #define UVD_JMI3_UVD_JMI_ATOMIC_CNTL__ATOMIC_SW_GATE__SHIFT 0xb 9516 #define UVD_JMI3_UVD_JMI_ATOMIC_CNTL__atomic_arb_wait_en_MASK 0x00000001L 9517 #define UVD_JMI3_UVD_JMI_ATOMIC_CNTL__atomic_max_burst_MASK 0x0000001EL 9518 #define UVD_JMI3_UVD_JMI_ATOMIC_CNTL__atomic_wr_drop_MASK 0x00000020L 9519 #define UVD_JMI3_UVD_JMI_ATOMIC_CNTL__atomic_wr_clamping_en_MASK 0x00000040L 9520 #define UVD_JMI3_UVD_JMI_ATOMIC_CNTL__ATOMIC_WR_URG_MASK 0x00000780L 9521 #define UVD_JMI3_UVD_JMI_ATOMIC_CNTL__ATOMIC_SW_GATE_MASK 0x00000800L 9522 //UVD_JMI3_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW 9523 #define UVD_JMI3_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 9524 #define UVD_JMI3_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 9525 //UVD_JMI3_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH 9526 #define UVD_JMI3_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 9527 #define UVD_JMI3_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 9528 //UVD_JMI3_UVD_LMI_JPEG_READ_64BIT_BAR_LOW 9529 #define UVD_JMI3_UVD_LMI_JPEG_READ_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 9530 #define UVD_JMI3_UVD_LMI_JPEG_READ_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 9531 //UVD_JMI3_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH 9532 #define UVD_JMI3_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 9533 #define UVD_JMI3_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 9534 //UVD_JMI3_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 9535 #define UVD_JMI3_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 9536 #define UVD_JMI3_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 9537 //UVD_JMI3_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 9538 #define UVD_JMI3_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 9539 #define UVD_JMI3_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 9540 //UVD_JMI3_UVD_LMI_JRBC_IB_64BIT_BAR_LOW 9541 #define UVD_JMI3_UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 9542 #define UVD_JMI3_UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 9543 //UVD_JMI3_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH 9544 #define UVD_JMI3_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 9545 #define UVD_JMI3_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 9546 //UVD_JMI3_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW 9547 #define UVD_JMI3_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 9548 #define UVD_JMI3_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 9549 //UVD_JMI3_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH 9550 #define UVD_JMI3_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 9551 #define UVD_JMI3_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 9552 //UVD_JMI3_UVD_JMI_ATOMIC_CNTL2 9553 #define UVD_JMI3_UVD_JMI_ATOMIC_CNTL2__atomic_uvd_swap__SHIFT 0x10 9554 #define UVD_JMI3_UVD_JMI_ATOMIC_CNTL2__ATOMIC_MC_SWAP__SHIFT 0x18 9555 #define UVD_JMI3_UVD_JMI_ATOMIC_CNTL2__atomic_uvd_swap_MASK 0x00FF0000L 9556 #define UVD_JMI3_UVD_JMI_ATOMIC_CNTL2__ATOMIC_MC_SWAP_MASK 0xFF000000L 9557 9558 9559 // addressBlock: aid_uvd0_uvd_jmi4_uvd_jmi_dec 9560 //UVD_JMI4_UVD_JPEG_DEC_PF_CTRL 9561 #define UVD_JMI4_UVD_JPEG_DEC_PF_CTRL__DEC_PF_HANDLING_DIS__SHIFT 0x0 9562 #define UVD_JMI4_UVD_JPEG_DEC_PF_CTRL__DEC_PF_SW_GATING__SHIFT 0x1 9563 #define UVD_JMI4_UVD_JPEG_DEC_PF_CTRL__DEC_PF_HANDLING_DIS_MASK 0x00000001L 9564 #define UVD_JMI4_UVD_JPEG_DEC_PF_CTRL__DEC_PF_SW_GATING_MASK 0x00000002L 9565 //UVD_JMI4_UVD_LMI_JRBC_CTRL 9566 #define UVD_JMI4_UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 9567 #define UVD_JMI4_UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 9568 #define UVD_JMI4_UVD_LMI_JRBC_CTRL__RD_MAX_BURST__SHIFT 0x4 9569 #define UVD_JMI4_UVD_LMI_JRBC_CTRL__WR_MAX_BURST__SHIFT 0x8 9570 #define UVD_JMI4_UVD_LMI_JRBC_CTRL__RD_SWAP__SHIFT 0x14 9571 #define UVD_JMI4_UVD_LMI_JRBC_CTRL__WR_SWAP__SHIFT 0x16 9572 #define UVD_JMI4_UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 9573 #define UVD_JMI4_UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 9574 #define UVD_JMI4_UVD_LMI_JRBC_CTRL__RD_MAX_BURST_MASK 0x000000F0L 9575 #define UVD_JMI4_UVD_LMI_JRBC_CTRL__WR_MAX_BURST_MASK 0x00000F00L 9576 #define UVD_JMI4_UVD_LMI_JRBC_CTRL__RD_SWAP_MASK 0x00300000L 9577 #define UVD_JMI4_UVD_LMI_JRBC_CTRL__WR_SWAP_MASK 0x00C00000L 9578 //UVD_JMI4_UVD_LMI_JPEG_CTRL 9579 #define UVD_JMI4_UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 9580 #define UVD_JMI4_UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 9581 #define UVD_JMI4_UVD_LMI_JPEG_CTRL__RD_MAX_BURST__SHIFT 0x4 9582 #define UVD_JMI4_UVD_LMI_JPEG_CTRL__WR_MAX_BURST__SHIFT 0x8 9583 #define UVD_JMI4_UVD_LMI_JPEG_CTRL__RD_SWAP__SHIFT 0x14 9584 #define UVD_JMI4_UVD_LMI_JPEG_CTRL__WR_SWAP__SHIFT 0x16 9585 #define UVD_JMI4_UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 9586 #define UVD_JMI4_UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 9587 #define UVD_JMI4_UVD_LMI_JPEG_CTRL__RD_MAX_BURST_MASK 0x000000F0L 9588 #define UVD_JMI4_UVD_LMI_JPEG_CTRL__WR_MAX_BURST_MASK 0x00000F00L 9589 #define UVD_JMI4_UVD_LMI_JPEG_CTRL__RD_SWAP_MASK 0x00300000L 9590 #define UVD_JMI4_UVD_LMI_JPEG_CTRL__WR_SWAP_MASK 0x00C00000L 9591 //UVD_JMI4_JPEG_LMI_DROP 9592 #define UVD_JMI4_JPEG_LMI_DROP__JPEG_WR_DROP__SHIFT 0x0 9593 #define UVD_JMI4_JPEG_LMI_DROP__JRBC_WR_DROP__SHIFT 0x1 9594 #define UVD_JMI4_JPEG_LMI_DROP__JPEG_RD_DROP__SHIFT 0x2 9595 #define UVD_JMI4_JPEG_LMI_DROP__JRBC_RD_DROP__SHIFT 0x3 9596 #define UVD_JMI4_JPEG_LMI_DROP__JPEG_ATOMIC_WR_DROP__SHIFT 0x4 9597 #define UVD_JMI4_JPEG_LMI_DROP__JPEG_WR_DROP_MASK 0x00000001L 9598 #define UVD_JMI4_JPEG_LMI_DROP__JRBC_WR_DROP_MASK 0x00000002L 9599 #define UVD_JMI4_JPEG_LMI_DROP__JPEG_RD_DROP_MASK 0x00000004L 9600 #define UVD_JMI4_JPEG_LMI_DROP__JRBC_RD_DROP_MASK 0x00000008L 9601 #define UVD_JMI4_JPEG_LMI_DROP__JPEG_ATOMIC_WR_DROP_MASK 0x00000010L 9602 //UVD_JMI4_UVD_LMI_JRBC_IB_VMID 9603 #define UVD_JMI4_UVD_LMI_JRBC_IB_VMID__IB_WR_VMID__SHIFT 0x0 9604 #define UVD_JMI4_UVD_LMI_JRBC_IB_VMID__IB_RD_VMID__SHIFT 0x4 9605 #define UVD_JMI4_UVD_LMI_JRBC_IB_VMID__MEM_RD_VMID__SHIFT 0x8 9606 #define UVD_JMI4_UVD_LMI_JRBC_IB_VMID__IB_WR_VMID_MASK 0x0000000FL 9607 #define UVD_JMI4_UVD_LMI_JRBC_IB_VMID__IB_RD_VMID_MASK 0x000000F0L 9608 #define UVD_JMI4_UVD_LMI_JRBC_IB_VMID__MEM_RD_VMID_MASK 0x00000F00L 9609 //UVD_JMI4_UVD_LMI_JRBC_RB_VMID 9610 #define UVD_JMI4_UVD_LMI_JRBC_RB_VMID__RB_WR_VMID__SHIFT 0x0 9611 #define UVD_JMI4_UVD_LMI_JRBC_RB_VMID__RB_RD_VMID__SHIFT 0x4 9612 #define UVD_JMI4_UVD_LMI_JRBC_RB_VMID__MEM_RD_VMID__SHIFT 0x8 9613 #define UVD_JMI4_UVD_LMI_JRBC_RB_VMID__RB_WR_VMID_MASK 0x0000000FL 9614 #define UVD_JMI4_UVD_LMI_JRBC_RB_VMID__RB_RD_VMID_MASK 0x000000F0L 9615 #define UVD_JMI4_UVD_LMI_JRBC_RB_VMID__MEM_RD_VMID_MASK 0x00000F00L 9616 //UVD_JMI4_UVD_LMI_JPEG_VMID 9617 #define UVD_JMI4_UVD_LMI_JPEG_VMID__JPEG_RD_VMID__SHIFT 0x0 9618 #define UVD_JMI4_UVD_LMI_JPEG_VMID__JPEG_WR_VMID__SHIFT 0x4 9619 #define UVD_JMI4_UVD_LMI_JPEG_VMID__ATOMIC_USER0_WR_VMID__SHIFT 0x8 9620 #define UVD_JMI4_UVD_LMI_JPEG_VMID__JPEG_RD_VMID_MASK 0x0000000FL 9621 #define UVD_JMI4_UVD_LMI_JPEG_VMID__JPEG_WR_VMID_MASK 0x000000F0L 9622 #define UVD_JMI4_UVD_LMI_JPEG_VMID__ATOMIC_USER0_WR_VMID_MASK 0x00000F00L 9623 //UVD_JMI4_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW 9624 #define UVD_JMI4_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 9625 #define UVD_JMI4_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 9626 //UVD_JMI4_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 9627 #define UVD_JMI4_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 9628 #define UVD_JMI4_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 9629 //UVD_JMI4_UVD_LMI_JRBC_RB_64BIT_BAR_LOW 9630 #define UVD_JMI4_UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 9631 #define UVD_JMI4_UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 9632 //UVD_JMI4_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH 9633 #define UVD_JMI4_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 9634 #define UVD_JMI4_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 9635 //UVD_JMI4_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW 9636 #define UVD_JMI4_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 9637 #define UVD_JMI4_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 9638 //UVD_JMI4_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH 9639 #define UVD_JMI4_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 9640 #define UVD_JMI4_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 9641 //UVD_JMI4_UVD_LMI_JPEG_PREEMPT_VMID 9642 #define UVD_JMI4_UVD_LMI_JPEG_PREEMPT_VMID__VMID__SHIFT 0x0 9643 #define UVD_JMI4_UVD_LMI_JPEG_PREEMPT_VMID__VMID_MASK 0x0000000FL 9644 //UVD_JMI4_UVD_JMI_DEC_SWAP_CNTL 9645 #define UVD_JMI4_UVD_JMI_DEC_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 9646 #define UVD_JMI4_UVD_JMI_DEC_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 9647 #define UVD_JMI4_UVD_JMI_DEC_SWAP_CNTL__RB_MEM_WR_MC_SWAP__SHIFT 0x4 9648 #define UVD_JMI4_UVD_JMI_DEC_SWAP_CNTL__IB_MEM_WR_MC_SWAP__SHIFT 0x6 9649 #define UVD_JMI4_UVD_JMI_DEC_SWAP_CNTL__RB_MEM_RD_MC_SWAP__SHIFT 0x8 9650 #define UVD_JMI4_UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT 0xa 9651 #define UVD_JMI4_UVD_JMI_DEC_SWAP_CNTL__PREEMPT_WR_MC_SWAP__SHIFT 0xc 9652 #define UVD_JMI4_UVD_JMI_DEC_SWAP_CNTL__JPEG_RD_MC_SWAP__SHIFT 0xe 9653 #define UVD_JMI4_UVD_JMI_DEC_SWAP_CNTL__JPEG_WR_MC_SWAP__SHIFT 0x10 9654 #define UVD_JMI4_UVD_JMI_DEC_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L 9655 #define UVD_JMI4_UVD_JMI_DEC_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL 9656 #define UVD_JMI4_UVD_JMI_DEC_SWAP_CNTL__RB_MEM_WR_MC_SWAP_MASK 0x00000030L 9657 #define UVD_JMI4_UVD_JMI_DEC_SWAP_CNTL__IB_MEM_WR_MC_SWAP_MASK 0x000000C0L 9658 #define UVD_JMI4_UVD_JMI_DEC_SWAP_CNTL__RB_MEM_RD_MC_SWAP_MASK 0x00000300L 9659 #define UVD_JMI4_UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP_MASK 0x00000C00L 9660 #define UVD_JMI4_UVD_JMI_DEC_SWAP_CNTL__PREEMPT_WR_MC_SWAP_MASK 0x00003000L 9661 #define UVD_JMI4_UVD_JMI_DEC_SWAP_CNTL__JPEG_RD_MC_SWAP_MASK 0x0000C000L 9662 #define UVD_JMI4_UVD_JMI_DEC_SWAP_CNTL__JPEG_WR_MC_SWAP_MASK 0x00030000L 9663 //UVD_JMI4_UVD_JMI_ATOMIC_CNTL 9664 #define UVD_JMI4_UVD_JMI_ATOMIC_CNTL__atomic_arb_wait_en__SHIFT 0x0 9665 #define UVD_JMI4_UVD_JMI_ATOMIC_CNTL__atomic_max_burst__SHIFT 0x1 9666 #define UVD_JMI4_UVD_JMI_ATOMIC_CNTL__atomic_wr_drop__SHIFT 0x5 9667 #define UVD_JMI4_UVD_JMI_ATOMIC_CNTL__atomic_wr_clamping_en__SHIFT 0x6 9668 #define UVD_JMI4_UVD_JMI_ATOMIC_CNTL__ATOMIC_WR_URG__SHIFT 0x7 9669 #define UVD_JMI4_UVD_JMI_ATOMIC_CNTL__ATOMIC_SW_GATE__SHIFT 0xb 9670 #define UVD_JMI4_UVD_JMI_ATOMIC_CNTL__atomic_arb_wait_en_MASK 0x00000001L 9671 #define UVD_JMI4_UVD_JMI_ATOMIC_CNTL__atomic_max_burst_MASK 0x0000001EL 9672 #define UVD_JMI4_UVD_JMI_ATOMIC_CNTL__atomic_wr_drop_MASK 0x00000020L 9673 #define UVD_JMI4_UVD_JMI_ATOMIC_CNTL__atomic_wr_clamping_en_MASK 0x00000040L 9674 #define UVD_JMI4_UVD_JMI_ATOMIC_CNTL__ATOMIC_WR_URG_MASK 0x00000780L 9675 #define UVD_JMI4_UVD_JMI_ATOMIC_CNTL__ATOMIC_SW_GATE_MASK 0x00000800L 9676 //UVD_JMI4_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW 9677 #define UVD_JMI4_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 9678 #define UVD_JMI4_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 9679 //UVD_JMI4_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH 9680 #define UVD_JMI4_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 9681 #define UVD_JMI4_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 9682 //UVD_JMI4_UVD_LMI_JPEG_READ_64BIT_BAR_LOW 9683 #define UVD_JMI4_UVD_LMI_JPEG_READ_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 9684 #define UVD_JMI4_UVD_LMI_JPEG_READ_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 9685 //UVD_JMI4_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH 9686 #define UVD_JMI4_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 9687 #define UVD_JMI4_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 9688 //UVD_JMI4_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 9689 #define UVD_JMI4_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 9690 #define UVD_JMI4_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 9691 //UVD_JMI4_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 9692 #define UVD_JMI4_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 9693 #define UVD_JMI4_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 9694 //UVD_JMI4_UVD_LMI_JRBC_IB_64BIT_BAR_LOW 9695 #define UVD_JMI4_UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 9696 #define UVD_JMI4_UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 9697 //UVD_JMI4_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH 9698 #define UVD_JMI4_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 9699 #define UVD_JMI4_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 9700 //UVD_JMI4_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW 9701 #define UVD_JMI4_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 9702 #define UVD_JMI4_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 9703 //UVD_JMI4_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH 9704 #define UVD_JMI4_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 9705 #define UVD_JMI4_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 9706 //UVD_JMI4_UVD_JMI_ATOMIC_CNTL2 9707 #define UVD_JMI4_UVD_JMI_ATOMIC_CNTL2__atomic_uvd_swap__SHIFT 0x10 9708 #define UVD_JMI4_UVD_JMI_ATOMIC_CNTL2__ATOMIC_MC_SWAP__SHIFT 0x18 9709 #define UVD_JMI4_UVD_JMI_ATOMIC_CNTL2__atomic_uvd_swap_MASK 0x00FF0000L 9710 #define UVD_JMI4_UVD_JMI_ATOMIC_CNTL2__ATOMIC_MC_SWAP_MASK 0xFF000000L 9711 9712 9713 // addressBlock: aid_uvd0_uvd_jmi5_uvd_jmi_dec 9714 //UVD_JMI5_UVD_JPEG_DEC_PF_CTRL 9715 #define UVD_JMI5_UVD_JPEG_DEC_PF_CTRL__DEC_PF_HANDLING_DIS__SHIFT 0x0 9716 #define UVD_JMI5_UVD_JPEG_DEC_PF_CTRL__DEC_PF_SW_GATING__SHIFT 0x1 9717 #define UVD_JMI5_UVD_JPEG_DEC_PF_CTRL__DEC_PF_HANDLING_DIS_MASK 0x00000001L 9718 #define UVD_JMI5_UVD_JPEG_DEC_PF_CTRL__DEC_PF_SW_GATING_MASK 0x00000002L 9719 //UVD_JMI5_UVD_LMI_JRBC_CTRL 9720 #define UVD_JMI5_UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 9721 #define UVD_JMI5_UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 9722 #define UVD_JMI5_UVD_LMI_JRBC_CTRL__RD_MAX_BURST__SHIFT 0x4 9723 #define UVD_JMI5_UVD_LMI_JRBC_CTRL__WR_MAX_BURST__SHIFT 0x8 9724 #define UVD_JMI5_UVD_LMI_JRBC_CTRL__RD_SWAP__SHIFT 0x14 9725 #define UVD_JMI5_UVD_LMI_JRBC_CTRL__WR_SWAP__SHIFT 0x16 9726 #define UVD_JMI5_UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 9727 #define UVD_JMI5_UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 9728 #define UVD_JMI5_UVD_LMI_JRBC_CTRL__RD_MAX_BURST_MASK 0x000000F0L 9729 #define UVD_JMI5_UVD_LMI_JRBC_CTRL__WR_MAX_BURST_MASK 0x00000F00L 9730 #define UVD_JMI5_UVD_LMI_JRBC_CTRL__RD_SWAP_MASK 0x00300000L 9731 #define UVD_JMI5_UVD_LMI_JRBC_CTRL__WR_SWAP_MASK 0x00C00000L 9732 //UVD_JMI5_UVD_LMI_JPEG_CTRL 9733 #define UVD_JMI5_UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 9734 #define UVD_JMI5_UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 9735 #define UVD_JMI5_UVD_LMI_JPEG_CTRL__RD_MAX_BURST__SHIFT 0x4 9736 #define UVD_JMI5_UVD_LMI_JPEG_CTRL__WR_MAX_BURST__SHIFT 0x8 9737 #define UVD_JMI5_UVD_LMI_JPEG_CTRL__RD_SWAP__SHIFT 0x14 9738 #define UVD_JMI5_UVD_LMI_JPEG_CTRL__WR_SWAP__SHIFT 0x16 9739 #define UVD_JMI5_UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 9740 #define UVD_JMI5_UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 9741 #define UVD_JMI5_UVD_LMI_JPEG_CTRL__RD_MAX_BURST_MASK 0x000000F0L 9742 #define UVD_JMI5_UVD_LMI_JPEG_CTRL__WR_MAX_BURST_MASK 0x00000F00L 9743 #define UVD_JMI5_UVD_LMI_JPEG_CTRL__RD_SWAP_MASK 0x00300000L 9744 #define UVD_JMI5_UVD_LMI_JPEG_CTRL__WR_SWAP_MASK 0x00C00000L 9745 //UVD_JMI5_JPEG_LMI_DROP 9746 #define UVD_JMI5_JPEG_LMI_DROP__JPEG_WR_DROP__SHIFT 0x0 9747 #define UVD_JMI5_JPEG_LMI_DROP__JRBC_WR_DROP__SHIFT 0x1 9748 #define UVD_JMI5_JPEG_LMI_DROP__JPEG_RD_DROP__SHIFT 0x2 9749 #define UVD_JMI5_JPEG_LMI_DROP__JRBC_RD_DROP__SHIFT 0x3 9750 #define UVD_JMI5_JPEG_LMI_DROP__JPEG_ATOMIC_WR_DROP__SHIFT 0x4 9751 #define UVD_JMI5_JPEG_LMI_DROP__JPEG_WR_DROP_MASK 0x00000001L 9752 #define UVD_JMI5_JPEG_LMI_DROP__JRBC_WR_DROP_MASK 0x00000002L 9753 #define UVD_JMI5_JPEG_LMI_DROP__JPEG_RD_DROP_MASK 0x00000004L 9754 #define UVD_JMI5_JPEG_LMI_DROP__JRBC_RD_DROP_MASK 0x00000008L 9755 #define UVD_JMI5_JPEG_LMI_DROP__JPEG_ATOMIC_WR_DROP_MASK 0x00000010L 9756 //UVD_JMI5_UVD_LMI_JRBC_IB_VMID 9757 #define UVD_JMI5_UVD_LMI_JRBC_IB_VMID__IB_WR_VMID__SHIFT 0x0 9758 #define UVD_JMI5_UVD_LMI_JRBC_IB_VMID__IB_RD_VMID__SHIFT 0x4 9759 #define UVD_JMI5_UVD_LMI_JRBC_IB_VMID__MEM_RD_VMID__SHIFT 0x8 9760 #define UVD_JMI5_UVD_LMI_JRBC_IB_VMID__IB_WR_VMID_MASK 0x0000000FL 9761 #define UVD_JMI5_UVD_LMI_JRBC_IB_VMID__IB_RD_VMID_MASK 0x000000F0L 9762 #define UVD_JMI5_UVD_LMI_JRBC_IB_VMID__MEM_RD_VMID_MASK 0x00000F00L 9763 //UVD_JMI5_UVD_LMI_JRBC_RB_VMID 9764 #define UVD_JMI5_UVD_LMI_JRBC_RB_VMID__RB_WR_VMID__SHIFT 0x0 9765 #define UVD_JMI5_UVD_LMI_JRBC_RB_VMID__RB_RD_VMID__SHIFT 0x4 9766 #define UVD_JMI5_UVD_LMI_JRBC_RB_VMID__MEM_RD_VMID__SHIFT 0x8 9767 #define UVD_JMI5_UVD_LMI_JRBC_RB_VMID__RB_WR_VMID_MASK 0x0000000FL 9768 #define UVD_JMI5_UVD_LMI_JRBC_RB_VMID__RB_RD_VMID_MASK 0x000000F0L 9769 #define UVD_JMI5_UVD_LMI_JRBC_RB_VMID__MEM_RD_VMID_MASK 0x00000F00L 9770 //UVD_JMI5_UVD_LMI_JPEG_VMID 9771 #define UVD_JMI5_UVD_LMI_JPEG_VMID__JPEG_RD_VMID__SHIFT 0x0 9772 #define UVD_JMI5_UVD_LMI_JPEG_VMID__JPEG_WR_VMID__SHIFT 0x4 9773 #define UVD_JMI5_UVD_LMI_JPEG_VMID__ATOMIC_USER0_WR_VMID__SHIFT 0x8 9774 #define UVD_JMI5_UVD_LMI_JPEG_VMID__JPEG_RD_VMID_MASK 0x0000000FL 9775 #define UVD_JMI5_UVD_LMI_JPEG_VMID__JPEG_WR_VMID_MASK 0x000000F0L 9776 #define UVD_JMI5_UVD_LMI_JPEG_VMID__ATOMIC_USER0_WR_VMID_MASK 0x00000F00L 9777 //UVD_JMI5_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW 9778 #define UVD_JMI5_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 9779 #define UVD_JMI5_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 9780 //UVD_JMI5_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 9781 #define UVD_JMI5_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 9782 #define UVD_JMI5_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 9783 //UVD_JMI5_UVD_LMI_JRBC_RB_64BIT_BAR_LOW 9784 #define UVD_JMI5_UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 9785 #define UVD_JMI5_UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 9786 //UVD_JMI5_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH 9787 #define UVD_JMI5_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 9788 #define UVD_JMI5_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 9789 //UVD_JMI5_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW 9790 #define UVD_JMI5_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 9791 #define UVD_JMI5_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 9792 //UVD_JMI5_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH 9793 #define UVD_JMI5_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 9794 #define UVD_JMI5_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 9795 //UVD_JMI5_UVD_LMI_JPEG_PREEMPT_VMID 9796 #define UVD_JMI5_UVD_LMI_JPEG_PREEMPT_VMID__VMID__SHIFT 0x0 9797 #define UVD_JMI5_UVD_LMI_JPEG_PREEMPT_VMID__VMID_MASK 0x0000000FL 9798 //UVD_JMI5_UVD_JMI_DEC_SWAP_CNTL 9799 #define UVD_JMI5_UVD_JMI_DEC_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 9800 #define UVD_JMI5_UVD_JMI_DEC_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 9801 #define UVD_JMI5_UVD_JMI_DEC_SWAP_CNTL__RB_MEM_WR_MC_SWAP__SHIFT 0x4 9802 #define UVD_JMI5_UVD_JMI_DEC_SWAP_CNTL__IB_MEM_WR_MC_SWAP__SHIFT 0x6 9803 #define UVD_JMI5_UVD_JMI_DEC_SWAP_CNTL__RB_MEM_RD_MC_SWAP__SHIFT 0x8 9804 #define UVD_JMI5_UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT 0xa 9805 #define UVD_JMI5_UVD_JMI_DEC_SWAP_CNTL__PREEMPT_WR_MC_SWAP__SHIFT 0xc 9806 #define UVD_JMI5_UVD_JMI_DEC_SWAP_CNTL__JPEG_RD_MC_SWAP__SHIFT 0xe 9807 #define UVD_JMI5_UVD_JMI_DEC_SWAP_CNTL__JPEG_WR_MC_SWAP__SHIFT 0x10 9808 #define UVD_JMI5_UVD_JMI_DEC_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L 9809 #define UVD_JMI5_UVD_JMI_DEC_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL 9810 #define UVD_JMI5_UVD_JMI_DEC_SWAP_CNTL__RB_MEM_WR_MC_SWAP_MASK 0x00000030L 9811 #define UVD_JMI5_UVD_JMI_DEC_SWAP_CNTL__IB_MEM_WR_MC_SWAP_MASK 0x000000C0L 9812 #define UVD_JMI5_UVD_JMI_DEC_SWAP_CNTL__RB_MEM_RD_MC_SWAP_MASK 0x00000300L 9813 #define UVD_JMI5_UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP_MASK 0x00000C00L 9814 #define UVD_JMI5_UVD_JMI_DEC_SWAP_CNTL__PREEMPT_WR_MC_SWAP_MASK 0x00003000L 9815 #define UVD_JMI5_UVD_JMI_DEC_SWAP_CNTL__JPEG_RD_MC_SWAP_MASK 0x0000C000L 9816 #define UVD_JMI5_UVD_JMI_DEC_SWAP_CNTL__JPEG_WR_MC_SWAP_MASK 0x00030000L 9817 //UVD_JMI5_UVD_JMI_ATOMIC_CNTL 9818 #define UVD_JMI5_UVD_JMI_ATOMIC_CNTL__atomic_arb_wait_en__SHIFT 0x0 9819 #define UVD_JMI5_UVD_JMI_ATOMIC_CNTL__atomic_max_burst__SHIFT 0x1 9820 #define UVD_JMI5_UVD_JMI_ATOMIC_CNTL__atomic_wr_drop__SHIFT 0x5 9821 #define UVD_JMI5_UVD_JMI_ATOMIC_CNTL__atomic_wr_clamping_en__SHIFT 0x6 9822 #define UVD_JMI5_UVD_JMI_ATOMIC_CNTL__ATOMIC_WR_URG__SHIFT 0x7 9823 #define UVD_JMI5_UVD_JMI_ATOMIC_CNTL__ATOMIC_SW_GATE__SHIFT 0xb 9824 #define UVD_JMI5_UVD_JMI_ATOMIC_CNTL__atomic_arb_wait_en_MASK 0x00000001L 9825 #define UVD_JMI5_UVD_JMI_ATOMIC_CNTL__atomic_max_burst_MASK 0x0000001EL 9826 #define UVD_JMI5_UVD_JMI_ATOMIC_CNTL__atomic_wr_drop_MASK 0x00000020L 9827 #define UVD_JMI5_UVD_JMI_ATOMIC_CNTL__atomic_wr_clamping_en_MASK 0x00000040L 9828 #define UVD_JMI5_UVD_JMI_ATOMIC_CNTL__ATOMIC_WR_URG_MASK 0x00000780L 9829 #define UVD_JMI5_UVD_JMI_ATOMIC_CNTL__ATOMIC_SW_GATE_MASK 0x00000800L 9830 //UVD_JMI5_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW 9831 #define UVD_JMI5_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 9832 #define UVD_JMI5_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 9833 //UVD_JMI5_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH 9834 #define UVD_JMI5_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 9835 #define UVD_JMI5_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 9836 //UVD_JMI5_UVD_LMI_JPEG_READ_64BIT_BAR_LOW 9837 #define UVD_JMI5_UVD_LMI_JPEG_READ_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 9838 #define UVD_JMI5_UVD_LMI_JPEG_READ_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 9839 //UVD_JMI5_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH 9840 #define UVD_JMI5_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 9841 #define UVD_JMI5_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 9842 //UVD_JMI5_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 9843 #define UVD_JMI5_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 9844 #define UVD_JMI5_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 9845 //UVD_JMI5_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 9846 #define UVD_JMI5_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 9847 #define UVD_JMI5_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 9848 //UVD_JMI5_UVD_LMI_JRBC_IB_64BIT_BAR_LOW 9849 #define UVD_JMI5_UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 9850 #define UVD_JMI5_UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 9851 //UVD_JMI5_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH 9852 #define UVD_JMI5_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 9853 #define UVD_JMI5_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 9854 //UVD_JMI5_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW 9855 #define UVD_JMI5_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 9856 #define UVD_JMI5_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 9857 //UVD_JMI5_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH 9858 #define UVD_JMI5_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 9859 #define UVD_JMI5_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 9860 //UVD_JMI5_UVD_JMI_ATOMIC_CNTL2 9861 #define UVD_JMI5_UVD_JMI_ATOMIC_CNTL2__atomic_uvd_swap__SHIFT 0x10 9862 #define UVD_JMI5_UVD_JMI_ATOMIC_CNTL2__ATOMIC_MC_SWAP__SHIFT 0x18 9863 #define UVD_JMI5_UVD_JMI_ATOMIC_CNTL2__atomic_uvd_swap_MASK 0x00FF0000L 9864 #define UVD_JMI5_UVD_JMI_ATOMIC_CNTL2__ATOMIC_MC_SWAP_MASK 0xFF000000L 9865 9866 9867 // addressBlock: aid_uvd0_uvd_jmi6_uvd_jmi_dec 9868 //UVD_JMI6_UVD_JPEG_DEC_PF_CTRL 9869 #define UVD_JMI6_UVD_JPEG_DEC_PF_CTRL__DEC_PF_HANDLING_DIS__SHIFT 0x0 9870 #define UVD_JMI6_UVD_JPEG_DEC_PF_CTRL__DEC_PF_SW_GATING__SHIFT 0x1 9871 #define UVD_JMI6_UVD_JPEG_DEC_PF_CTRL__DEC_PF_HANDLING_DIS_MASK 0x00000001L 9872 #define UVD_JMI6_UVD_JPEG_DEC_PF_CTRL__DEC_PF_SW_GATING_MASK 0x00000002L 9873 //UVD_JMI6_UVD_LMI_JRBC_CTRL 9874 #define UVD_JMI6_UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 9875 #define UVD_JMI6_UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 9876 #define UVD_JMI6_UVD_LMI_JRBC_CTRL__RD_MAX_BURST__SHIFT 0x4 9877 #define UVD_JMI6_UVD_LMI_JRBC_CTRL__WR_MAX_BURST__SHIFT 0x8 9878 #define UVD_JMI6_UVD_LMI_JRBC_CTRL__RD_SWAP__SHIFT 0x14 9879 #define UVD_JMI6_UVD_LMI_JRBC_CTRL__WR_SWAP__SHIFT 0x16 9880 #define UVD_JMI6_UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 9881 #define UVD_JMI6_UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 9882 #define UVD_JMI6_UVD_LMI_JRBC_CTRL__RD_MAX_BURST_MASK 0x000000F0L 9883 #define UVD_JMI6_UVD_LMI_JRBC_CTRL__WR_MAX_BURST_MASK 0x00000F00L 9884 #define UVD_JMI6_UVD_LMI_JRBC_CTRL__RD_SWAP_MASK 0x00300000L 9885 #define UVD_JMI6_UVD_LMI_JRBC_CTRL__WR_SWAP_MASK 0x00C00000L 9886 //UVD_JMI6_UVD_LMI_JPEG_CTRL 9887 #define UVD_JMI6_UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 9888 #define UVD_JMI6_UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 9889 #define UVD_JMI6_UVD_LMI_JPEG_CTRL__RD_MAX_BURST__SHIFT 0x4 9890 #define UVD_JMI6_UVD_LMI_JPEG_CTRL__WR_MAX_BURST__SHIFT 0x8 9891 #define UVD_JMI6_UVD_LMI_JPEG_CTRL__RD_SWAP__SHIFT 0x14 9892 #define UVD_JMI6_UVD_LMI_JPEG_CTRL__WR_SWAP__SHIFT 0x16 9893 #define UVD_JMI6_UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 9894 #define UVD_JMI6_UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 9895 #define UVD_JMI6_UVD_LMI_JPEG_CTRL__RD_MAX_BURST_MASK 0x000000F0L 9896 #define UVD_JMI6_UVD_LMI_JPEG_CTRL__WR_MAX_BURST_MASK 0x00000F00L 9897 #define UVD_JMI6_UVD_LMI_JPEG_CTRL__RD_SWAP_MASK 0x00300000L 9898 #define UVD_JMI6_UVD_LMI_JPEG_CTRL__WR_SWAP_MASK 0x00C00000L 9899 //UVD_JMI6_JPEG_LMI_DROP 9900 #define UVD_JMI6_JPEG_LMI_DROP__JPEG_WR_DROP__SHIFT 0x0 9901 #define UVD_JMI6_JPEG_LMI_DROP__JRBC_WR_DROP__SHIFT 0x1 9902 #define UVD_JMI6_JPEG_LMI_DROP__JPEG_RD_DROP__SHIFT 0x2 9903 #define UVD_JMI6_JPEG_LMI_DROP__JRBC_RD_DROP__SHIFT 0x3 9904 #define UVD_JMI6_JPEG_LMI_DROP__JPEG_ATOMIC_WR_DROP__SHIFT 0x4 9905 #define UVD_JMI6_JPEG_LMI_DROP__JPEG_WR_DROP_MASK 0x00000001L 9906 #define UVD_JMI6_JPEG_LMI_DROP__JRBC_WR_DROP_MASK 0x00000002L 9907 #define UVD_JMI6_JPEG_LMI_DROP__JPEG_RD_DROP_MASK 0x00000004L 9908 #define UVD_JMI6_JPEG_LMI_DROP__JRBC_RD_DROP_MASK 0x00000008L 9909 #define UVD_JMI6_JPEG_LMI_DROP__JPEG_ATOMIC_WR_DROP_MASK 0x00000010L 9910 //UVD_JMI6_UVD_LMI_JRBC_IB_VMID 9911 #define UVD_JMI6_UVD_LMI_JRBC_IB_VMID__IB_WR_VMID__SHIFT 0x0 9912 #define UVD_JMI6_UVD_LMI_JRBC_IB_VMID__IB_RD_VMID__SHIFT 0x4 9913 #define UVD_JMI6_UVD_LMI_JRBC_IB_VMID__MEM_RD_VMID__SHIFT 0x8 9914 #define UVD_JMI6_UVD_LMI_JRBC_IB_VMID__IB_WR_VMID_MASK 0x0000000FL 9915 #define UVD_JMI6_UVD_LMI_JRBC_IB_VMID__IB_RD_VMID_MASK 0x000000F0L 9916 #define UVD_JMI6_UVD_LMI_JRBC_IB_VMID__MEM_RD_VMID_MASK 0x00000F00L 9917 //UVD_JMI6_UVD_LMI_JRBC_RB_VMID 9918 #define UVD_JMI6_UVD_LMI_JRBC_RB_VMID__RB_WR_VMID__SHIFT 0x0 9919 #define UVD_JMI6_UVD_LMI_JRBC_RB_VMID__RB_RD_VMID__SHIFT 0x4 9920 #define UVD_JMI6_UVD_LMI_JRBC_RB_VMID__MEM_RD_VMID__SHIFT 0x8 9921 #define UVD_JMI6_UVD_LMI_JRBC_RB_VMID__RB_WR_VMID_MASK 0x0000000FL 9922 #define UVD_JMI6_UVD_LMI_JRBC_RB_VMID__RB_RD_VMID_MASK 0x000000F0L 9923 #define UVD_JMI6_UVD_LMI_JRBC_RB_VMID__MEM_RD_VMID_MASK 0x00000F00L 9924 //UVD_JMI6_UVD_LMI_JPEG_VMID 9925 #define UVD_JMI6_UVD_LMI_JPEG_VMID__JPEG_RD_VMID__SHIFT 0x0 9926 #define UVD_JMI6_UVD_LMI_JPEG_VMID__JPEG_WR_VMID__SHIFT 0x4 9927 #define UVD_JMI6_UVD_LMI_JPEG_VMID__ATOMIC_USER0_WR_VMID__SHIFT 0x8 9928 #define UVD_JMI6_UVD_LMI_JPEG_VMID__JPEG_RD_VMID_MASK 0x0000000FL 9929 #define UVD_JMI6_UVD_LMI_JPEG_VMID__JPEG_WR_VMID_MASK 0x000000F0L 9930 #define UVD_JMI6_UVD_LMI_JPEG_VMID__ATOMIC_USER0_WR_VMID_MASK 0x00000F00L 9931 //UVD_JMI6_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW 9932 #define UVD_JMI6_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 9933 #define UVD_JMI6_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 9934 //UVD_JMI6_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 9935 #define UVD_JMI6_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 9936 #define UVD_JMI6_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 9937 //UVD_JMI6_UVD_LMI_JRBC_RB_64BIT_BAR_LOW 9938 #define UVD_JMI6_UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 9939 #define UVD_JMI6_UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 9940 //UVD_JMI6_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH 9941 #define UVD_JMI6_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 9942 #define UVD_JMI6_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 9943 //UVD_JMI6_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW 9944 #define UVD_JMI6_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 9945 #define UVD_JMI6_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 9946 //UVD_JMI6_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH 9947 #define UVD_JMI6_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 9948 #define UVD_JMI6_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 9949 //UVD_JMI6_UVD_LMI_JPEG_PREEMPT_VMID 9950 #define UVD_JMI6_UVD_LMI_JPEG_PREEMPT_VMID__VMID__SHIFT 0x0 9951 #define UVD_JMI6_UVD_LMI_JPEG_PREEMPT_VMID__VMID_MASK 0x0000000FL 9952 //UVD_JMI6_UVD_JMI_DEC_SWAP_CNTL 9953 #define UVD_JMI6_UVD_JMI_DEC_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 9954 #define UVD_JMI6_UVD_JMI_DEC_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 9955 #define UVD_JMI6_UVD_JMI_DEC_SWAP_CNTL__RB_MEM_WR_MC_SWAP__SHIFT 0x4 9956 #define UVD_JMI6_UVD_JMI_DEC_SWAP_CNTL__IB_MEM_WR_MC_SWAP__SHIFT 0x6 9957 #define UVD_JMI6_UVD_JMI_DEC_SWAP_CNTL__RB_MEM_RD_MC_SWAP__SHIFT 0x8 9958 #define UVD_JMI6_UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT 0xa 9959 #define UVD_JMI6_UVD_JMI_DEC_SWAP_CNTL__PREEMPT_WR_MC_SWAP__SHIFT 0xc 9960 #define UVD_JMI6_UVD_JMI_DEC_SWAP_CNTL__JPEG_RD_MC_SWAP__SHIFT 0xe 9961 #define UVD_JMI6_UVD_JMI_DEC_SWAP_CNTL__JPEG_WR_MC_SWAP__SHIFT 0x10 9962 #define UVD_JMI6_UVD_JMI_DEC_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L 9963 #define UVD_JMI6_UVD_JMI_DEC_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL 9964 #define UVD_JMI6_UVD_JMI_DEC_SWAP_CNTL__RB_MEM_WR_MC_SWAP_MASK 0x00000030L 9965 #define UVD_JMI6_UVD_JMI_DEC_SWAP_CNTL__IB_MEM_WR_MC_SWAP_MASK 0x000000C0L 9966 #define UVD_JMI6_UVD_JMI_DEC_SWAP_CNTL__RB_MEM_RD_MC_SWAP_MASK 0x00000300L 9967 #define UVD_JMI6_UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP_MASK 0x00000C00L 9968 #define UVD_JMI6_UVD_JMI_DEC_SWAP_CNTL__PREEMPT_WR_MC_SWAP_MASK 0x00003000L 9969 #define UVD_JMI6_UVD_JMI_DEC_SWAP_CNTL__JPEG_RD_MC_SWAP_MASK 0x0000C000L 9970 #define UVD_JMI6_UVD_JMI_DEC_SWAP_CNTL__JPEG_WR_MC_SWAP_MASK 0x00030000L 9971 //UVD_JMI6_UVD_JMI_ATOMIC_CNTL 9972 #define UVD_JMI6_UVD_JMI_ATOMIC_CNTL__atomic_arb_wait_en__SHIFT 0x0 9973 #define UVD_JMI6_UVD_JMI_ATOMIC_CNTL__atomic_max_burst__SHIFT 0x1 9974 #define UVD_JMI6_UVD_JMI_ATOMIC_CNTL__atomic_wr_drop__SHIFT 0x5 9975 #define UVD_JMI6_UVD_JMI_ATOMIC_CNTL__atomic_wr_clamping_en__SHIFT 0x6 9976 #define UVD_JMI6_UVD_JMI_ATOMIC_CNTL__ATOMIC_WR_URG__SHIFT 0x7 9977 #define UVD_JMI6_UVD_JMI_ATOMIC_CNTL__ATOMIC_SW_GATE__SHIFT 0xb 9978 #define UVD_JMI6_UVD_JMI_ATOMIC_CNTL__atomic_arb_wait_en_MASK 0x00000001L 9979 #define UVD_JMI6_UVD_JMI_ATOMIC_CNTL__atomic_max_burst_MASK 0x0000001EL 9980 #define UVD_JMI6_UVD_JMI_ATOMIC_CNTL__atomic_wr_drop_MASK 0x00000020L 9981 #define UVD_JMI6_UVD_JMI_ATOMIC_CNTL__atomic_wr_clamping_en_MASK 0x00000040L 9982 #define UVD_JMI6_UVD_JMI_ATOMIC_CNTL__ATOMIC_WR_URG_MASK 0x00000780L 9983 #define UVD_JMI6_UVD_JMI_ATOMIC_CNTL__ATOMIC_SW_GATE_MASK 0x00000800L 9984 //UVD_JMI6_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW 9985 #define UVD_JMI6_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 9986 #define UVD_JMI6_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 9987 //UVD_JMI6_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH 9988 #define UVD_JMI6_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 9989 #define UVD_JMI6_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 9990 //UVD_JMI6_UVD_LMI_JPEG_READ_64BIT_BAR_LOW 9991 #define UVD_JMI6_UVD_LMI_JPEG_READ_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 9992 #define UVD_JMI6_UVD_LMI_JPEG_READ_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 9993 //UVD_JMI6_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH 9994 #define UVD_JMI6_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 9995 #define UVD_JMI6_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 9996 //UVD_JMI6_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 9997 #define UVD_JMI6_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 9998 #define UVD_JMI6_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 9999 //UVD_JMI6_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 10000 #define UVD_JMI6_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 10001 #define UVD_JMI6_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 10002 //UVD_JMI6_UVD_LMI_JRBC_IB_64BIT_BAR_LOW 10003 #define UVD_JMI6_UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 10004 #define UVD_JMI6_UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 10005 //UVD_JMI6_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH 10006 #define UVD_JMI6_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 10007 #define UVD_JMI6_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 10008 //UVD_JMI6_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW 10009 #define UVD_JMI6_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 10010 #define UVD_JMI6_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 10011 //UVD_JMI6_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH 10012 #define UVD_JMI6_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 10013 #define UVD_JMI6_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 10014 //UVD_JMI6_UVD_JMI_ATOMIC_CNTL2 10015 #define UVD_JMI6_UVD_JMI_ATOMIC_CNTL2__atomic_uvd_swap__SHIFT 0x10 10016 #define UVD_JMI6_UVD_JMI_ATOMIC_CNTL2__ATOMIC_MC_SWAP__SHIFT 0x18 10017 #define UVD_JMI6_UVD_JMI_ATOMIC_CNTL2__atomic_uvd_swap_MASK 0x00FF0000L 10018 #define UVD_JMI6_UVD_JMI_ATOMIC_CNTL2__ATOMIC_MC_SWAP_MASK 0xFF000000L 10019 10020 10021 // addressBlock: aid_uvd0_uvd_jmi7_uvd_jmi_dec 10022 //UVD_JMI7_UVD_JPEG_DEC_PF_CTRL 10023 #define UVD_JMI7_UVD_JPEG_DEC_PF_CTRL__DEC_PF_HANDLING_DIS__SHIFT 0x0 10024 #define UVD_JMI7_UVD_JPEG_DEC_PF_CTRL__DEC_PF_SW_GATING__SHIFT 0x1 10025 #define UVD_JMI7_UVD_JPEG_DEC_PF_CTRL__DEC_PF_HANDLING_DIS_MASK 0x00000001L 10026 #define UVD_JMI7_UVD_JPEG_DEC_PF_CTRL__DEC_PF_SW_GATING_MASK 0x00000002L 10027 //UVD_JMI7_UVD_LMI_JRBC_CTRL 10028 #define UVD_JMI7_UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 10029 #define UVD_JMI7_UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 10030 #define UVD_JMI7_UVD_LMI_JRBC_CTRL__RD_MAX_BURST__SHIFT 0x4 10031 #define UVD_JMI7_UVD_LMI_JRBC_CTRL__WR_MAX_BURST__SHIFT 0x8 10032 #define UVD_JMI7_UVD_LMI_JRBC_CTRL__RD_SWAP__SHIFT 0x14 10033 #define UVD_JMI7_UVD_LMI_JRBC_CTRL__WR_SWAP__SHIFT 0x16 10034 #define UVD_JMI7_UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 10035 #define UVD_JMI7_UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 10036 #define UVD_JMI7_UVD_LMI_JRBC_CTRL__RD_MAX_BURST_MASK 0x000000F0L 10037 #define UVD_JMI7_UVD_LMI_JRBC_CTRL__WR_MAX_BURST_MASK 0x00000F00L 10038 #define UVD_JMI7_UVD_LMI_JRBC_CTRL__RD_SWAP_MASK 0x00300000L 10039 #define UVD_JMI7_UVD_LMI_JRBC_CTRL__WR_SWAP_MASK 0x00C00000L 10040 //UVD_JMI7_UVD_LMI_JPEG_CTRL 10041 #define UVD_JMI7_UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 10042 #define UVD_JMI7_UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 10043 #define UVD_JMI7_UVD_LMI_JPEG_CTRL__RD_MAX_BURST__SHIFT 0x4 10044 #define UVD_JMI7_UVD_LMI_JPEG_CTRL__WR_MAX_BURST__SHIFT 0x8 10045 #define UVD_JMI7_UVD_LMI_JPEG_CTRL__RD_SWAP__SHIFT 0x14 10046 #define UVD_JMI7_UVD_LMI_JPEG_CTRL__WR_SWAP__SHIFT 0x16 10047 #define UVD_JMI7_UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 10048 #define UVD_JMI7_UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 10049 #define UVD_JMI7_UVD_LMI_JPEG_CTRL__RD_MAX_BURST_MASK 0x000000F0L 10050 #define UVD_JMI7_UVD_LMI_JPEG_CTRL__WR_MAX_BURST_MASK 0x00000F00L 10051 #define UVD_JMI7_UVD_LMI_JPEG_CTRL__RD_SWAP_MASK 0x00300000L 10052 #define UVD_JMI7_UVD_LMI_JPEG_CTRL__WR_SWAP_MASK 0x00C00000L 10053 //UVD_JMI7_JPEG_LMI_DROP 10054 #define UVD_JMI7_JPEG_LMI_DROP__JPEG_WR_DROP__SHIFT 0x0 10055 #define UVD_JMI7_JPEG_LMI_DROP__JRBC_WR_DROP__SHIFT 0x1 10056 #define UVD_JMI7_JPEG_LMI_DROP__JPEG_RD_DROP__SHIFT 0x2 10057 #define UVD_JMI7_JPEG_LMI_DROP__JRBC_RD_DROP__SHIFT 0x3 10058 #define UVD_JMI7_JPEG_LMI_DROP__JPEG_ATOMIC_WR_DROP__SHIFT 0x4 10059 #define UVD_JMI7_JPEG_LMI_DROP__JPEG_WR_DROP_MASK 0x00000001L 10060 #define UVD_JMI7_JPEG_LMI_DROP__JRBC_WR_DROP_MASK 0x00000002L 10061 #define UVD_JMI7_JPEG_LMI_DROP__JPEG_RD_DROP_MASK 0x00000004L 10062 #define UVD_JMI7_JPEG_LMI_DROP__JRBC_RD_DROP_MASK 0x00000008L 10063 #define UVD_JMI7_JPEG_LMI_DROP__JPEG_ATOMIC_WR_DROP_MASK 0x00000010L 10064 //UVD_JMI7_UVD_LMI_JRBC_IB_VMID 10065 #define UVD_JMI7_UVD_LMI_JRBC_IB_VMID__IB_WR_VMID__SHIFT 0x0 10066 #define UVD_JMI7_UVD_LMI_JRBC_IB_VMID__IB_RD_VMID__SHIFT 0x4 10067 #define UVD_JMI7_UVD_LMI_JRBC_IB_VMID__MEM_RD_VMID__SHIFT 0x8 10068 #define UVD_JMI7_UVD_LMI_JRBC_IB_VMID__IB_WR_VMID_MASK 0x0000000FL 10069 #define UVD_JMI7_UVD_LMI_JRBC_IB_VMID__IB_RD_VMID_MASK 0x000000F0L 10070 #define UVD_JMI7_UVD_LMI_JRBC_IB_VMID__MEM_RD_VMID_MASK 0x00000F00L 10071 //UVD_JMI7_UVD_LMI_JRBC_RB_VMID 10072 #define UVD_JMI7_UVD_LMI_JRBC_RB_VMID__RB_WR_VMID__SHIFT 0x0 10073 #define UVD_JMI7_UVD_LMI_JRBC_RB_VMID__RB_RD_VMID__SHIFT 0x4 10074 #define UVD_JMI7_UVD_LMI_JRBC_RB_VMID__MEM_RD_VMID__SHIFT 0x8 10075 #define UVD_JMI7_UVD_LMI_JRBC_RB_VMID__RB_WR_VMID_MASK 0x0000000FL 10076 #define UVD_JMI7_UVD_LMI_JRBC_RB_VMID__RB_RD_VMID_MASK 0x000000F0L 10077 #define UVD_JMI7_UVD_LMI_JRBC_RB_VMID__MEM_RD_VMID_MASK 0x00000F00L 10078 //UVD_JMI7_UVD_LMI_JPEG_VMID 10079 #define UVD_JMI7_UVD_LMI_JPEG_VMID__JPEG_RD_VMID__SHIFT 0x0 10080 #define UVD_JMI7_UVD_LMI_JPEG_VMID__JPEG_WR_VMID__SHIFT 0x4 10081 #define UVD_JMI7_UVD_LMI_JPEG_VMID__ATOMIC_USER0_WR_VMID__SHIFT 0x8 10082 #define UVD_JMI7_UVD_LMI_JPEG_VMID__JPEG_RD_VMID_MASK 0x0000000FL 10083 #define UVD_JMI7_UVD_LMI_JPEG_VMID__JPEG_WR_VMID_MASK 0x000000F0L 10084 #define UVD_JMI7_UVD_LMI_JPEG_VMID__ATOMIC_USER0_WR_VMID_MASK 0x00000F00L 10085 //UVD_JMI7_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW 10086 #define UVD_JMI7_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 10087 #define UVD_JMI7_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 10088 //UVD_JMI7_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 10089 #define UVD_JMI7_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 10090 #define UVD_JMI7_UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 10091 //UVD_JMI7_UVD_LMI_JRBC_RB_64BIT_BAR_LOW 10092 #define UVD_JMI7_UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 10093 #define UVD_JMI7_UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 10094 //UVD_JMI7_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH 10095 #define UVD_JMI7_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 10096 #define UVD_JMI7_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 10097 //UVD_JMI7_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW 10098 #define UVD_JMI7_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 10099 #define UVD_JMI7_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 10100 //UVD_JMI7_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH 10101 #define UVD_JMI7_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 10102 #define UVD_JMI7_UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 10103 //UVD_JMI7_UVD_LMI_JPEG_PREEMPT_VMID 10104 #define UVD_JMI7_UVD_LMI_JPEG_PREEMPT_VMID__VMID__SHIFT 0x0 10105 #define UVD_JMI7_UVD_LMI_JPEG_PREEMPT_VMID__VMID_MASK 0x0000000FL 10106 //UVD_JMI7_UVD_JMI_DEC_SWAP_CNTL 10107 #define UVD_JMI7_UVD_JMI_DEC_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 10108 #define UVD_JMI7_UVD_JMI_DEC_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 10109 #define UVD_JMI7_UVD_JMI_DEC_SWAP_CNTL__RB_MEM_WR_MC_SWAP__SHIFT 0x4 10110 #define UVD_JMI7_UVD_JMI_DEC_SWAP_CNTL__IB_MEM_WR_MC_SWAP__SHIFT 0x6 10111 #define UVD_JMI7_UVD_JMI_DEC_SWAP_CNTL__RB_MEM_RD_MC_SWAP__SHIFT 0x8 10112 #define UVD_JMI7_UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT 0xa 10113 #define UVD_JMI7_UVD_JMI_DEC_SWAP_CNTL__PREEMPT_WR_MC_SWAP__SHIFT 0xc 10114 #define UVD_JMI7_UVD_JMI_DEC_SWAP_CNTL__JPEG_RD_MC_SWAP__SHIFT 0xe 10115 #define UVD_JMI7_UVD_JMI_DEC_SWAP_CNTL__JPEG_WR_MC_SWAP__SHIFT 0x10 10116 #define UVD_JMI7_UVD_JMI_DEC_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L 10117 #define UVD_JMI7_UVD_JMI_DEC_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL 10118 #define UVD_JMI7_UVD_JMI_DEC_SWAP_CNTL__RB_MEM_WR_MC_SWAP_MASK 0x00000030L 10119 #define UVD_JMI7_UVD_JMI_DEC_SWAP_CNTL__IB_MEM_WR_MC_SWAP_MASK 0x000000C0L 10120 #define UVD_JMI7_UVD_JMI_DEC_SWAP_CNTL__RB_MEM_RD_MC_SWAP_MASK 0x00000300L 10121 #define UVD_JMI7_UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP_MASK 0x00000C00L 10122 #define UVD_JMI7_UVD_JMI_DEC_SWAP_CNTL__PREEMPT_WR_MC_SWAP_MASK 0x00003000L 10123 #define UVD_JMI7_UVD_JMI_DEC_SWAP_CNTL__JPEG_RD_MC_SWAP_MASK 0x0000C000L 10124 #define UVD_JMI7_UVD_JMI_DEC_SWAP_CNTL__JPEG_WR_MC_SWAP_MASK 0x00030000L 10125 //UVD_JMI7_UVD_JMI_ATOMIC_CNTL 10126 #define UVD_JMI7_UVD_JMI_ATOMIC_CNTL__atomic_arb_wait_en__SHIFT 0x0 10127 #define UVD_JMI7_UVD_JMI_ATOMIC_CNTL__atomic_max_burst__SHIFT 0x1 10128 #define UVD_JMI7_UVD_JMI_ATOMIC_CNTL__atomic_wr_drop__SHIFT 0x5 10129 #define UVD_JMI7_UVD_JMI_ATOMIC_CNTL__atomic_wr_clamping_en__SHIFT 0x6 10130 #define UVD_JMI7_UVD_JMI_ATOMIC_CNTL__ATOMIC_WR_URG__SHIFT 0x7 10131 #define UVD_JMI7_UVD_JMI_ATOMIC_CNTL__ATOMIC_SW_GATE__SHIFT 0xb 10132 #define UVD_JMI7_UVD_JMI_ATOMIC_CNTL__atomic_arb_wait_en_MASK 0x00000001L 10133 #define UVD_JMI7_UVD_JMI_ATOMIC_CNTL__atomic_max_burst_MASK 0x0000001EL 10134 #define UVD_JMI7_UVD_JMI_ATOMIC_CNTL__atomic_wr_drop_MASK 0x00000020L 10135 #define UVD_JMI7_UVD_JMI_ATOMIC_CNTL__atomic_wr_clamping_en_MASK 0x00000040L 10136 #define UVD_JMI7_UVD_JMI_ATOMIC_CNTL__ATOMIC_WR_URG_MASK 0x00000780L 10137 #define UVD_JMI7_UVD_JMI_ATOMIC_CNTL__ATOMIC_SW_GATE_MASK 0x00000800L 10138 //UVD_JMI7_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW 10139 #define UVD_JMI7_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 10140 #define UVD_JMI7_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 10141 //UVD_JMI7_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH 10142 #define UVD_JMI7_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 10143 #define UVD_JMI7_UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 10144 //UVD_JMI7_UVD_LMI_JPEG_READ_64BIT_BAR_LOW 10145 #define UVD_JMI7_UVD_LMI_JPEG_READ_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 10146 #define UVD_JMI7_UVD_LMI_JPEG_READ_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 10147 //UVD_JMI7_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH 10148 #define UVD_JMI7_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 10149 #define UVD_JMI7_UVD_LMI_JPEG_READ_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 10150 //UVD_JMI7_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 10151 #define UVD_JMI7_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 10152 #define UVD_JMI7_UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 10153 //UVD_JMI7_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 10154 #define UVD_JMI7_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 10155 #define UVD_JMI7_UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 10156 //UVD_JMI7_UVD_LMI_JRBC_IB_64BIT_BAR_LOW 10157 #define UVD_JMI7_UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 10158 #define UVD_JMI7_UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 10159 //UVD_JMI7_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH 10160 #define UVD_JMI7_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 10161 #define UVD_JMI7_UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 10162 //UVD_JMI7_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW 10163 #define UVD_JMI7_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 10164 #define UVD_JMI7_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 10165 //UVD_JMI7_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH 10166 #define UVD_JMI7_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 10167 #define UVD_JMI7_UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 10168 //UVD_JMI7_UVD_JMI_ATOMIC_CNTL2 10169 #define UVD_JMI7_UVD_JMI_ATOMIC_CNTL2__atomic_uvd_swap__SHIFT 0x10 10170 #define UVD_JMI7_UVD_JMI_ATOMIC_CNTL2__ATOMIC_MC_SWAP__SHIFT 0x18 10171 #define UVD_JMI7_UVD_JMI_ATOMIC_CNTL2__atomic_uvd_swap_MASK 0x00FF0000L 10172 #define UVD_JMI7_UVD_JMI_ATOMIC_CNTL2__ATOMIC_MC_SWAP_MASK 0xFF000000L 10173 10174 10175 // addressBlock: uvdctxind 10176 //UVD_CGC_MEM_CTRL 10177 #define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN__SHIFT 0x0 10178 #define UVD_CGC_MEM_CTRL__MPC_LS_EN__SHIFT 0x1 10179 #define UVD_CGC_MEM_CTRL__MPRD_LS_EN__SHIFT 0x2 10180 #define UVD_CGC_MEM_CTRL__WCB_LS_EN__SHIFT 0x3 10181 #define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN__SHIFT 0x4 10182 #define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN__SHIFT 0x5 10183 #define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN__SHIFT 0x6 10184 #define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN__SHIFT 0x7 10185 #define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN__SHIFT 0x8 10186 #define UVD_CGC_MEM_CTRL__SYS_LS_EN__SHIFT 0x9 10187 #define UVD_CGC_MEM_CTRL__VCPU_LS_EN__SHIFT 0xa 10188 #define UVD_CGC_MEM_CTRL__MIF_LS_EN__SHIFT 0xc 10189 #define UVD_CGC_MEM_CTRL__LCM_LS_EN__SHIFT 0xd 10190 #define UVD_CGC_MEM_CTRL__MMSCH_LS_EN__SHIFT 0xe 10191 #define UVD_CGC_MEM_CTRL__MPC1_LS_EN__SHIFT 0xf 10192 #define UVD_CGC_MEM_CTRL__LS_SET_DELAY__SHIFT 0x10 10193 #define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY__SHIFT 0x14 10194 #define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN_MASK 0x00000001L 10195 #define UVD_CGC_MEM_CTRL__MPC_LS_EN_MASK 0x00000002L 10196 #define UVD_CGC_MEM_CTRL__MPRD_LS_EN_MASK 0x00000004L 10197 #define UVD_CGC_MEM_CTRL__WCB_LS_EN_MASK 0x00000008L 10198 #define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN_MASK 0x00000010L 10199 #define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN_MASK 0x00000020L 10200 #define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN_MASK 0x00000040L 10201 #define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN_MASK 0x00000080L 10202 #define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN_MASK 0x00000100L 10203 #define UVD_CGC_MEM_CTRL__SYS_LS_EN_MASK 0x00000200L 10204 #define UVD_CGC_MEM_CTRL__VCPU_LS_EN_MASK 0x00000400L 10205 #define UVD_CGC_MEM_CTRL__MIF_LS_EN_MASK 0x00001000L 10206 #define UVD_CGC_MEM_CTRL__LCM_LS_EN_MASK 0x00002000L 10207 #define UVD_CGC_MEM_CTRL__MMSCH_LS_EN_MASK 0x00004000L 10208 #define UVD_CGC_MEM_CTRL__MPC1_LS_EN_MASK 0x00008000L 10209 #define UVD_CGC_MEM_CTRL__LS_SET_DELAY_MASK 0x000F0000L 10210 #define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY_MASK 0x00F00000L 10211 //UVD_CGC_CTRL2 10212 #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x0 10213 #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x1 10214 #define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x2 10215 #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x00000001L 10216 #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x00000002L 10217 #define UVD_CGC_CTRL2__GATER_DIV_ID_MASK 0x0000001CL 10218 //UVD_CGC_MEM_DS_CTRL 10219 #define UVD_CGC_MEM_DS_CTRL__LMI_MC_DS_EN__SHIFT 0x0 10220 #define UVD_CGC_MEM_DS_CTRL__MPC_DS_EN__SHIFT 0x1 10221 #define UVD_CGC_MEM_DS_CTRL__MPRD_DS_EN__SHIFT 0x2 10222 #define UVD_CGC_MEM_DS_CTRL__WCB_DS_EN__SHIFT 0x3 10223 #define UVD_CGC_MEM_DS_CTRL__UDEC_RE_DS_EN__SHIFT 0x4 10224 #define UVD_CGC_MEM_DS_CTRL__UDEC_CM_DS_EN__SHIFT 0x5 10225 #define UVD_CGC_MEM_DS_CTRL__UDEC_IT_DS_EN__SHIFT 0x6 10226 #define UVD_CGC_MEM_DS_CTRL__UDEC_DB_DS_EN__SHIFT 0x7 10227 #define UVD_CGC_MEM_DS_CTRL__UDEC_MP_DS_EN__SHIFT 0x8 10228 #define UVD_CGC_MEM_DS_CTRL__SYS_DS_EN__SHIFT 0x9 10229 #define UVD_CGC_MEM_DS_CTRL__VCPU_DS_EN__SHIFT 0xa 10230 #define UVD_CGC_MEM_DS_CTRL__MIF_DS_EN__SHIFT 0xc 10231 #define UVD_CGC_MEM_DS_CTRL__LCM_DS_EN__SHIFT 0xd 10232 #define UVD_CGC_MEM_DS_CTRL__MMSCH_DS_EN__SHIFT 0xe 10233 #define UVD_CGC_MEM_DS_CTRL__MPC1_DS_EN__SHIFT 0xf 10234 #define UVD_CGC_MEM_DS_CTRL__LMI_MC_DS_EN_MASK 0x00000001L 10235 #define UVD_CGC_MEM_DS_CTRL__MPC_DS_EN_MASK 0x00000002L 10236 #define UVD_CGC_MEM_DS_CTRL__MPRD_DS_EN_MASK 0x00000004L 10237 #define UVD_CGC_MEM_DS_CTRL__WCB_DS_EN_MASK 0x00000008L 10238 #define UVD_CGC_MEM_DS_CTRL__UDEC_RE_DS_EN_MASK 0x00000010L 10239 #define UVD_CGC_MEM_DS_CTRL__UDEC_CM_DS_EN_MASK 0x00000020L 10240 #define UVD_CGC_MEM_DS_CTRL__UDEC_IT_DS_EN_MASK 0x00000040L 10241 #define UVD_CGC_MEM_DS_CTRL__UDEC_DB_DS_EN_MASK 0x00000080L 10242 #define UVD_CGC_MEM_DS_CTRL__UDEC_MP_DS_EN_MASK 0x00000100L 10243 #define UVD_CGC_MEM_DS_CTRL__SYS_DS_EN_MASK 0x00000200L 10244 #define UVD_CGC_MEM_DS_CTRL__VCPU_DS_EN_MASK 0x00000400L 10245 #define UVD_CGC_MEM_DS_CTRL__MIF_DS_EN_MASK 0x00001000L 10246 #define UVD_CGC_MEM_DS_CTRL__LCM_DS_EN_MASK 0x00002000L 10247 #define UVD_CGC_MEM_DS_CTRL__MMSCH_DS_EN_MASK 0x00004000L 10248 #define UVD_CGC_MEM_DS_CTRL__MPC1_DS_EN_MASK 0x00008000L 10249 //UVD_CGC_MEM_SD_CTRL 10250 #define UVD_CGC_MEM_SD_CTRL__LMI_MC_SD_EN__SHIFT 0x0 10251 #define UVD_CGC_MEM_SD_CTRL__MPC_SD_EN__SHIFT 0x1 10252 #define UVD_CGC_MEM_SD_CTRL__MPRD_SD_EN__SHIFT 0x2 10253 #define UVD_CGC_MEM_SD_CTRL__WCB_SD_EN__SHIFT 0x3 10254 #define UVD_CGC_MEM_SD_CTRL__UDEC_RE_SD_EN__SHIFT 0x4 10255 #define UVD_CGC_MEM_SD_CTRL__UDEC_CM_SD_EN__SHIFT 0x5 10256 #define UVD_CGC_MEM_SD_CTRL__UDEC_IT_SD_EN__SHIFT 0x6 10257 #define UVD_CGC_MEM_SD_CTRL__UDEC_DB_SD_EN__SHIFT 0x7 10258 #define UVD_CGC_MEM_SD_CTRL__UDEC_MP_SD_EN__SHIFT 0x8 10259 #define UVD_CGC_MEM_SD_CTRL__SYS_SD_EN__SHIFT 0x9 10260 #define UVD_CGC_MEM_SD_CTRL__VCPU_SD_EN__SHIFT 0xa 10261 #define UVD_CGC_MEM_SD_CTRL__MIF_SD_EN__SHIFT 0xc 10262 #define UVD_CGC_MEM_SD_CTRL__LCM_SD_EN__SHIFT 0xd 10263 #define UVD_CGC_MEM_SD_CTRL__MMSCH_SD_EN__SHIFT 0xe 10264 #define UVD_CGC_MEM_SD_CTRL__MPC1_SD_EN__SHIFT 0xf 10265 #define UVD_CGC_MEM_SD_CTRL__LMI_MC_SD_EN_MASK 0x00000001L 10266 #define UVD_CGC_MEM_SD_CTRL__MPC_SD_EN_MASK 0x00000002L 10267 #define UVD_CGC_MEM_SD_CTRL__MPRD_SD_EN_MASK 0x00000004L 10268 #define UVD_CGC_MEM_SD_CTRL__WCB_SD_EN_MASK 0x00000008L 10269 #define UVD_CGC_MEM_SD_CTRL__UDEC_RE_SD_EN_MASK 0x00000010L 10270 #define UVD_CGC_MEM_SD_CTRL__UDEC_CM_SD_EN_MASK 0x00000020L 10271 #define UVD_CGC_MEM_SD_CTRL__UDEC_IT_SD_EN_MASK 0x00000040L 10272 #define UVD_CGC_MEM_SD_CTRL__UDEC_DB_SD_EN_MASK 0x00000080L 10273 #define UVD_CGC_MEM_SD_CTRL__UDEC_MP_SD_EN_MASK 0x00000100L 10274 #define UVD_CGC_MEM_SD_CTRL__SYS_SD_EN_MASK 0x00000200L 10275 #define UVD_CGC_MEM_SD_CTRL__VCPU_SD_EN_MASK 0x00000400L 10276 #define UVD_CGC_MEM_SD_CTRL__MIF_SD_EN_MASK 0x00001000L 10277 #define UVD_CGC_MEM_SD_CTRL__LCM_SD_EN_MASK 0x00002000L 10278 #define UVD_CGC_MEM_SD_CTRL__MMSCH_SD_EN_MASK 0x00004000L 10279 #define UVD_CGC_MEM_SD_CTRL__MPC1_SD_EN_MASK 0x00008000L 10280 //UVD_SW_SCRATCH_00 10281 #define UVD_SW_SCRATCH_00__DATA__SHIFT 0x0 10282 #define UVD_SW_SCRATCH_00__DATA_MASK 0xFFFFFFFFL 10283 //UVD_SW_SCRATCH_01 10284 #define UVD_SW_SCRATCH_01__DATA__SHIFT 0x0 10285 #define UVD_SW_SCRATCH_01__DATA_MASK 0xFFFFFFFFL 10286 //UVD_SW_SCRATCH_02 10287 #define UVD_SW_SCRATCH_02__DATA__SHIFT 0x0 10288 #define UVD_SW_SCRATCH_02__DATA_MASK 0xFFFFFFFFL 10289 //UVD_SW_SCRATCH_03 10290 #define UVD_SW_SCRATCH_03__DATA__SHIFT 0x0 10291 #define UVD_SW_SCRATCH_03__DATA_MASK 0xFFFFFFFFL 10292 //UVD_SW_SCRATCH_04 10293 #define UVD_SW_SCRATCH_04__DATA__SHIFT 0x0 10294 #define UVD_SW_SCRATCH_04__DATA_MASK 0xFFFFFFFFL 10295 //UVD_SW_SCRATCH_05 10296 #define UVD_SW_SCRATCH_05__DATA__SHIFT 0x0 10297 #define UVD_SW_SCRATCH_05__DATA_MASK 0xFFFFFFFFL 10298 //UVD_SW_SCRATCH_06 10299 #define UVD_SW_SCRATCH_06__DATA__SHIFT 0x0 10300 #define UVD_SW_SCRATCH_06__DATA_MASK 0xFFFFFFFFL 10301 //UVD_SW_SCRATCH_07 10302 #define UVD_SW_SCRATCH_07__DATA__SHIFT 0x0 10303 #define UVD_SW_SCRATCH_07__DATA_MASK 0xFFFFFFFFL 10304 //UVD_SW_SCRATCH_08 10305 #define UVD_SW_SCRATCH_08__DATA__SHIFT 0x0 10306 #define UVD_SW_SCRATCH_08__DATA_MASK 0xFFFFFFFFL 10307 //UVD_SW_SCRATCH_09 10308 #define UVD_SW_SCRATCH_09__DATA__SHIFT 0x0 10309 #define UVD_SW_SCRATCH_09__DATA_MASK 0xFFFFFFFFL 10310 //UVD_SW_SCRATCH_10 10311 #define UVD_SW_SCRATCH_10__DATA__SHIFT 0x0 10312 #define UVD_SW_SCRATCH_10__DATA_MASK 0xFFFFFFFFL 10313 //UVD_SW_SCRATCH_11 10314 #define UVD_SW_SCRATCH_11__DATA__SHIFT 0x0 10315 #define UVD_SW_SCRATCH_11__DATA_MASK 0xFFFFFFFFL 10316 //UVD_SW_SCRATCH_12 10317 #define UVD_SW_SCRATCH_12__DATA__SHIFT 0x0 10318 #define UVD_SW_SCRATCH_12__DATA_MASK 0xFFFFFFFFL 10319 //UVD_SW_SCRATCH_13 10320 #define UVD_SW_SCRATCH_13__DATA__SHIFT 0x0 10321 #define UVD_SW_SCRATCH_13__DATA_MASK 0xFFFFFFFFL 10322 //UVD_SW_SCRATCH_14 10323 #define UVD_SW_SCRATCH_14__DATA__SHIFT 0x0 10324 #define UVD_SW_SCRATCH_14__DATA_MASK 0xFFFFFFFFL 10325 //UVD_SW_SCRATCH_15 10326 #define UVD_SW_SCRATCH_15__DATA__SHIFT 0x0 10327 #define UVD_SW_SCRATCH_15__DATA_MASK 0xFFFFFFFFL 10328 //UVD_IH_SEM_CTRL 10329 #define UVD_IH_SEM_CTRL__IH_STALL_EN__SHIFT 0x0 10330 #define UVD_IH_SEM_CTRL__SEM_STALL_EN__SHIFT 0x1 10331 #define UVD_IH_SEM_CTRL__IH_STATUS_CLEAN__SHIFT 0x2 10332 #define UVD_IH_SEM_CTRL__SEM_STATUS_CLEAN__SHIFT 0x3 10333 #define UVD_IH_SEM_CTRL__IH_VMID__SHIFT 0x4 10334 #define UVD_IH_SEM_CTRL__IH_USER_DATA__SHIFT 0x8 10335 #define UVD_IH_SEM_CTRL__IH_RINGID__SHIFT 0x14 10336 #define UVD_IH_SEM_CTRL__IH_STALL_EN_MASK 0x00000001L 10337 #define UVD_IH_SEM_CTRL__SEM_STALL_EN_MASK 0x00000002L 10338 #define UVD_IH_SEM_CTRL__IH_STATUS_CLEAN_MASK 0x00000004L 10339 #define UVD_IH_SEM_CTRL__SEM_STATUS_CLEAN_MASK 0x00000008L 10340 #define UVD_IH_SEM_CTRL__IH_VMID_MASK 0x000000F0L 10341 #define UVD_IH_SEM_CTRL__IH_USER_DATA_MASK 0x000FFF00L 10342 #define UVD_IH_SEM_CTRL__IH_RINGID_MASK 0x0FF00000L 10343 10344 10345 // addressBlock: lmi_adp_indirect 10346 //UVD_LMI_CRC0 10347 #define UVD_LMI_CRC0__CRC32__SHIFT 0x0 10348 #define UVD_LMI_CRC0__CRC32_MASK 0xFFFFFFFFL 10349 //UVD_LMI_CRC1 10350 #define UVD_LMI_CRC1__CRC32__SHIFT 0x0 10351 #define UVD_LMI_CRC1__CRC32_MASK 0xFFFFFFFFL 10352 //UVD_LMI_CRC2 10353 #define UVD_LMI_CRC2__CRC32__SHIFT 0x0 10354 #define UVD_LMI_CRC2__CRC32_MASK 0xFFFFFFFFL 10355 //UVD_LMI_CRC3 10356 #define UVD_LMI_CRC3__CRC32__SHIFT 0x0 10357 #define UVD_LMI_CRC3__CRC32_MASK 0xFFFFFFFFL 10358 //UVD_LMI_CRC10 10359 #define UVD_LMI_CRC10__CRC32__SHIFT 0x0 10360 #define UVD_LMI_CRC10__CRC32_MASK 0xFFFFFFFFL 10361 //UVD_LMI_CRC11 10362 #define UVD_LMI_CRC11__CRC32__SHIFT 0x0 10363 #define UVD_LMI_CRC11__CRC32_MASK 0xFFFFFFFFL 10364 //UVD_LMI_CRC12 10365 #define UVD_LMI_CRC12__CRC32__SHIFT 0x0 10366 #define UVD_LMI_CRC12__CRC32_MASK 0xFFFFFFFFL 10367 //UVD_LMI_CRC13 10368 #define UVD_LMI_CRC13__CRC32__SHIFT 0x0 10369 #define UVD_LMI_CRC13__CRC32_MASK 0xFFFFFFFFL 10370 //UVD_LMI_CRC14 10371 #define UVD_LMI_CRC14__CRC32__SHIFT 0x0 10372 #define UVD_LMI_CRC14__CRC32_MASK 0xFFFFFFFFL 10373 //UVD_LMI_CRC15 10374 #define UVD_LMI_CRC15__CRC32__SHIFT 0x0 10375 #define UVD_LMI_CRC15__CRC32_MASK 0xFFFFFFFFL 10376 //UVD_LMI_SWAP_CNTL2 10377 #define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP__SHIFT 0x0 10378 #define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP__SHIFT 0x2 10379 #define UVD_LMI_SWAP_CNTL2__ATOMIC_MC_SWAP__SHIFT 0x4 10380 #define UVD_LMI_SWAP_CNTL2__CENC_MC_SWAP__SHIFT 0xc 10381 #define UVD_LMI_SWAP_CNTL2__FBC_KEY_MC_SWAP__SHIFT 0xe 10382 #define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP_MASK 0x00000003L 10383 #define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP_MASK 0x0000000CL 10384 #define UVD_LMI_SWAP_CNTL2__ATOMIC_MC_SWAP_MASK 0x00000FF0L 10385 #define UVD_LMI_SWAP_CNTL2__CENC_MC_SWAP_MASK 0x00003000L 10386 #define UVD_LMI_SWAP_CNTL2__FBC_KEY_MC_SWAP_MASK 0x0000C000L 10387 //UVD_MEMCHECK_SYS_INT_EN 10388 #define UVD_MEMCHECK_SYS_INT_EN__RE_ERR_EN__SHIFT 0x0 10389 #define UVD_MEMCHECK_SYS_INT_EN__IT_ERR_EN__SHIFT 0x1 10390 #define UVD_MEMCHECK_SYS_INT_EN__MP_ERR_EN__SHIFT 0x2 10391 #define UVD_MEMCHECK_SYS_INT_EN__DB_ERR_EN__SHIFT 0x3 10392 #define UVD_MEMCHECK_SYS_INT_EN__DBW_ERR_EN__SHIFT 0x4 10393 #define UVD_MEMCHECK_SYS_INT_EN__CM_ERR_EN__SHIFT 0x5 10394 #define UVD_MEMCHECK_SYS_INT_EN__MIF_REF_ERR_EN__SHIFT 0x6 10395 #define UVD_MEMCHECK_SYS_INT_EN__VCPU_ERR_EN__SHIFT 0x7 10396 #define UVD_MEMCHECK_SYS_INT_EN__MIF_DBW_ERR_EN__SHIFT 0x8 10397 #define UVD_MEMCHECK_SYS_INT_EN__MIF_CM_COLOC_ERR_EN__SHIFT 0x9 10398 #define UVD_MEMCHECK_SYS_INT_EN__MIF_BSP0_ERR_EN__SHIFT 0xa 10399 #define UVD_MEMCHECK_SYS_INT_EN__MIF_BSP1_ERR_EN__SHIFT 0xb 10400 #define UVD_MEMCHECK_SYS_INT_EN__SRE_ERR_EN__SHIFT 0xc 10401 #define UVD_MEMCHECK_SYS_INT_EN__IT_RD_ERR_EN__SHIFT 0xf 10402 #define UVD_MEMCHECK_SYS_INT_EN__CM_RD_ERR_EN__SHIFT 0x10 10403 #define UVD_MEMCHECK_SYS_INT_EN__DB_RD_ERR_EN__SHIFT 0x11 10404 #define UVD_MEMCHECK_SYS_INT_EN__MIF_RD_ERR_EN__SHIFT 0x12 10405 #define UVD_MEMCHECK_SYS_INT_EN__IDCT_RD_ERR_EN__SHIFT 0x13 10406 #define UVD_MEMCHECK_SYS_INT_EN__MPC_RD_ERR_EN__SHIFT 0x14 10407 #define UVD_MEMCHECK_SYS_INT_EN__LBSI_RD_ERR_EN__SHIFT 0x15 10408 #define UVD_MEMCHECK_SYS_INT_EN__RBC_RD_ERR_EN__SHIFT 0x18 10409 #define UVD_MEMCHECK_SYS_INT_EN__MIF_BSP2_ERR_EN__SHIFT 0x1b 10410 #define UVD_MEMCHECK_SYS_INT_EN__MIF_BSP3_ERR_EN__SHIFT 0x1c 10411 #define UVD_MEMCHECK_SYS_INT_EN__MIF_SCLR_ERR_EN__SHIFT 0x1d 10412 #define UVD_MEMCHECK_SYS_INT_EN__MIF_SCLR2_ERR_EN__SHIFT 0x1e 10413 #define UVD_MEMCHECK_SYS_INT_EN__PREF_ERR_EN__SHIFT 0x1f 10414 #define UVD_MEMCHECK_SYS_INT_EN__RE_ERR_EN_MASK 0x00000001L 10415 #define UVD_MEMCHECK_SYS_INT_EN__IT_ERR_EN_MASK 0x00000002L 10416 #define UVD_MEMCHECK_SYS_INT_EN__MP_ERR_EN_MASK 0x00000004L 10417 #define UVD_MEMCHECK_SYS_INT_EN__DB_ERR_EN_MASK 0x00000008L 10418 #define UVD_MEMCHECK_SYS_INT_EN__DBW_ERR_EN_MASK 0x00000010L 10419 #define UVD_MEMCHECK_SYS_INT_EN__CM_ERR_EN_MASK 0x00000020L 10420 #define UVD_MEMCHECK_SYS_INT_EN__MIF_REF_ERR_EN_MASK 0x00000040L 10421 #define UVD_MEMCHECK_SYS_INT_EN__VCPU_ERR_EN_MASK 0x00000080L 10422 #define UVD_MEMCHECK_SYS_INT_EN__MIF_DBW_ERR_EN_MASK 0x00000100L 10423 #define UVD_MEMCHECK_SYS_INT_EN__MIF_CM_COLOC_ERR_EN_MASK 0x00000200L 10424 #define UVD_MEMCHECK_SYS_INT_EN__MIF_BSP0_ERR_EN_MASK 0x00000400L 10425 #define UVD_MEMCHECK_SYS_INT_EN__MIF_BSP1_ERR_EN_MASK 0x00000800L 10426 #define UVD_MEMCHECK_SYS_INT_EN__SRE_ERR_EN_MASK 0x00001000L 10427 #define UVD_MEMCHECK_SYS_INT_EN__IT_RD_ERR_EN_MASK 0x00008000L 10428 #define UVD_MEMCHECK_SYS_INT_EN__CM_RD_ERR_EN_MASK 0x00010000L 10429 #define UVD_MEMCHECK_SYS_INT_EN__DB_RD_ERR_EN_MASK 0x00020000L 10430 #define UVD_MEMCHECK_SYS_INT_EN__MIF_RD_ERR_EN_MASK 0x00040000L 10431 #define UVD_MEMCHECK_SYS_INT_EN__IDCT_RD_ERR_EN_MASK 0x00080000L 10432 #define UVD_MEMCHECK_SYS_INT_EN__MPC_RD_ERR_EN_MASK 0x00100000L 10433 #define UVD_MEMCHECK_SYS_INT_EN__LBSI_RD_ERR_EN_MASK 0x00200000L 10434 #define UVD_MEMCHECK_SYS_INT_EN__RBC_RD_ERR_EN_MASK 0x01000000L 10435 #define UVD_MEMCHECK_SYS_INT_EN__MIF_BSP2_ERR_EN_MASK 0x08000000L 10436 #define UVD_MEMCHECK_SYS_INT_EN__MIF_BSP3_ERR_EN_MASK 0x10000000L 10437 #define UVD_MEMCHECK_SYS_INT_EN__MIF_SCLR_ERR_EN_MASK 0x20000000L 10438 #define UVD_MEMCHECK_SYS_INT_EN__MIF_SCLR2_ERR_EN_MASK 0x40000000L 10439 #define UVD_MEMCHECK_SYS_INT_EN__PREF_ERR_EN_MASK 0x80000000L 10440 //UVD_MEMCHECK_SYS_INT_STAT 10441 #define UVD_MEMCHECK_SYS_INT_STAT__RE_LO_ERR__SHIFT 0x0 10442 #define UVD_MEMCHECK_SYS_INT_STAT__RE_HI_ERR__SHIFT 0x1 10443 #define UVD_MEMCHECK_SYS_INT_STAT__IT_LO_ERR__SHIFT 0x2 10444 #define UVD_MEMCHECK_SYS_INT_STAT__IT_HI_ERR__SHIFT 0x3 10445 #define UVD_MEMCHECK_SYS_INT_STAT__MP_LO_ERR__SHIFT 0x4 10446 #define UVD_MEMCHECK_SYS_INT_STAT__MP_HI_ERR__SHIFT 0x5 10447 #define UVD_MEMCHECK_SYS_INT_STAT__DB_LO_ERR__SHIFT 0x6 10448 #define UVD_MEMCHECK_SYS_INT_STAT__DB_HI_ERR__SHIFT 0x7 10449 #define UVD_MEMCHECK_SYS_INT_STAT__DBW_LO_ERR__SHIFT 0x8 10450 #define UVD_MEMCHECK_SYS_INT_STAT__DBW_HI_ERR__SHIFT 0x9 10451 #define UVD_MEMCHECK_SYS_INT_STAT__CM_LO_ERR__SHIFT 0xa 10452 #define UVD_MEMCHECK_SYS_INT_STAT__CM_HI_ERR__SHIFT 0xb 10453 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_REF_LO_ERR__SHIFT 0xc 10454 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_REF_HI_ERR__SHIFT 0xd 10455 #define UVD_MEMCHECK_SYS_INT_STAT__VCPU_LO_ERR__SHIFT 0xe 10456 #define UVD_MEMCHECK_SYS_INT_STAT__VCPU_HI_ERR__SHIFT 0xf 10457 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_DBW_LO_ERR__SHIFT 0x10 10458 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_DBW_HI_ERR__SHIFT 0x11 10459 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_CM_COLOC_LO_ERR__SHIFT 0x12 10460 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_CM_COLOC_HI_ERR__SHIFT 0x13 10461 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_BSP0_LO_ERR__SHIFT 0x14 10462 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_BSP0_HI_ERR__SHIFT 0x15 10463 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_BSP1_LO_ERR__SHIFT 0x16 10464 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_BSP1_HI_ERR__SHIFT 0x17 10465 #define UVD_MEMCHECK_SYS_INT_STAT__SRE_LO_ERR__SHIFT 0x18 10466 #define UVD_MEMCHECK_SYS_INT_STAT__SRE_HI_ERR__SHIFT 0x19 10467 #define UVD_MEMCHECK_SYS_INT_STAT__IT_RD_LO_ERR__SHIFT 0x1e 10468 #define UVD_MEMCHECK_SYS_INT_STAT__IT_RD_HI_ERR__SHIFT 0x1f 10469 #define UVD_MEMCHECK_SYS_INT_STAT__RE_LO_ERR_MASK 0x00000001L 10470 #define UVD_MEMCHECK_SYS_INT_STAT__RE_HI_ERR_MASK 0x00000002L 10471 #define UVD_MEMCHECK_SYS_INT_STAT__IT_LO_ERR_MASK 0x00000004L 10472 #define UVD_MEMCHECK_SYS_INT_STAT__IT_HI_ERR_MASK 0x00000008L 10473 #define UVD_MEMCHECK_SYS_INT_STAT__MP_LO_ERR_MASK 0x00000010L 10474 #define UVD_MEMCHECK_SYS_INT_STAT__MP_HI_ERR_MASK 0x00000020L 10475 #define UVD_MEMCHECK_SYS_INT_STAT__DB_LO_ERR_MASK 0x00000040L 10476 #define UVD_MEMCHECK_SYS_INT_STAT__DB_HI_ERR_MASK 0x00000080L 10477 #define UVD_MEMCHECK_SYS_INT_STAT__DBW_LO_ERR_MASK 0x00000100L 10478 #define UVD_MEMCHECK_SYS_INT_STAT__DBW_HI_ERR_MASK 0x00000200L 10479 #define UVD_MEMCHECK_SYS_INT_STAT__CM_LO_ERR_MASK 0x00000400L 10480 #define UVD_MEMCHECK_SYS_INT_STAT__CM_HI_ERR_MASK 0x00000800L 10481 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_REF_LO_ERR_MASK 0x00001000L 10482 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_REF_HI_ERR_MASK 0x00002000L 10483 #define UVD_MEMCHECK_SYS_INT_STAT__VCPU_LO_ERR_MASK 0x00004000L 10484 #define UVD_MEMCHECK_SYS_INT_STAT__VCPU_HI_ERR_MASK 0x00008000L 10485 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_DBW_LO_ERR_MASK 0x00010000L 10486 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_DBW_HI_ERR_MASK 0x00020000L 10487 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_CM_COLOC_LO_ERR_MASK 0x00040000L 10488 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_CM_COLOC_HI_ERR_MASK 0x00080000L 10489 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_BSP0_LO_ERR_MASK 0x00100000L 10490 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_BSP0_HI_ERR_MASK 0x00200000L 10491 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_BSP1_LO_ERR_MASK 0x00400000L 10492 #define UVD_MEMCHECK_SYS_INT_STAT__MIF_BSP1_HI_ERR_MASK 0x00800000L 10493 #define UVD_MEMCHECK_SYS_INT_STAT__SRE_LO_ERR_MASK 0x01000000L 10494 #define UVD_MEMCHECK_SYS_INT_STAT__SRE_HI_ERR_MASK 0x02000000L 10495 #define UVD_MEMCHECK_SYS_INT_STAT__IT_RD_LO_ERR_MASK 0x40000000L 10496 #define UVD_MEMCHECK_SYS_INT_STAT__IT_RD_HI_ERR_MASK 0x80000000L 10497 //UVD_MEMCHECK_SYS_INT_ACK 10498 #define UVD_MEMCHECK_SYS_INT_ACK__RE_LO_ACK__SHIFT 0x0 10499 #define UVD_MEMCHECK_SYS_INT_ACK__RE_HI_ACK__SHIFT 0x1 10500 #define UVD_MEMCHECK_SYS_INT_ACK__IT_LO_ACK__SHIFT 0x2 10501 #define UVD_MEMCHECK_SYS_INT_ACK__IT_HI_ACK__SHIFT 0x3 10502 #define UVD_MEMCHECK_SYS_INT_ACK__MP_LO_ACK__SHIFT 0x4 10503 #define UVD_MEMCHECK_SYS_INT_ACK__MP_HI_ACK__SHIFT 0x5 10504 #define UVD_MEMCHECK_SYS_INT_ACK__DB_LO_ACK__SHIFT 0x6 10505 #define UVD_MEMCHECK_SYS_INT_ACK__DB_HI_ACK__SHIFT 0x7 10506 #define UVD_MEMCHECK_SYS_INT_ACK__DBW_LO_ACK__SHIFT 0x8 10507 #define UVD_MEMCHECK_SYS_INT_ACK__DBW_HI_ACK__SHIFT 0x9 10508 #define UVD_MEMCHECK_SYS_INT_ACK__CM_LO_ACK__SHIFT 0xa 10509 #define UVD_MEMCHECK_SYS_INT_ACK__CM_HI_ACK__SHIFT 0xb 10510 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_REF_LO_ACK__SHIFT 0xc 10511 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_REF_HI_ACK__SHIFT 0xd 10512 #define UVD_MEMCHECK_SYS_INT_ACK__VCPU_LO_ACK__SHIFT 0xe 10513 #define UVD_MEMCHECK_SYS_INT_ACK__VCPU_HI_ACK__SHIFT 0xf 10514 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_DBW_LO_ACK__SHIFT 0x10 10515 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_DBW_HI_ACK__SHIFT 0x11 10516 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_CM_COLOC_LO_ACK__SHIFT 0x12 10517 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_CM_COLOC_HI_ACK__SHIFT 0x13 10518 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_BSP0_LO_ACK__SHIFT 0x14 10519 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_BSP0_HI_ACK__SHIFT 0x15 10520 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_BSP1_LO_ACK__SHIFT 0x16 10521 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_BSP1_HI_ACK__SHIFT 0x17 10522 #define UVD_MEMCHECK_SYS_INT_ACK__SRE_LO_ACK__SHIFT 0x18 10523 #define UVD_MEMCHECK_SYS_INT_ACK__SRE_HI_ACK__SHIFT 0x19 10524 #define UVD_MEMCHECK_SYS_INT_ACK__IT_RD_LO_ACK__SHIFT 0x1e 10525 #define UVD_MEMCHECK_SYS_INT_ACK__IT_RD_HI_ACK__SHIFT 0x1f 10526 #define UVD_MEMCHECK_SYS_INT_ACK__RE_LO_ACK_MASK 0x00000001L 10527 #define UVD_MEMCHECK_SYS_INT_ACK__RE_HI_ACK_MASK 0x00000002L 10528 #define UVD_MEMCHECK_SYS_INT_ACK__IT_LO_ACK_MASK 0x00000004L 10529 #define UVD_MEMCHECK_SYS_INT_ACK__IT_HI_ACK_MASK 0x00000008L 10530 #define UVD_MEMCHECK_SYS_INT_ACK__MP_LO_ACK_MASK 0x00000010L 10531 #define UVD_MEMCHECK_SYS_INT_ACK__MP_HI_ACK_MASK 0x00000020L 10532 #define UVD_MEMCHECK_SYS_INT_ACK__DB_LO_ACK_MASK 0x00000040L 10533 #define UVD_MEMCHECK_SYS_INT_ACK__DB_HI_ACK_MASK 0x00000080L 10534 #define UVD_MEMCHECK_SYS_INT_ACK__DBW_LO_ACK_MASK 0x00000100L 10535 #define UVD_MEMCHECK_SYS_INT_ACK__DBW_HI_ACK_MASK 0x00000200L 10536 #define UVD_MEMCHECK_SYS_INT_ACK__CM_LO_ACK_MASK 0x00000400L 10537 #define UVD_MEMCHECK_SYS_INT_ACK__CM_HI_ACK_MASK 0x00000800L 10538 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_REF_LO_ACK_MASK 0x00001000L 10539 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_REF_HI_ACK_MASK 0x00002000L 10540 #define UVD_MEMCHECK_SYS_INT_ACK__VCPU_LO_ACK_MASK 0x00004000L 10541 #define UVD_MEMCHECK_SYS_INT_ACK__VCPU_HI_ACK_MASK 0x00008000L 10542 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_DBW_LO_ACK_MASK 0x00010000L 10543 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_DBW_HI_ACK_MASK 0x00020000L 10544 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_CM_COLOC_LO_ACK_MASK 0x00040000L 10545 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_CM_COLOC_HI_ACK_MASK 0x00080000L 10546 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_BSP0_LO_ACK_MASK 0x00100000L 10547 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_BSP0_HI_ACK_MASK 0x00200000L 10548 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_BSP1_LO_ACK_MASK 0x00400000L 10549 #define UVD_MEMCHECK_SYS_INT_ACK__MIF_BSP1_HI_ACK_MASK 0x00800000L 10550 #define UVD_MEMCHECK_SYS_INT_ACK__SRE_LO_ACK_MASK 0x01000000L 10551 #define UVD_MEMCHECK_SYS_INT_ACK__SRE_HI_ACK_MASK 0x02000000L 10552 #define UVD_MEMCHECK_SYS_INT_ACK__IT_RD_LO_ACK_MASK 0x40000000L 10553 #define UVD_MEMCHECK_SYS_INT_ACK__IT_RD_HI_ACK_MASK 0x80000000L 10554 //UVD_MEMCHECK_VCPU_INT_EN 10555 #define UVD_MEMCHECK_VCPU_INT_EN__RE_ERR_EN__SHIFT 0x0 10556 #define UVD_MEMCHECK_VCPU_INT_EN__IT_ERR_EN__SHIFT 0x1 10557 #define UVD_MEMCHECK_VCPU_INT_EN__MP_ERR_EN__SHIFT 0x2 10558 #define UVD_MEMCHECK_VCPU_INT_EN__DB_ERR_EN__SHIFT 0x3 10559 #define UVD_MEMCHECK_VCPU_INT_EN__DBW_ERR_EN__SHIFT 0x4 10560 #define UVD_MEMCHECK_VCPU_INT_EN__CM_ERR_EN__SHIFT 0x5 10561 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_REF_ERR_EN__SHIFT 0x6 10562 #define UVD_MEMCHECK_VCPU_INT_EN__VCPU_ERR_EN__SHIFT 0x7 10563 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_DBW_ERR_EN__SHIFT 0x8 10564 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_CM_COLOC_ERR_EN__SHIFT 0x9 10565 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_BSP0_ERR_EN__SHIFT 0xa 10566 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_BSP1_ERR_EN__SHIFT 0xb 10567 #define UVD_MEMCHECK_VCPU_INT_EN__SRE_ERR_EN__SHIFT 0xc 10568 #define UVD_MEMCHECK_VCPU_INT_EN__IT_RD_ERR_EN__SHIFT 0xf 10569 #define UVD_MEMCHECK_VCPU_INT_EN__CM_RD_ERR_EN__SHIFT 0x10 10570 #define UVD_MEMCHECK_VCPU_INT_EN__DB_RD_ERR_EN__SHIFT 0x11 10571 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_RD_ERR_EN__SHIFT 0x12 10572 #define UVD_MEMCHECK_VCPU_INT_EN__IDCT_RD_ERR_EN__SHIFT 0x13 10573 #define UVD_MEMCHECK_VCPU_INT_EN__MPC_RD_ERR_EN__SHIFT 0x14 10574 #define UVD_MEMCHECK_VCPU_INT_EN__LBSI_RD_ERR_EN__SHIFT 0x15 10575 #define UVD_MEMCHECK_VCPU_INT_EN__RBC_RD_ERR_EN__SHIFT 0x18 10576 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_BSP2_ERR_EN__SHIFT 0x19 10577 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_BSP3_ERR_EN__SHIFT 0x1a 10578 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_SCLR_ERR_EN__SHIFT 0x1b 10579 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_SCLR2_ERR_EN__SHIFT 0x1c 10580 #define UVD_MEMCHECK_VCPU_INT_EN__PREF_ERR_EN__SHIFT 0x1d 10581 #define UVD_MEMCHECK_VCPU_INT_EN__RE_ERR_EN_MASK 0x00000001L 10582 #define UVD_MEMCHECK_VCPU_INT_EN__IT_ERR_EN_MASK 0x00000002L 10583 #define UVD_MEMCHECK_VCPU_INT_EN__MP_ERR_EN_MASK 0x00000004L 10584 #define UVD_MEMCHECK_VCPU_INT_EN__DB_ERR_EN_MASK 0x00000008L 10585 #define UVD_MEMCHECK_VCPU_INT_EN__DBW_ERR_EN_MASK 0x00000010L 10586 #define UVD_MEMCHECK_VCPU_INT_EN__CM_ERR_EN_MASK 0x00000020L 10587 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_REF_ERR_EN_MASK 0x00000040L 10588 #define UVD_MEMCHECK_VCPU_INT_EN__VCPU_ERR_EN_MASK 0x00000080L 10589 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_DBW_ERR_EN_MASK 0x00000100L 10590 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_CM_COLOC_ERR_EN_MASK 0x00000200L 10591 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_BSP0_ERR_EN_MASK 0x00000400L 10592 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_BSP1_ERR_EN_MASK 0x00000800L 10593 #define UVD_MEMCHECK_VCPU_INT_EN__SRE_ERR_EN_MASK 0x00001000L 10594 #define UVD_MEMCHECK_VCPU_INT_EN__IT_RD_ERR_EN_MASK 0x00008000L 10595 #define UVD_MEMCHECK_VCPU_INT_EN__CM_RD_ERR_EN_MASK 0x00010000L 10596 #define UVD_MEMCHECK_VCPU_INT_EN__DB_RD_ERR_EN_MASK 0x00020000L 10597 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_RD_ERR_EN_MASK 0x00040000L 10598 #define UVD_MEMCHECK_VCPU_INT_EN__IDCT_RD_ERR_EN_MASK 0x00080000L 10599 #define UVD_MEMCHECK_VCPU_INT_EN__MPC_RD_ERR_EN_MASK 0x00100000L 10600 #define UVD_MEMCHECK_VCPU_INT_EN__LBSI_RD_ERR_EN_MASK 0x00200000L 10601 #define UVD_MEMCHECK_VCPU_INT_EN__RBC_RD_ERR_EN_MASK 0x01000000L 10602 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_BSP2_ERR_EN_MASK 0x02000000L 10603 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_BSP3_ERR_EN_MASK 0x04000000L 10604 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_SCLR_ERR_EN_MASK 0x08000000L 10605 #define UVD_MEMCHECK_VCPU_INT_EN__MIF_SCLR2_ERR_EN_MASK 0x10000000L 10606 #define UVD_MEMCHECK_VCPU_INT_EN__PREF_ERR_EN_MASK 0x20000000L 10607 //UVD_MEMCHECK_VCPU_INT_STAT 10608 #define UVD_MEMCHECK_VCPU_INT_STAT__RE_LO_ERR__SHIFT 0x0 10609 #define UVD_MEMCHECK_VCPU_INT_STAT__RE_HI_ERR__SHIFT 0x1 10610 #define UVD_MEMCHECK_VCPU_INT_STAT__IT_LO_ERR__SHIFT 0x2 10611 #define UVD_MEMCHECK_VCPU_INT_STAT__IT_HI_ERR__SHIFT 0x3 10612 #define UVD_MEMCHECK_VCPU_INT_STAT__MP_LO_ERR__SHIFT 0x4 10613 #define UVD_MEMCHECK_VCPU_INT_STAT__MP_HI_ERR__SHIFT 0x5 10614 #define UVD_MEMCHECK_VCPU_INT_STAT__DB_LO_ERR__SHIFT 0x6 10615 #define UVD_MEMCHECK_VCPU_INT_STAT__DB_HI_ERR__SHIFT 0x7 10616 #define UVD_MEMCHECK_VCPU_INT_STAT__DBW_LO_ERR__SHIFT 0x8 10617 #define UVD_MEMCHECK_VCPU_INT_STAT__DBW_HI_ERR__SHIFT 0x9 10618 #define UVD_MEMCHECK_VCPU_INT_STAT__CM_LO_ERR__SHIFT 0xa 10619 #define UVD_MEMCHECK_VCPU_INT_STAT__CM_HI_ERR__SHIFT 0xb 10620 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_REF_LO_ERR__SHIFT 0xc 10621 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_REF_HI_ERR__SHIFT 0xd 10622 #define UVD_MEMCHECK_VCPU_INT_STAT__VCPU_LO_ERR__SHIFT 0xe 10623 #define UVD_MEMCHECK_VCPU_INT_STAT__VCPU_HI_ERR__SHIFT 0xf 10624 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_DBW_LO_ERR__SHIFT 0x10 10625 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_DBW_HI_ERR__SHIFT 0x11 10626 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_CM_COLOC_LO_ERR__SHIFT 0x12 10627 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_CM_COLOC_HI_ERR__SHIFT 0x13 10628 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_BSP0_LO_ERR__SHIFT 0x14 10629 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_BSP0_HI_ERR__SHIFT 0x15 10630 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_BSP1_LO_ERR__SHIFT 0x16 10631 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_BSP1_HI_ERR__SHIFT 0x17 10632 #define UVD_MEMCHECK_VCPU_INT_STAT__SRE_LO_ERR__SHIFT 0x18 10633 #define UVD_MEMCHECK_VCPU_INT_STAT__SRE_HI_ERR__SHIFT 0x19 10634 #define UVD_MEMCHECK_VCPU_INT_STAT__IT_RD_LO_ERR__SHIFT 0x1e 10635 #define UVD_MEMCHECK_VCPU_INT_STAT__IT_RD_HI_ERR__SHIFT 0x1f 10636 #define UVD_MEMCHECK_VCPU_INT_STAT__RE_LO_ERR_MASK 0x00000001L 10637 #define UVD_MEMCHECK_VCPU_INT_STAT__RE_HI_ERR_MASK 0x00000002L 10638 #define UVD_MEMCHECK_VCPU_INT_STAT__IT_LO_ERR_MASK 0x00000004L 10639 #define UVD_MEMCHECK_VCPU_INT_STAT__IT_HI_ERR_MASK 0x00000008L 10640 #define UVD_MEMCHECK_VCPU_INT_STAT__MP_LO_ERR_MASK 0x00000010L 10641 #define UVD_MEMCHECK_VCPU_INT_STAT__MP_HI_ERR_MASK 0x00000020L 10642 #define UVD_MEMCHECK_VCPU_INT_STAT__DB_LO_ERR_MASK 0x00000040L 10643 #define UVD_MEMCHECK_VCPU_INT_STAT__DB_HI_ERR_MASK 0x00000080L 10644 #define UVD_MEMCHECK_VCPU_INT_STAT__DBW_LO_ERR_MASK 0x00000100L 10645 #define UVD_MEMCHECK_VCPU_INT_STAT__DBW_HI_ERR_MASK 0x00000200L 10646 #define UVD_MEMCHECK_VCPU_INT_STAT__CM_LO_ERR_MASK 0x00000400L 10647 #define UVD_MEMCHECK_VCPU_INT_STAT__CM_HI_ERR_MASK 0x00000800L 10648 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_REF_LO_ERR_MASK 0x00001000L 10649 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_REF_HI_ERR_MASK 0x00002000L 10650 #define UVD_MEMCHECK_VCPU_INT_STAT__VCPU_LO_ERR_MASK 0x00004000L 10651 #define UVD_MEMCHECK_VCPU_INT_STAT__VCPU_HI_ERR_MASK 0x00008000L 10652 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_DBW_LO_ERR_MASK 0x00010000L 10653 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_DBW_HI_ERR_MASK 0x00020000L 10654 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_CM_COLOC_LO_ERR_MASK 0x00040000L 10655 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_CM_COLOC_HI_ERR_MASK 0x00080000L 10656 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_BSP0_LO_ERR_MASK 0x00100000L 10657 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_BSP0_HI_ERR_MASK 0x00200000L 10658 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_BSP1_LO_ERR_MASK 0x00400000L 10659 #define UVD_MEMCHECK_VCPU_INT_STAT__MIF_BSP1_HI_ERR_MASK 0x00800000L 10660 #define UVD_MEMCHECK_VCPU_INT_STAT__SRE_LO_ERR_MASK 0x01000000L 10661 #define UVD_MEMCHECK_VCPU_INT_STAT__SRE_HI_ERR_MASK 0x02000000L 10662 #define UVD_MEMCHECK_VCPU_INT_STAT__IT_RD_LO_ERR_MASK 0x40000000L 10663 #define UVD_MEMCHECK_VCPU_INT_STAT__IT_RD_HI_ERR_MASK 0x80000000L 10664 //UVD_MEMCHECK_VCPU_INT_ACK 10665 #define UVD_MEMCHECK_VCPU_INT_ACK__RE_LO_ACK__SHIFT 0x0 10666 #define UVD_MEMCHECK_VCPU_INT_ACK__RE_HI_ACK__SHIFT 0x1 10667 #define UVD_MEMCHECK_VCPU_INT_ACK__IT_LO_ACK__SHIFT 0x2 10668 #define UVD_MEMCHECK_VCPU_INT_ACK__IT_HI_ACK__SHIFT 0x3 10669 #define UVD_MEMCHECK_VCPU_INT_ACK__MP_LO_ACK__SHIFT 0x4 10670 #define UVD_MEMCHECK_VCPU_INT_ACK__MP_HI_ACK__SHIFT 0x5 10671 #define UVD_MEMCHECK_VCPU_INT_ACK__DB_LO_ACK__SHIFT 0x6 10672 #define UVD_MEMCHECK_VCPU_INT_ACK__DB_HI_ACK__SHIFT 0x7 10673 #define UVD_MEMCHECK_VCPU_INT_ACK__DBW_LO_ACK__SHIFT 0x8 10674 #define UVD_MEMCHECK_VCPU_INT_ACK__DBW_HI_ACK__SHIFT 0x9 10675 #define UVD_MEMCHECK_VCPU_INT_ACK__CM_LO_ACK__SHIFT 0xa 10676 #define UVD_MEMCHECK_VCPU_INT_ACK__CM_HI_ACK__SHIFT 0xb 10677 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_REF_LO_ACK__SHIFT 0xc 10678 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_REF_HI_ACK__SHIFT 0xd 10679 #define UVD_MEMCHECK_VCPU_INT_ACK__VCPU_LO_ACK__SHIFT 0xe 10680 #define UVD_MEMCHECK_VCPU_INT_ACK__VCPU_HI_ACK__SHIFT 0xf 10681 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_DBW_LO_ACK__SHIFT 0x10 10682 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_DBW_HI_ACK__SHIFT 0x11 10683 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_CM_COLOC_LO_ACK__SHIFT 0x12 10684 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_CM_COLOC_HI_ACK__SHIFT 0x13 10685 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_BSP0_LO_ACK__SHIFT 0x14 10686 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_BSP0_HI_ACK__SHIFT 0x15 10687 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_BSP1_LO_ACK__SHIFT 0x16 10688 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_BSP1_HI_ACK__SHIFT 0x17 10689 #define UVD_MEMCHECK_VCPU_INT_ACK__SRE_LO_ACK__SHIFT 0x18 10690 #define UVD_MEMCHECK_VCPU_INT_ACK__SRE_HI_ACK__SHIFT 0x19 10691 #define UVD_MEMCHECK_VCPU_INT_ACK__IT_RD_LO_ACK__SHIFT 0x1e 10692 #define UVD_MEMCHECK_VCPU_INT_ACK__IT_RD_HI_ACK__SHIFT 0x1f 10693 #define UVD_MEMCHECK_VCPU_INT_ACK__RE_LO_ACK_MASK 0x00000001L 10694 #define UVD_MEMCHECK_VCPU_INT_ACK__RE_HI_ACK_MASK 0x00000002L 10695 #define UVD_MEMCHECK_VCPU_INT_ACK__IT_LO_ACK_MASK 0x00000004L 10696 #define UVD_MEMCHECK_VCPU_INT_ACK__IT_HI_ACK_MASK 0x00000008L 10697 #define UVD_MEMCHECK_VCPU_INT_ACK__MP_LO_ACK_MASK 0x00000010L 10698 #define UVD_MEMCHECK_VCPU_INT_ACK__MP_HI_ACK_MASK 0x00000020L 10699 #define UVD_MEMCHECK_VCPU_INT_ACK__DB_LO_ACK_MASK 0x00000040L 10700 #define UVD_MEMCHECK_VCPU_INT_ACK__DB_HI_ACK_MASK 0x00000080L 10701 #define UVD_MEMCHECK_VCPU_INT_ACK__DBW_LO_ACK_MASK 0x00000100L 10702 #define UVD_MEMCHECK_VCPU_INT_ACK__DBW_HI_ACK_MASK 0x00000200L 10703 #define UVD_MEMCHECK_VCPU_INT_ACK__CM_LO_ACK_MASK 0x00000400L 10704 #define UVD_MEMCHECK_VCPU_INT_ACK__CM_HI_ACK_MASK 0x00000800L 10705 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_REF_LO_ACK_MASK 0x00001000L 10706 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_REF_HI_ACK_MASK 0x00002000L 10707 #define UVD_MEMCHECK_VCPU_INT_ACK__VCPU_LO_ACK_MASK 0x00004000L 10708 #define UVD_MEMCHECK_VCPU_INT_ACK__VCPU_HI_ACK_MASK 0x00008000L 10709 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_DBW_LO_ACK_MASK 0x00010000L 10710 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_DBW_HI_ACK_MASK 0x00020000L 10711 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_CM_COLOC_LO_ACK_MASK 0x00040000L 10712 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_CM_COLOC_HI_ACK_MASK 0x00080000L 10713 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_BSP0_LO_ACK_MASK 0x00100000L 10714 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_BSP0_HI_ACK_MASK 0x00200000L 10715 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_BSP1_LO_ACK_MASK 0x00400000L 10716 #define UVD_MEMCHECK_VCPU_INT_ACK__MIF_BSP1_HI_ACK_MASK 0x00800000L 10717 #define UVD_MEMCHECK_VCPU_INT_ACK__SRE_LO_ACK_MASK 0x01000000L 10718 #define UVD_MEMCHECK_VCPU_INT_ACK__SRE_HI_ACK_MASK 0x02000000L 10719 #define UVD_MEMCHECK_VCPU_INT_ACK__IT_RD_LO_ACK_MASK 0x40000000L 10720 #define UVD_MEMCHECK_VCPU_INT_ACK__IT_RD_HI_ACK_MASK 0x80000000L 10721 //UVD_MEMCHECK2_SYS_INT_STAT 10722 #define UVD_MEMCHECK2_SYS_INT_STAT__CM_RD_LO_ERR__SHIFT 0x0 10723 #define UVD_MEMCHECK2_SYS_INT_STAT__CM_RD_HI_ERR__SHIFT 0x1 10724 #define UVD_MEMCHECK2_SYS_INT_STAT__DB_RD_LO_ERR__SHIFT 0x2 10725 #define UVD_MEMCHECK2_SYS_INT_STAT__DB_RD_HI_ERR__SHIFT 0x3 10726 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_RD_LO_ERR__SHIFT 0x4 10727 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_RD_HI_ERR__SHIFT 0x5 10728 #define UVD_MEMCHECK2_SYS_INT_STAT__IDCT_RD_LO_ERR__SHIFT 0x6 10729 #define UVD_MEMCHECK2_SYS_INT_STAT__IDCT_RD_HI_ERR__SHIFT 0x7 10730 #define UVD_MEMCHECK2_SYS_INT_STAT__MPC_RD_LO_ERR__SHIFT 0x8 10731 #define UVD_MEMCHECK2_SYS_INT_STAT__MPC_RD_HI_ERR__SHIFT 0x9 10732 #define UVD_MEMCHECK2_SYS_INT_STAT__LBSI_RD_LO_ERR__SHIFT 0xa 10733 #define UVD_MEMCHECK2_SYS_INT_STAT__LBSI_RD_HI_ERR__SHIFT 0xb 10734 #define UVD_MEMCHECK2_SYS_INT_STAT__RBC_RD_LO_ERR__SHIFT 0x10 10735 #define UVD_MEMCHECK2_SYS_INT_STAT__RBC_RD_HI_ERR__SHIFT 0x11 10736 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP2_LO_ERR__SHIFT 0x16 10737 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP2_HI_ERR__SHIFT 0x17 10738 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP3_LO_ERR__SHIFT 0x18 10739 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP3_HI_ERR__SHIFT 0x19 10740 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR_LO_ERR__SHIFT 0x1a 10741 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR_HI_ERR__SHIFT 0x1b 10742 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR2_LO_ERR__SHIFT 0x1c 10743 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR2_HI_ERR__SHIFT 0x1d 10744 #define UVD_MEMCHECK2_SYS_INT_STAT__PREF_LO_ERR__SHIFT 0x1e 10745 #define UVD_MEMCHECK2_SYS_INT_STAT__PREF_HI_ERR__SHIFT 0x1f 10746 #define UVD_MEMCHECK2_SYS_INT_STAT__CM_RD_LO_ERR_MASK 0x00000001L 10747 #define UVD_MEMCHECK2_SYS_INT_STAT__CM_RD_HI_ERR_MASK 0x00000002L 10748 #define UVD_MEMCHECK2_SYS_INT_STAT__DB_RD_LO_ERR_MASK 0x00000004L 10749 #define UVD_MEMCHECK2_SYS_INT_STAT__DB_RD_HI_ERR_MASK 0x00000008L 10750 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_RD_LO_ERR_MASK 0x00000010L 10751 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_RD_HI_ERR_MASK 0x00000020L 10752 #define UVD_MEMCHECK2_SYS_INT_STAT__IDCT_RD_LO_ERR_MASK 0x00000040L 10753 #define UVD_MEMCHECK2_SYS_INT_STAT__IDCT_RD_HI_ERR_MASK 0x00000080L 10754 #define UVD_MEMCHECK2_SYS_INT_STAT__MPC_RD_LO_ERR_MASK 0x00000100L 10755 #define UVD_MEMCHECK2_SYS_INT_STAT__MPC_RD_HI_ERR_MASK 0x00000200L 10756 #define UVD_MEMCHECK2_SYS_INT_STAT__LBSI_RD_LO_ERR_MASK 0x00000400L 10757 #define UVD_MEMCHECK2_SYS_INT_STAT__LBSI_RD_HI_ERR_MASK 0x00000800L 10758 #define UVD_MEMCHECK2_SYS_INT_STAT__RBC_RD_LO_ERR_MASK 0x00010000L 10759 #define UVD_MEMCHECK2_SYS_INT_STAT__RBC_RD_HI_ERR_MASK 0x00020000L 10760 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP2_LO_ERR_MASK 0x00400000L 10761 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP2_HI_ERR_MASK 0x00800000L 10762 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP3_LO_ERR_MASK 0x01000000L 10763 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP3_HI_ERR_MASK 0x02000000L 10764 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR_LO_ERR_MASK 0x04000000L 10765 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR_HI_ERR_MASK 0x08000000L 10766 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR2_LO_ERR_MASK 0x10000000L 10767 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR2_HI_ERR_MASK 0x20000000L 10768 #define UVD_MEMCHECK2_SYS_INT_STAT__PREF_LO_ERR_MASK 0x40000000L 10769 #define UVD_MEMCHECK2_SYS_INT_STAT__PREF_HI_ERR_MASK 0x80000000L 10770 //UVD_MEMCHECK2_SYS_INT_ACK 10771 #define UVD_MEMCHECK2_SYS_INT_ACK__CM_RD_LO_ACK__SHIFT 0x0 10772 #define UVD_MEMCHECK2_SYS_INT_ACK__CM_RD_HI_ACK__SHIFT 0x1 10773 #define UVD_MEMCHECK2_SYS_INT_ACK__DB_RD_LO_ACK__SHIFT 0x2 10774 #define UVD_MEMCHECK2_SYS_INT_ACK__DB_RD_HI_ACK__SHIFT 0x3 10775 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_RD_LO_ACK__SHIFT 0x4 10776 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_RD_HI_ACK__SHIFT 0x5 10777 #define UVD_MEMCHECK2_SYS_INT_ACK__IDCT_RD_LO_ACK__SHIFT 0x6 10778 #define UVD_MEMCHECK2_SYS_INT_ACK__IDCT_RD_HI_ACK__SHIFT 0x7 10779 #define UVD_MEMCHECK2_SYS_INT_ACK__MPC_RD_LO_ACK__SHIFT 0x8 10780 #define UVD_MEMCHECK2_SYS_INT_ACK__MPC_RD_HI_ACK__SHIFT 0x9 10781 #define UVD_MEMCHECK2_SYS_INT_ACK__LBSI_RD_LO_ACK__SHIFT 0xa 10782 #define UVD_MEMCHECK2_SYS_INT_ACK__LBSI_RD_HI_ACK__SHIFT 0xb 10783 #define UVD_MEMCHECK2_SYS_INT_ACK__RBC_RD_LO_ACK__SHIFT 0x10 10784 #define UVD_MEMCHECK2_SYS_INT_ACK__RBC_RD_HI_ACK__SHIFT 0x11 10785 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP2_LO_ACK__SHIFT 0x16 10786 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP2_HI_ACK__SHIFT 0x17 10787 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP3_LO_ACK__SHIFT 0x18 10788 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP3_HI_ACK__SHIFT 0x19 10789 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR_LO_ACK__SHIFT 0x1a 10790 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR_HI_ACK__SHIFT 0x1b 10791 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR2_LO_ACK__SHIFT 0x1c 10792 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR2_HI_ACK__SHIFT 0x1d 10793 #define UVD_MEMCHECK2_SYS_INT_ACK__PREF_LO_ACK__SHIFT 0x1e 10794 #define UVD_MEMCHECK2_SYS_INT_ACK__PREF_HI_ACK__SHIFT 0x1f 10795 #define UVD_MEMCHECK2_SYS_INT_ACK__CM_RD_LO_ACK_MASK 0x00000001L 10796 #define UVD_MEMCHECK2_SYS_INT_ACK__CM_RD_HI_ACK_MASK 0x00000002L 10797 #define UVD_MEMCHECK2_SYS_INT_ACK__DB_RD_LO_ACK_MASK 0x00000004L 10798 #define UVD_MEMCHECK2_SYS_INT_ACK__DB_RD_HI_ACK_MASK 0x00000008L 10799 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_RD_LO_ACK_MASK 0x00000010L 10800 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_RD_HI_ACK_MASK 0x00000020L 10801 #define UVD_MEMCHECK2_SYS_INT_ACK__IDCT_RD_LO_ACK_MASK 0x00000040L 10802 #define UVD_MEMCHECK2_SYS_INT_ACK__IDCT_RD_HI_ACK_MASK 0x00000080L 10803 #define UVD_MEMCHECK2_SYS_INT_ACK__MPC_RD_LO_ACK_MASK 0x00000100L 10804 #define UVD_MEMCHECK2_SYS_INT_ACK__MPC_RD_HI_ACK_MASK 0x00000200L 10805 #define UVD_MEMCHECK2_SYS_INT_ACK__LBSI_RD_LO_ACK_MASK 0x00000400L 10806 #define UVD_MEMCHECK2_SYS_INT_ACK__LBSI_RD_HI_ACK_MASK 0x00000800L 10807 #define UVD_MEMCHECK2_SYS_INT_ACK__RBC_RD_LO_ACK_MASK 0x00010000L 10808 #define UVD_MEMCHECK2_SYS_INT_ACK__RBC_RD_HI_ACK_MASK 0x00020000L 10809 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP2_LO_ACK_MASK 0x00400000L 10810 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP2_HI_ACK_MASK 0x00800000L 10811 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP3_LO_ACK_MASK 0x01000000L 10812 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP3_HI_ACK_MASK 0x02000000L 10813 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR_LO_ACK_MASK 0x04000000L 10814 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR_HI_ACK_MASK 0x08000000L 10815 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR2_LO_ACK_MASK 0x10000000L 10816 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR2_HI_ACK_MASK 0x20000000L 10817 #define UVD_MEMCHECK2_SYS_INT_ACK__PREF_LO_ACK_MASK 0x40000000L 10818 #define UVD_MEMCHECK2_SYS_INT_ACK__PREF_HI_ACK_MASK 0x80000000L 10819 //UVD_MEMCHECK2_VCPU_INT_STAT 10820 #define UVD_MEMCHECK2_VCPU_INT_STAT__CM_RD_LO_ERR__SHIFT 0x0 10821 #define UVD_MEMCHECK2_VCPU_INT_STAT__CM_RD_HI_ERR__SHIFT 0x1 10822 #define UVD_MEMCHECK2_VCPU_INT_STAT__DB_RD_LO_ERR__SHIFT 0x2 10823 #define UVD_MEMCHECK2_VCPU_INT_STAT__DB_RD_HI_ERR__SHIFT 0x3 10824 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_RD_LO_ERR__SHIFT 0x4 10825 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_RD_HI_ERR__SHIFT 0x5 10826 #define UVD_MEMCHECK2_VCPU_INT_STAT__IDCT_RD_LO_ERR__SHIFT 0x6 10827 #define UVD_MEMCHECK2_VCPU_INT_STAT__IDCT_RD_HI_ERR__SHIFT 0x7 10828 #define UVD_MEMCHECK2_VCPU_INT_STAT__MPC_RD_LO_ERR__SHIFT 0x8 10829 #define UVD_MEMCHECK2_VCPU_INT_STAT__MPC_RD_HI_ERR__SHIFT 0x9 10830 #define UVD_MEMCHECK2_VCPU_INT_STAT__LBSI_RD_LO_ERR__SHIFT 0xa 10831 #define UVD_MEMCHECK2_VCPU_INT_STAT__LBSI_RD_HI_ERR__SHIFT 0xb 10832 #define UVD_MEMCHECK2_VCPU_INT_STAT__RBC_RD_LO_ERR__SHIFT 0x10 10833 #define UVD_MEMCHECK2_VCPU_INT_STAT__RBC_RD_HI_ERR__SHIFT 0x11 10834 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP2_LO_ERR__SHIFT 0x12 10835 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP2_HI_ERR__SHIFT 0x13 10836 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP3_LO_ERR__SHIFT 0x14 10837 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP3_HI_ERR__SHIFT 0x15 10838 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR_LO_ERR__SHIFT 0x16 10839 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR_HI_ERR__SHIFT 0x17 10840 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR2_LO_ERR__SHIFT 0x18 10841 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR2_HI_ERR__SHIFT 0x19 10842 #define UVD_MEMCHECK2_VCPU_INT_STAT__PREF_LO_ERR__SHIFT 0x1a 10843 #define UVD_MEMCHECK2_VCPU_INT_STAT__PREF_HI_ERR__SHIFT 0x1b 10844 #define UVD_MEMCHECK2_VCPU_INT_STAT__CM_RD_LO_ERR_MASK 0x00000001L 10845 #define UVD_MEMCHECK2_VCPU_INT_STAT__CM_RD_HI_ERR_MASK 0x00000002L 10846 #define UVD_MEMCHECK2_VCPU_INT_STAT__DB_RD_LO_ERR_MASK 0x00000004L 10847 #define UVD_MEMCHECK2_VCPU_INT_STAT__DB_RD_HI_ERR_MASK 0x00000008L 10848 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_RD_LO_ERR_MASK 0x00000010L 10849 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_RD_HI_ERR_MASK 0x00000020L 10850 #define UVD_MEMCHECK2_VCPU_INT_STAT__IDCT_RD_LO_ERR_MASK 0x00000040L 10851 #define UVD_MEMCHECK2_VCPU_INT_STAT__IDCT_RD_HI_ERR_MASK 0x00000080L 10852 #define UVD_MEMCHECK2_VCPU_INT_STAT__MPC_RD_LO_ERR_MASK 0x00000100L 10853 #define UVD_MEMCHECK2_VCPU_INT_STAT__MPC_RD_HI_ERR_MASK 0x00000200L 10854 #define UVD_MEMCHECK2_VCPU_INT_STAT__LBSI_RD_LO_ERR_MASK 0x00000400L 10855 #define UVD_MEMCHECK2_VCPU_INT_STAT__LBSI_RD_HI_ERR_MASK 0x00000800L 10856 #define UVD_MEMCHECK2_VCPU_INT_STAT__RBC_RD_LO_ERR_MASK 0x00010000L 10857 #define UVD_MEMCHECK2_VCPU_INT_STAT__RBC_RD_HI_ERR_MASK 0x00020000L 10858 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP2_LO_ERR_MASK 0x00040000L 10859 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP2_HI_ERR_MASK 0x00080000L 10860 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP3_LO_ERR_MASK 0x00100000L 10861 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP3_HI_ERR_MASK 0x00200000L 10862 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR_LO_ERR_MASK 0x00400000L 10863 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR_HI_ERR_MASK 0x00800000L 10864 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR2_LO_ERR_MASK 0x01000000L 10865 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR2_HI_ERR_MASK 0x02000000L 10866 #define UVD_MEMCHECK2_VCPU_INT_STAT__PREF_LO_ERR_MASK 0x04000000L 10867 #define UVD_MEMCHECK2_VCPU_INT_STAT__PREF_HI_ERR_MASK 0x08000000L 10868 //UVD_MEMCHECK2_VCPU_INT_ACK 10869 #define UVD_MEMCHECK2_VCPU_INT_ACK__CM_RD_LO_ACK__SHIFT 0x0 10870 #define UVD_MEMCHECK2_VCPU_INT_ACK__CM_RD_HI_ACK__SHIFT 0x1 10871 #define UVD_MEMCHECK2_VCPU_INT_ACK__DB_RD_LO_ACK__SHIFT 0x2 10872 #define UVD_MEMCHECK2_VCPU_INT_ACK__DB_RD_HI_ACK__SHIFT 0x3 10873 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_RD_LO_ACK__SHIFT 0x4 10874 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_RD_HI_ACK__SHIFT 0x5 10875 #define UVD_MEMCHECK2_VCPU_INT_ACK__IDCT_RD_LO_ACK__SHIFT 0x6 10876 #define UVD_MEMCHECK2_VCPU_INT_ACK__IDCT_RD_HI_ACK__SHIFT 0x7 10877 #define UVD_MEMCHECK2_VCPU_INT_ACK__MPC_RD_LO_ACK__SHIFT 0x8 10878 #define UVD_MEMCHECK2_VCPU_INT_ACK__MPC_RD_HI_ACK__SHIFT 0x9 10879 #define UVD_MEMCHECK2_VCPU_INT_ACK__LBSI_RD_LO_ACK__SHIFT 0xa 10880 #define UVD_MEMCHECK2_VCPU_INT_ACK__LBSI_RD_HI_ACK__SHIFT 0xb 10881 #define UVD_MEMCHECK2_VCPU_INT_ACK__RBC_RD_LO_ACK__SHIFT 0x10 10882 #define UVD_MEMCHECK2_VCPU_INT_ACK__RBC_RD_HI_ACK__SHIFT 0x11 10883 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP2_LO_ACK__SHIFT 0x12 10884 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP2_HI_ACK__SHIFT 0x13 10885 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP3_LO_ACK__SHIFT 0x14 10886 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP3_HI_ACK__SHIFT 0x15 10887 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR_LO_ACK__SHIFT 0x16 10888 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR_HI_ACK__SHIFT 0x17 10889 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR2_LO_ACK__SHIFT 0x18 10890 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR2_HI_ACK__SHIFT 0x19 10891 #define UVD_MEMCHECK2_VCPU_INT_ACK__PREF_LO_ACK__SHIFT 0x1a 10892 #define UVD_MEMCHECK2_VCPU_INT_ACK__PREF_HI_ACK__SHIFT 0x1b 10893 #define UVD_MEMCHECK2_VCPU_INT_ACK__CM_RD_LO_ACK_MASK 0x00000001L 10894 #define UVD_MEMCHECK2_VCPU_INT_ACK__CM_RD_HI_ACK_MASK 0x00000002L 10895 #define UVD_MEMCHECK2_VCPU_INT_ACK__DB_RD_LO_ACK_MASK 0x00000004L 10896 #define UVD_MEMCHECK2_VCPU_INT_ACK__DB_RD_HI_ACK_MASK 0x00000008L 10897 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_RD_LO_ACK_MASK 0x00000010L 10898 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_RD_HI_ACK_MASK 0x00000020L 10899 #define UVD_MEMCHECK2_VCPU_INT_ACK__IDCT_RD_LO_ACK_MASK 0x00000040L 10900 #define UVD_MEMCHECK2_VCPU_INT_ACK__IDCT_RD_HI_ACK_MASK 0x00000080L 10901 #define UVD_MEMCHECK2_VCPU_INT_ACK__MPC_RD_LO_ACK_MASK 0x00000100L 10902 #define UVD_MEMCHECK2_VCPU_INT_ACK__MPC_RD_HI_ACK_MASK 0x00000200L 10903 #define UVD_MEMCHECK2_VCPU_INT_ACK__LBSI_RD_LO_ACK_MASK 0x00000400L 10904 #define UVD_MEMCHECK2_VCPU_INT_ACK__LBSI_RD_HI_ACK_MASK 0x00000800L 10905 #define UVD_MEMCHECK2_VCPU_INT_ACK__RBC_RD_LO_ACK_MASK 0x00010000L 10906 #define UVD_MEMCHECK2_VCPU_INT_ACK__RBC_RD_HI_ACK_MASK 0x00020000L 10907 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP2_LO_ACK_MASK 0x00040000L 10908 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP2_HI_ACK_MASK 0x00080000L 10909 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP3_LO_ACK_MASK 0x00100000L 10910 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP3_HI_ACK_MASK 0x00200000L 10911 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR_LO_ACK_MASK 0x00400000L 10912 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR_HI_ACK_MASK 0x00800000L 10913 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR2_LO_ACK_MASK 0x01000000L 10914 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR2_HI_ACK_MASK 0x02000000L 10915 #define UVD_MEMCHECK2_VCPU_INT_ACK__PREF_LO_ACK_MASK 0x04000000L 10916 #define UVD_MEMCHECK2_VCPU_INT_ACK__PREF_HI_ACK_MASK 0x08000000L 10917 10918 10919 #endif 10920
