1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2// 3// Device Tree Source for UniPhier PXs2 SoC 4// 5// Copyright (C) 2015-2016 Socionext Inc. 6// Author: Masahiro Yamada <yamada.masahiro@socionext.com> 7 8#include <dt-bindings/gpio/uniphier-gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/thermal/thermal.h> 11 12/ { 13 compatible = "socionext,uniphier-pxs2"; 14 #address-cells = <1>; 15 #size-cells = <1>; 16 17 cpus { 18 #address-cells = <1>; 19 #size-cells = <0>; 20 21 cpu0: cpu@0 { 22 device_type = "cpu"; 23 compatible = "arm,cortex-a9"; 24 reg = <0>; 25 clocks = <&sys_clk 32>; 26 enable-method = "psci"; 27 next-level-cache = <&l2>; 28 operating-points-v2 = <&cpu_opp>; 29 #cooling-cells = <2>; 30 }; 31 32 cpu1: cpu@1 { 33 device_type = "cpu"; 34 compatible = "arm,cortex-a9"; 35 reg = <1>; 36 clocks = <&sys_clk 32>; 37 enable-method = "psci"; 38 next-level-cache = <&l2>; 39 operating-points-v2 = <&cpu_opp>; 40 #cooling-cells = <2>; 41 }; 42 43 cpu2: cpu@2 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a9"; 46 reg = <2>; 47 clocks = <&sys_clk 32>; 48 enable-method = "psci"; 49 next-level-cache = <&l2>; 50 operating-points-v2 = <&cpu_opp>; 51 #cooling-cells = <2>; 52 }; 53 54 cpu3: cpu@3 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-a9"; 57 reg = <3>; 58 clocks = <&sys_clk 32>; 59 enable-method = "psci"; 60 next-level-cache = <&l2>; 61 operating-points-v2 = <&cpu_opp>; 62 #cooling-cells = <2>; 63 }; 64 }; 65 66 cpu_opp: opp-table { 67 compatible = "operating-points-v2"; 68 opp-shared; 69 70 opp-100000000 { 71 opp-hz = /bits/ 64 <100000000>; 72 clock-latency-ns = <300>; 73 }; 74 opp-150000000 { 75 opp-hz = /bits/ 64 <150000000>; 76 clock-latency-ns = <300>; 77 }; 78 opp-200000000 { 79 opp-hz = /bits/ 64 <200000000>; 80 clock-latency-ns = <300>; 81 }; 82 opp-300000000 { 83 opp-hz = /bits/ 64 <300000000>; 84 clock-latency-ns = <300>; 85 }; 86 opp-400000000 { 87 opp-hz = /bits/ 64 <400000000>; 88 clock-latency-ns = <300>; 89 }; 90 opp-600000000 { 91 opp-hz = /bits/ 64 <600000000>; 92 clock-latency-ns = <300>; 93 }; 94 opp-800000000 { 95 opp-hz = /bits/ 64 <800000000>; 96 clock-latency-ns = <300>; 97 }; 98 opp-1200000000 { 99 opp-hz = /bits/ 64 <1200000000>; 100 clock-latency-ns = <300>; 101 }; 102 }; 103 104 psci { 105 compatible = "arm,psci-0.2"; 106 method = "smc"; 107 }; 108 109 clocks { 110 refclk: ref { 111 compatible = "fixed-clock"; 112 #clock-cells = <0>; 113 clock-frequency = <25000000>; 114 }; 115 116 arm_timer_clk: arm-timer { 117 #clock-cells = <0>; 118 compatible = "fixed-clock"; 119 clock-frequency = <50000000>; 120 }; 121 }; 122 123 thermal-zones { 124 cpu-thermal { 125 polling-delay-passive = <250>; /* 250ms */ 126 polling-delay = <1000>; /* 1000ms */ 127 thermal-sensors = <&pvtctl>; 128 129 trips { 130 cpu_crit: cpu-crit { 131 temperature = <95000>; /* 95C */ 132 hysteresis = <2000>; 133 type = "critical"; 134 }; 135 cpu_alert: cpu-alert { 136 temperature = <85000>; /* 85C */ 137 hysteresis = <2000>; 138 type = "passive"; 139 }; 140 }; 141 142 cooling-maps { 143 map { 144 trip = <&cpu_alert>; 145 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 146 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 147 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 148 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 149 }; 150 }; 151 }; 152 }; 153 154 soc { 155 compatible = "simple-bus"; 156 #address-cells = <1>; 157 #size-cells = <1>; 158 ranges; 159 interrupt-parent = <&intc>; 160 161 l2: cache-controller@500c0000 { 162 compatible = "socionext,uniphier-system-cache"; 163 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, 164 <0x506c0000 0x400>; 165 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 167 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 168 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 169 cache-unified; 170 cache-size = <(1280 * 1024)>; 171 cache-sets = <512>; 172 cache-line-size = <128>; 173 cache-level = <2>; 174 }; 175 176 spi0: spi@54006000 { 177 compatible = "socionext,uniphier-scssi"; 178 status = "disabled"; 179 reg = <0x54006000 0x100>; 180 #address-cells = <1>; 181 #size-cells = <0>; 182 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 183 pinctrl-names = "default"; 184 pinctrl-0 = <&pinctrl_spi0>; 185 clocks = <&peri_clk 11>; 186 resets = <&peri_rst 11>; 187 }; 188 189 spi1: spi@54006100 { 190 compatible = "socionext,uniphier-scssi"; 191 status = "disabled"; 192 reg = <0x54006100 0x100>; 193 #address-cells = <1>; 194 #size-cells = <0>; 195 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 196 pinctrl-names = "default"; 197 pinctrl-0 = <&pinctrl_spi1>; 198 clocks = <&peri_clk 12>; 199 resets = <&peri_rst 12>; 200 }; 201 202 serial0: serial@54006800 { 203 compatible = "socionext,uniphier-uart"; 204 status = "disabled"; 205 reg = <0x54006800 0x40>; 206 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 207 pinctrl-names = "default"; 208 pinctrl-0 = <&pinctrl_uart0>; 209 clocks = <&peri_clk 0>; 210 resets = <&peri_rst 0>; 211 }; 212 213 serial1: serial@54006900 { 214 compatible = "socionext,uniphier-uart"; 215 status = "disabled"; 216 reg = <0x54006900 0x40>; 217 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 218 pinctrl-names = "default"; 219 pinctrl-0 = <&pinctrl_uart1>; 220 clocks = <&peri_clk 1>; 221 resets = <&peri_rst 1>; 222 }; 223 224 serial2: serial@54006a00 { 225 compatible = "socionext,uniphier-uart"; 226 status = "disabled"; 227 reg = <0x54006a00 0x40>; 228 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 229 pinctrl-names = "default"; 230 pinctrl-0 = <&pinctrl_uart2>; 231 clocks = <&peri_clk 2>; 232 resets = <&peri_rst 2>; 233 }; 234 235 serial3: serial@54006b00 { 236 compatible = "socionext,uniphier-uart"; 237 status = "disabled"; 238 reg = <0x54006b00 0x40>; 239 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 240 pinctrl-names = "default"; 241 pinctrl-0 = <&pinctrl_uart3>; 242 clocks = <&peri_clk 3>; 243 resets = <&peri_rst 3>; 244 }; 245 246 gpio: gpio@55000000 { 247 compatible = "socionext,uniphier-gpio"; 248 reg = <0x55000000 0x200>; 249 interrupt-parent = <&aidet>; 250 interrupt-controller; 251 #interrupt-cells = <2>; 252 gpio-controller; 253 #gpio-cells = <2>; 254 gpio-ranges = <&pinctrl 0 0 0>, 255 <&pinctrl 96 0 0>; 256 gpio-ranges-group-names = "gpio_range0", 257 "gpio_range1"; 258 ngpios = <232>; 259 socionext,interrupt-ranges = <0 48 16>, <16 154 5>, 260 <21 217 3>; 261 }; 262 263 audio@56000000 { 264 compatible = "socionext,uniphier-pxs2-aio"; 265 reg = <0x56000000 0x80000>; 266 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 267 pinctrl-names = "default"; 268 pinctrl-0 = <&pinctrl_ain1>, 269 <&pinctrl_ain2>, 270 <&pinctrl_ainiec1>, 271 <&pinctrl_aout2>, 272 <&pinctrl_aout3>, 273 <&pinctrl_aoutiec1>, 274 <&pinctrl_aoutiec2>; 275 clock-names = "aio"; 276 clocks = <&sys_clk 40>; 277 reset-names = "aio"; 278 resets = <&sys_rst 40>; 279 #sound-dai-cells = <1>; 280 socionext,syscon = <&soc_glue>; 281 282 i2s_port0: port@0 { 283 i2s_hdmi: endpoint { 284 }; 285 }; 286 287 i2s_port1: port@1 { 288 i2s_line: endpoint { 289 }; 290 }; 291 292 i2s_port2: port@2 { 293 i2s_aux: endpoint { 294 }; 295 }; 296 297 spdif_port0: port@3 { 298 spdif_hiecout1: endpoint { 299 }; 300 }; 301 302 spdif_port1: port@4 { 303 spdif_iecout1: endpoint { 304 }; 305 }; 306 307 comp_spdif_port0: port@5 { 308 comp_spdif_hiecout1: endpoint { 309 }; 310 }; 311 312 comp_spdif_port1: port@6 { 313 comp_spdif_iecout1: endpoint { 314 }; 315 }; 316 }; 317 318 i2c0: i2c@58780000 { 319 compatible = "socionext,uniphier-fi2c"; 320 status = "disabled"; 321 reg = <0x58780000 0x80>; 322 #address-cells = <1>; 323 #size-cells = <0>; 324 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 325 pinctrl-names = "default"; 326 pinctrl-0 = <&pinctrl_i2c0>; 327 clocks = <&peri_clk 4>; 328 resets = <&peri_rst 4>; 329 clock-frequency = <100000>; 330 }; 331 332 i2c1: i2c@58781000 { 333 compatible = "socionext,uniphier-fi2c"; 334 status = "disabled"; 335 reg = <0x58781000 0x80>; 336 #address-cells = <1>; 337 #size-cells = <0>; 338 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 339 pinctrl-names = "default"; 340 pinctrl-0 = <&pinctrl_i2c1>; 341 clocks = <&peri_clk 5>; 342 resets = <&peri_rst 5>; 343 clock-frequency = <100000>; 344 }; 345 346 i2c2: i2c@58782000 { 347 compatible = "socionext,uniphier-fi2c"; 348 status = "disabled"; 349 reg = <0x58782000 0x80>; 350 #address-cells = <1>; 351 #size-cells = <0>; 352 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 353 pinctrl-names = "default"; 354 pinctrl-0 = <&pinctrl_i2c2>; 355 clocks = <&peri_clk 6>; 356 resets = <&peri_rst 6>; 357 clock-frequency = <100000>; 358 }; 359 360 i2c3: i2c@58783000 { 361 compatible = "socionext,uniphier-fi2c"; 362 status = "disabled"; 363 reg = <0x58783000 0x80>; 364 #address-cells = <1>; 365 #size-cells = <0>; 366 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 367 pinctrl-names = "default"; 368 pinctrl-0 = <&pinctrl_i2c3>; 369 clocks = <&peri_clk 7>; 370 resets = <&peri_rst 7>; 371 clock-frequency = <100000>; 372 }; 373 374 /* chip-internal connection for DMD */ 375 i2c4: i2c@58784000 { 376 compatible = "socionext,uniphier-fi2c"; 377 reg = <0x58784000 0x80>; 378 #address-cells = <1>; 379 #size-cells = <0>; 380 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 381 clocks = <&peri_clk 8>; 382 resets = <&peri_rst 8>; 383 clock-frequency = <400000>; 384 }; 385 386 /* chip-internal connection for STM */ 387 i2c5: i2c@58785000 { 388 compatible = "socionext,uniphier-fi2c"; 389 reg = <0x58785000 0x80>; 390 #address-cells = <1>; 391 #size-cells = <0>; 392 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 393 clocks = <&peri_clk 9>; 394 resets = <&peri_rst 9>; 395 clock-frequency = <400000>; 396 }; 397 398 /* chip-internal connection for HDMI */ 399 i2c6: i2c@58786000 { 400 compatible = "socionext,uniphier-fi2c"; 401 reg = <0x58786000 0x80>; 402 #address-cells = <1>; 403 #size-cells = <0>; 404 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 405 clocks = <&peri_clk 10>; 406 resets = <&peri_rst 10>; 407 clock-frequency = <400000>; 408 }; 409 410 system_bus: system-bus@58c00000 { 411 compatible = "socionext,uniphier-system-bus"; 412 status = "disabled"; 413 reg = <0x58c00000 0x400>; 414 #address-cells = <2>; 415 #size-cells = <1>; 416 pinctrl-names = "default"; 417 pinctrl-0 = <&pinctrl_system_bus>; 418 }; 419 420 smpctrl@59801000 { 421 compatible = "socionext,uniphier-smpctrl"; 422 reg = <0x59801000 0x400>; 423 }; 424 425 sdctrl@59810000 { 426 compatible = "socionext,uniphier-pxs2-sdctrl", 427 "simple-mfd", "syscon"; 428 reg = <0x59810000 0x400>; 429 430 sd_clk: clock { 431 compatible = "socionext,uniphier-pxs2-sd-clock"; 432 #clock-cells = <1>; 433 }; 434 435 sd_rst: reset { 436 compatible = "socionext,uniphier-pxs2-sd-reset"; 437 #reset-cells = <1>; 438 }; 439 }; 440 441 perictrl@59820000 { 442 compatible = "socionext,uniphier-pxs2-perictrl", 443 "simple-mfd", "syscon"; 444 reg = <0x59820000 0x200>; 445 446 peri_clk: clock { 447 compatible = "socionext,uniphier-pxs2-peri-clock"; 448 #clock-cells = <1>; 449 }; 450 451 peri_rst: reset { 452 compatible = "socionext,uniphier-pxs2-peri-reset"; 453 #reset-cells = <1>; 454 }; 455 }; 456 457 emmc: mmc@5a000000 { 458 compatible = "socionext,uniphier-sd-v3.1.1"; 459 status = "disabled"; 460 reg = <0x5a000000 0x800>; 461 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 462 pinctrl-names = "default"; 463 pinctrl-0 = <&pinctrl_emmc>; 464 clocks = <&sd_clk 1>; 465 reset-names = "host", "hw"; 466 resets = <&sd_rst 1>, <&sd_rst 6>; 467 bus-width = <8>; 468 cap-mmc-highspeed; 469 cap-mmc-hw-reset; 470 non-removable; 471 }; 472 473 sd: mmc@5a400000 { 474 compatible = "socionext,uniphier-sd-v3.1.1"; 475 status = "disabled"; 476 reg = <0x5a400000 0x800>; 477 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 478 pinctrl-names = "default", "uhs"; 479 pinctrl-0 = <&pinctrl_sd>; 480 pinctrl-1 = <&pinctrl_sd_uhs>; 481 clocks = <&sd_clk 0>; 482 reset-names = "host"; 483 resets = <&sd_rst 0>; 484 bus-width = <4>; 485 cap-sd-highspeed; 486 sd-uhs-sdr12; 487 sd-uhs-sdr25; 488 sd-uhs-sdr50; 489 }; 490 491 soc_glue: soc-glue@5f800000 { 492 compatible = "socionext,uniphier-pxs2-soc-glue", 493 "simple-mfd", "syscon"; 494 reg = <0x5f800000 0x2000>; 495 496 pinctrl: pinctrl { 497 compatible = "socionext,uniphier-pxs2-pinctrl"; 498 }; 499 }; 500 501 soc-glue@5f900000 { 502 compatible = "socionext,uniphier-pxs2-soc-glue-debug", 503 "simple-mfd"; 504 #address-cells = <1>; 505 #size-cells = <1>; 506 ranges = <0 0x5f900000 0x2000>; 507 508 efuse@100 { 509 compatible = "socionext,uniphier-efuse"; 510 reg = <0x100 0x28>; 511 }; 512 513 efuse@200 { 514 compatible = "socionext,uniphier-efuse"; 515 reg = <0x200 0x58>; 516 }; 517 }; 518 519 xdmac: dma-controller@5fc10000 { 520 compatible = "socionext,uniphier-xdmac"; 521 reg = <0x5fc10000 0x5300>; 522 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 523 dma-channels = <16>; 524 #dma-cells = <2>; 525 }; 526 527 aidet: interrupt-controller@5fc20000 { 528 compatible = "socionext,uniphier-pxs2-aidet"; 529 reg = <0x5fc20000 0x200>; 530 interrupt-controller; 531 #interrupt-cells = <2>; 532 }; 533 534 timer@60000200 { 535 compatible = "arm,cortex-a9-global-timer"; 536 reg = <0x60000200 0x20>; 537 interrupts = <GIC_PPI 11 538 (GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_HIGH)>; 539 clocks = <&arm_timer_clk>; 540 }; 541 542 timer@60000600 { 543 compatible = "arm,cortex-a9-twd-timer"; 544 reg = <0x60000600 0x20>; 545 interrupts = <GIC_PPI 13 546 (GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_HIGH)>; 547 clocks = <&arm_timer_clk>; 548 }; 549 550 intc: interrupt-controller@60001000 { 551 compatible = "arm,cortex-a9-gic"; 552 reg = <0x60001000 0x1000>, 553 <0x60000100 0x100>; 554 #interrupt-cells = <3>; 555 interrupt-controller; 556 }; 557 558 sysctrl@61840000 { 559 compatible = "socionext,uniphier-pxs2-sysctrl", 560 "simple-mfd", "syscon"; 561 reg = <0x61840000 0x10000>; 562 563 sys_clk: clock { 564 compatible = "socionext,uniphier-pxs2-clock"; 565 #clock-cells = <1>; 566 }; 567 568 sys_rst: reset { 569 compatible = "socionext,uniphier-pxs2-reset"; 570 #reset-cells = <1>; 571 }; 572 573 pvtctl: thermal-sensor { 574 compatible = "socionext,uniphier-pxs2-thermal"; 575 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 576 #thermal-sensor-cells = <0>; 577 socionext,tmod-calibration = <0x0f86 0x6844>; 578 }; 579 }; 580 581 eth: ethernet@65000000 { 582 compatible = "socionext,uniphier-pxs2-ave4"; 583 status = "disabled"; 584 reg = <0x65000000 0x8500>; 585 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 586 pinctrl-names = "default"; 587 pinctrl-0 = <&pinctrl_ether_rgmii>; 588 clock-names = "ether"; 589 clocks = <&sys_clk 6>; 590 reset-names = "ether"; 591 resets = <&sys_rst 6>; 592 phy-mode = "rgmii-id"; 593 local-mac-address = [00 00 00 00 00 00]; 594 socionext,syscon-phy-mode = <&soc_glue 0>; 595 596 mdio: mdio { 597 #address-cells = <1>; 598 #size-cells = <0>; 599 }; 600 }; 601 602 ahci: sata@65600000 { 603 compatible = "socionext,uniphier-pxs2-ahci", 604 "generic-ahci"; 605 status = "disabled"; 606 reg = <0x65600000 0x10000>; 607 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 608 clocks = <&sys_clk 28>; 609 resets = <&sys_rst 28>, <&ahci_rst 0>; 610 ports-implemented = <1>; 611 phys = <&ahci_phy>; 612 }; 613 614 sata-controller@65700000 { 615 compatible = "socionext,uniphier-pxs2-ahci-glue", 616 "simple-mfd"; 617 #address-cells = <1>; 618 #size-cells = <1>; 619 ranges = <0 0x65700000 0x100>; 620 621 ahci_rst: reset-controller@0 { 622 compatible = "socionext,uniphier-pxs2-ahci-reset"; 623 reg = <0x0 0x4>; 624 clock-names = "link"; 625 clocks = <&sys_clk 28>; 626 reset-names = "link"; 627 resets = <&sys_rst 28>; 628 #reset-cells = <1>; 629 }; 630 631 ahci_phy: sata-phy@10 { 632 compatible = "socionext,uniphier-pxs2-ahci-phy"; 633 reg = <0x10 0x10>; 634 clock-names = "link"; 635 clocks = <&sys_clk 28>; 636 reset-names = "link", "phy"; 637 resets = <&sys_rst 28>, <&sys_rst 30>; 638 #phy-cells = <0>; 639 }; 640 }; 641 642 usb0: usb@65a00000 { 643 compatible = "socionext,uniphier-dwc3", "snps,dwc3"; 644 status = "disabled"; 645 reg = <0x65a00000 0xcd00>; 646 interrupt-names = "dwc_usb3"; 647 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 648 pinctrl-names = "default"; 649 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>; 650 clock-names = "ref", "bus_early", "suspend"; 651 clocks = <&sys_clk 14>, <&sys_clk 14>, <&sys_clk 14>; 652 resets = <&usb0_rst 15>; 653 phys = <&usb0_hsphy0>, <&usb0_hsphy1>, 654 <&usb0_ssphy0>, <&usb0_ssphy1>; 655 dr_mode = "host"; 656 }; 657 658 usb-controller@65b00000 { 659 compatible = "socionext,uniphier-pxs2-dwc3-glue", 660 "simple-mfd"; 661 #address-cells = <1>; 662 #size-cells = <1>; 663 ranges = <0 0x65b00000 0x400>; 664 665 usb0_rst: reset@0 { 666 compatible = "socionext,uniphier-pxs2-usb3-reset"; 667 reg = <0x0 0x4>; 668 #reset-cells = <1>; 669 clock-names = "link"; 670 clocks = <&sys_clk 14>; 671 reset-names = "link"; 672 resets = <&sys_rst 14>; 673 }; 674 675 usb0_vbus0: regulator@100 { 676 compatible = "socionext,uniphier-pxs2-usb3-regulator"; 677 reg = <0x100 0x10>; 678 clock-names = "link"; 679 clocks = <&sys_clk 14>; 680 reset-names = "link"; 681 resets = <&sys_rst 14>; 682 }; 683 684 usb0_vbus1: regulator@110 { 685 compatible = "socionext,uniphier-pxs2-usb3-regulator"; 686 reg = <0x110 0x10>; 687 clock-names = "link"; 688 clocks = <&sys_clk 14>; 689 reset-names = "link"; 690 resets = <&sys_rst 14>; 691 }; 692 693 usb0_hsphy0: hs-phy@200 { 694 compatible = "socionext,uniphier-pxs2-usb3-hsphy"; 695 reg = <0x200 0x10>; 696 #phy-cells = <0>; 697 clock-names = "link", "phy"; 698 clocks = <&sys_clk 14>, <&sys_clk 16>; 699 reset-names = "link", "phy"; 700 resets = <&sys_rst 14>, <&sys_rst 16>; 701 vbus-supply = <&usb0_vbus0>; 702 }; 703 704 usb0_hsphy1: hs-phy@210 { 705 compatible = "socionext,uniphier-pxs2-usb3-hsphy"; 706 reg = <0x210 0x10>; 707 #phy-cells = <0>; 708 clock-names = "link", "phy"; 709 clocks = <&sys_clk 14>, <&sys_clk 16>; 710 reset-names = "link", "phy"; 711 resets = <&sys_rst 14>, <&sys_rst 16>; 712 vbus-supply = <&usb0_vbus1>; 713 }; 714 715 usb0_ssphy0: ss-phy@300 { 716 compatible = "socionext,uniphier-pxs2-usb3-ssphy"; 717 reg = <0x300 0x10>; 718 #phy-cells = <0>; 719 clock-names = "link", "phy"; 720 clocks = <&sys_clk 14>, <&sys_clk 17>; 721 reset-names = "link", "phy"; 722 resets = <&sys_rst 14>, <&sys_rst 17>; 723 vbus-supply = <&usb0_vbus0>; 724 }; 725 726 usb0_ssphy1: ss-phy@310 { 727 compatible = "socionext,uniphier-pxs2-usb3-ssphy"; 728 reg = <0x310 0x10>; 729 #phy-cells = <0>; 730 clock-names = "link", "phy"; 731 clocks = <&sys_clk 14>, <&sys_clk 18>; 732 reset-names = "link", "phy"; 733 resets = <&sys_rst 14>, <&sys_rst 18>; 734 vbus-supply = <&usb0_vbus1>; 735 }; 736 }; 737 738 usb1: usb@65c00000 { 739 compatible = "socionext,uniphier-dwc3", "snps,dwc3"; 740 status = "disabled"; 741 reg = <0x65c00000 0xcd00>; 742 interrupt-names = "dwc_usb3"; 743 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 744 pinctrl-names = "default"; 745 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>; 746 clock-names = "ref", "bus_early", "suspend"; 747 clocks = <&sys_clk 15>, <&sys_clk 15>, <&sys_clk 15>; 748 resets = <&usb1_rst 15>; 749 phys = <&usb1_hsphy0>, <&usb1_hsphy1>, <&usb1_ssphy0>; 750 dr_mode = "host"; 751 }; 752 753 usb-controller@65d00000 { 754 compatible = "socionext,uniphier-pxs2-dwc3-glue", 755 "simple-mfd"; 756 #address-cells = <1>; 757 #size-cells = <1>; 758 ranges = <0 0x65d00000 0x400>; 759 760 usb1_rst: reset@0 { 761 compatible = "socionext,uniphier-pxs2-usb3-reset"; 762 reg = <0x0 0x4>; 763 #reset-cells = <1>; 764 clock-names = "link"; 765 clocks = <&sys_clk 15>; 766 reset-names = "link"; 767 resets = <&sys_rst 15>; 768 }; 769 770 usb1_vbus0: regulator@100 { 771 compatible = "socionext,uniphier-pxs2-usb3-regulator"; 772 reg = <0x100 0x10>; 773 clock-names = "link"; 774 clocks = <&sys_clk 15>; 775 reset-names = "link"; 776 resets = <&sys_rst 15>; 777 }; 778 779 usb1_vbus1: regulator@110 { 780 compatible = "socionext,uniphier-pxs2-usb3-regulator"; 781 reg = <0x110 0x10>; 782 clock-names = "link"; 783 clocks = <&sys_clk 15>; 784 reset-names = "link"; 785 resets = <&sys_rst 15>; 786 }; 787 788 usb1_hsphy0: hs-phy@200 { 789 compatible = "socionext,uniphier-pxs2-usb3-hsphy"; 790 reg = <0x200 0x10>; 791 #phy-cells = <0>; 792 clock-names = "link", "phy"; 793 clocks = <&sys_clk 15>, <&sys_clk 20>; 794 reset-names = "link", "phy"; 795 resets = <&sys_rst 15>, <&sys_rst 20>; 796 vbus-supply = <&usb1_vbus0>; 797 }; 798 799 usb1_hsphy1: hs-phy@210 { 800 compatible = "socionext,uniphier-pxs2-usb3-hsphy"; 801 reg = <0x210 0x10>; 802 #phy-cells = <0>; 803 clock-names = "link", "phy"; 804 clocks = <&sys_clk 15>, <&sys_clk 20>; 805 reset-names = "link", "phy"; 806 resets = <&sys_rst 15>, <&sys_rst 20>; 807 vbus-supply = <&usb1_vbus1>; 808 }; 809 810 usb1_ssphy0: ss-phy@300 { 811 compatible = "socionext,uniphier-pxs2-usb3-ssphy"; 812 reg = <0x300 0x10>; 813 #phy-cells = <0>; 814 clock-names = "link", "phy"; 815 clocks = <&sys_clk 15>, <&sys_clk 21>; 816 reset-names = "link", "phy"; 817 resets = <&sys_rst 15>, <&sys_rst 21>; 818 vbus-supply = <&usb1_vbus0>; 819 }; 820 }; 821 822 nand: nand-controller@68000000 { 823 compatible = "socionext,uniphier-denali-nand-v5b"; 824 status = "disabled"; 825 reg-names = "nand_data", "denali_reg"; 826 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 827 #address-cells = <1>; 828 #size-cells = <0>; 829 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 830 pinctrl-names = "default"; 831 pinctrl-0 = <&pinctrl_nand>; 832 clock-names = "nand", "nand_x", "ecc"; 833 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; 834 reset-names = "nand", "reg"; 835 resets = <&sys_rst 2>, <&sys_rst 2>; 836 }; 837 }; 838}; 839 840#include "uniphier-pinctrl.dtsi" 841
