1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright(C) 2015 Linaro Limited. All rights reserved.
4 * Author: Mathieu Poirier <mathieu.poirier@linaro.org>
5 */
6
7 #include <stdbool.h>
8 #include <linux/coresight-pmu.h>
9
10 #include "../../util/auxtrace.h"
11 #include "../../util/evlist.h"
12 #include "../../util/pmu.h"
13 #include "cs-etm.h"
14 #include "arm-spe.h"
15
find_all_arm_spe_pmus(int * nr_spes,int * err)16 static struct perf_pmu **find_all_arm_spe_pmus(int *nr_spes, int *err)
17 {
18 struct perf_pmu **arm_spe_pmus = NULL;
19 int ret, i, nr_cpus = sysconf(_SC_NPROCESSORS_CONF);
20 /* arm_spe_xxxxxxxxx\0 */
21 char arm_spe_pmu_name[sizeof(ARM_SPE_PMU_NAME) + 10];
22
23 arm_spe_pmus = zalloc(sizeof(struct perf_pmu *) * nr_cpus);
24 if (!arm_spe_pmus) {
25 pr_err("spes alloc failed\n");
26 *err = -ENOMEM;
27 return NULL;
28 }
29
30 for (i = 0; i < nr_cpus; i++) {
31 ret = sprintf(arm_spe_pmu_name, "%s%d", ARM_SPE_PMU_NAME, i);
32 if (ret < 0) {
33 pr_err("sprintf failed\n");
34 *err = -ENOMEM;
35 return NULL;
36 }
37
38 arm_spe_pmus[*nr_spes] = perf_pmu__find(arm_spe_pmu_name);
39 if (arm_spe_pmus[*nr_spes]) {
40 pr_debug2("%s %d: arm_spe_pmu %d type %d name %s\n",
41 __func__, __LINE__, *nr_spes,
42 arm_spe_pmus[*nr_spes]->type,
43 arm_spe_pmus[*nr_spes]->name);
44 (*nr_spes)++;
45 }
46 }
47
48 return arm_spe_pmus;
49 }
50
51 struct auxtrace_record
auxtrace_record__init(struct perf_evlist * evlist,int * err)52 *auxtrace_record__init(struct perf_evlist *evlist, int *err)
53 {
54 struct perf_pmu *cs_etm_pmu;
55 struct perf_evsel *evsel;
56 bool found_etm = false;
57 bool found_spe = false;
58 static struct perf_pmu **arm_spe_pmus = NULL;
59 static int nr_spes = 0;
60 int i = 0;
61
62 if (!evlist)
63 return NULL;
64
65 cs_etm_pmu = perf_pmu__find(CORESIGHT_ETM_PMU_NAME);
66
67 if (!arm_spe_pmus)
68 arm_spe_pmus = find_all_arm_spe_pmus(&nr_spes, err);
69
70 evlist__for_each_entry(evlist, evsel) {
71 if (cs_etm_pmu &&
72 evsel->attr.type == cs_etm_pmu->type)
73 found_etm = true;
74
75 if (!nr_spes)
76 continue;
77
78 for (i = 0; i < nr_spes; i++) {
79 if (evsel->attr.type == arm_spe_pmus[i]->type) {
80 found_spe = true;
81 break;
82 }
83 }
84 }
85
86 if (found_etm && found_spe) {
87 pr_err("Concurrent ARM Coresight ETM and SPE operation not currently supported\n");
88 *err = -EOPNOTSUPP;
89 return NULL;
90 }
91
92 if (found_etm)
93 return cs_etm_record_init(err);
94
95 #if defined(__aarch64__)
96 if (found_spe)
97 return arm_spe_recording_init(err, arm_spe_pmus[i]);
98 #endif
99
100 /*
101 * Clear 'err' even if we haven't found an event - that way perf
102 * record can still be used even if tracers aren't present. The NULL
103 * return value will take care of telling the infrastructure HW tracing
104 * isn't available.
105 */
106 *err = 0;
107 return NULL;
108 }
109
