1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * tifm_sd.c - TI FlashMedia driver
4 *
5 * Copyright (C) 2006 Alex Dubov <oakad@yahoo.com>
6 *
7 * Special thanks to Brad Campbell for extensive testing of this driver.
8 */
9
10
11 #include <linux/tifm.h>
12 #include <linux/mmc/host.h>
13 #include <linux/highmem.h>
14 #include <linux/scatterlist.h>
15 #include <linux/module.h>
16 #include <asm/io.h>
17
18 #define DRIVER_NAME "tifm_sd"
19 #define DRIVER_VERSION "0.8"
20
21 static bool no_dma = 0;
22 static bool fixed_timeout = 0;
23 module_param(no_dma, bool, 0644);
24 module_param(fixed_timeout, bool, 0644);
25
26 /* Constants here are mostly from OMAP5912 datasheet */
27 #define TIFM_MMCSD_RESET 0x0002
28 #define TIFM_MMCSD_CLKMASK 0x03ff
29 #define TIFM_MMCSD_POWER 0x0800
30 #define TIFM_MMCSD_4BBUS 0x8000
31 #define TIFM_MMCSD_RXDE 0x8000 /* rx dma enable */
32 #define TIFM_MMCSD_TXDE 0x0080 /* tx dma enable */
33 #define TIFM_MMCSD_BUFINT 0x0c00 /* set bits: AE, AF */
34 #define TIFM_MMCSD_DPE 0x0020 /* data timeout counted in kilocycles */
35 #define TIFM_MMCSD_INAB 0x0080 /* abort / initialize command */
36 #define TIFM_MMCSD_READ 0x8000
37
38 #define TIFM_MMCSD_ERRMASK 0x01e0 /* set bits: CCRC, CTO, DCRC, DTO */
39 #define TIFM_MMCSD_EOC 0x0001 /* end of command phase */
40 #define TIFM_MMCSD_CD 0x0002 /* card detect */
41 #define TIFM_MMCSD_CB 0x0004 /* card enter busy state */
42 #define TIFM_MMCSD_BRS 0x0008 /* block received/sent */
43 #define TIFM_MMCSD_EOFB 0x0010 /* card exit busy state */
44 #define TIFM_MMCSD_DTO 0x0020 /* data time-out */
45 #define TIFM_MMCSD_DCRC 0x0040 /* data crc error */
46 #define TIFM_MMCSD_CTO 0x0080 /* command time-out */
47 #define TIFM_MMCSD_CCRC 0x0100 /* command crc error */
48 #define TIFM_MMCSD_AF 0x0400 /* fifo almost full */
49 #define TIFM_MMCSD_AE 0x0800 /* fifo almost empty */
50 #define TIFM_MMCSD_OCRB 0x1000 /* OCR busy */
51 #define TIFM_MMCSD_CIRQ 0x2000 /* card irq (cmd40/sdio) */
52 #define TIFM_MMCSD_CERR 0x4000 /* card status error */
53
54 #define TIFM_MMCSD_ODTO 0x0040 /* open drain / extended timeout */
55 #define TIFM_MMCSD_CARD_RO 0x0200 /* card is read-only */
56
57 #define TIFM_MMCSD_FIFO_SIZE 0x0020
58
59 #define TIFM_MMCSD_RSP_R0 0x0000
60 #define TIFM_MMCSD_RSP_R1 0x0100
61 #define TIFM_MMCSD_RSP_R2 0x0200
62 #define TIFM_MMCSD_RSP_R3 0x0300
63 #define TIFM_MMCSD_RSP_R4 0x0400
64 #define TIFM_MMCSD_RSP_R5 0x0500
65 #define TIFM_MMCSD_RSP_R6 0x0600
66
67 #define TIFM_MMCSD_RSP_BUSY 0x0800
68
69 #define TIFM_MMCSD_CMD_BC 0x0000
70 #define TIFM_MMCSD_CMD_BCR 0x1000
71 #define TIFM_MMCSD_CMD_AC 0x2000
72 #define TIFM_MMCSD_CMD_ADTC 0x3000
73
74 #define TIFM_MMCSD_MAX_BLOCK_SIZE 0x0800UL
75
76 enum {
77 CMD_READY = 0x0001,
78 FIFO_READY = 0x0002,
79 BRS_READY = 0x0004,
80 SCMD_ACTIVE = 0x0008,
81 SCMD_READY = 0x0010,
82 CARD_BUSY = 0x0020,
83 DATA_CARRY = 0x0040
84 };
85
86 struct tifm_sd {
87 struct tifm_dev *dev;
88
89 unsigned short eject:1,
90 open_drain:1,
91 no_dma:1;
92 unsigned short cmd_flags;
93
94 unsigned int clk_freq;
95 unsigned int clk_div;
96 unsigned long timeout_jiffies;
97
98 struct tasklet_struct finish_tasklet;
99 struct timer_list timer;
100 struct mmc_request *req;
101
102 int sg_len;
103 int sg_pos;
104 unsigned int block_pos;
105 struct scatterlist bounce_buf;
106 unsigned char bounce_buf_data[TIFM_MMCSD_MAX_BLOCK_SIZE];
107 };
108
109 /* for some reason, host won't respond correctly to readw/writew */
tifm_sd_read_fifo(struct tifm_sd * host,struct page * pg,unsigned int off,unsigned int cnt)110 static void tifm_sd_read_fifo(struct tifm_sd *host, struct page *pg,
111 unsigned int off, unsigned int cnt)
112 {
113 struct tifm_dev *sock = host->dev;
114 unsigned char *buf;
115 unsigned int pos = 0, val;
116
117 buf = kmap_atomic(pg) + off;
118 if (host->cmd_flags & DATA_CARRY) {
119 buf[pos++] = host->bounce_buf_data[0];
120 host->cmd_flags &= ~DATA_CARRY;
121 }
122
123 while (pos < cnt) {
124 val = readl(sock->addr + SOCK_MMCSD_DATA);
125 buf[pos++] = val & 0xff;
126 if (pos == cnt) {
127 host->bounce_buf_data[0] = (val >> 8) & 0xff;
128 host->cmd_flags |= DATA_CARRY;
129 break;
130 }
131 buf[pos++] = (val >> 8) & 0xff;
132 }
133 kunmap_atomic(buf - off);
134 }
135
tifm_sd_write_fifo(struct tifm_sd * host,struct page * pg,unsigned int off,unsigned int cnt)136 static void tifm_sd_write_fifo(struct tifm_sd *host, struct page *pg,
137 unsigned int off, unsigned int cnt)
138 {
139 struct tifm_dev *sock = host->dev;
140 unsigned char *buf;
141 unsigned int pos = 0, val;
142
143 buf = kmap_atomic(pg) + off;
144 if (host->cmd_flags & DATA_CARRY) {
145 val = host->bounce_buf_data[0] | ((buf[pos++] << 8) & 0xff00);
146 writel(val, sock->addr + SOCK_MMCSD_DATA);
147 host->cmd_flags &= ~DATA_CARRY;
148 }
149
150 while (pos < cnt) {
151 val = buf[pos++];
152 if (pos == cnt) {
153 host->bounce_buf_data[0] = val & 0xff;
154 host->cmd_flags |= DATA_CARRY;
155 break;
156 }
157 val |= (buf[pos++] << 8) & 0xff00;
158 writel(val, sock->addr + SOCK_MMCSD_DATA);
159 }
160 kunmap_atomic(buf - off);
161 }
162
tifm_sd_transfer_data(struct tifm_sd * host)163 static void tifm_sd_transfer_data(struct tifm_sd *host)
164 {
165 struct mmc_data *r_data = host->req->cmd->data;
166 struct scatterlist *sg = r_data->sg;
167 unsigned int off, cnt, t_size = TIFM_MMCSD_FIFO_SIZE * 2;
168 unsigned int p_off, p_cnt;
169 struct page *pg;
170
171 if (host->sg_pos == host->sg_len)
172 return;
173 while (t_size) {
174 cnt = sg[host->sg_pos].length - host->block_pos;
175 if (!cnt) {
176 host->block_pos = 0;
177 host->sg_pos++;
178 if (host->sg_pos == host->sg_len) {
179 if ((r_data->flags & MMC_DATA_WRITE)
180 && (host->cmd_flags & DATA_CARRY))
181 writel(host->bounce_buf_data[0],
182 host->dev->addr
183 + SOCK_MMCSD_DATA);
184
185 return;
186 }
187 cnt = sg[host->sg_pos].length;
188 }
189 off = sg[host->sg_pos].offset + host->block_pos;
190
191 pg = nth_page(sg_page(&sg[host->sg_pos]), off >> PAGE_SHIFT);
192 p_off = offset_in_page(off);
193 p_cnt = PAGE_SIZE - p_off;
194 p_cnt = min(p_cnt, cnt);
195 p_cnt = min(p_cnt, t_size);
196
197 if (r_data->flags & MMC_DATA_READ)
198 tifm_sd_read_fifo(host, pg, p_off, p_cnt);
199 else if (r_data->flags & MMC_DATA_WRITE)
200 tifm_sd_write_fifo(host, pg, p_off, p_cnt);
201
202 t_size -= p_cnt;
203 host->block_pos += p_cnt;
204 }
205 }
206
tifm_sd_copy_page(struct page * dst,unsigned int dst_off,struct page * src,unsigned int src_off,unsigned int count)207 static void tifm_sd_copy_page(struct page *dst, unsigned int dst_off,
208 struct page *src, unsigned int src_off,
209 unsigned int count)
210 {
211 unsigned char *src_buf = kmap_atomic(src) + src_off;
212 unsigned char *dst_buf = kmap_atomic(dst) + dst_off;
213
214 memcpy(dst_buf, src_buf, count);
215
216 kunmap_atomic(dst_buf - dst_off);
217 kunmap_atomic(src_buf - src_off);
218 }
219
tifm_sd_bounce_block(struct tifm_sd * host,struct mmc_data * r_data)220 static void tifm_sd_bounce_block(struct tifm_sd *host, struct mmc_data *r_data)
221 {
222 struct scatterlist *sg = r_data->sg;
223 unsigned int t_size = r_data->blksz;
224 unsigned int off, cnt;
225 unsigned int p_off, p_cnt;
226 struct page *pg;
227
228 dev_dbg(&host->dev->dev, "bouncing block\n");
229 while (t_size) {
230 cnt = sg[host->sg_pos].length - host->block_pos;
231 if (!cnt) {
232 host->block_pos = 0;
233 host->sg_pos++;
234 if (host->sg_pos == host->sg_len)
235 return;
236 cnt = sg[host->sg_pos].length;
237 }
238 off = sg[host->sg_pos].offset + host->block_pos;
239
240 pg = nth_page(sg_page(&sg[host->sg_pos]), off >> PAGE_SHIFT);
241 p_off = offset_in_page(off);
242 p_cnt = PAGE_SIZE - p_off;
243 p_cnt = min(p_cnt, cnt);
244 p_cnt = min(p_cnt, t_size);
245
246 if (r_data->flags & MMC_DATA_WRITE)
247 tifm_sd_copy_page(sg_page(&host->bounce_buf),
248 r_data->blksz - t_size,
249 pg, p_off, p_cnt);
250 else if (r_data->flags & MMC_DATA_READ)
251 tifm_sd_copy_page(pg, p_off, sg_page(&host->bounce_buf),
252 r_data->blksz - t_size, p_cnt);
253
254 t_size -= p_cnt;
255 host->block_pos += p_cnt;
256 }
257 }
258
tifm_sd_set_dma_data(struct tifm_sd * host,struct mmc_data * r_data)259 static int tifm_sd_set_dma_data(struct tifm_sd *host, struct mmc_data *r_data)
260 {
261 struct tifm_dev *sock = host->dev;
262 unsigned int t_size = TIFM_DMA_TSIZE * r_data->blksz;
263 unsigned int dma_len, dma_blk_cnt, dma_off;
264 struct scatterlist *sg = NULL;
265 unsigned long flags;
266
267 if (host->sg_pos == host->sg_len)
268 return 1;
269
270 if (host->cmd_flags & DATA_CARRY) {
271 host->cmd_flags &= ~DATA_CARRY;
272 local_irq_save(flags);
273 tifm_sd_bounce_block(host, r_data);
274 local_irq_restore(flags);
275 if (host->sg_pos == host->sg_len)
276 return 1;
277 }
278
279 dma_len = sg_dma_len(&r_data->sg[host->sg_pos]) - host->block_pos;
280 if (!dma_len) {
281 host->block_pos = 0;
282 host->sg_pos++;
283 if (host->sg_pos == host->sg_len)
284 return 1;
285 dma_len = sg_dma_len(&r_data->sg[host->sg_pos]);
286 }
287
288 if (dma_len < t_size) {
289 dma_blk_cnt = dma_len / r_data->blksz;
290 dma_off = host->block_pos;
291 host->block_pos += dma_blk_cnt * r_data->blksz;
292 } else {
293 dma_blk_cnt = TIFM_DMA_TSIZE;
294 dma_off = host->block_pos;
295 host->block_pos += t_size;
296 }
297
298 if (dma_blk_cnt)
299 sg = &r_data->sg[host->sg_pos];
300 else if (dma_len) {
301 if (r_data->flags & MMC_DATA_WRITE) {
302 local_irq_save(flags);
303 tifm_sd_bounce_block(host, r_data);
304 local_irq_restore(flags);
305 } else
306 host->cmd_flags |= DATA_CARRY;
307
308 sg = &host->bounce_buf;
309 dma_off = 0;
310 dma_blk_cnt = 1;
311 } else
312 return 1;
313
314 dev_dbg(&sock->dev, "setting dma for %d blocks\n", dma_blk_cnt);
315 writel(sg_dma_address(sg) + dma_off, sock->addr + SOCK_DMA_ADDRESS);
316 if (r_data->flags & MMC_DATA_WRITE)
317 writel((dma_blk_cnt << 8) | TIFM_DMA_TX | TIFM_DMA_EN,
318 sock->addr + SOCK_DMA_CONTROL);
319 else
320 writel((dma_blk_cnt << 8) | TIFM_DMA_EN,
321 sock->addr + SOCK_DMA_CONTROL);
322
323 return 0;
324 }
325
tifm_sd_op_flags(struct mmc_command * cmd)326 static unsigned int tifm_sd_op_flags(struct mmc_command *cmd)
327 {
328 unsigned int rc = 0;
329
330 switch (mmc_resp_type(cmd)) {
331 case MMC_RSP_NONE:
332 rc |= TIFM_MMCSD_RSP_R0;
333 break;
334 case MMC_RSP_R1B:
335 rc |= TIFM_MMCSD_RSP_BUSY;
336 /* fall-through */
337 case MMC_RSP_R1:
338 rc |= TIFM_MMCSD_RSP_R1;
339 break;
340 case MMC_RSP_R2:
341 rc |= TIFM_MMCSD_RSP_R2;
342 break;
343 case MMC_RSP_R3:
344 rc |= TIFM_MMCSD_RSP_R3;
345 break;
346 default:
347 BUG();
348 }
349
350 switch (mmc_cmd_type(cmd)) {
351 case MMC_CMD_BC:
352 rc |= TIFM_MMCSD_CMD_BC;
353 break;
354 case MMC_CMD_BCR:
355 rc |= TIFM_MMCSD_CMD_BCR;
356 break;
357 case MMC_CMD_AC:
358 rc |= TIFM_MMCSD_CMD_AC;
359 break;
360 case MMC_CMD_ADTC:
361 rc |= TIFM_MMCSD_CMD_ADTC;
362 break;
363 default:
364 BUG();
365 }
366 return rc;
367 }
368
tifm_sd_exec(struct tifm_sd * host,struct mmc_command * cmd)369 static void tifm_sd_exec(struct tifm_sd *host, struct mmc_command *cmd)
370 {
371 struct tifm_dev *sock = host->dev;
372 unsigned int cmd_mask = tifm_sd_op_flags(cmd);
373
374 if (host->open_drain)
375 cmd_mask |= TIFM_MMCSD_ODTO;
376
377 if (cmd->data && (cmd->data->flags & MMC_DATA_READ))
378 cmd_mask |= TIFM_MMCSD_READ;
379
380 dev_dbg(&sock->dev, "executing opcode 0x%x, arg: 0x%x, mask: 0x%x\n",
381 cmd->opcode, cmd->arg, cmd_mask);
382
383 writel((cmd->arg >> 16) & 0xffff, sock->addr + SOCK_MMCSD_ARG_HIGH);
384 writel(cmd->arg & 0xffff, sock->addr + SOCK_MMCSD_ARG_LOW);
385 writel(cmd->opcode | cmd_mask, sock->addr + SOCK_MMCSD_COMMAND);
386 }
387
tifm_sd_fetch_resp(struct mmc_command * cmd,struct tifm_dev * sock)388 static void tifm_sd_fetch_resp(struct mmc_command *cmd, struct tifm_dev *sock)
389 {
390 cmd->resp[0] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x1c) << 16)
391 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x18);
392 cmd->resp[1] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x14) << 16)
393 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x10);
394 cmd->resp[2] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x0c) << 16)
395 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x08);
396 cmd->resp[3] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x04) << 16)
397 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x00);
398 }
399
tifm_sd_check_status(struct tifm_sd * host)400 static void tifm_sd_check_status(struct tifm_sd *host)
401 {
402 struct tifm_dev *sock = host->dev;
403 struct mmc_command *cmd = host->req->cmd;
404
405 if (cmd->error)
406 goto finish_request;
407
408 if (!(host->cmd_flags & CMD_READY))
409 return;
410
411 if (cmd->data) {
412 if (cmd->data->error) {
413 if ((host->cmd_flags & SCMD_ACTIVE)
414 && !(host->cmd_flags & SCMD_READY))
415 return;
416
417 goto finish_request;
418 }
419
420 if (!(host->cmd_flags & BRS_READY))
421 return;
422
423 if (!(host->no_dma || (host->cmd_flags & FIFO_READY)))
424 return;
425
426 if (cmd->data->flags & MMC_DATA_WRITE) {
427 if (host->req->stop) {
428 if (!(host->cmd_flags & SCMD_ACTIVE)) {
429 host->cmd_flags |= SCMD_ACTIVE;
430 writel(TIFM_MMCSD_EOFB
431 | readl(sock->addr
432 + SOCK_MMCSD_INT_ENABLE),
433 sock->addr
434 + SOCK_MMCSD_INT_ENABLE);
435 tifm_sd_exec(host, host->req->stop);
436 return;
437 } else {
438 if (!(host->cmd_flags & SCMD_READY)
439 || (host->cmd_flags & CARD_BUSY))
440 return;
441 writel((~TIFM_MMCSD_EOFB)
442 & readl(sock->addr
443 + SOCK_MMCSD_INT_ENABLE),
444 sock->addr
445 + SOCK_MMCSD_INT_ENABLE);
446 }
447 } else {
448 if (host->cmd_flags & CARD_BUSY)
449 return;
450 writel((~TIFM_MMCSD_EOFB)
451 & readl(sock->addr
452 + SOCK_MMCSD_INT_ENABLE),
453 sock->addr + SOCK_MMCSD_INT_ENABLE);
454 }
455 } else {
456 if (host->req->stop) {
457 if (!(host->cmd_flags & SCMD_ACTIVE)) {
458 host->cmd_flags |= SCMD_ACTIVE;
459 tifm_sd_exec(host, host->req->stop);
460 return;
461 } else {
462 if (!(host->cmd_flags & SCMD_READY))
463 return;
464 }
465 }
466 }
467 }
468 finish_request:
469 tasklet_schedule(&host->finish_tasklet);
470 }
471
472 /* Called from interrupt handler */
tifm_sd_data_event(struct tifm_dev * sock)473 static void tifm_sd_data_event(struct tifm_dev *sock)
474 {
475 struct tifm_sd *host;
476 unsigned int fifo_status = 0;
477 struct mmc_data *r_data = NULL;
478
479 spin_lock(&sock->lock);
480 host = mmc_priv((struct mmc_host*)tifm_get_drvdata(sock));
481 fifo_status = readl(sock->addr + SOCK_DMA_FIFO_STATUS);
482 dev_dbg(&sock->dev, "data event: fifo_status %x, flags %x\n",
483 fifo_status, host->cmd_flags);
484
485 if (host->req) {
486 r_data = host->req->cmd->data;
487
488 if (r_data && (fifo_status & TIFM_FIFO_READY)) {
489 if (tifm_sd_set_dma_data(host, r_data)) {
490 host->cmd_flags |= FIFO_READY;
491 tifm_sd_check_status(host);
492 }
493 }
494 }
495
496 writel(fifo_status, sock->addr + SOCK_DMA_FIFO_STATUS);
497 spin_unlock(&sock->lock);
498 }
499
500 /* Called from interrupt handler */
tifm_sd_card_event(struct tifm_dev * sock)501 static void tifm_sd_card_event(struct tifm_dev *sock)
502 {
503 struct tifm_sd *host;
504 unsigned int host_status = 0;
505 int cmd_error = 0;
506 struct mmc_command *cmd = NULL;
507 unsigned long flags;
508
509 spin_lock(&sock->lock);
510 host = mmc_priv((struct mmc_host*)tifm_get_drvdata(sock));
511 host_status = readl(sock->addr + SOCK_MMCSD_STATUS);
512 dev_dbg(&sock->dev, "host event: host_status %x, flags %x\n",
513 host_status, host->cmd_flags);
514
515 if (host->req) {
516 cmd = host->req->cmd;
517
518 if (host_status & TIFM_MMCSD_ERRMASK) {
519 writel(host_status & TIFM_MMCSD_ERRMASK,
520 sock->addr + SOCK_MMCSD_STATUS);
521 if (host_status & TIFM_MMCSD_CTO)
522 cmd_error = -ETIMEDOUT;
523 else if (host_status & TIFM_MMCSD_CCRC)
524 cmd_error = -EILSEQ;
525
526 if (cmd->data) {
527 if (host_status & TIFM_MMCSD_DTO)
528 cmd->data->error = -ETIMEDOUT;
529 else if (host_status & TIFM_MMCSD_DCRC)
530 cmd->data->error = -EILSEQ;
531 }
532
533 writel(TIFM_FIFO_INT_SETALL,
534 sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
535 writel(TIFM_DMA_RESET, sock->addr + SOCK_DMA_CONTROL);
536
537 if (host->req->stop) {
538 if (host->cmd_flags & SCMD_ACTIVE) {
539 host->req->stop->error = cmd_error;
540 host->cmd_flags |= SCMD_READY;
541 } else {
542 cmd->error = cmd_error;
543 host->cmd_flags |= SCMD_ACTIVE;
544 tifm_sd_exec(host, host->req->stop);
545 goto done;
546 }
547 } else
548 cmd->error = cmd_error;
549 } else {
550 if (host_status & (TIFM_MMCSD_EOC | TIFM_MMCSD_CERR)) {
551 if (!(host->cmd_flags & CMD_READY)) {
552 host->cmd_flags |= CMD_READY;
553 tifm_sd_fetch_resp(cmd, sock);
554 } else if (host->cmd_flags & SCMD_ACTIVE) {
555 host->cmd_flags |= SCMD_READY;
556 tifm_sd_fetch_resp(host->req->stop,
557 sock);
558 }
559 }
560 if (host_status & TIFM_MMCSD_BRS)
561 host->cmd_flags |= BRS_READY;
562 }
563
564 if (host->no_dma && cmd->data) {
565 if (host_status & TIFM_MMCSD_AE)
566 writel(host_status & TIFM_MMCSD_AE,
567 sock->addr + SOCK_MMCSD_STATUS);
568
569 if (host_status & (TIFM_MMCSD_AE | TIFM_MMCSD_AF
570 | TIFM_MMCSD_BRS)) {
571 local_irq_save(flags);
572 tifm_sd_transfer_data(host);
573 local_irq_restore(flags);
574 host_status &= ~TIFM_MMCSD_AE;
575 }
576 }
577
578 if (host_status & TIFM_MMCSD_EOFB)
579 host->cmd_flags &= ~CARD_BUSY;
580 else if (host_status & TIFM_MMCSD_CB)
581 host->cmd_flags |= CARD_BUSY;
582
583 tifm_sd_check_status(host);
584 }
585 done:
586 writel(host_status, sock->addr + SOCK_MMCSD_STATUS);
587 spin_unlock(&sock->lock);
588 }
589
tifm_sd_set_data_timeout(struct tifm_sd * host,struct mmc_data * data)590 static void tifm_sd_set_data_timeout(struct tifm_sd *host,
591 struct mmc_data *data)
592 {
593 struct tifm_dev *sock = host->dev;
594 unsigned int data_timeout = data->timeout_clks;
595
596 if (fixed_timeout)
597 return;
598
599 data_timeout += data->timeout_ns /
600 ((1000000000UL / host->clk_freq) * host->clk_div);
601
602 if (data_timeout < 0xffff) {
603 writel(data_timeout, sock->addr + SOCK_MMCSD_DATA_TO);
604 writel((~TIFM_MMCSD_DPE)
605 & readl(sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG),
606 sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG);
607 } else {
608 data_timeout = (data_timeout >> 10) + 1;
609 if (data_timeout > 0xffff)
610 data_timeout = 0; /* set to unlimited */
611 writel(data_timeout, sock->addr + SOCK_MMCSD_DATA_TO);
612 writel(TIFM_MMCSD_DPE
613 | readl(sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG),
614 sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG);
615 }
616 }
617
tifm_sd_request(struct mmc_host * mmc,struct mmc_request * mrq)618 static void tifm_sd_request(struct mmc_host *mmc, struct mmc_request *mrq)
619 {
620 struct tifm_sd *host = mmc_priv(mmc);
621 struct tifm_dev *sock = host->dev;
622 unsigned long flags;
623 struct mmc_data *r_data = mrq->cmd->data;
624
625 spin_lock_irqsave(&sock->lock, flags);
626 if (host->eject) {
627 mrq->cmd->error = -ENOMEDIUM;
628 goto err_out;
629 }
630
631 if (host->req) {
632 pr_err("%s : unfinished request detected\n",
633 dev_name(&sock->dev));
634 mrq->cmd->error = -ETIMEDOUT;
635 goto err_out;
636 }
637
638 host->cmd_flags = 0;
639 host->block_pos = 0;
640 host->sg_pos = 0;
641
642 if (mrq->data && !is_power_of_2(mrq->data->blksz))
643 host->no_dma = 1;
644 else
645 host->no_dma = no_dma ? 1 : 0;
646
647 if (r_data) {
648 tifm_sd_set_data_timeout(host, r_data);
649
650 if ((r_data->flags & MMC_DATA_WRITE) && !mrq->stop)
651 writel(TIFM_MMCSD_EOFB
652 | readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
653 sock->addr + SOCK_MMCSD_INT_ENABLE);
654
655 if (host->no_dma) {
656 writel(TIFM_MMCSD_BUFINT
657 | readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
658 sock->addr + SOCK_MMCSD_INT_ENABLE);
659 writel(((TIFM_MMCSD_FIFO_SIZE - 1) << 8)
660 | (TIFM_MMCSD_FIFO_SIZE - 1),
661 sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
662
663 host->sg_len = r_data->sg_len;
664 } else {
665 sg_init_one(&host->bounce_buf, host->bounce_buf_data,
666 r_data->blksz);
667
668 if(1 != tifm_map_sg(sock, &host->bounce_buf, 1,
669 r_data->flags & MMC_DATA_WRITE
670 ? PCI_DMA_TODEVICE
671 : PCI_DMA_FROMDEVICE)) {
672 pr_err("%s : scatterlist map failed\n",
673 dev_name(&sock->dev));
674 mrq->cmd->error = -ENOMEM;
675 goto err_out;
676 }
677 host->sg_len = tifm_map_sg(sock, r_data->sg,
678 r_data->sg_len,
679 r_data->flags
680 & MMC_DATA_WRITE
681 ? PCI_DMA_TODEVICE
682 : PCI_DMA_FROMDEVICE);
683 if (host->sg_len < 1) {
684 pr_err("%s : scatterlist map failed\n",
685 dev_name(&sock->dev));
686 tifm_unmap_sg(sock, &host->bounce_buf, 1,
687 r_data->flags & MMC_DATA_WRITE
688 ? PCI_DMA_TODEVICE
689 : PCI_DMA_FROMDEVICE);
690 mrq->cmd->error = -ENOMEM;
691 goto err_out;
692 }
693
694 writel(TIFM_FIFO_INT_SETALL,
695 sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
696 writel(ilog2(r_data->blksz) - 2,
697 sock->addr + SOCK_FIFO_PAGE_SIZE);
698 writel(TIFM_FIFO_ENABLE,
699 sock->addr + SOCK_FIFO_CONTROL);
700 writel(TIFM_FIFO_INTMASK,
701 sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
702
703 if (r_data->flags & MMC_DATA_WRITE)
704 writel(TIFM_MMCSD_TXDE,
705 sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
706 else
707 writel(TIFM_MMCSD_RXDE,
708 sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
709
710 tifm_sd_set_dma_data(host, r_data);
711 }
712
713 writel(r_data->blocks - 1,
714 sock->addr + SOCK_MMCSD_NUM_BLOCKS);
715 writel(r_data->blksz - 1,
716 sock->addr + SOCK_MMCSD_BLOCK_LEN);
717 }
718
719 host->req = mrq;
720 mod_timer(&host->timer, jiffies + host->timeout_jiffies);
721 writel(TIFM_CTRL_LED | readl(sock->addr + SOCK_CONTROL),
722 sock->addr + SOCK_CONTROL);
723 tifm_sd_exec(host, mrq->cmd);
724 spin_unlock_irqrestore(&sock->lock, flags);
725 return;
726
727 err_out:
728 spin_unlock_irqrestore(&sock->lock, flags);
729 mmc_request_done(mmc, mrq);
730 }
731
tifm_sd_end_cmd(unsigned long data)732 static void tifm_sd_end_cmd(unsigned long data)
733 {
734 struct tifm_sd *host = (struct tifm_sd*)data;
735 struct tifm_dev *sock = host->dev;
736 struct mmc_host *mmc = tifm_get_drvdata(sock);
737 struct mmc_request *mrq;
738 struct mmc_data *r_data = NULL;
739 unsigned long flags;
740
741 spin_lock_irqsave(&sock->lock, flags);
742
743 del_timer(&host->timer);
744 mrq = host->req;
745 host->req = NULL;
746
747 if (!mrq) {
748 pr_err(" %s : no request to complete?\n",
749 dev_name(&sock->dev));
750 spin_unlock_irqrestore(&sock->lock, flags);
751 return;
752 }
753
754 r_data = mrq->cmd->data;
755 if (r_data) {
756 if (host->no_dma) {
757 writel((~TIFM_MMCSD_BUFINT)
758 & readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
759 sock->addr + SOCK_MMCSD_INT_ENABLE);
760 } else {
761 tifm_unmap_sg(sock, &host->bounce_buf, 1,
762 (r_data->flags & MMC_DATA_WRITE)
763 ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
764 tifm_unmap_sg(sock, r_data->sg, r_data->sg_len,
765 (r_data->flags & MMC_DATA_WRITE)
766 ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
767 }
768
769 r_data->bytes_xfered = r_data->blocks
770 - readl(sock->addr + SOCK_MMCSD_NUM_BLOCKS) - 1;
771 r_data->bytes_xfered *= r_data->blksz;
772 r_data->bytes_xfered += r_data->blksz
773 - readl(sock->addr + SOCK_MMCSD_BLOCK_LEN) + 1;
774 }
775
776 writel((~TIFM_CTRL_LED) & readl(sock->addr + SOCK_CONTROL),
777 sock->addr + SOCK_CONTROL);
778
779 spin_unlock_irqrestore(&sock->lock, flags);
780 mmc_request_done(mmc, mrq);
781 }
782
tifm_sd_abort(struct timer_list * t)783 static void tifm_sd_abort(struct timer_list *t)
784 {
785 struct tifm_sd *host = from_timer(host, t, timer);
786
787 pr_err("%s : card failed to respond for a long period of time "
788 "(%x, %x)\n",
789 dev_name(&host->dev->dev), host->req->cmd->opcode, host->cmd_flags);
790
791 tifm_eject(host->dev);
792 }
793
tifm_sd_ios(struct mmc_host * mmc,struct mmc_ios * ios)794 static void tifm_sd_ios(struct mmc_host *mmc, struct mmc_ios *ios)
795 {
796 struct tifm_sd *host = mmc_priv(mmc);
797 struct tifm_dev *sock = host->dev;
798 unsigned int clk_div1, clk_div2;
799 unsigned long flags;
800
801 spin_lock_irqsave(&sock->lock, flags);
802
803 dev_dbg(&sock->dev, "ios: clock = %u, vdd = %x, bus_mode = %x, "
804 "chip_select = %x, power_mode = %x, bus_width = %x\n",
805 ios->clock, ios->vdd, ios->bus_mode, ios->chip_select,
806 ios->power_mode, ios->bus_width);
807
808 if (ios->bus_width == MMC_BUS_WIDTH_4) {
809 writel(TIFM_MMCSD_4BBUS | readl(sock->addr + SOCK_MMCSD_CONFIG),
810 sock->addr + SOCK_MMCSD_CONFIG);
811 } else {
812 writel((~TIFM_MMCSD_4BBUS)
813 & readl(sock->addr + SOCK_MMCSD_CONFIG),
814 sock->addr + SOCK_MMCSD_CONFIG);
815 }
816
817 if (ios->clock) {
818 clk_div1 = 20000000 / ios->clock;
819 if (!clk_div1)
820 clk_div1 = 1;
821
822 clk_div2 = 24000000 / ios->clock;
823 if (!clk_div2)
824 clk_div2 = 1;
825
826 if ((20000000 / clk_div1) > ios->clock)
827 clk_div1++;
828 if ((24000000 / clk_div2) > ios->clock)
829 clk_div2++;
830 if ((20000000 / clk_div1) > (24000000 / clk_div2)) {
831 host->clk_freq = 20000000;
832 host->clk_div = clk_div1;
833 writel((~TIFM_CTRL_FAST_CLK)
834 & readl(sock->addr + SOCK_CONTROL),
835 sock->addr + SOCK_CONTROL);
836 } else {
837 host->clk_freq = 24000000;
838 host->clk_div = clk_div2;
839 writel(TIFM_CTRL_FAST_CLK
840 | readl(sock->addr + SOCK_CONTROL),
841 sock->addr + SOCK_CONTROL);
842 }
843 } else {
844 host->clk_div = 0;
845 }
846 host->clk_div &= TIFM_MMCSD_CLKMASK;
847 writel(host->clk_div
848 | ((~TIFM_MMCSD_CLKMASK)
849 & readl(sock->addr + SOCK_MMCSD_CONFIG)),
850 sock->addr + SOCK_MMCSD_CONFIG);
851
852 host->open_drain = (ios->bus_mode == MMC_BUSMODE_OPENDRAIN);
853
854 /* chip_select : maybe later */
855 //vdd
856 //power is set before probe / after remove
857
858 spin_unlock_irqrestore(&sock->lock, flags);
859 }
860
tifm_sd_ro(struct mmc_host * mmc)861 static int tifm_sd_ro(struct mmc_host *mmc)
862 {
863 int rc = 0;
864 struct tifm_sd *host = mmc_priv(mmc);
865 struct tifm_dev *sock = host->dev;
866 unsigned long flags;
867
868 spin_lock_irqsave(&sock->lock, flags);
869 if (TIFM_MMCSD_CARD_RO & readl(sock->addr + SOCK_PRESENT_STATE))
870 rc = 1;
871 spin_unlock_irqrestore(&sock->lock, flags);
872 return rc;
873 }
874
875 static const struct mmc_host_ops tifm_sd_ops = {
876 .request = tifm_sd_request,
877 .set_ios = tifm_sd_ios,
878 .get_ro = tifm_sd_ro
879 };
880
tifm_sd_initialize_host(struct tifm_sd * host)881 static int tifm_sd_initialize_host(struct tifm_sd *host)
882 {
883 int rc;
884 unsigned int host_status = 0;
885 struct tifm_dev *sock = host->dev;
886
887 writel(0, sock->addr + SOCK_MMCSD_INT_ENABLE);
888 host->clk_div = 61;
889 host->clk_freq = 20000000;
890 writel(TIFM_MMCSD_RESET, sock->addr + SOCK_MMCSD_SYSTEM_CONTROL);
891 writel(host->clk_div | TIFM_MMCSD_POWER,
892 sock->addr + SOCK_MMCSD_CONFIG);
893
894 /* wait up to 0.51 sec for reset */
895 for (rc = 32; rc <= 256; rc <<= 1) {
896 if (1 & readl(sock->addr + SOCK_MMCSD_SYSTEM_STATUS)) {
897 rc = 0;
898 break;
899 }
900 msleep(rc);
901 }
902
903 if (rc) {
904 pr_err("%s : controller failed to reset\n",
905 dev_name(&sock->dev));
906 return -ENODEV;
907 }
908
909 writel(0, sock->addr + SOCK_MMCSD_NUM_BLOCKS);
910 writel(host->clk_div | TIFM_MMCSD_POWER,
911 sock->addr + SOCK_MMCSD_CONFIG);
912 writel(TIFM_MMCSD_RXDE, sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
913
914 // command timeout fixed to 64 clocks for now
915 writel(64, sock->addr + SOCK_MMCSD_COMMAND_TO);
916 writel(TIFM_MMCSD_INAB, sock->addr + SOCK_MMCSD_COMMAND);
917
918 for (rc = 16; rc <= 64; rc <<= 1) {
919 host_status = readl(sock->addr + SOCK_MMCSD_STATUS);
920 writel(host_status, sock->addr + SOCK_MMCSD_STATUS);
921 if (!(host_status & TIFM_MMCSD_ERRMASK)
922 && (host_status & TIFM_MMCSD_EOC)) {
923 rc = 0;
924 break;
925 }
926 msleep(rc);
927 }
928
929 if (rc) {
930 pr_err("%s : card not ready - probe failed on initialization\n",
931 dev_name(&sock->dev));
932 return -ENODEV;
933 }
934
935 writel(TIFM_MMCSD_CERR | TIFM_MMCSD_BRS | TIFM_MMCSD_EOC
936 | TIFM_MMCSD_ERRMASK,
937 sock->addr + SOCK_MMCSD_INT_ENABLE);
938
939 return 0;
940 }
941
tifm_sd_probe(struct tifm_dev * sock)942 static int tifm_sd_probe(struct tifm_dev *sock)
943 {
944 struct mmc_host *mmc;
945 struct tifm_sd *host;
946 int rc = -EIO;
947
948 if (!(TIFM_SOCK_STATE_OCCUPIED
949 & readl(sock->addr + SOCK_PRESENT_STATE))) {
950 pr_warn("%s : card gone, unexpectedly\n",
951 dev_name(&sock->dev));
952 return rc;
953 }
954
955 mmc = mmc_alloc_host(sizeof(struct tifm_sd), &sock->dev);
956 if (!mmc)
957 return -ENOMEM;
958
959 host = mmc_priv(mmc);
960 tifm_set_drvdata(sock, mmc);
961 host->dev = sock;
962 host->timeout_jiffies = msecs_to_jiffies(1000);
963
964 tasklet_init(&host->finish_tasklet, tifm_sd_end_cmd,
965 (unsigned long)host);
966 timer_setup(&host->timer, tifm_sd_abort, 0);
967
968 mmc->ops = &tifm_sd_ops;
969 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
970 mmc->caps = MMC_CAP_4_BIT_DATA;
971 mmc->f_min = 20000000 / 60;
972 mmc->f_max = 24000000;
973
974 mmc->max_blk_count = 2048;
975 mmc->max_segs = mmc->max_blk_count;
976 mmc->max_blk_size = min(TIFM_MMCSD_MAX_BLOCK_SIZE, PAGE_SIZE);
977 mmc->max_seg_size = mmc->max_blk_count * mmc->max_blk_size;
978 mmc->max_req_size = mmc->max_seg_size;
979
980 sock->card_event = tifm_sd_card_event;
981 sock->data_event = tifm_sd_data_event;
982 rc = tifm_sd_initialize_host(host);
983
984 if (!rc)
985 rc = mmc_add_host(mmc);
986 if (!rc)
987 return 0;
988
989 mmc_free_host(mmc);
990 return rc;
991 }
992
tifm_sd_remove(struct tifm_dev * sock)993 static void tifm_sd_remove(struct tifm_dev *sock)
994 {
995 struct mmc_host *mmc = tifm_get_drvdata(sock);
996 struct tifm_sd *host = mmc_priv(mmc);
997 unsigned long flags;
998
999 spin_lock_irqsave(&sock->lock, flags);
1000 host->eject = 1;
1001 writel(0, sock->addr + SOCK_MMCSD_INT_ENABLE);
1002 spin_unlock_irqrestore(&sock->lock, flags);
1003
1004 tasklet_kill(&host->finish_tasklet);
1005
1006 spin_lock_irqsave(&sock->lock, flags);
1007 if (host->req) {
1008 writel(TIFM_FIFO_INT_SETALL,
1009 sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
1010 writel(0, sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
1011 host->req->cmd->error = -ENOMEDIUM;
1012 if (host->req->stop)
1013 host->req->stop->error = -ENOMEDIUM;
1014 tasklet_schedule(&host->finish_tasklet);
1015 }
1016 spin_unlock_irqrestore(&sock->lock, flags);
1017 mmc_remove_host(mmc);
1018 dev_dbg(&sock->dev, "after remove\n");
1019
1020 mmc_free_host(mmc);
1021 }
1022
1023 #ifdef CONFIG_PM
1024
tifm_sd_suspend(struct tifm_dev * sock,pm_message_t state)1025 static int tifm_sd_suspend(struct tifm_dev *sock, pm_message_t state)
1026 {
1027 return 0;
1028 }
1029
tifm_sd_resume(struct tifm_dev * sock)1030 static int tifm_sd_resume(struct tifm_dev *sock)
1031 {
1032 struct mmc_host *mmc = tifm_get_drvdata(sock);
1033 struct tifm_sd *host = mmc_priv(mmc);
1034 int rc;
1035
1036 rc = tifm_sd_initialize_host(host);
1037 dev_dbg(&sock->dev, "resume initialize %d\n", rc);
1038
1039 if (rc)
1040 host->eject = 1;
1041
1042 return rc;
1043 }
1044
1045 #else
1046
1047 #define tifm_sd_suspend NULL
1048 #define tifm_sd_resume NULL
1049
1050 #endif /* CONFIG_PM */
1051
1052 static struct tifm_device_id tifm_sd_id_tbl[] = {
1053 { TIFM_TYPE_SD }, { }
1054 };
1055
1056 static struct tifm_driver tifm_sd_driver = {
1057 .driver = {
1058 .name = DRIVER_NAME,
1059 .owner = THIS_MODULE
1060 },
1061 .id_table = tifm_sd_id_tbl,
1062 .probe = tifm_sd_probe,
1063 .remove = tifm_sd_remove,
1064 .suspend = tifm_sd_suspend,
1065 .resume = tifm_sd_resume
1066 };
1067
tifm_sd_init(void)1068 static int __init tifm_sd_init(void)
1069 {
1070 return tifm_register_driver(&tifm_sd_driver);
1071 }
1072
tifm_sd_exit(void)1073 static void __exit tifm_sd_exit(void)
1074 {
1075 tifm_unregister_driver(&tifm_sd_driver);
1076 }
1077
1078 MODULE_AUTHOR("Alex Dubov");
1079 MODULE_DESCRIPTION("TI FlashMedia SD driver");
1080 MODULE_LICENSE("GPL");
1081 MODULE_DEVICE_TABLE(tifm, tifm_sd_id_tbl);
1082 MODULE_VERSION(DRIVER_VERSION);
1083
1084 module_init(tifm_sd_init);
1085 module_exit(tifm_sd_exit);
1086
