1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra30-car.h> 3#include <dt-bindings/gpio/tegra-gpio.h> 4#include <dt-bindings/memory/tegra30-mc.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra.h> 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7 8/ { 9 compatible = "nvidia,tegra30"; 10 interrupt-parent = <&lic>; 11 #address-cells = <1>; 12 #size-cells = <1>; 13 14 memory@80000000 { 15 device_type = "memory"; 16 reg = <0x80000000 0x0>; 17 }; 18 19 pcie@3000 { 20 compatible = "nvidia,tegra30-pcie"; 21 device_type = "pci"; 22 reg = <0x00003000 0x00000800 /* PADS registers */ 23 0x00003800 0x00000200 /* AFI registers */ 24 0x10000000 0x10000000>; /* configuration space */ 25 reg-names = "pads", "afi", "cs"; 26 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */ 27 GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 28 interrupt-names = "intr", "msi"; 29 30 #interrupt-cells = <1>; 31 interrupt-map-mask = <0 0 0 0>; 32 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 33 34 bus-range = <0x00 0xff>; 35 #address-cells = <3>; 36 #size-cells = <2>; 37 38 ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */ 39 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */ 40 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */ 41 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */ 42 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */ 43 0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */ 44 45 clocks = <&tegra_car TEGRA30_CLK_PCIE>, 46 <&tegra_car TEGRA30_CLK_AFI>, 47 <&tegra_car TEGRA30_CLK_PLL_E>, 48 <&tegra_car TEGRA30_CLK_CML0>; 49 clock-names = "pex", "afi", "pll_e", "cml"; 50 resets = <&tegra_car 70>, 51 <&tegra_car 72>, 52 <&tegra_car 74>; 53 reset-names = "pex", "afi", "pcie_x"; 54 status = "disabled"; 55 56 pci@1,0 { 57 device_type = "pci"; 58 assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>; 59 reg = <0x000800 0 0 0 0>; 60 bus-range = <0x00 0xff>; 61 status = "disabled"; 62 63 #address-cells = <3>; 64 #size-cells = <2>; 65 ranges; 66 67 nvidia,num-lanes = <2>; 68 }; 69 70 pci@2,0 { 71 device_type = "pci"; 72 assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>; 73 reg = <0x001000 0 0 0 0>; 74 bus-range = <0x00 0xff>; 75 status = "disabled"; 76 77 #address-cells = <3>; 78 #size-cells = <2>; 79 ranges; 80 81 nvidia,num-lanes = <2>; 82 }; 83 84 pci@3,0 { 85 device_type = "pci"; 86 assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>; 87 reg = <0x001800 0 0 0 0>; 88 bus-range = <0x00 0xff>; 89 status = "disabled"; 90 91 #address-cells = <3>; 92 #size-cells = <2>; 93 ranges; 94 95 nvidia,num-lanes = <2>; 96 }; 97 }; 98 99 iram@40000000 { 100 compatible = "mmio-sram"; 101 reg = <0x40000000 0x40000>; 102 #address-cells = <1>; 103 #size-cells = <1>; 104 ranges = <0 0x40000000 0x40000>; 105 106 vde_pool: vde@400 { 107 reg = <0x400 0x3fc00>; 108 pool; 109 }; 110 }; 111 112 host1x@50000000 { 113 compatible = "nvidia,tegra30-host1x", "simple-bus"; 114 reg = <0x50000000 0x00024000>; 115 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 116 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 117 clocks = <&tegra_car TEGRA30_CLK_HOST1X>; 118 resets = <&tegra_car 28>; 119 reset-names = "host1x"; 120 iommus = <&mc TEGRA_SWGROUP_HC>; 121 122 #address-cells = <1>; 123 #size-cells = <1>; 124 125 ranges = <0x54000000 0x54000000 0x04000000>; 126 127 mpe@54040000 { 128 compatible = "nvidia,tegra30-mpe"; 129 reg = <0x54040000 0x00040000>; 130 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 131 clocks = <&tegra_car TEGRA30_CLK_MPE>; 132 resets = <&tegra_car 60>; 133 reset-names = "mpe"; 134 135 iommus = <&mc TEGRA_SWGROUP_MPE>; 136 }; 137 138 vi@54080000 { 139 compatible = "nvidia,tegra30-vi"; 140 reg = <0x54080000 0x00040000>; 141 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 142 clocks = <&tegra_car TEGRA30_CLK_VI>; 143 resets = <&tegra_car 20>; 144 reset-names = "vi"; 145 146 iommus = <&mc TEGRA_SWGROUP_VI>; 147 }; 148 149 epp@540c0000 { 150 compatible = "nvidia,tegra30-epp"; 151 reg = <0x540c0000 0x00040000>; 152 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 153 clocks = <&tegra_car TEGRA30_CLK_EPP>; 154 resets = <&tegra_car 19>; 155 reset-names = "epp"; 156 157 iommus = <&mc TEGRA_SWGROUP_EPP>; 158 }; 159 160 isp@54100000 { 161 compatible = "nvidia,tegra30-isp"; 162 reg = <0x54100000 0x00040000>; 163 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 164 clocks = <&tegra_car TEGRA30_CLK_ISP>; 165 resets = <&tegra_car 23>; 166 reset-names = "isp"; 167 168 iommus = <&mc TEGRA_SWGROUP_ISP>; 169 }; 170 171 gr2d@54140000 { 172 compatible = "nvidia,tegra30-gr2d"; 173 reg = <0x54140000 0x00040000>; 174 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 175 clocks = <&tegra_car TEGRA30_CLK_GR2D>; 176 resets = <&tegra_car 21>; 177 reset-names = "2d"; 178 179 iommus = <&mc TEGRA_SWGROUP_G2>; 180 }; 181 182 gr3d@54180000 { 183 compatible = "nvidia,tegra30-gr3d"; 184 reg = <0x54180000 0x00040000>; 185 clocks = <&tegra_car TEGRA30_CLK_GR3D 186 &tegra_car TEGRA30_CLK_GR3D2>; 187 clock-names = "3d", "3d2"; 188 resets = <&tegra_car 24>, 189 <&tegra_car 98>; 190 reset-names = "3d", "3d2"; 191 192 iommus = <&mc TEGRA_SWGROUP_NV>, 193 <&mc TEGRA_SWGROUP_NV2>; 194 }; 195 196 dc@54200000 { 197 compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc"; 198 reg = <0x54200000 0x00040000>; 199 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 200 clocks = <&tegra_car TEGRA30_CLK_DISP1>, 201 <&tegra_car TEGRA30_CLK_PLL_P>; 202 clock-names = "dc", "parent"; 203 resets = <&tegra_car 27>; 204 reset-names = "dc"; 205 206 iommus = <&mc TEGRA_SWGROUP_DC>; 207 208 nvidia,head = <0>; 209 210 rgb { 211 status = "disabled"; 212 }; 213 }; 214 215 dc@54240000 { 216 compatible = "nvidia,tegra30-dc"; 217 reg = <0x54240000 0x00040000>; 218 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 219 clocks = <&tegra_car TEGRA30_CLK_DISP2>, 220 <&tegra_car TEGRA30_CLK_PLL_P>; 221 clock-names = "dc", "parent"; 222 resets = <&tegra_car 26>; 223 reset-names = "dc"; 224 225 iommus = <&mc TEGRA_SWGROUP_DCB>; 226 227 nvidia,head = <1>; 228 229 rgb { 230 status = "disabled"; 231 }; 232 }; 233 234 hdmi@54280000 { 235 compatible = "nvidia,tegra30-hdmi"; 236 reg = <0x54280000 0x00040000>; 237 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 238 clocks = <&tegra_car TEGRA30_CLK_HDMI>, 239 <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>; 240 clock-names = "hdmi", "parent"; 241 resets = <&tegra_car 51>; 242 reset-names = "hdmi"; 243 status = "disabled"; 244 }; 245 246 tvo@542c0000 { 247 compatible = "nvidia,tegra30-tvo"; 248 reg = <0x542c0000 0x00040000>; 249 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 250 clocks = <&tegra_car TEGRA30_CLK_TVO>; 251 status = "disabled"; 252 }; 253 254 dsi@54300000 { 255 compatible = "nvidia,tegra30-dsi"; 256 reg = <0x54300000 0x00040000>; 257 clocks = <&tegra_car TEGRA30_CLK_DSIA>; 258 resets = <&tegra_car 48>; 259 reset-names = "dsi"; 260 status = "disabled"; 261 }; 262 }; 263 264 timer@50040600 { 265 compatible = "arm,cortex-a9-twd-timer"; 266 reg = <0x50040600 0x20>; 267 interrupt-parent = <&intc>; 268 interrupts = <GIC_PPI 13 269 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; 270 clocks = <&tegra_car TEGRA30_CLK_TWD>; 271 }; 272 273 intc: interrupt-controller@50041000 { 274 compatible = "arm,cortex-a9-gic"; 275 reg = <0x50041000 0x1000 276 0x50040100 0x0100>; 277 interrupt-controller; 278 #interrupt-cells = <3>; 279 interrupt-parent = <&intc>; 280 }; 281 282 cache-controller@50043000 { 283 compatible = "arm,pl310-cache"; 284 reg = <0x50043000 0x1000>; 285 arm,data-latency = <6 6 2>; 286 arm,tag-latency = <5 5 2>; 287 cache-unified; 288 cache-level = <2>; 289 }; 290 291 lic: interrupt-controller@60004000 { 292 compatible = "nvidia,tegra30-ictlr"; 293 reg = <0x60004000 0x100>, 294 <0x60004100 0x50>, 295 <0x60004200 0x50>, 296 <0x60004300 0x50>, 297 <0x60004400 0x50>; 298 interrupt-controller; 299 #interrupt-cells = <3>; 300 interrupt-parent = <&intc>; 301 }; 302 303 timer@60005000 { 304 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer"; 305 reg = <0x60005000 0x400>; 306 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 307 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 308 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 309 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 310 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 311 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 312 clocks = <&tegra_car TEGRA30_CLK_TIMER>; 313 }; 314 315 tegra_car: clock@60006000 { 316 compatible = "nvidia,tegra30-car"; 317 reg = <0x60006000 0x1000>; 318 #clock-cells = <1>; 319 #reset-cells = <1>; 320 }; 321 322 flow-controller@60007000 { 323 compatible = "nvidia,tegra30-flowctrl"; 324 reg = <0x60007000 0x1000>; 325 }; 326 327 apbdma: dma@6000a000 { 328 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; 329 reg = <0x6000a000 0x1400>; 330 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 331 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 332 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 333 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 334 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 335 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 336 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 337 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 338 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 339 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 340 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 341 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 342 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 343 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 344 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 345 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 346 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 347 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 348 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 349 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 350 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 351 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 352 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 353 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 354 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 355 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 356 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 357 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 358 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 359 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 360 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 361 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 362 clocks = <&tegra_car TEGRA30_CLK_APBDMA>; 363 resets = <&tegra_car 34>; 364 reset-names = "dma"; 365 #dma-cells = <1>; 366 }; 367 368 ahb: ahb@6000c000 { 369 compatible = "nvidia,tegra30-ahb"; 370 reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */ 371 }; 372 373 gpio: gpio@6000d000 { 374 compatible = "nvidia,tegra30-gpio"; 375 reg = <0x6000d000 0x1000>; 376 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 377 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 378 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 379 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 380 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 381 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 382 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 383 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 384 #gpio-cells = <2>; 385 gpio-controller; 386 #interrupt-cells = <2>; 387 interrupt-controller; 388 /* 389 gpio-ranges = <&pinmux 0 0 248>; 390 */ 391 }; 392 393 vde@6001a000 { 394 compatible = "nvidia,tegra30-vde", "nvidia,tegra20-vde"; 395 reg = <0x6001a000 0x1000 /* Syntax Engine */ 396 0x6001b000 0x1000 /* Video Bitstream Engine */ 397 0x6001c000 0x100 /* Macroblock Engine */ 398 0x6001c200 0x100 /* Post-processing Engine */ 399 0x6001c400 0x100 /* Motion Compensation Engine */ 400 0x6001c600 0x100 /* Transform Engine */ 401 0x6001c800 0x100 /* Pixel prediction block */ 402 0x6001ca00 0x100 /* Video DMA */ 403 0x6001d800 0x400>; /* Video frame controls */ 404 reg-names = "sxe", "bsev", "mbe", "ppe", "mce", 405 "tfe", "ppb", "vdma", "frameid"; 406 iram = <&vde_pool>; /* IRAM region */ 407 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */ 408 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */ 409 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */ 410 interrupt-names = "sync-token", "bsev", "sxe"; 411 clocks = <&tegra_car TEGRA30_CLK_VDE>; 412 reset-names = "vde", "mc"; 413 resets = <&tegra_car 61>, <&mc TEGRA30_MC_RESET_VDE>; 414 }; 415 416 apbmisc@70000800 { 417 compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc"; 418 reg = <0x70000800 0x64 /* Chip revision */ 419 0x70000008 0x04>; /* Strapping options */ 420 }; 421 422 pinmux: pinmux@70000868 { 423 compatible = "nvidia,tegra30-pinmux"; 424 reg = <0x70000868 0xd4 /* Pad control registers */ 425 0x70003000 0x3e4>; /* Mux registers */ 426 }; 427 428 /* 429 * There are two serial driver i.e. 8250 based simple serial 430 * driver and APB DMA based serial driver for higher baudrate 431 * and performace. To enable the 8250 based driver, the compatible 432 * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable 433 * the APB DMA based serial driver, the compatible is 434 * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart". 435 */ 436 uarta: serial@70006000 { 437 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 438 reg = <0x70006000 0x40>; 439 reg-shift = <2>; 440 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 441 clocks = <&tegra_car TEGRA30_CLK_UARTA>; 442 resets = <&tegra_car 6>; 443 reset-names = "serial"; 444 dmas = <&apbdma 8>, <&apbdma 8>; 445 dma-names = "rx", "tx"; 446 status = "disabled"; 447 }; 448 449 uartb: serial@70006040 { 450 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 451 reg = <0x70006040 0x40>; 452 reg-shift = <2>; 453 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 454 clocks = <&tegra_car TEGRA30_CLK_UARTB>; 455 resets = <&tegra_car 7>; 456 reset-names = "serial"; 457 dmas = <&apbdma 9>, <&apbdma 9>; 458 dma-names = "rx", "tx"; 459 status = "disabled"; 460 }; 461 462 uartc: serial@70006200 { 463 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 464 reg = <0x70006200 0x100>; 465 reg-shift = <2>; 466 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 467 clocks = <&tegra_car TEGRA30_CLK_UARTC>; 468 resets = <&tegra_car 55>; 469 reset-names = "serial"; 470 dmas = <&apbdma 10>, <&apbdma 10>; 471 dma-names = "rx", "tx"; 472 status = "disabled"; 473 }; 474 475 uartd: serial@70006300 { 476 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 477 reg = <0x70006300 0x100>; 478 reg-shift = <2>; 479 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 480 clocks = <&tegra_car TEGRA30_CLK_UARTD>; 481 resets = <&tegra_car 65>; 482 reset-names = "serial"; 483 dmas = <&apbdma 19>, <&apbdma 19>; 484 dma-names = "rx", "tx"; 485 status = "disabled"; 486 }; 487 488 uarte: serial@70006400 { 489 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 490 reg = <0x70006400 0x100>; 491 reg-shift = <2>; 492 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 493 clocks = <&tegra_car TEGRA30_CLK_UARTE>; 494 resets = <&tegra_car 66>; 495 reset-names = "serial"; 496 dmas = <&apbdma 20>, <&apbdma 20>; 497 dma-names = "rx", "tx"; 498 status = "disabled"; 499 }; 500 501 gmi@70009000 { 502 compatible = "nvidia,tegra30-gmi"; 503 reg = <0x70009000 0x1000>; 504 #address-cells = <2>; 505 #size-cells = <1>; 506 ranges = <0 0 0x48000000 0x7ffffff>; 507 clocks = <&tegra_car TEGRA30_CLK_NOR>; 508 clock-names = "gmi"; 509 resets = <&tegra_car 42>; 510 reset-names = "gmi"; 511 status = "disabled"; 512 }; 513 514 pwm: pwm@7000a000 { 515 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm"; 516 reg = <0x7000a000 0x100>; 517 #pwm-cells = <2>; 518 clocks = <&tegra_car TEGRA30_CLK_PWM>; 519 resets = <&tegra_car 17>; 520 reset-names = "pwm"; 521 status = "disabled"; 522 }; 523 524 rtc@7000e000 { 525 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc"; 526 reg = <0x7000e000 0x100>; 527 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 528 clocks = <&tegra_car TEGRA30_CLK_RTC>; 529 }; 530 531 i2c@7000c000 { 532 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 533 reg = <0x7000c000 0x100>; 534 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 535 #address-cells = <1>; 536 #size-cells = <0>; 537 clocks = <&tegra_car TEGRA30_CLK_I2C1>, 538 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; 539 clock-names = "div-clk", "fast-clk"; 540 resets = <&tegra_car 12>; 541 reset-names = "i2c"; 542 dmas = <&apbdma 21>, <&apbdma 21>; 543 dma-names = "rx", "tx"; 544 status = "disabled"; 545 }; 546 547 i2c@7000c400 { 548 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 549 reg = <0x7000c400 0x100>; 550 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 551 #address-cells = <1>; 552 #size-cells = <0>; 553 clocks = <&tegra_car TEGRA30_CLK_I2C2>, 554 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; 555 clock-names = "div-clk", "fast-clk"; 556 resets = <&tegra_car 54>; 557 reset-names = "i2c"; 558 dmas = <&apbdma 22>, <&apbdma 22>; 559 dma-names = "rx", "tx"; 560 status = "disabled"; 561 }; 562 563 i2c@7000c500 { 564 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 565 reg = <0x7000c500 0x100>; 566 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 567 #address-cells = <1>; 568 #size-cells = <0>; 569 clocks = <&tegra_car TEGRA30_CLK_I2C3>, 570 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; 571 clock-names = "div-clk", "fast-clk"; 572 resets = <&tegra_car 67>; 573 reset-names = "i2c"; 574 dmas = <&apbdma 23>, <&apbdma 23>; 575 dma-names = "rx", "tx"; 576 status = "disabled"; 577 }; 578 579 i2c@7000c700 { 580 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 581 reg = <0x7000c700 0x100>; 582 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 583 #address-cells = <1>; 584 #size-cells = <0>; 585 clocks = <&tegra_car TEGRA30_CLK_I2C4>, 586 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; 587 resets = <&tegra_car 103>; 588 reset-names = "i2c"; 589 clock-names = "div-clk", "fast-clk"; 590 dmas = <&apbdma 26>, <&apbdma 26>; 591 dma-names = "rx", "tx"; 592 status = "disabled"; 593 }; 594 595 i2c@7000d000 { 596 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 597 reg = <0x7000d000 0x100>; 598 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 599 #address-cells = <1>; 600 #size-cells = <0>; 601 clocks = <&tegra_car TEGRA30_CLK_I2C5>, 602 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; 603 clock-names = "div-clk", "fast-clk"; 604 resets = <&tegra_car 47>; 605 reset-names = "i2c"; 606 dmas = <&apbdma 24>, <&apbdma 24>; 607 dma-names = "rx", "tx"; 608 status = "disabled"; 609 }; 610 611 spi@7000d400 { 612 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; 613 reg = <0x7000d400 0x200>; 614 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 615 #address-cells = <1>; 616 #size-cells = <0>; 617 clocks = <&tegra_car TEGRA30_CLK_SBC1>; 618 resets = <&tegra_car 41>; 619 reset-names = "spi"; 620 dmas = <&apbdma 15>, <&apbdma 15>; 621 dma-names = "rx", "tx"; 622 status = "disabled"; 623 }; 624 625 spi@7000d600 { 626 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; 627 reg = <0x7000d600 0x200>; 628 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 629 #address-cells = <1>; 630 #size-cells = <0>; 631 clocks = <&tegra_car TEGRA30_CLK_SBC2>; 632 resets = <&tegra_car 44>; 633 reset-names = "spi"; 634 dmas = <&apbdma 16>, <&apbdma 16>; 635 dma-names = "rx", "tx"; 636 status = "disabled"; 637 }; 638 639 spi@7000d800 { 640 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; 641 reg = <0x7000d800 0x200>; 642 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 643 #address-cells = <1>; 644 #size-cells = <0>; 645 clocks = <&tegra_car TEGRA30_CLK_SBC3>; 646 resets = <&tegra_car 46>; 647 reset-names = "spi"; 648 dmas = <&apbdma 17>, <&apbdma 17>; 649 dma-names = "rx", "tx"; 650 status = "disabled"; 651 }; 652 653 spi@7000da00 { 654 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; 655 reg = <0x7000da00 0x200>; 656 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 657 #address-cells = <1>; 658 #size-cells = <0>; 659 clocks = <&tegra_car TEGRA30_CLK_SBC4>; 660 resets = <&tegra_car 68>; 661 reset-names = "spi"; 662 dmas = <&apbdma 18>, <&apbdma 18>; 663 dma-names = "rx", "tx"; 664 status = "disabled"; 665 }; 666 667 spi@7000dc00 { 668 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; 669 reg = <0x7000dc00 0x200>; 670 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 671 #address-cells = <1>; 672 #size-cells = <0>; 673 clocks = <&tegra_car TEGRA30_CLK_SBC5>; 674 resets = <&tegra_car 104>; 675 reset-names = "spi"; 676 dmas = <&apbdma 27>, <&apbdma 27>; 677 dma-names = "rx", "tx"; 678 status = "disabled"; 679 }; 680 681 spi@7000de00 { 682 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; 683 reg = <0x7000de00 0x200>; 684 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 685 #address-cells = <1>; 686 #size-cells = <0>; 687 clocks = <&tegra_car TEGRA30_CLK_SBC6>; 688 resets = <&tegra_car 106>; 689 reset-names = "spi"; 690 dmas = <&apbdma 28>, <&apbdma 28>; 691 dma-names = "rx", "tx"; 692 status = "disabled"; 693 }; 694 695 kbc@7000e200 { 696 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc"; 697 reg = <0x7000e200 0x100>; 698 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 699 clocks = <&tegra_car TEGRA30_CLK_KBC>; 700 resets = <&tegra_car 36>; 701 reset-names = "kbc"; 702 status = "disabled"; 703 }; 704 705 pmc@7000e400 { 706 compatible = "nvidia,tegra30-pmc"; 707 reg = <0x7000e400 0x400>; 708 clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>; 709 clock-names = "pclk", "clk32k_in"; 710 }; 711 712 mc: memory-controller@7000f000 { 713 compatible = "nvidia,tegra30-mc"; 714 reg = <0x7000f000 0x400>; 715 clocks = <&tegra_car TEGRA30_CLK_MC>; 716 clock-names = "mc"; 717 718 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 719 720 #iommu-cells = <1>; 721 #reset-cells = <1>; 722 }; 723 724 fuse@7000f800 { 725 compatible = "nvidia,tegra30-efuse"; 726 reg = <0x7000f800 0x400>; 727 clocks = <&tegra_car TEGRA30_CLK_FUSE>; 728 clock-names = "fuse"; 729 resets = <&tegra_car 39>; 730 reset-names = "fuse"; 731 }; 732 733 hda@70030000 { 734 compatible = "nvidia,tegra30-hda"; 735 reg = <0x70030000 0x10000>; 736 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 737 clocks = <&tegra_car TEGRA30_CLK_HDA>, 738 <&tegra_car TEGRA30_CLK_HDA2HDMI>, 739 <&tegra_car TEGRA30_CLK_HDA2CODEC_2X>; 740 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 741 resets = <&tegra_car 125>, /* hda */ 742 <&tegra_car 128>, /* hda2hdmi */ 743 <&tegra_car 111>; /* hda2codec_2x */ 744 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 745 status = "disabled"; 746 }; 747 748 ahub@70080000 { 749 compatible = "nvidia,tegra30-ahub"; 750 reg = <0x70080000 0x200 751 0x70080200 0x100>; 752 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 753 clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>, 754 <&tegra_car TEGRA30_CLK_APBIF>; 755 clock-names = "d_audio", "apbif"; 756 resets = <&tegra_car 106>, /* d_audio */ 757 <&tegra_car 107>, /* apbif */ 758 <&tegra_car 30>, /* i2s0 */ 759 <&tegra_car 11>, /* i2s1 */ 760 <&tegra_car 18>, /* i2s2 */ 761 <&tegra_car 101>, /* i2s3 */ 762 <&tegra_car 102>, /* i2s4 */ 763 <&tegra_car 108>, /* dam0 */ 764 <&tegra_car 109>, /* dam1 */ 765 <&tegra_car 110>, /* dam2 */ 766 <&tegra_car 10>; /* spdif */ 767 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", 768 "i2s3", "i2s4", "dam0", "dam1", "dam2", 769 "spdif"; 770 dmas = <&apbdma 1>, <&apbdma 1>, 771 <&apbdma 2>, <&apbdma 2>, 772 <&apbdma 3>, <&apbdma 3>, 773 <&apbdma 4>, <&apbdma 4>; 774 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", 775 "rx3", "tx3"; 776 ranges; 777 #address-cells = <1>; 778 #size-cells = <1>; 779 780 tegra_i2s0: i2s@70080300 { 781 compatible = "nvidia,tegra30-i2s"; 782 reg = <0x70080300 0x100>; 783 nvidia,ahub-cif-ids = <4 4>; 784 clocks = <&tegra_car TEGRA30_CLK_I2S0>; 785 resets = <&tegra_car 30>; 786 reset-names = "i2s"; 787 status = "disabled"; 788 }; 789 790 tegra_i2s1: i2s@70080400 { 791 compatible = "nvidia,tegra30-i2s"; 792 reg = <0x70080400 0x100>; 793 nvidia,ahub-cif-ids = <5 5>; 794 clocks = <&tegra_car TEGRA30_CLK_I2S1>; 795 resets = <&tegra_car 11>; 796 reset-names = "i2s"; 797 status = "disabled"; 798 }; 799 800 tegra_i2s2: i2s@70080500 { 801 compatible = "nvidia,tegra30-i2s"; 802 reg = <0x70080500 0x100>; 803 nvidia,ahub-cif-ids = <6 6>; 804 clocks = <&tegra_car TEGRA30_CLK_I2S2>; 805 resets = <&tegra_car 18>; 806 reset-names = "i2s"; 807 status = "disabled"; 808 }; 809 810 tegra_i2s3: i2s@70080600 { 811 compatible = "nvidia,tegra30-i2s"; 812 reg = <0x70080600 0x100>; 813 nvidia,ahub-cif-ids = <7 7>; 814 clocks = <&tegra_car TEGRA30_CLK_I2S3>; 815 resets = <&tegra_car 101>; 816 reset-names = "i2s"; 817 status = "disabled"; 818 }; 819 820 tegra_i2s4: i2s@70080700 { 821 compatible = "nvidia,tegra30-i2s"; 822 reg = <0x70080700 0x100>; 823 nvidia,ahub-cif-ids = <8 8>; 824 clocks = <&tegra_car TEGRA30_CLK_I2S4>; 825 resets = <&tegra_car 102>; 826 reset-names = "i2s"; 827 status = "disabled"; 828 }; 829 }; 830 831 sdhci@78000000 { 832 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; 833 reg = <0x78000000 0x200>; 834 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 835 clocks = <&tegra_car TEGRA30_CLK_SDMMC1>; 836 resets = <&tegra_car 14>; 837 reset-names = "sdhci"; 838 status = "disabled"; 839 }; 840 841 sdhci@78000200 { 842 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; 843 reg = <0x78000200 0x200>; 844 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 845 clocks = <&tegra_car TEGRA30_CLK_SDMMC2>; 846 resets = <&tegra_car 9>; 847 reset-names = "sdhci"; 848 status = "disabled"; 849 }; 850 851 sdhci@78000400 { 852 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; 853 reg = <0x78000400 0x200>; 854 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 855 clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; 856 resets = <&tegra_car 69>; 857 reset-names = "sdhci"; 858 status = "disabled"; 859 }; 860 861 sdhci@78000600 { 862 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; 863 reg = <0x78000600 0x200>; 864 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 865 clocks = <&tegra_car TEGRA30_CLK_SDMMC4>; 866 resets = <&tegra_car 15>; 867 reset-names = "sdhci"; 868 status = "disabled"; 869 }; 870 871 usb@7d000000 { 872 compatible = "nvidia,tegra30-ehci", "usb-ehci"; 873 reg = <0x7d000000 0x4000>; 874 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 875 phy_type = "utmi"; 876 clocks = <&tegra_car TEGRA30_CLK_USBD>; 877 resets = <&tegra_car 22>; 878 reset-names = "usb"; 879 nvidia,needs-double-reset; 880 nvidia,phy = <&phy1>; 881 status = "disabled"; 882 }; 883 884 phy1: usb-phy@7d000000 { 885 compatible = "nvidia,tegra30-usb-phy"; 886 reg = <0x7d000000 0x4000 0x7d000000 0x4000>; 887 phy_type = "utmi"; 888 clocks = <&tegra_car TEGRA30_CLK_USBD>, 889 <&tegra_car TEGRA30_CLK_PLL_U>, 890 <&tegra_car TEGRA30_CLK_USBD>; 891 clock-names = "reg", "pll_u", "utmi-pads"; 892 resets = <&tegra_car 22>, <&tegra_car 22>; 893 reset-names = "usb", "utmi-pads"; 894 nvidia,hssync-start-delay = <9>; 895 nvidia,idle-wait-delay = <17>; 896 nvidia,elastic-limit = <16>; 897 nvidia,term-range-adj = <6>; 898 nvidia,xcvr-setup = <51>; 899 nvidia.xcvr-setup-use-fuses; 900 nvidia,xcvr-lsfslew = <1>; 901 nvidia,xcvr-lsrslew = <1>; 902 nvidia,xcvr-hsslew = <32>; 903 nvidia,hssquelch-level = <2>; 904 nvidia,hsdiscon-level = <5>; 905 nvidia,has-utmi-pad-registers; 906 status = "disabled"; 907 }; 908 909 usb@7d004000 { 910 compatible = "nvidia,tegra30-ehci", "usb-ehci"; 911 reg = <0x7d004000 0x4000>; 912 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 913 phy_type = "utmi"; 914 clocks = <&tegra_car TEGRA30_CLK_USB2>; 915 resets = <&tegra_car 58>; 916 reset-names = "usb"; 917 nvidia,phy = <&phy2>; 918 status = "disabled"; 919 }; 920 921 phy2: usb-phy@7d004000 { 922 compatible = "nvidia,tegra30-usb-phy"; 923 reg = <0x7d004000 0x4000 0x7d000000 0x4000>; 924 phy_type = "utmi"; 925 clocks = <&tegra_car TEGRA30_CLK_USB2>, 926 <&tegra_car TEGRA30_CLK_PLL_U>, 927 <&tegra_car TEGRA30_CLK_USBD>; 928 clock-names = "reg", "pll_u", "utmi-pads"; 929 resets = <&tegra_car 58>, <&tegra_car 22>; 930 reset-names = "usb", "utmi-pads"; 931 nvidia,hssync-start-delay = <9>; 932 nvidia,idle-wait-delay = <17>; 933 nvidia,elastic-limit = <16>; 934 nvidia,term-range-adj = <6>; 935 nvidia,xcvr-setup = <51>; 936 nvidia.xcvr-setup-use-fuses; 937 nvidia,xcvr-lsfslew = <2>; 938 nvidia,xcvr-lsrslew = <2>; 939 nvidia,xcvr-hsslew = <32>; 940 nvidia,hssquelch-level = <2>; 941 nvidia,hsdiscon-level = <5>; 942 status = "disabled"; 943 }; 944 945 usb@7d008000 { 946 compatible = "nvidia,tegra30-ehci", "usb-ehci"; 947 reg = <0x7d008000 0x4000>; 948 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 949 phy_type = "utmi"; 950 clocks = <&tegra_car TEGRA30_CLK_USB3>; 951 resets = <&tegra_car 59>; 952 reset-names = "usb"; 953 nvidia,phy = <&phy3>; 954 status = "disabled"; 955 }; 956 957 phy3: usb-phy@7d008000 { 958 compatible = "nvidia,tegra30-usb-phy"; 959 reg = <0x7d008000 0x4000 0x7d000000 0x4000>; 960 phy_type = "utmi"; 961 clocks = <&tegra_car TEGRA30_CLK_USB3>, 962 <&tegra_car TEGRA30_CLK_PLL_U>, 963 <&tegra_car TEGRA30_CLK_USBD>; 964 clock-names = "reg", "pll_u", "utmi-pads"; 965 resets = <&tegra_car 59>, <&tegra_car 22>; 966 reset-names = "usb", "utmi-pads"; 967 nvidia,hssync-start-delay = <0>; 968 nvidia,idle-wait-delay = <17>; 969 nvidia,elastic-limit = <16>; 970 nvidia,term-range-adj = <6>; 971 nvidia,xcvr-setup = <51>; 972 nvidia.xcvr-setup-use-fuses; 973 nvidia,xcvr-lsfslew = <2>; 974 nvidia,xcvr-lsrslew = <2>; 975 nvidia,xcvr-hsslew = <32>; 976 nvidia,hssquelch-level = <2>; 977 nvidia,hsdiscon-level = <5>; 978 status = "disabled"; 979 }; 980 981 cpus { 982 #address-cells = <1>; 983 #size-cells = <0>; 984 985 cpu@0 { 986 device_type = "cpu"; 987 compatible = "arm,cortex-a9"; 988 reg = <0>; 989 }; 990 991 cpu@1 { 992 device_type = "cpu"; 993 compatible = "arm,cortex-a9"; 994 reg = <1>; 995 }; 996 997 cpu@2 { 998 device_type = "cpu"; 999 compatible = "arm,cortex-a9"; 1000 reg = <2>; 1001 }; 1002 1003 cpu@3 { 1004 device_type = "cpu"; 1005 compatible = "arm,cortex-a9"; 1006 reg = <3>; 1007 }; 1008 }; 1009 1010 pmu { 1011 compatible = "arm,cortex-a9-pmu"; 1012 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1013 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1014 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1015 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 1016 }; 1017}; 1018
