1/* 2 * Copyright 2017 Chen-Yu Tsai <wens@csie.org> 3 * Copyright 2017 Icenowy Zheng <icenowy@aosc.io> 4 * 5 * This file is dual-licensed: you can use it either under the terms 6 * of the GPL or the X11 license, at your option. Note that this dual 7 * licensing only applies to this file, and not this project as a 8 * whole. 9 * 10 * a) This file is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of the 13 * License, or (at your option) any later version. 14 * 15 * This file is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * Or, alternatively, 21 * 22 * b) Permission is hereby granted, free of charge, to any person 23 * obtaining a copy of this software and associated documentation 24 * files (the "Software"), to deal in the Software without 25 * restriction, including without limitation the rights to use, 26 * copy, modify, merge, publish, distribute, sublicense, and/or 27 * sell copies of the Software, and to permit persons to whom the 28 * Software is furnished to do so, subject to the following 29 * conditions: 30 * 31 * The above copyright notice and this permission notice shall be 32 * included in all copies or substantial portions of the Software. 33 * 34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 41 * OTHER DEALINGS IN THE SOFTWARE. 42 */ 43 44#include <dt-bindings/interrupt-controller/arm-gic.h> 45#include <dt-bindings/clock/sun8i-de2.h> 46#include <dt-bindings/clock/sun8i-r40-ccu.h> 47#include <dt-bindings/clock/sun8i-tcon-top.h> 48#include <dt-bindings/reset/sun8i-r40-ccu.h> 49#include <dt-bindings/reset/sun8i-de2.h> 50#include <dt-bindings/thermal/thermal.h> 51 52/ { 53 #address-cells = <1>; 54 #size-cells = <1>; 55 interrupt-parent = <&gic>; 56 57 clocks { 58 #address-cells = <1>; 59 #size-cells = <1>; 60 ranges; 61 62 osc24M: osc24M { 63 #clock-cells = <0>; 64 compatible = "fixed-clock"; 65 clock-frequency = <24000000>; 66 clock-accuracy = <50000>; 67 clock-output-names = "osc24M"; 68 }; 69 70 osc32k: osc32k { 71 #clock-cells = <0>; 72 compatible = "fixed-clock"; 73 clock-frequency = <32768>; 74 clock-accuracy = <20000>; 75 clock-output-names = "ext-osc32k"; 76 }; 77 }; 78 79 cpus { 80 #address-cells = <1>; 81 #size-cells = <0>; 82 83 cpu0: cpu@0 { 84 compatible = "arm,cortex-a7"; 85 device_type = "cpu"; 86 reg = <0>; 87 }; 88 89 cpu1: cpu@1 { 90 compatible = "arm,cortex-a7"; 91 device_type = "cpu"; 92 reg = <1>; 93 }; 94 95 cpu2: cpu@2 { 96 compatible = "arm,cortex-a7"; 97 device_type = "cpu"; 98 reg = <2>; 99 }; 100 101 cpu3: cpu@3 { 102 compatible = "arm,cortex-a7"; 103 device_type = "cpu"; 104 reg = <3>; 105 }; 106 }; 107 108 de: display-engine { 109 compatible = "allwinner,sun8i-r40-display-engine"; 110 allwinner,pipelines = <&mixer0>, <&mixer1>; 111 status = "disabled"; 112 }; 113 114 thermal-zones { 115 cpu_thermal: cpu0-thermal { 116 /* milliseconds */ 117 polling-delay-passive = <0>; 118 polling-delay = <0>; 119 thermal-sensors = <&ths 0>; 120 }; 121 122 gpu_thermal: gpu-thermal { 123 /* milliseconds */ 124 polling-delay-passive = <0>; 125 polling-delay = <0>; 126 thermal-sensors = <&ths 1>; 127 }; 128 }; 129 130 soc { 131 compatible = "simple-bus"; 132 #address-cells = <1>; 133 #size-cells = <1>; 134 ranges; 135 136 display_clocks: clock@1000000 { 137 compatible = "allwinner,sun8i-r40-de2-clk", 138 "allwinner,sun8i-h3-de2-clk"; 139 reg = <0x01000000 0x10000>; 140 clocks = <&ccu CLK_BUS_DE>, 141 <&ccu CLK_DE>; 142 clock-names = "bus", 143 "mod"; 144 resets = <&ccu RST_BUS_DE>; 145 #clock-cells = <1>; 146 #reset-cells = <1>; 147 }; 148 149 mixer0: mixer@1100000 { 150 compatible = "allwinner,sun8i-r40-de2-mixer-0"; 151 reg = <0x01100000 0x100000>; 152 clocks = <&display_clocks CLK_BUS_MIXER0>, 153 <&display_clocks CLK_MIXER0>; 154 clock-names = "bus", 155 "mod"; 156 resets = <&display_clocks RST_MIXER0>; 157 158 ports { 159 #address-cells = <1>; 160 #size-cells = <0>; 161 162 mixer0_out: port@1 { 163 reg = <1>; 164 mixer0_out_tcon_top: endpoint { 165 remote-endpoint = <&tcon_top_mixer0_in_mixer0>; 166 }; 167 }; 168 }; 169 }; 170 171 mixer1: mixer@1200000 { 172 compatible = "allwinner,sun8i-r40-de2-mixer-1"; 173 reg = <0x01200000 0x100000>; 174 clocks = <&display_clocks CLK_BUS_MIXER1>, 175 <&display_clocks CLK_MIXER1>; 176 clock-names = "bus", 177 "mod"; 178 resets = <&display_clocks RST_WB>; 179 180 ports { 181 #address-cells = <1>; 182 #size-cells = <0>; 183 184 mixer1_out: port@1 { 185 reg = <1>; 186 mixer1_out_tcon_top: endpoint { 187 remote-endpoint = <&tcon_top_mixer1_in_mixer1>; 188 }; 189 }; 190 }; 191 }; 192 193 syscon: system-control@1c00000 { 194 compatible = "allwinner,sun8i-r40-system-control", 195 "allwinner,sun4i-a10-system-control"; 196 reg = <0x01c00000 0x30>; 197 #address-cells = <1>; 198 #size-cells = <1>; 199 ranges; 200 201 sram_c: sram@1d00000 { 202 compatible = "mmio-sram"; 203 reg = <0x01d00000 0xd0000>; 204 #address-cells = <1>; 205 #size-cells = <1>; 206 ranges = <0 0x01d00000 0xd0000>; 207 208 ve_sram: sram-section@0 { 209 compatible = "allwinner,sun8i-r40-sram-c1", 210 "allwinner,sun4i-a10-sram-c1"; 211 reg = <0x000000 0x80000>; 212 }; 213 }; 214 }; 215 216 nmi_intc: interrupt-controller@1c00030 { 217 compatible = "allwinner,sun7i-a20-sc-nmi"; 218 interrupt-controller; 219 #interrupt-cells = <2>; 220 reg = <0x01c00030 0x0c>; 221 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 222 }; 223 224 dma: dma-controller@1c02000 { 225 compatible = "allwinner,sun8i-r40-dma", 226 "allwinner,sun50i-a64-dma"; 227 reg = <0x01c02000 0x1000>; 228 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 229 clocks = <&ccu CLK_BUS_DMA>; 230 dma-channels = <16>; 231 dma-requests = <31>; 232 resets = <&ccu RST_BUS_DMA>; 233 #dma-cells = <1>; 234 }; 235 236 spi0: spi@1c05000 { 237 compatible = "allwinner,sun8i-r40-spi", 238 "allwinner,sun8i-h3-spi"; 239 reg = <0x01c05000 0x1000>; 240 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 241 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 242 clock-names = "ahb", "mod"; 243 resets = <&ccu RST_BUS_SPI0>; 244 status = "disabled"; 245 #address-cells = <1>; 246 #size-cells = <0>; 247 }; 248 249 spi1: spi@1c06000 { 250 compatible = "allwinner,sun8i-r40-spi", 251 "allwinner,sun8i-h3-spi"; 252 reg = <0x01c06000 0x1000>; 253 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 254 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 255 clock-names = "ahb", "mod"; 256 resets = <&ccu RST_BUS_SPI1>; 257 status = "disabled"; 258 #address-cells = <1>; 259 #size-cells = <0>; 260 }; 261 262 csi0: csi@1c09000 { 263 compatible = "allwinner,sun8i-r40-csi0", 264 "allwinner,sun7i-a20-csi0"; 265 reg = <0x01c09000 0x1000>; 266 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 267 clocks = <&ccu CLK_BUS_CSI0>, <&ccu CLK_CSI_SCLK>, 268 <&ccu CLK_DRAM_CSI0>; 269 clock-names = "bus", "isp", "ram"; 270 resets = <&ccu RST_BUS_CSI0>; 271 interconnects = <&mbus 5>; 272 interconnect-names = "dma-mem"; 273 status = "disabled"; 274 }; 275 276 video-codec@1c0e000 { 277 compatible = "allwinner,sun8i-r40-video-engine"; 278 reg = <0x01c0e000 0x1000>; 279 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, 280 <&ccu CLK_DRAM_VE>; 281 clock-names = "ahb", "mod", "ram"; 282 resets = <&ccu RST_BUS_VE>; 283 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 284 allwinner,sram = <&ve_sram 1>; 285 }; 286 287 mmc0: mmc@1c0f000 { 288 compatible = "allwinner,sun8i-r40-mmc", 289 "allwinner,sun50i-a64-mmc"; 290 reg = <0x01c0f000 0x1000>; 291 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 292 clock-names = "ahb", "mmc"; 293 resets = <&ccu RST_BUS_MMC0>; 294 reset-names = "ahb"; 295 pinctrl-0 = <&mmc0_pins>; 296 pinctrl-names = "default"; 297 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 298 status = "disabled"; 299 #address-cells = <1>; 300 #size-cells = <0>; 301 }; 302 303 mmc1: mmc@1c10000 { 304 compatible = "allwinner,sun8i-r40-mmc", 305 "allwinner,sun50i-a64-mmc"; 306 reg = <0x01c10000 0x1000>; 307 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 308 clock-names = "ahb", "mmc"; 309 resets = <&ccu RST_BUS_MMC1>; 310 reset-names = "ahb"; 311 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 312 status = "disabled"; 313 #address-cells = <1>; 314 #size-cells = <0>; 315 }; 316 317 mmc2: mmc@1c11000 { 318 compatible = "allwinner,sun8i-r40-emmc", 319 "allwinner,sun50i-a64-emmc"; 320 reg = <0x01c11000 0x1000>; 321 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 322 clock-names = "ahb", "mmc"; 323 resets = <&ccu RST_BUS_MMC2>; 324 reset-names = "ahb"; 325 pinctrl-0 = <&mmc2_pins>; 326 pinctrl-names = "default"; 327 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 328 status = "disabled"; 329 #address-cells = <1>; 330 #size-cells = <0>; 331 }; 332 333 mmc3: mmc@1c12000 { 334 compatible = "allwinner,sun8i-r40-mmc", 335 "allwinner,sun50i-a64-mmc"; 336 reg = <0x01c12000 0x1000>; 337 clocks = <&ccu CLK_BUS_MMC3>, <&ccu CLK_MMC3>; 338 clock-names = "ahb", "mmc"; 339 resets = <&ccu RST_BUS_MMC3>; 340 reset-names = "ahb"; 341 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 342 status = "disabled"; 343 #address-cells = <1>; 344 #size-cells = <0>; 345 }; 346 347 usbphy: phy@1c13400 { 348 compatible = "allwinner,sun8i-r40-usb-phy"; 349 reg = <0x01c13400 0x14>, 350 <0x01c14800 0x4>, 351 <0x01c19800 0x4>, 352 <0x01c1c800 0x4>; 353 reg-names = "phy_ctrl", 354 "pmu0", 355 "pmu1", 356 "pmu2"; 357 clocks = <&ccu CLK_USB_PHY0>, 358 <&ccu CLK_USB_PHY1>, 359 <&ccu CLK_USB_PHY2>; 360 clock-names = "usb0_phy", 361 "usb1_phy", 362 "usb2_phy"; 363 resets = <&ccu RST_USB_PHY0>, 364 <&ccu RST_USB_PHY1>, 365 <&ccu RST_USB_PHY2>; 366 reset-names = "usb0_reset", 367 "usb1_reset", 368 "usb2_reset"; 369 status = "disabled"; 370 #phy-cells = <1>; 371 }; 372 373 crypto: crypto@1c15000 { 374 compatible = "allwinner,sun8i-r40-crypto"; 375 reg = <0x01c15000 0x1000>; 376 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 377 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; 378 clock-names = "bus", "mod"; 379 resets = <&ccu RST_BUS_CE>; 380 }; 381 382 spi2: spi@1c17000 { 383 compatible = "allwinner,sun8i-r40-spi", 384 "allwinner,sun8i-h3-spi"; 385 reg = <0x01c17000 0x1000>; 386 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 387 clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>; 388 clock-names = "ahb", "mod"; 389 resets = <&ccu RST_BUS_SPI2>; 390 status = "disabled"; 391 #address-cells = <1>; 392 #size-cells = <0>; 393 }; 394 395 ahci: sata@1c18000 { 396 compatible = "allwinner,sun8i-r40-ahci"; 397 reg = <0x01c18000 0x1000>; 398 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 399 clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>; 400 resets = <&ccu RST_BUS_SATA>; 401 reset-names = "ahci"; 402 status = "disabled"; 403 }; 404 405 ehci1: usb@1c19000 { 406 compatible = "allwinner,sun8i-r40-ehci", "generic-ehci"; 407 reg = <0x01c19000 0x100>; 408 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 409 clocks = <&ccu CLK_BUS_EHCI1>; 410 resets = <&ccu RST_BUS_EHCI1>; 411 phys = <&usbphy 1>; 412 phy-names = "usb"; 413 status = "disabled"; 414 }; 415 416 ohci1: usb@1c19400 { 417 compatible = "allwinner,sun8i-r40-ohci", "generic-ohci"; 418 reg = <0x01c19400 0x100>; 419 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 420 clocks = <&ccu CLK_BUS_OHCI1>, 421 <&ccu CLK_USB_OHCI1>; 422 resets = <&ccu RST_BUS_OHCI1>; 423 phys = <&usbphy 1>; 424 phy-names = "usb"; 425 status = "disabled"; 426 }; 427 428 ehci2: usb@1c1c000 { 429 compatible = "allwinner,sun8i-r40-ehci", "generic-ehci"; 430 reg = <0x01c1c000 0x100>; 431 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 432 clocks = <&ccu CLK_BUS_EHCI2>; 433 resets = <&ccu RST_BUS_EHCI2>; 434 phys = <&usbphy 2>; 435 phy-names = "usb"; 436 status = "disabled"; 437 }; 438 439 ohci2: usb@1c1c400 { 440 compatible = "allwinner,sun8i-r40-ohci", "generic-ohci"; 441 reg = <0x01c1c400 0x100>; 442 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 443 clocks = <&ccu CLK_BUS_OHCI2>, 444 <&ccu CLK_USB_OHCI2>; 445 resets = <&ccu RST_BUS_OHCI2>; 446 phys = <&usbphy 2>; 447 phy-names = "usb"; 448 status = "disabled"; 449 }; 450 451 spi3: spi@1c1f000 { 452 compatible = "allwinner,sun8i-r40-spi", 453 "allwinner,sun8i-h3-spi"; 454 reg = <0x01c1f000 0x1000>; 455 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 456 clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>; 457 clock-names = "ahb", "mod"; 458 resets = <&ccu RST_BUS_SPI3>; 459 status = "disabled"; 460 #address-cells = <1>; 461 #size-cells = <0>; 462 }; 463 464 ccu: clock@1c20000 { 465 compatible = "allwinner,sun8i-r40-ccu"; 466 reg = <0x01c20000 0x400>; 467 clocks = <&osc24M>, <&rtc 0>; 468 clock-names = "hosc", "losc"; 469 #clock-cells = <1>; 470 #reset-cells = <1>; 471 }; 472 473 rtc: rtc@1c20400 { 474 compatible = "allwinner,sun8i-r40-rtc"; 475 reg = <0x01c20400 0x400>; 476 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 477 clock-output-names = "osc32k", "osc32k-out"; 478 clocks = <&osc32k>; 479 #clock-cells = <1>; 480 }; 481 482 pio: pinctrl@1c20800 { 483 compatible = "allwinner,sun8i-r40-pinctrl"; 484 reg = <0x01c20800 0x400>; 485 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 486 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; 487 clock-names = "apb", "hosc", "losc"; 488 gpio-controller; 489 interrupt-controller; 490 #interrupt-cells = <3>; 491 #gpio-cells = <3>; 492 493 clk_out_a_pin: clk-out-a-pin { 494 pins = "PI12"; 495 function = "clk_out_a"; 496 }; 497 498 /omit-if-no-ref/ 499 csi0_8bits_pins: csi0-8bits-pins { 500 pins = "PE0", "PE2", "PE3", "PE4", "PE5", 501 "PE6", "PE7", "PE8", "PE9", "PE10", 502 "PE11"; 503 function = "csi0"; 504 }; 505 506 /omit-if-no-ref/ 507 csi0_mclk_pin: csi0-mclk-pin { 508 pins = "PE1"; 509 function = "csi0"; 510 }; 511 512 gmac_rgmii_pins: gmac-rgmii-pins { 513 pins = "PA0", "PA1", "PA2", "PA3", 514 "PA4", "PA5", "PA6", "PA7", 515 "PA8", "PA10", "PA11", "PA12", 516 "PA13", "PA15", "PA16"; 517 function = "gmac"; 518 /* 519 * data lines in RGMII mode use DDR mode 520 * and need a higher signal drive strength 521 */ 522 drive-strength = <40>; 523 }; 524 525 i2c0_pins: i2c0-pins { 526 pins = "PB0", "PB1"; 527 function = "i2c0"; 528 }; 529 530 i2c1_pins: i2c1-pins { 531 pins = "PB18", "PB19"; 532 function = "i2c1"; 533 }; 534 535 i2c2_pins: i2c2-pins { 536 pins = "PB20", "PB21"; 537 function = "i2c2"; 538 }; 539 540 i2c3_pins: i2c3-pins { 541 pins = "PI0", "PI1"; 542 function = "i2c3"; 543 }; 544 545 i2c4_pins: i2c4-pins { 546 pins = "PI2", "PI3"; 547 function = "i2c4"; 548 }; 549 550 ir0_pins: ir0-pins { 551 pins = "PB4"; 552 function = "ir0"; 553 }; 554 555 ir1_pins: ir1-pins { 556 pins = "PB23"; 557 function = "ir1"; 558 }; 559 560 mmc0_pins: mmc0-pins { 561 pins = "PF0", "PF1", "PF2", 562 "PF3", "PF4", "PF5"; 563 function = "mmc0"; 564 drive-strength = <30>; 565 bias-pull-up; 566 }; 567 568 mmc1_pg_pins: mmc1-pg-pins { 569 pins = "PG0", "PG1", "PG2", 570 "PG3", "PG4", "PG5"; 571 function = "mmc1"; 572 drive-strength = <30>; 573 bias-pull-up; 574 }; 575 576 mmc2_pins: mmc2-pins { 577 pins = "PC5", "PC6", "PC7", "PC8", "PC9", 578 "PC10", "PC11", "PC12", "PC13", "PC14", 579 "PC15", "PC24"; 580 function = "mmc2"; 581 drive-strength = <30>; 582 bias-pull-up; 583 }; 584 585 /omit-if-no-ref/ 586 spi0_pc_pins: spi0-pc-pins { 587 pins = "PC0", "PC1", "PC2"; 588 function = "spi0"; 589 }; 590 591 /omit-if-no-ref/ 592 spi0_cs0_pc_pin: spi0-cs0-pc-pin { 593 pins = "PC23"; 594 function = "spi0"; 595 }; 596 597 /omit-if-no-ref/ 598 spi1_pi_pins: spi1-pi-pins { 599 pins = "PI17", "PI18", "PI19"; 600 function = "spi1"; 601 }; 602 603 /omit-if-no-ref/ 604 spi1_cs0_pi_pin: spi1-cs0-pi-pin { 605 pins = "PI16"; 606 function = "spi1"; 607 }; 608 609 /omit-if-no-ref/ 610 spi1_cs1_pi_pin: spi1-cs1-pi-pin { 611 pins = "PI15"; 612 function = "spi1"; 613 }; 614 615 uart0_pb_pins: uart0-pb-pins { 616 pins = "PB22", "PB23"; 617 function = "uart0"; 618 }; 619 620 uart3_pg_pins: uart3-pg-pins { 621 pins = "PG6", "PG7"; 622 function = "uart3"; 623 }; 624 625 uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins { 626 pins = "PG8", "PG9"; 627 function = "uart3"; 628 }; 629 }; 630 631 wdt: watchdog@1c20c90 { 632 compatible = "allwinner,sun4i-a10-wdt"; 633 reg = <0x01c20c90 0x10>; 634 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 635 clocks = <&osc24M>; 636 }; 637 638 ir0: ir@1c21800 { 639 compatible = "allwinner,sun8i-r40-ir", 640 "allwinner,sun6i-a31-ir"; 641 reg = <0x01c21800 0x400>; 642 pinctrl-0 = <&ir0_pins>; 643 pinctrl-names = "default"; 644 clocks = <&ccu CLK_BUS_IR0>, <&ccu CLK_IR0>; 645 clock-names = "apb", "ir"; 646 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 647 resets = <&ccu RST_BUS_IR0>; 648 status = "disabled"; 649 }; 650 651 ir1: ir@1c21c00 { 652 compatible = "allwinner,sun8i-r40-ir", 653 "allwinner,sun6i-a31-ir"; 654 reg = <0x01c21c00 0x400>; 655 pinctrl-0 = <&ir1_pins>; 656 pinctrl-names = "default"; 657 clocks = <&ccu CLK_BUS_IR1>, <&ccu CLK_IR1>; 658 clock-names = "apb", "ir"; 659 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 660 resets = <&ccu RST_BUS_IR1>; 661 status = "disabled"; 662 }; 663 664 ths: thermal-sensor@1c24c00 { 665 compatible = "allwinner,sun8i-r40-ths"; 666 reg = <0x01c24c00 0x100>; 667 clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; 668 clock-names = "bus", "mod"; 669 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 670 resets = <&ccu RST_BUS_THS>; 671 /* TODO: add nvmem-cells for calibration */ 672 #thermal-sensor-cells = <1>; 673 }; 674 675 uart0: serial@1c28000 { 676 compatible = "snps,dw-apb-uart"; 677 reg = <0x01c28000 0x400>; 678 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 679 reg-shift = <2>; 680 reg-io-width = <4>; 681 clocks = <&ccu CLK_BUS_UART0>; 682 resets = <&ccu RST_BUS_UART0>; 683 status = "disabled"; 684 }; 685 686 uart1: serial@1c28400 { 687 compatible = "snps,dw-apb-uart"; 688 reg = <0x01c28400 0x400>; 689 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 690 reg-shift = <2>; 691 reg-io-width = <4>; 692 clocks = <&ccu CLK_BUS_UART1>; 693 resets = <&ccu RST_BUS_UART1>; 694 status = "disabled"; 695 }; 696 697 uart2: serial@1c28800 { 698 compatible = "snps,dw-apb-uart"; 699 reg = <0x01c28800 0x400>; 700 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 701 reg-shift = <2>; 702 reg-io-width = <4>; 703 clocks = <&ccu CLK_BUS_UART2>; 704 resets = <&ccu RST_BUS_UART2>; 705 status = "disabled"; 706 }; 707 708 uart3: serial@1c28c00 { 709 compatible = "snps,dw-apb-uart"; 710 reg = <0x01c28c00 0x400>; 711 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 712 reg-shift = <2>; 713 reg-io-width = <4>; 714 clocks = <&ccu CLK_BUS_UART3>; 715 resets = <&ccu RST_BUS_UART3>; 716 status = "disabled"; 717 }; 718 719 uart4: serial@1c29000 { 720 compatible = "snps,dw-apb-uart"; 721 reg = <0x01c29000 0x400>; 722 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 723 reg-shift = <2>; 724 reg-io-width = <4>; 725 clocks = <&ccu CLK_BUS_UART4>; 726 resets = <&ccu RST_BUS_UART4>; 727 status = "disabled"; 728 }; 729 730 uart5: serial@1c29400 { 731 compatible = "snps,dw-apb-uart"; 732 reg = <0x01c29400 0x400>; 733 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 734 reg-shift = <2>; 735 reg-io-width = <4>; 736 clocks = <&ccu CLK_BUS_UART5>; 737 resets = <&ccu RST_BUS_UART5>; 738 status = "disabled"; 739 }; 740 741 uart6: serial@1c29800 { 742 compatible = "snps,dw-apb-uart"; 743 reg = <0x01c29800 0x400>; 744 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 745 reg-shift = <2>; 746 reg-io-width = <4>; 747 clocks = <&ccu CLK_BUS_UART6>; 748 resets = <&ccu RST_BUS_UART6>; 749 status = "disabled"; 750 }; 751 752 uart7: serial@1c29c00 { 753 compatible = "snps,dw-apb-uart"; 754 reg = <0x01c29c00 0x400>; 755 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 756 reg-shift = <2>; 757 reg-io-width = <4>; 758 clocks = <&ccu CLK_BUS_UART7>; 759 resets = <&ccu RST_BUS_UART7>; 760 status = "disabled"; 761 }; 762 763 i2c0: i2c@1c2ac00 { 764 compatible = "allwinner,sun6i-a31-i2c"; 765 reg = <0x01c2ac00 0x400>; 766 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 767 clocks = <&ccu CLK_BUS_I2C0>; 768 resets = <&ccu RST_BUS_I2C0>; 769 pinctrl-0 = <&i2c0_pins>; 770 pinctrl-names = "default"; 771 status = "disabled"; 772 #address-cells = <1>; 773 #size-cells = <0>; 774 }; 775 776 i2c1: i2c@1c2b000 { 777 compatible = "allwinner,sun6i-a31-i2c"; 778 reg = <0x01c2b000 0x400>; 779 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 780 clocks = <&ccu CLK_BUS_I2C1>; 781 resets = <&ccu RST_BUS_I2C1>; 782 pinctrl-0 = <&i2c1_pins>; 783 pinctrl-names = "default"; 784 status = "disabled"; 785 #address-cells = <1>; 786 #size-cells = <0>; 787 }; 788 789 i2c2: i2c@1c2b400 { 790 compatible = "allwinner,sun6i-a31-i2c"; 791 reg = <0x01c2b400 0x400>; 792 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 793 clocks = <&ccu CLK_BUS_I2C2>; 794 resets = <&ccu RST_BUS_I2C2>; 795 pinctrl-0 = <&i2c2_pins>; 796 pinctrl-names = "default"; 797 status = "disabled"; 798 #address-cells = <1>; 799 #size-cells = <0>; 800 }; 801 802 i2c3: i2c@1c2b800 { 803 compatible = "allwinner,sun6i-a31-i2c"; 804 reg = <0x01c2b800 0x400>; 805 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 806 clocks = <&ccu CLK_BUS_I2C3>; 807 resets = <&ccu RST_BUS_I2C3>; 808 pinctrl-0 = <&i2c3_pins>; 809 pinctrl-names = "default"; 810 status = "disabled"; 811 #address-cells = <1>; 812 #size-cells = <0>; 813 }; 814 815 i2c4: i2c@1c2c000 { 816 compatible = "allwinner,sun6i-a31-i2c"; 817 reg = <0x01c2c000 0x400>; 818 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 819 clocks = <&ccu CLK_BUS_I2C4>; 820 resets = <&ccu RST_BUS_I2C4>; 821 pinctrl-0 = <&i2c4_pins>; 822 pinctrl-names = "default"; 823 status = "disabled"; 824 #address-cells = <1>; 825 #size-cells = <0>; 826 }; 827 828 mali: gpu@1c40000 { 829 compatible = "allwinner,sun8i-r40-mali", "arm,mali-400"; 830 reg = <0x01c40000 0x10000>; 831 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 832 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 833 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 834 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 835 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 836 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 837 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 838 interrupt-names = "gp", 839 "gpmmu", 840 "pp0", 841 "ppmmu0", 842 "pp1", 843 "ppmmu1", 844 "pmu"; 845 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; 846 clock-names = "bus", "core"; 847 resets = <&ccu RST_BUS_GPU>; 848 }; 849 850 gmac: ethernet@1c50000 { 851 compatible = "allwinner,sun8i-r40-gmac"; 852 syscon = <&ccu>; 853 reg = <0x01c50000 0x10000>; 854 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 855 interrupt-names = "macirq"; 856 resets = <&ccu RST_BUS_GMAC>; 857 reset-names = "stmmaceth"; 858 clocks = <&ccu CLK_BUS_GMAC>; 859 clock-names = "stmmaceth"; 860 status = "disabled"; 861 862 gmac_mdio: mdio { 863 compatible = "snps,dwmac-mdio"; 864 #address-cells = <1>; 865 #size-cells = <0>; 866 }; 867 }; 868 869 mbus: dram-controller@1c62000 { 870 compatible = "allwinner,sun8i-r40-mbus"; 871 reg = <0x01c62000 0x1000>; 872 clocks = <&ccu 155>; 873 #address-cells = <1>; 874 #size-cells = <1>; 875 dma-ranges = <0x00000000 0x40000000 0x80000000>; 876 #interconnect-cells = <1>; 877 }; 878 879 tcon_top: tcon-top@1c70000 { 880 compatible = "allwinner,sun8i-r40-tcon-top"; 881 reg = <0x01c70000 0x1000>; 882 clocks = <&ccu CLK_BUS_TCON_TOP>, 883 <&ccu CLK_TCON_TV0>, 884 <&ccu CLK_TVE0>, 885 <&ccu CLK_TCON_TV1>, 886 <&ccu CLK_TVE1>, 887 <&ccu CLK_DSI_DPHY>; 888 clock-names = "bus", 889 "tcon-tv0", 890 "tve0", 891 "tcon-tv1", 892 "tve1", 893 "dsi"; 894 clock-output-names = "tcon-top-tv0", 895 "tcon-top-tv1", 896 "tcon-top-dsi"; 897 resets = <&ccu RST_BUS_TCON_TOP>; 898 #clock-cells = <1>; 899 900 ports { 901 #address-cells = <1>; 902 #size-cells = <0>; 903 904 tcon_top_mixer0_in: port@0 { 905 reg = <0>; 906 907 tcon_top_mixer0_in_mixer0: endpoint { 908 remote-endpoint = <&mixer0_out_tcon_top>; 909 }; 910 }; 911 912 tcon_top_mixer0_out: port@1 { 913 #address-cells = <1>; 914 #size-cells = <0>; 915 reg = <1>; 916 917 tcon_top_mixer0_out_tcon_lcd0: endpoint@0 { 918 reg = <0>; 919 }; 920 921 tcon_top_mixer0_out_tcon_lcd1: endpoint@1 { 922 reg = <1>; 923 }; 924 925 tcon_top_mixer0_out_tcon_tv0: endpoint@2 { 926 reg = <2>; 927 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>; 928 }; 929 930 tcon_top_mixer0_out_tcon_tv1: endpoint@3 { 931 reg = <3>; 932 remote-endpoint = <&tcon_tv1_in_tcon_top_mixer0>; 933 }; 934 }; 935 936 tcon_top_mixer1_in: port@2 { 937 #address-cells = <1>; 938 #size-cells = <0>; 939 reg = <2>; 940 941 tcon_top_mixer1_in_mixer1: endpoint@1 { 942 reg = <1>; 943 remote-endpoint = <&mixer1_out_tcon_top>; 944 }; 945 }; 946 947 tcon_top_mixer1_out: port@3 { 948 #address-cells = <1>; 949 #size-cells = <0>; 950 reg = <3>; 951 952 tcon_top_mixer1_out_tcon_lcd0: endpoint@0 { 953 reg = <0>; 954 }; 955 956 tcon_top_mixer1_out_tcon_lcd1: endpoint@1 { 957 reg = <1>; 958 }; 959 960 tcon_top_mixer1_out_tcon_tv0: endpoint@2 { 961 reg = <2>; 962 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>; 963 }; 964 965 tcon_top_mixer1_out_tcon_tv1: endpoint@3 { 966 reg = <3>; 967 remote-endpoint = <&tcon_tv1_in_tcon_top_mixer1>; 968 }; 969 }; 970 971 tcon_top_hdmi_in: port@4 { 972 #address-cells = <1>; 973 #size-cells = <0>; 974 reg = <4>; 975 976 tcon_top_hdmi_in_tcon_tv0: endpoint@0 { 977 reg = <0>; 978 remote-endpoint = <&tcon_tv0_out_tcon_top>; 979 }; 980 981 tcon_top_hdmi_in_tcon_tv1: endpoint@1 { 982 reg = <1>; 983 remote-endpoint = <&tcon_tv1_out_tcon_top>; 984 }; 985 }; 986 987 tcon_top_hdmi_out: port@5 { 988 reg = <5>; 989 990 tcon_top_hdmi_out_hdmi: endpoint { 991 remote-endpoint = <&hdmi_in_tcon_top>; 992 }; 993 }; 994 }; 995 }; 996 997 tcon_tv0: lcd-controller@1c73000 { 998 compatible = "allwinner,sun8i-r40-tcon-tv"; 999 reg = <0x01c73000 0x1000>; 1000 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1001 clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top CLK_TCON_TOP_TV0>; 1002 clock-names = "ahb", "tcon-ch1"; 1003 resets = <&ccu RST_BUS_TCON_TV0>; 1004 reset-names = "lcd"; 1005 status = "disabled"; 1006 1007 ports { 1008 #address-cells = <1>; 1009 #size-cells = <0>; 1010 1011 tcon_tv0_in: port@0 { 1012 #address-cells = <1>; 1013 #size-cells = <0>; 1014 reg = <0>; 1015 1016 tcon_tv0_in_tcon_top_mixer0: endpoint@0 { 1017 reg = <0>; 1018 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>; 1019 }; 1020 1021 tcon_tv0_in_tcon_top_mixer1: endpoint@1 { 1022 reg = <1>; 1023 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>; 1024 }; 1025 }; 1026 1027 tcon_tv0_out: port@1 { 1028 #address-cells = <1>; 1029 #size-cells = <0>; 1030 reg = <1>; 1031 1032 tcon_tv0_out_tcon_top: endpoint@1 { 1033 reg = <1>; 1034 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>; 1035 }; 1036 }; 1037 }; 1038 }; 1039 1040 tcon_tv1: lcd-controller@1c74000 { 1041 compatible = "allwinner,sun8i-r40-tcon-tv"; 1042 reg = <0x01c74000 0x1000>; 1043 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1044 clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top CLK_TCON_TOP_TV1>; 1045 clock-names = "ahb", "tcon-ch1"; 1046 resets = <&ccu RST_BUS_TCON_TV1>; 1047 reset-names = "lcd"; 1048 status = "disabled"; 1049 1050 ports { 1051 #address-cells = <1>; 1052 #size-cells = <0>; 1053 1054 tcon_tv1_in: port@0 { 1055 #address-cells = <1>; 1056 #size-cells = <0>; 1057 reg = <0>; 1058 1059 tcon_tv1_in_tcon_top_mixer0: endpoint@0 { 1060 reg = <0>; 1061 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv1>; 1062 }; 1063 1064 tcon_tv1_in_tcon_top_mixer1: endpoint@1 { 1065 reg = <1>; 1066 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv1>; 1067 }; 1068 }; 1069 1070 tcon_tv1_out: port@1 { 1071 #address-cells = <1>; 1072 #size-cells = <0>; 1073 reg = <1>; 1074 1075 tcon_tv1_out_tcon_top: endpoint@1 { 1076 reg = <1>; 1077 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv1>; 1078 }; 1079 }; 1080 }; 1081 }; 1082 1083 gic: interrupt-controller@1c81000 { 1084 compatible = "arm,gic-400"; 1085 reg = <0x01c81000 0x1000>, 1086 <0x01c82000 0x2000>, 1087 <0x01c84000 0x2000>, 1088 <0x01c86000 0x2000>; 1089 interrupt-controller; 1090 #interrupt-cells = <3>; 1091 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1092 }; 1093 1094 hdmi: hdmi@1ee0000 { 1095 compatible = "allwinner,sun8i-r40-dw-hdmi", 1096 "allwinner,sun8i-a83t-dw-hdmi"; 1097 reg = <0x01ee0000 0x10000>; 1098 reg-io-width = <1>; 1099 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 1100 clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>, 1101 <&ccu CLK_HDMI>; 1102 clock-names = "iahb", "isfr", "tmds"; 1103 resets = <&ccu RST_BUS_HDMI1>; 1104 reset-names = "ctrl"; 1105 phys = <&hdmi_phy>; 1106 phy-names = "phy"; 1107 status = "disabled"; 1108 1109 ports { 1110 #address-cells = <1>; 1111 #size-cells = <0>; 1112 1113 hdmi_in: port@0 { 1114 reg = <0>; 1115 1116 hdmi_in_tcon_top: endpoint { 1117 remote-endpoint = <&tcon_top_hdmi_out_hdmi>; 1118 }; 1119 }; 1120 1121 hdmi_out: port@1 { 1122 reg = <1>; 1123 }; 1124 }; 1125 }; 1126 1127 hdmi_phy: hdmi-phy@1ef0000 { 1128 compatible = "allwinner,sun8i-r40-hdmi-phy"; 1129 reg = <0x01ef0000 0x10000>; 1130 clocks = <&ccu CLK_BUS_HDMI1>, <&ccu CLK_HDMI_SLOW>, 1131 <&ccu CLK_PLL_VIDEO0>, <&ccu CLK_PLL_VIDEO1>; 1132 clock-names = "bus", "mod", "pll-0", "pll-1"; 1133 resets = <&ccu RST_BUS_HDMI0>; 1134 reset-names = "phy"; 1135 #phy-cells = <0>; 1136 }; 1137 }; 1138 1139 pmu { 1140 compatible = "arm,cortex-a7-pmu"; 1141 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1142 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1143 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1144 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 1145 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 1146 }; 1147 1148 timer { 1149 compatible = "arm,armv7-timer"; 1150 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1151 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1152 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1153 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1154 }; 1155}; 1156
