1/*
2 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 *  a) This file is free software; you can redistribute it and/or
10 *     modify it under the terms of the GNU General Public License as
11 *     published by the Free Software Foundation; either version 2 of the
12 *     License, or (at your option) any later version.
13 *
14 *     This file is distributed in the hope that it will be useful,
15 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
16 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17 *     GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 *  b) Permission is hereby granted, free of charge, to any person
22 *     obtaining a copy of this software and associated documentation
23 *     files (the "Software"), to deal in the Software without
24 *     restriction, including without limitation the rights to use,
25 *     copy, modify, merge, publish, distribute, sublicense, and/or
26 *     sell copies of the Software, and to permit persons to whom the
27 *     Software is furnished to do so, subject to the following
28 *     conditions:
29 *
30 *     The above copyright notice and this permission notice shall be
31 *     included in all copies or substantial portions of the Software.
32 *
33 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 *     OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43#include "sunxi-h3-h5.dtsi"
44#include <dt-bindings/thermal/thermal.h>
45
46/ {
47	cpu0_opp_table: opp_table0 {
48		compatible = "operating-points-v2";
49		opp-shared;
50
51		opp-648000000 {
52			opp-hz = /bits/ 64 <648000000>;
53			opp-microvolt = <1040000 1040000 1300000>;
54			clock-latency-ns = <244144>; /* 8 32k periods */
55		};
56
57		opp-816000000 {
58			opp-hz = /bits/ 64 <816000000>;
59			opp-microvolt = <1100000 1100000 1300000>;
60			clock-latency-ns = <244144>; /* 8 32k periods */
61		};
62
63		opp-1008000000 {
64			opp-hz = /bits/ 64 <1008000000>;
65			opp-microvolt = <1200000 1200000 1300000>;
66			clock-latency-ns = <244144>; /* 8 32k periods */
67		};
68	};
69
70	cpus {
71		#address-cells = <1>;
72		#size-cells = <0>;
73
74		cpu0: cpu@0 {
75			compatible = "arm,cortex-a7";
76			device_type = "cpu";
77			reg = <0>;
78			clocks = <&ccu CLK_CPUX>;
79			clock-names = "cpu";
80			operating-points-v2 = <&cpu0_opp_table>;
81			#cooling-cells = <2>;
82		};
83
84		cpu1: cpu@1 {
85			compatible = "arm,cortex-a7";
86			device_type = "cpu";
87			reg = <1>;
88			clocks = <&ccu CLK_CPUX>;
89			clock-names = "cpu";
90			operating-points-v2 = <&cpu0_opp_table>;
91			#cooling-cells = <2>;
92		};
93
94		cpu2: cpu@2 {
95			compatible = "arm,cortex-a7";
96			device_type = "cpu";
97			reg = <2>;
98			clocks = <&ccu CLK_CPUX>;
99			clock-names = "cpu";
100			operating-points-v2 = <&cpu0_opp_table>;
101			#cooling-cells = <2>;
102		};
103
104		cpu3: cpu@3 {
105			compatible = "arm,cortex-a7";
106			device_type = "cpu";
107			reg = <3>;
108			clocks = <&ccu CLK_CPUX>;
109			clock-names = "cpu";
110			operating-points-v2 = <&cpu0_opp_table>;
111			#cooling-cells = <2>;
112		};
113	};
114
115	gpu_opp_table: gpu-opp-table {
116		compatible = "operating-points-v2";
117
118		opp-120000000 {
119			opp-hz = /bits/ 64 <120000000>;
120		};
121
122		opp-312000000 {
123			opp-hz = /bits/ 64 <312000000>;
124		};
125
126		opp-432000000 {
127			opp-hz = /bits/ 64 <432000000>;
128		};
129
130		opp-576000000 {
131			opp-hz = /bits/ 64 <576000000>;
132		};
133	};
134
135	pmu {
136		compatible = "arm,cortex-a7-pmu";
137		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
138			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
139			     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
140			     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
141		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
142	};
143
144	timer {
145		compatible = "arm,armv7-timer";
146		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
147			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
148			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
149			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
150	};
151
152	soc {
153		deinterlace: deinterlace@1400000 {
154			compatible = "allwinner,sun8i-h3-deinterlace";
155			reg = <0x01400000 0x20000>;
156			clocks = <&ccu CLK_BUS_DEINTERLACE>,
157				 <&ccu CLK_DEINTERLACE>,
158				 <&ccu CLK_DRAM_DEINTERLACE>;
159			clock-names = "bus", "mod", "ram";
160			resets = <&ccu RST_BUS_DEINTERLACE>;
161			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
162			interconnects = <&mbus 9>;
163			interconnect-names = "dma-mem";
164		};
165
166		syscon: system-control@1c00000 {
167			compatible = "allwinner,sun8i-h3-system-control";
168			reg = <0x01c00000 0x1000>;
169			#address-cells = <1>;
170			#size-cells = <1>;
171			ranges;
172
173			sram_c: sram@1d00000 {
174				compatible = "mmio-sram";
175				reg = <0x01d00000 0x80000>;
176				#address-cells = <1>;
177				#size-cells = <1>;
178				ranges = <0 0x01d00000 0x80000>;
179
180				ve_sram: sram-section@0 {
181					compatible = "allwinner,sun8i-h3-sram-c1",
182						     "allwinner,sun4i-a10-sram-c1";
183					reg = <0x000000 0x80000>;
184				};
185			};
186		};
187
188		video-codec@1c0e000 {
189			compatible = "allwinner,sun8i-h3-video-engine";
190			reg = <0x01c0e000 0x1000>;
191			clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
192				 <&ccu CLK_DRAM_VE>;
193			clock-names = "ahb", "mod", "ram";
194			resets = <&ccu RST_BUS_VE>;
195			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
196			allwinner,sram = <&ve_sram 1>;
197		};
198
199		crypto: crypto@1c15000 {
200			compatible = "allwinner,sun8i-h3-crypto";
201			reg = <0x01c15000 0x1000>;
202			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
203			clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
204			clock-names = "bus", "mod";
205			resets = <&ccu RST_BUS_CE>;
206		};
207
208		mali: gpu@1c40000 {
209			compatible = "allwinner,sun8i-h3-mali", "arm,mali-400";
210			reg = <0x01c40000 0x10000>;
211			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
212				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
213				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
214				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
215				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
216				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
217				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
218			interrupt-names = "gp",
219					  "gpmmu",
220					  "pp0",
221					  "ppmmu0",
222					  "pp1",
223					  "ppmmu1",
224					  "pmu";
225			clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
226			clock-names = "bus", "core";
227			resets = <&ccu RST_BUS_GPU>;
228			operating-points-v2 = <&gpu_opp_table>;
229		};
230
231		ths: thermal-sensor@1c25000 {
232			compatible = "allwinner,sun8i-h3-ths";
233			reg = <0x01c25000 0x400>;
234			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
235			resets = <&ccu RST_BUS_THS>;
236			clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
237			clock-names = "bus", "mod";
238			nvmem-cells = <&ths_calibration>;
239			nvmem-cell-names = "calibration";
240			#thermal-sensor-cells = <0>;
241		};
242	};
243
244	thermal-zones {
245		cpu_thermal: cpu-thermal {
246			polling-delay-passive = <0>;
247			polling-delay = <0>;
248			thermal-sensors = <&ths 0>;
249
250			trips {
251				cpu_hot_trip: cpu-hot {
252					temperature = <80000>;
253					hysteresis = <2000>;
254					type = "passive";
255				};
256
257				cpu_very_hot_trip: cpu-very-hot {
258					temperature = <100000>;
259					hysteresis = <0>;
260					type = "critical";
261				};
262			};
263
264			cooling-maps {
265				cpu-hot-limit {
266					trip = <&cpu_hot_trip>;
267					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
268							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
269							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
270							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
271				};
272			};
273		};
274	};
275};
276
277&ccu {
278	compatible = "allwinner,sun8i-h3-ccu";
279};
280
281&display_clocks {
282	compatible = "allwinner,sun8i-h3-de2-clk";
283};
284
285&mmc0 {
286	compatible = "allwinner,sun7i-a20-mmc";
287	clocks = <&ccu CLK_BUS_MMC0>,
288		 <&ccu CLK_MMC0>,
289		 <&ccu CLK_MMC0_OUTPUT>,
290		 <&ccu CLK_MMC0_SAMPLE>;
291	clock-names = "ahb",
292		      "mmc",
293		      "output",
294		      "sample";
295};
296
297&mmc1 {
298	compatible = "allwinner,sun7i-a20-mmc";
299	clocks = <&ccu CLK_BUS_MMC1>,
300		 <&ccu CLK_MMC1>,
301		 <&ccu CLK_MMC1_OUTPUT>,
302		 <&ccu CLK_MMC1_SAMPLE>;
303	clock-names = "ahb",
304		      "mmc",
305		      "output",
306		      "sample";
307};
308
309&mmc2 {
310	compatible = "allwinner,sun7i-a20-mmc";
311	clocks = <&ccu CLK_BUS_MMC2>,
312		 <&ccu CLK_MMC2>,
313		 <&ccu CLK_MMC2_OUTPUT>,
314		 <&ccu CLK_MMC2_SAMPLE>;
315	clock-names = "ahb",
316		      "mmc",
317		      "output",
318		      "sample";
319};
320
321&pio {
322	compatible = "allwinner,sun8i-h3-pinctrl";
323};
324
325&rtc {
326	compatible = "allwinner,sun8i-h3-rtc";
327};
328
329&sid {
330	compatible = "allwinner,sun8i-h3-sid";
331};
332