1/*
2 * Copyright 2013 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 *  a) This file is free software; you can redistribute it and/or
12 *     modify it under the terms of the GNU General Public License as
13 *     published by the Free Software Foundation; either version 2 of the
14 *     License, or (at your option) any later version.
15 *
16 *     This file is distributed in the hope that it will be useful,
17 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
18 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19 *     GNU General Public License for more details.
20 *
21 * Or, alternatively,
22 *
23 *  b) Permission is hereby granted, free of charge, to any person
24 *     obtaining a copy of this software and associated documentation
25 *     files (the "Software"), to deal in the Software without
26 *     restriction, including without limitation the rights to use,
27 *     copy, modify, merge, publish, distribute, sublicense, and/or
28 *     sell copies of the Software, and to permit persons to whom the
29 *     Software is furnished to do so, subject to the following
30 *     conditions:
31 *
32 *     The above copyright notice and this permission notice shall be
33 *     included in all copies or substantial portions of the Software.
34 *
35 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 *     OTHER DEALINGS IN THE SOFTWARE.
43 */
44
45#include "skeleton.dtsi"
46
47#include <dt-bindings/interrupt-controller/arm-gic.h>
48#include <dt-bindings/thermal/thermal.h>
49#include <dt-bindings/dma/sun4i-a10.h>
50#include <dt-bindings/clock/sun7i-a20-ccu.h>
51#include <dt-bindings/reset/sun4i-a10-ccu.h>
52
53/ {
54	interrupt-parent = <&gic>;
55
56	aliases {
57		ethernet0 = &gmac;
58	};
59
60	chosen {
61		#address-cells = <1>;
62		#size-cells = <1>;
63		ranges;
64
65		framebuffer@0 {
66			compatible = "allwinner,simple-framebuffer",
67				     "simple-framebuffer";
68			allwinner,pipeline = "de_be0-lcd0-hdmi";
69			clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
70				 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
71				 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>,
72				 <&ccu CLK_HDMI>;
73			status = "disabled";
74		};
75
76		framebuffer@1 {
77			compatible = "allwinner,simple-framebuffer",
78				     "simple-framebuffer";
79			allwinner,pipeline = "de_be0-lcd0";
80			clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>,
81				 <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH0>,
82				 <&ccu CLK_DRAM_DE_BE0>;
83			status = "disabled";
84		};
85
86		framebuffer@2 {
87			compatible = "allwinner,simple-framebuffer",
88				     "simple-framebuffer";
89			allwinner,pipeline = "de_be0-lcd0-tve0";
90			clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>,
91				 <&ccu CLK_AHB_DE_BE0>,
92				 <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH1>,
93				 <&ccu CLK_DRAM_TVE0>, <&ccu CLK_DRAM_DE_BE0>;
94			status = "disabled";
95		};
96	};
97
98	cpus {
99		#address-cells = <1>;
100		#size-cells = <0>;
101
102		cpu0: cpu@0 {
103			compatible = "arm,cortex-a7";
104			device_type = "cpu";
105			reg = <0>;
106			clocks = <&ccu CLK_CPU>;
107			clock-latency = <244144>; /* 8 32k periods */
108			operating-points = <
109				/* kHz	  uV */
110				960000	1400000
111				912000	1400000
112				864000	1300000
113				720000	1200000
114				528000	1100000
115				312000	1000000
116				144000	1000000
117				>;
118			#cooling-cells = <2>;
119		};
120
121		cpu@1 {
122			compatible = "arm,cortex-a7";
123			device_type = "cpu";
124			reg = <1>;
125			clocks = <&ccu CLK_CPU>;
126			clock-latency = <244144>; /* 8 32k periods */
127			operating-points = <
128				/* kHz	  uV */
129				960000	1400000
130				912000	1400000
131				864000	1300000
132				720000	1200000
133				528000	1100000
134				312000	1000000
135				144000	1000000
136				>;
137			#cooling-cells = <2>;
138		};
139	};
140
141	thermal-zones {
142		cpu_thermal {
143			/* milliseconds */
144			polling-delay-passive = <250>;
145			polling-delay = <1000>;
146			thermal-sensors = <&rtp>;
147
148			cooling-maps {
149				map0 {
150					trip = <&cpu_alert0>;
151					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
152				};
153			};
154
155			trips {
156				cpu_alert0: cpu_alert0 {
157					/* milliCelsius */
158					temperature = <75000>;
159					hysteresis = <2000>;
160					type = "passive";
161				};
162
163				cpu_crit: cpu_crit {
164					/* milliCelsius */
165					temperature = <100000>;
166					hysteresis = <2000>;
167					type = "critical";
168				};
169			};
170		};
171	};
172
173	memory {
174		reg = <0x40000000 0x80000000>;
175	};
176
177	timer {
178		compatible = "arm,armv7-timer";
179		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
180			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
181			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
182			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
183	};
184
185	pmu {
186		compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
187		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
188			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
189	};
190
191	clocks {
192		#address-cells = <1>;
193		#size-cells = <1>;
194		ranges;
195
196		osc24M: clk@1c20050 {
197			#clock-cells = <0>;
198			compatible = "fixed-clock";
199			clock-frequency = <24000000>;
200			clock-output-names = "osc24M";
201		};
202
203		osc32k: clk@0 {
204			#clock-cells = <0>;
205			compatible = "fixed-clock";
206			clock-frequency = <32768>;
207			clock-output-names = "osc32k";
208		};
209
210		/*
211		 * The following two are dummy clocks, placeholders
212		 * used in the gmac_tx clock. The gmac driver will
213		 * choose one parent depending on the PHY interface
214		 * mode, using clk_set_rate auto-reparenting.
215		 *
216		 * The actual TX clock rate is not controlled by the
217		 * gmac_tx clock.
218		 */
219		mii_phy_tx_clk: clk@1 {
220			#clock-cells = <0>;
221			compatible = "fixed-clock";
222			clock-frequency = <25000000>;
223			clock-output-names = "mii_phy_tx";
224		};
225
226		gmac_int_tx_clk: clk@2 {
227			#clock-cells = <0>;
228			compatible = "fixed-clock";
229			clock-frequency = <125000000>;
230			clock-output-names = "gmac_int_tx";
231		};
232
233		gmac_tx_clk: clk@1c20164 {
234			#clock-cells = <0>;
235			compatible = "allwinner,sun7i-a20-gmac-clk";
236			reg = <0x01c20164 0x4>;
237			clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
238			clock-output-names = "gmac_tx";
239		};
240	};
241
242
243	de: display-engine {
244		compatible = "allwinner,sun7i-a20-display-engine";
245		allwinner,pipelines = <&fe0>, <&fe1>;
246		status = "disabled";
247	};
248
249	soc@1c00000 {
250		compatible = "simple-bus";
251		#address-cells = <1>;
252		#size-cells = <1>;
253		ranges;
254
255		system-control@1c00000 {
256			compatible = "allwinner,sun7i-a20-system-control",
257				     "allwinner,sun4i-a10-system-control";
258			reg = <0x01c00000 0x30>;
259			#address-cells = <1>;
260			#size-cells = <1>;
261			ranges;
262
263			sram_a: sram@0 {
264				compatible = "mmio-sram";
265				reg = <0x00000000 0xc000>;
266				#address-cells = <1>;
267				#size-cells = <1>;
268				ranges = <0 0x00000000 0xc000>;
269
270				emac_sram: sram-section@8000 {
271					compatible = "allwinner,sun7i-a20-sram-a3-a4",
272						     "allwinner,sun4i-a10-sram-a3-a4";
273					reg = <0x8000 0x4000>;
274					status = "disabled";
275				};
276			};
277
278			sram_d: sram@10000 {
279				compatible = "mmio-sram";
280				reg = <0x00010000 0x1000>;
281				#address-cells = <1>;
282				#size-cells = <1>;
283				ranges = <0 0x00010000 0x1000>;
284
285				otg_sram: sram-section@0 {
286					compatible = "allwinner,sun7i-a20-sram-d",
287						     "allwinner,sun4i-a10-sram-d";
288					reg = <0x0000 0x1000>;
289					status = "disabled";
290				};
291			};
292
293			sram_c: sram@1d00000 {
294				compatible = "mmio-sram";
295				reg = <0x01d00000 0xd0000>;
296				#address-cells = <1>;
297				#size-cells = <1>;
298				ranges = <0 0x01d00000 0xd0000>;
299
300				ve_sram: sram-section@0 {
301					compatible = "allwinner,sun7i-a20-sram-c1",
302						     "allwinner,sun4i-a10-sram-c1";
303					reg = <0x000000 0x80000>;
304				};
305			};
306		};
307
308		nmi_intc: interrupt-controller@1c00030 {
309			compatible = "allwinner,sun7i-a20-sc-nmi";
310			interrupt-controller;
311			#interrupt-cells = <2>;
312			reg = <0x01c00030 0x0c>;
313			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
314		};
315
316		dma: dma-controller@1c02000 {
317			compatible = "allwinner,sun4i-a10-dma";
318			reg = <0x01c02000 0x1000>;
319			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
320			clocks = <&ccu CLK_AHB_DMA>;
321			#dma-cells = <2>;
322		};
323
324		nfc: nand@1c03000 {
325			compatible = "allwinner,sun4i-a10-nand";
326			reg = <0x01c03000 0x1000>;
327			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
328			clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
329			clock-names = "ahb", "mod";
330			dmas = <&dma SUN4I_DMA_DEDICATED 3>;
331			dma-names = "rxtx";
332			status = "disabled";
333			#address-cells = <1>;
334			#size-cells = <0>;
335		};
336
337		spi0: spi@1c05000 {
338			compatible = "allwinner,sun4i-a10-spi";
339			reg = <0x01c05000 0x1000>;
340			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
341			clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
342			clock-names = "ahb", "mod";
343			dmas = <&dma SUN4I_DMA_DEDICATED 27>,
344			       <&dma SUN4I_DMA_DEDICATED 26>;
345			dma-names = "rx", "tx";
346			status = "disabled";
347			#address-cells = <1>;
348			#size-cells = <0>;
349			num-cs = <4>;
350		};
351
352		spi1: spi@1c06000 {
353			compatible = "allwinner,sun4i-a10-spi";
354			reg = <0x01c06000 0x1000>;
355			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
356			clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
357			clock-names = "ahb", "mod";
358			dmas = <&dma SUN4I_DMA_DEDICATED 9>,
359			       <&dma SUN4I_DMA_DEDICATED 8>;
360			dma-names = "rx", "tx";
361			status = "disabled";
362			#address-cells = <1>;
363			#size-cells = <0>;
364			num-cs = <1>;
365		};
366
367		emac: ethernet@1c0b000 {
368			compatible = "allwinner,sun4i-a10-emac";
369			reg = <0x01c0b000 0x1000>;
370			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
371			clocks = <&ccu CLK_AHB_EMAC>;
372			allwinner,sram = <&emac_sram 1>;
373			status = "disabled";
374		};
375
376		mdio: mdio@1c0b080 {
377			compatible = "allwinner,sun4i-a10-mdio";
378			reg = <0x01c0b080 0x14>;
379			status = "disabled";
380			#address-cells = <1>;
381			#size-cells = <0>;
382		};
383
384		tcon0: lcd-controller@1c0c000 {
385			compatible = "allwinner,sun7i-a20-tcon";
386			reg = <0x01c0c000 0x1000>;
387			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
388			resets = <&ccu RST_TCON0>;
389			reset-names = "lcd";
390			clocks = <&ccu CLK_AHB_LCD0>,
391				 <&ccu CLK_TCON0_CH0>,
392				 <&ccu CLK_TCON0_CH1>;
393			clock-names = "ahb",
394				      "tcon-ch0",
395				      "tcon-ch1";
396			clock-output-names = "tcon0-pixel-clock";
397			dmas = <&dma SUN4I_DMA_DEDICATED 14>;
398
399			ports {
400				#address-cells = <1>;
401				#size-cells = <0>;
402
403				tcon0_in: port@0 {
404					#address-cells = <1>;
405					#size-cells = <0>;
406					reg = <0>;
407
408					tcon0_in_be0: endpoint@0 {
409						reg = <0>;
410						remote-endpoint = <&be0_out_tcon0>;
411					};
412
413					tcon0_in_be1: endpoint@1 {
414						reg = <1>;
415						remote-endpoint = <&be1_out_tcon0>;
416					};
417				};
418
419				tcon0_out: port@1 {
420					#address-cells = <1>;
421					#size-cells = <0>;
422					reg = <1>;
423
424					tcon0_out_hdmi: endpoint@1 {
425						reg = <1>;
426						remote-endpoint = <&hdmi_in_tcon0>;
427						allwinner,tcon-channel = <1>;
428					};
429				};
430			};
431		};
432
433		tcon1: lcd-controller@1c0d000 {
434			compatible = "allwinner,sun7i-a20-tcon";
435			reg = <0x01c0d000 0x1000>;
436			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
437			resets = <&ccu RST_TCON1>;
438			reset-names = "lcd";
439			clocks = <&ccu CLK_AHB_LCD1>,
440				 <&ccu CLK_TCON1_CH0>,
441				 <&ccu CLK_TCON1_CH1>;
442			clock-names = "ahb",
443				      "tcon-ch0",
444				      "tcon-ch1";
445			clock-output-names = "tcon1-pixel-clock";
446			dmas = <&dma SUN4I_DMA_DEDICATED 15>;
447
448			ports {
449				#address-cells = <1>;
450				#size-cells = <0>;
451
452				tcon1_in: port@0 {
453					#address-cells = <1>;
454					#size-cells = <0>;
455					reg = <0>;
456
457					tcon1_in_be0: endpoint@0 {
458						reg = <0>;
459						remote-endpoint = <&be0_out_tcon1>;
460					};
461
462					tcon1_in_be1: endpoint@1 {
463						reg = <1>;
464						remote-endpoint = <&be1_out_tcon1>;
465					};
466				};
467
468				tcon1_out: port@1 {
469					#address-cells = <1>;
470					#size-cells = <0>;
471					reg = <1>;
472
473					tcon1_out_hdmi: endpoint@1 {
474						reg = <1>;
475						remote-endpoint = <&hdmi_in_tcon1>;
476						allwinner,tcon-channel = <1>;
477					};
478				};
479			};
480		};
481
482		mmc0: mmc@1c0f000 {
483			compatible = "allwinner,sun7i-a20-mmc";
484			reg = <0x01c0f000 0x1000>;
485			clocks = <&ccu CLK_AHB_MMC0>,
486				 <&ccu CLK_MMC0>,
487				 <&ccu CLK_MMC0_OUTPUT>,
488				 <&ccu CLK_MMC0_SAMPLE>;
489			clock-names = "ahb",
490				      "mmc",
491				      "output",
492				      "sample";
493			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
494			status = "disabled";
495			#address-cells = <1>;
496			#size-cells = <0>;
497		};
498
499		mmc1: mmc@1c10000 {
500			compatible = "allwinner,sun7i-a20-mmc";
501			reg = <0x01c10000 0x1000>;
502			clocks = <&ccu CLK_AHB_MMC1>,
503				 <&ccu CLK_MMC1>,
504				 <&ccu CLK_MMC1_OUTPUT>,
505				 <&ccu CLK_MMC1_SAMPLE>;
506			clock-names = "ahb",
507				      "mmc",
508				      "output",
509				      "sample";
510			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
511			status = "disabled";
512			#address-cells = <1>;
513			#size-cells = <0>;
514		};
515
516		mmc2: mmc@1c11000 {
517			compatible = "allwinner,sun7i-a20-mmc";
518			reg = <0x01c11000 0x1000>;
519			clocks = <&ccu CLK_AHB_MMC2>,
520				 <&ccu CLK_MMC2>,
521				 <&ccu CLK_MMC2_OUTPUT>,
522				 <&ccu CLK_MMC2_SAMPLE>;
523			clock-names = "ahb",
524				      "mmc",
525				      "output",
526				      "sample";
527			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
528			status = "disabled";
529			#address-cells = <1>;
530			#size-cells = <0>;
531		};
532
533		mmc3: mmc@1c12000 {
534			compatible = "allwinner,sun7i-a20-mmc";
535			reg = <0x01c12000 0x1000>;
536			clocks = <&ccu CLK_AHB_MMC3>,
537				 <&ccu CLK_MMC3>,
538				 <&ccu CLK_MMC3_OUTPUT>,
539				 <&ccu CLK_MMC3_SAMPLE>;
540			clock-names = "ahb",
541				      "mmc",
542				      "output",
543				      "sample";
544			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
545			status = "disabled";
546			#address-cells = <1>;
547			#size-cells = <0>;
548		};
549
550		usb_otg: usb@1c13000 {
551			compatible = "allwinner,sun4i-a10-musb";
552			reg = <0x01c13000 0x0400>;
553			clocks = <&ccu CLK_AHB_OTG>;
554			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
555			interrupt-names = "mc";
556			phys = <&usbphy 0>;
557			phy-names = "usb";
558			extcon = <&usbphy 0>;
559			allwinner,sram = <&otg_sram 1>;
560			status = "disabled";
561		};
562
563		usbphy: phy@1c13400 {
564			#phy-cells = <1>;
565			compatible = "allwinner,sun7i-a20-usb-phy";
566			reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
567			reg-names = "phy_ctrl", "pmu1", "pmu2";
568			clocks = <&ccu CLK_USB_PHY>;
569			clock-names = "usb_phy";
570			resets = <&ccu RST_USB_PHY0>,
571				 <&ccu RST_USB_PHY1>,
572				 <&ccu RST_USB_PHY2>;
573			reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
574			status = "disabled";
575		};
576
577		ehci0: usb@1c14000 {
578			compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
579			reg = <0x01c14000 0x100>;
580			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
581			clocks = <&ccu CLK_AHB_EHCI0>;
582			phys = <&usbphy 1>;
583			phy-names = "usb";
584			status = "disabled";
585		};
586
587		ohci0: usb@1c14400 {
588			compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
589			reg = <0x01c14400 0x100>;
590			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
591			clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>;
592			phys = <&usbphy 1>;
593			phy-names = "usb";
594			status = "disabled";
595		};
596
597		crypto: crypto-engine@1c15000 {
598			compatible = "allwinner,sun7i-a20-crypto",
599				     "allwinner,sun4i-a10-crypto";
600			reg = <0x01c15000 0x1000>;
601			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
602			clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
603			clock-names = "ahb", "mod";
604		};
605
606		hdmi: hdmi@1c16000 {
607			compatible = "allwinner,sun7i-a20-hdmi",
608				     "allwinner,sun5i-a10s-hdmi";
609			reg = <0x01c16000 0x1000>;
610			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
611			clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>,
612				 <&ccu CLK_PLL_VIDEO0_2X>,
613				 <&ccu CLK_PLL_VIDEO1_2X>;
614			clock-names = "ahb", "mod", "pll-0", "pll-1";
615			dmas = <&dma SUN4I_DMA_NORMAL 16>,
616			       <&dma SUN4I_DMA_NORMAL 16>,
617			       <&dma SUN4I_DMA_DEDICATED 24>;
618			dma-names = "ddc-tx", "ddc-rx", "audio-tx";
619			status = "disabled";
620
621			ports {
622				#address-cells = <1>;
623				#size-cells = <0>;
624
625				hdmi_in: port@0 {
626					#address-cells = <1>;
627					#size-cells = <0>;
628					reg = <0>;
629
630					hdmi_in_tcon0: endpoint@0 {
631						reg = <0>;
632						remote-endpoint = <&tcon0_out_hdmi>;
633					};
634
635					hdmi_in_tcon1: endpoint@1 {
636						reg = <1>;
637						remote-endpoint = <&tcon1_out_hdmi>;
638					};
639				};
640
641				hdmi_out: port@1 {
642					#address-cells = <1>;
643					#size-cells = <0>;
644					reg = <1>;
645				};
646			};
647		};
648
649		spi2: spi@1c17000 {
650			compatible = "allwinner,sun4i-a10-spi";
651			reg = <0x01c17000 0x1000>;
652			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
653			clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
654			clock-names = "ahb", "mod";
655			dmas = <&dma SUN4I_DMA_DEDICATED 29>,
656			       <&dma SUN4I_DMA_DEDICATED 28>;
657			dma-names = "rx", "tx";
658			status = "disabled";
659			#address-cells = <1>;
660			#size-cells = <0>;
661			num-cs = <1>;
662		};
663
664		ahci: sata@1c18000 {
665			compatible = "allwinner,sun4i-a10-ahci";
666			reg = <0x01c18000 0x1000>;
667			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
668			clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>;
669			status = "disabled";
670		};
671
672		ehci1: usb@1c1c000 {
673			compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
674			reg = <0x01c1c000 0x100>;
675			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
676			clocks = <&ccu CLK_AHB_EHCI1>;
677			phys = <&usbphy 2>;
678			phy-names = "usb";
679			status = "disabled";
680		};
681
682		ohci1: usb@1c1c400 {
683			compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
684			reg = <0x01c1c400 0x100>;
685			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
686			clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>;
687			phys = <&usbphy 2>;
688			phy-names = "usb";
689			status = "disabled";
690		};
691
692		spi3: spi@1c1f000 {
693			compatible = "allwinner,sun4i-a10-spi";
694			reg = <0x01c1f000 0x1000>;
695			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
696			clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>;
697			clock-names = "ahb", "mod";
698			dmas = <&dma SUN4I_DMA_DEDICATED 31>,
699			       <&dma SUN4I_DMA_DEDICATED 30>;
700			dma-names = "rx", "tx";
701			status = "disabled";
702			#address-cells = <1>;
703			#size-cells = <0>;
704			num-cs = <1>;
705		};
706
707		ccu: clock@1c20000 {
708			compatible = "allwinner,sun7i-a20-ccu";
709			reg = <0x01c20000 0x400>;
710			clocks = <&osc24M>, <&osc32k>;
711			clock-names = "hosc", "losc";
712			#clock-cells = <1>;
713			#reset-cells = <1>;
714		};
715
716		pio: pinctrl@1c20800 {
717			compatible = "allwinner,sun7i-a20-pinctrl";
718			reg = <0x01c20800 0x400>;
719			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
720			clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
721			clock-names = "apb", "hosc", "losc";
722			gpio-controller;
723			interrupt-controller;
724			#interrupt-cells = <3>;
725			#gpio-cells = <3>;
726
727			can0_pins_a: can0@0 {
728				pins = "PH20", "PH21";
729				function = "can";
730			};
731
732			clk_out_a_pins_a: clk_out_a@0 {
733				pins = "PI12";
734				function = "clk_out_a";
735			};
736
737			clk_out_b_pins_a: clk_out_b@0 {
738				pins = "PI13";
739				function = "clk_out_b";
740			};
741
742			emac_pins_a: emac0@0 {
743				pins = "PA0", "PA1", "PA2",
744				       "PA3", "PA4", "PA5", "PA6",
745				       "PA7", "PA8", "PA9", "PA10",
746				       "PA11", "PA12", "PA13", "PA14",
747				       "PA15", "PA16";
748				function = "emac";
749			};
750
751			gmac_pins_mii_a: gmac_mii@0 {
752				pins = "PA0", "PA1", "PA2",
753				       "PA3", "PA4", "PA5", "PA6",
754				       "PA7", "PA8", "PA9", "PA10",
755				       "PA11", "PA12", "PA13", "PA14",
756				       "PA15", "PA16";
757				function = "gmac";
758			};
759
760			gmac_pins_rgmii_a: gmac_rgmii@0 {
761				pins = "PA0", "PA1", "PA2",
762				       "PA3", "PA4", "PA5", "PA6",
763				        "PA7", "PA8", "PA10",
764				       "PA11", "PA12", "PA13",
765				       "PA15", "PA16";
766				function = "gmac";
767				/*
768				 * data lines in RGMII mode use DDR mode
769				 * and need a higher signal drive strength
770				 */
771				drive-strength = <40>;
772			};
773
774			i2c0_pins_a: i2c0@0 {
775				pins = "PB0", "PB1";
776				function = "i2c0";
777			};
778
779			i2c1_pins_a: i2c1@0 {
780				pins = "PB18", "PB19";
781				function = "i2c1";
782			};
783
784			i2c2_pins_a: i2c2@0 {
785				pins = "PB20", "PB21";
786				function = "i2c2";
787			};
788
789			i2c3_pins_a: i2c3@0 {
790				pins = "PI0", "PI1";
791				function = "i2c3";
792			};
793
794			ir0_rx_pins_a: ir0@0 {
795				pins = "PB4";
796				function = "ir0";
797			};
798
799			ir0_tx_pins_a: ir0@1 {
800				pins = "PB3";
801				function = "ir0";
802			};
803
804			ir1_rx_pins_a: ir1@0 {
805				pins = "PB23";
806				function = "ir1";
807			};
808
809			ir1_tx_pins_a: ir1@1 {
810				pins = "PB22";
811				function = "ir1";
812			};
813
814			mmc0_pins_a: mmc0@0 {
815				pins = "PF0", "PF1", "PF2",
816				       "PF3", "PF4", "PF5";
817				function = "mmc0";
818				drive-strength = <30>;
819				bias-pull-up;
820			};
821
822			mmc2_pins_a: mmc2@0 {
823				pins = "PC6", "PC7", "PC8",
824				       "PC9", "PC10", "PC11";
825				function = "mmc2";
826				drive-strength = <30>;
827				bias-pull-up;
828			};
829
830			mmc3_pins_a: mmc3@0 {
831				pins = "PI4", "PI5", "PI6",
832				       "PI7", "PI8", "PI9";
833				function = "mmc3";
834				drive-strength = <30>;
835				bias-pull-up;
836			};
837
838			ps20_pins_a: ps20@0 {
839				pins = "PI20", "PI21";
840				function = "ps2";
841			};
842
843			ps21_pins_a: ps21@0 {
844				pins = "PH12", "PH13";
845				function = "ps2";
846			};
847
848			pwm0_pins_a: pwm0@0 {
849				pins = "PB2";
850				function = "pwm";
851			};
852
853			pwm1_pins_a: pwm1@0 {
854				pins = "PI3";
855				function = "pwm";
856			};
857
858			spdif_tx_pins_a: spdif@0 {
859				pins = "PB13";
860				function = "spdif";
861				bias-pull-up;
862			};
863
864			spi0_pins_a: spi0@0 {
865				pins = "PI11", "PI12", "PI13";
866				function = "spi0";
867			};
868
869			spi0_cs0_pins_a: spi0_cs0@0 {
870				pins = "PI10";
871				function = "spi0";
872			};
873
874			spi0_cs1_pins_a: spi0_cs1@0 {
875				pins = "PI14";
876				function = "spi0";
877			};
878
879			spi1_pins_a: spi1@0 {
880				pins = "PI17", "PI18", "PI19";
881				function = "spi1";
882			};
883
884			spi1_cs0_pins_a: spi1_cs0@0 {
885				pins = "PI16";
886				function = "spi1";
887			};
888
889			spi2_pins_a: spi2@0 {
890				pins = "PC20", "PC21", "PC22";
891				function = "spi2";
892			};
893
894			spi2_pins_b: spi2@1 {
895				pins = "PB15", "PB16", "PB17";
896				function = "spi2";
897			};
898
899			spi2_cs0_pins_a: spi2_cs0@0 {
900				pins = "PC19";
901				function = "spi2";
902			};
903
904			spi2_cs0_pins_b: spi2_cs0@1 {
905				pins = "PB14";
906				function = "spi2";
907			};
908
909			uart0_pins_a: uart0@0 {
910				pins = "PB22", "PB23";
911				function = "uart0";
912			};
913
914			uart2_pins_a: uart2@0 {
915				pins = "PI16", "PI17", "PI18", "PI19";
916				function = "uart2";
917			};
918
919			uart3_pins_a: uart3@0 {
920				pins = "PG6", "PG7", "PG8", "PG9";
921				function = "uart3";
922			};
923
924			uart3_pins_b: uart3@1 {
925				pins = "PH0", "PH1";
926				function = "uart3";
927			};
928
929			uart4_pins_a: uart4@0 {
930				pins = "PG10", "PG11";
931				function = "uart4";
932			};
933
934			uart4_pins_b: uart4@1 {
935				pins = "PH4", "PH5";
936				function = "uart4";
937			};
938
939			uart5_pins_a: uart5@0 {
940				pins = "PI10", "PI11";
941				function = "uart5";
942			};
943
944			uart6_pins_a: uart6@0 {
945				pins = "PI12", "PI13";
946				function = "uart6";
947			};
948
949			uart7_pins_a: uart7@0 {
950				pins = "PI20", "PI21";
951				function = "uart7";
952			};
953		};
954
955		timer@1c20c00 {
956			compatible = "allwinner,sun4i-a10-timer";
957			reg = <0x01c20c00 0x90>;
958			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
959				     <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
960				     <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
961				     <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
962				     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
963				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
964			clocks = <&osc24M>;
965		};
966
967		wdt: watchdog@1c20c90 {
968			compatible = "allwinner,sun4i-a10-wdt";
969			reg = <0x01c20c90 0x10>;
970		};
971
972		rtc: rtc@1c20d00 {
973			compatible = "allwinner,sun7i-a20-rtc";
974			reg = <0x01c20d00 0x20>;
975			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
976		};
977
978		pwm: pwm@1c20e00 {
979			compatible = "allwinner,sun7i-a20-pwm";
980			reg = <0x01c20e00 0xc>;
981			clocks = <&osc24M>;
982			#pwm-cells = <3>;
983			status = "disabled";
984		};
985
986		spdif: spdif@1c21000 {
987			#sound-dai-cells = <0>;
988			compatible = "allwinner,sun4i-a10-spdif";
989			reg = <0x01c21000 0x400>;
990			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
991			clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>;
992			clock-names = "apb", "spdif";
993			dmas = <&dma SUN4I_DMA_NORMAL 2>,
994			       <&dma SUN4I_DMA_NORMAL 2>;
995			dma-names = "rx", "tx";
996			status = "disabled";
997		};
998
999		ir0: ir@1c21800 {
1000			compatible = "allwinner,sun4i-a10-ir";
1001			clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>;
1002			clock-names = "apb", "ir";
1003			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1004			reg = <0x01c21800 0x40>;
1005			status = "disabled";
1006		};
1007
1008		ir1: ir@1c21c00 {
1009			compatible = "allwinner,sun4i-a10-ir";
1010			clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>;
1011			clock-names = "apb", "ir";
1012			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1013			reg = <0x01c21c00 0x40>;
1014			status = "disabled";
1015		};
1016
1017		i2s1: i2s@1c22000 {
1018			#sound-dai-cells = <0>;
1019			compatible = "allwinner,sun4i-a10-i2s";
1020			reg = <0x01c22000 0x400>;
1021			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1022			clocks = <&ccu CLK_APB0_I2S1>, <&ccu CLK_I2S1>;
1023			clock-names = "apb", "mod";
1024			dmas = <&dma SUN4I_DMA_NORMAL 4>,
1025			       <&dma SUN4I_DMA_NORMAL 4>;
1026			dma-names = "rx", "tx";
1027			status = "disabled";
1028		};
1029
1030		i2s0: i2s@1c22400 {
1031			#sound-dai-cells = <0>;
1032			compatible = "allwinner,sun4i-a10-i2s";
1033			reg = <0x01c22400 0x400>;
1034			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1035			clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>;
1036			clock-names = "apb", "mod";
1037			dmas = <&dma SUN4I_DMA_NORMAL 3>,
1038			       <&dma SUN4I_DMA_NORMAL 3>;
1039			dma-names = "rx", "tx";
1040			status = "disabled";
1041		};
1042
1043		lradc: lradc@1c22800 {
1044			compatible = "allwinner,sun4i-a10-lradc-keys";
1045			reg = <0x01c22800 0x100>;
1046			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1047			status = "disabled";
1048		};
1049
1050		codec: codec@1c22c00 {
1051			#sound-dai-cells = <0>;
1052			compatible = "allwinner,sun7i-a20-codec";
1053			reg = <0x01c22c00 0x40>;
1054			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1055			clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
1056			clock-names = "apb", "codec";
1057			dmas = <&dma SUN4I_DMA_NORMAL 19>,
1058			       <&dma SUN4I_DMA_NORMAL 19>;
1059			dma-names = "rx", "tx";
1060			status = "disabled";
1061		};
1062
1063		sid: eeprom@1c23800 {
1064			compatible = "allwinner,sun7i-a20-sid";
1065			reg = <0x01c23800 0x200>;
1066		};
1067
1068		i2s2: i2s@1c24400 {
1069			#sound-dai-cells = <0>;
1070			compatible = "allwinner,sun4i-a10-i2s";
1071			reg = <0x01c24400 0x400>;
1072			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1073			clocks = <&ccu CLK_APB0_I2S2>, <&ccu CLK_I2S2>;
1074			clock-names = "apb", "mod";
1075			dmas = <&dma SUN4I_DMA_NORMAL 6>,
1076			       <&dma SUN4I_DMA_NORMAL 6>;
1077			dma-names = "rx", "tx";
1078			status = "disabled";
1079		};
1080
1081		rtp: rtp@1c25000 {
1082			compatible = "allwinner,sun5i-a13-ts";
1083			reg = <0x01c25000 0x100>;
1084			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1085			#thermal-sensor-cells = <0>;
1086		};
1087
1088		uart0: serial@1c28000 {
1089			compatible = "snps,dw-apb-uart";
1090			reg = <0x01c28000 0x400>;
1091			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1092			reg-shift = <2>;
1093			reg-io-width = <4>;
1094			clocks = <&ccu CLK_APB1_UART0>;
1095			status = "disabled";
1096		};
1097
1098		uart1: serial@1c28400 {
1099			compatible = "snps,dw-apb-uart";
1100			reg = <0x01c28400 0x400>;
1101			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1102			reg-shift = <2>;
1103			reg-io-width = <4>;
1104			clocks = <&ccu CLK_APB1_UART1>;
1105			status = "disabled";
1106		};
1107
1108		uart2: serial@1c28800 {
1109			compatible = "snps,dw-apb-uart";
1110			reg = <0x01c28800 0x400>;
1111			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1112			reg-shift = <2>;
1113			reg-io-width = <4>;
1114			clocks = <&ccu CLK_APB1_UART2>;
1115			status = "disabled";
1116		};
1117
1118		uart3: serial@1c28c00 {
1119			compatible = "snps,dw-apb-uart";
1120			reg = <0x01c28c00 0x400>;
1121			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1122			reg-shift = <2>;
1123			reg-io-width = <4>;
1124			clocks = <&ccu CLK_APB1_UART3>;
1125			status = "disabled";
1126		};
1127
1128		uart4: serial@1c29000 {
1129			compatible = "snps,dw-apb-uart";
1130			reg = <0x01c29000 0x400>;
1131			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1132			reg-shift = <2>;
1133			reg-io-width = <4>;
1134			clocks = <&ccu CLK_APB1_UART4>;
1135			status = "disabled";
1136		};
1137
1138		uart5: serial@1c29400 {
1139			compatible = "snps,dw-apb-uart";
1140			reg = <0x01c29400 0x400>;
1141			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1142			reg-shift = <2>;
1143			reg-io-width = <4>;
1144			clocks = <&ccu CLK_APB1_UART5>;
1145			status = "disabled";
1146		};
1147
1148		uart6: serial@1c29800 {
1149			compatible = "snps,dw-apb-uart";
1150			reg = <0x01c29800 0x400>;
1151			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1152			reg-shift = <2>;
1153			reg-io-width = <4>;
1154			clocks = <&ccu CLK_APB1_UART6>;
1155			status = "disabled";
1156		};
1157
1158		uart7: serial@1c29c00 {
1159			compatible = "snps,dw-apb-uart";
1160			reg = <0x01c29c00 0x400>;
1161			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1162			reg-shift = <2>;
1163			reg-io-width = <4>;
1164			clocks = <&ccu CLK_APB1_UART7>;
1165			status = "disabled";
1166		};
1167
1168		ps20: ps2@1c2a000 {
1169			compatible = "allwinner,sun4i-a10-ps2";
1170			reg = <0x01c2a000 0x400>;
1171			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1172			clocks = <&ccu CLK_APB1_PS20>;
1173			status = "disabled";
1174		};
1175
1176		ps21: ps2@1c2a400 {
1177			compatible = "allwinner,sun4i-a10-ps2";
1178			reg = <0x01c2a400 0x400>;
1179			interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1180			clocks = <&ccu CLK_APB1_PS21>;
1181			status = "disabled";
1182		};
1183
1184		i2c0: i2c@1c2ac00 {
1185			compatible = "allwinner,sun7i-a20-i2c",
1186				     "allwinner,sun4i-a10-i2c";
1187			reg = <0x01c2ac00 0x400>;
1188			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1189			clocks = <&ccu CLK_APB1_I2C0>;
1190			status = "disabled";
1191			#address-cells = <1>;
1192			#size-cells = <0>;
1193		};
1194
1195		i2c1: i2c@1c2b000 {
1196			compatible = "allwinner,sun7i-a20-i2c",
1197				     "allwinner,sun4i-a10-i2c";
1198			reg = <0x01c2b000 0x400>;
1199			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1200			clocks = <&ccu CLK_APB1_I2C1>;
1201			status = "disabled";
1202			#address-cells = <1>;
1203			#size-cells = <0>;
1204		};
1205
1206		i2c2: i2c@1c2b400 {
1207			compatible = "allwinner,sun7i-a20-i2c",
1208				     "allwinner,sun4i-a10-i2c";
1209			reg = <0x01c2b400 0x400>;
1210			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1211			clocks = <&ccu CLK_APB1_I2C2>;
1212			status = "disabled";
1213			#address-cells = <1>;
1214			#size-cells = <0>;
1215		};
1216
1217		i2c3: i2c@1c2b800 {
1218			compatible = "allwinner,sun7i-a20-i2c",
1219				     "allwinner,sun4i-a10-i2c";
1220			reg = <0x01c2b800 0x400>;
1221			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1222			clocks = <&ccu CLK_APB1_I2C3>;
1223			status = "disabled";
1224			#address-cells = <1>;
1225			#size-cells = <0>;
1226		};
1227
1228		can0: can@1c2bc00 {
1229			compatible = "allwinner,sun7i-a20-can",
1230				     "allwinner,sun4i-a10-can";
1231			reg = <0x01c2bc00 0x400>;
1232			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1233			clocks = <&ccu CLK_APB1_CAN>;
1234			status = "disabled";
1235		};
1236
1237		i2c4: i2c@1c2c000 {
1238			compatible = "allwinner,sun7i-a20-i2c",
1239				     "allwinner,sun4i-a10-i2c";
1240			reg = <0x01c2c000 0x400>;
1241			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1242			clocks = <&ccu CLK_APB1_I2C4>;
1243			status = "disabled";
1244			#address-cells = <1>;
1245			#size-cells = <0>;
1246		};
1247
1248		mali: gpu@1c40000 {
1249			compatible = "allwinner,sun7i-a20-mali", "arm,mali-400";
1250			reg = <0x01c40000 0x10000>;
1251			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1252				     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
1253				     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1254				     <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
1255				     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
1256				     <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
1257				     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1258			interrupt-names = "gp",
1259					  "gpmmu",
1260					  "pp0",
1261					  "ppmmu0",
1262					  "pp1",
1263					  "ppmmu1",
1264					  "pmu";
1265			clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>;
1266			clock-names = "bus", "core";
1267			resets = <&ccu RST_GPU>;
1268
1269			assigned-clocks = <&ccu CLK_GPU>;
1270			assigned-clock-rates = <384000000>;
1271		};
1272
1273		gmac: ethernet@1c50000 {
1274			compatible = "allwinner,sun7i-a20-gmac";
1275			reg = <0x01c50000 0x10000>;
1276			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1277			interrupt-names = "macirq";
1278			clocks = <&ccu CLK_AHB_GMAC>, <&gmac_tx_clk>;
1279			clock-names = "stmmaceth", "allwinner_gmac_tx";
1280			snps,pbl = <2>;
1281			snps,fixed-burst;
1282			snps,force_sf_dma_mode;
1283			status = "disabled";
1284			#address-cells = <1>;
1285			#size-cells = <0>;
1286		};
1287
1288		hstimer@1c60000 {
1289			compatible = "allwinner,sun7i-a20-hstimer";
1290			reg = <0x01c60000 0x1000>;
1291			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
1292				     <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
1293				     <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
1294				     <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1295			clocks = <&ccu CLK_AHB_HSTIMER>;
1296		};
1297
1298		gic: interrupt-controller@1c81000 {
1299			compatible = "arm,gic-400", "arm,cortex-a7-gic", "arm,cortex-a15-gic";
1300			reg = <0x01c81000 0x1000>,
1301			      <0x01c82000 0x2000>,
1302			      <0x01c84000 0x2000>,
1303			      <0x01c86000 0x2000>;
1304			interrupt-controller;
1305			#interrupt-cells = <3>;
1306			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1307		};
1308
1309		fe0: display-frontend@1e00000 {
1310			compatible = "allwinner,sun7i-a20-display-frontend";
1311			reg = <0x01e00000 0x20000>;
1312			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1313			clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>,
1314				 <&ccu CLK_DRAM_DE_FE0>;
1315			clock-names = "ahb", "mod",
1316				      "ram";
1317			resets = <&ccu RST_DE_FE0>;
1318
1319			ports {
1320				#address-cells = <1>;
1321				#size-cells = <0>;
1322
1323				fe0_out: port@1 {
1324					#address-cells = <1>;
1325					#size-cells = <0>;
1326					reg = <1>;
1327
1328					fe0_out_be0: endpoint@0 {
1329						reg = <0>;
1330						remote-endpoint = <&be0_in_fe0>;
1331					};
1332
1333					fe0_out_be1: endpoint@1 {
1334						reg = <1>;
1335						remote-endpoint = <&be1_in_fe0>;
1336					};
1337				};
1338			};
1339		};
1340
1341		fe1: display-frontend@1e20000 {
1342			compatible = "allwinner,sun7i-a20-display-frontend";
1343			reg = <0x01e20000 0x20000>;
1344			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1345			clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>,
1346				 <&ccu CLK_DRAM_DE_FE1>;
1347			clock-names = "ahb", "mod",
1348				      "ram";
1349			resets = <&ccu RST_DE_FE1>;
1350
1351			ports {
1352				#address-cells = <1>;
1353				#size-cells = <0>;
1354
1355				fe1_out: port@1 {
1356					#address-cells = <1>;
1357					#size-cells = <0>;
1358					reg = <1>;
1359
1360					fe1_out_be0: endpoint@0 {
1361						reg = <0>;
1362						remote-endpoint = <&be0_in_fe1>;
1363					};
1364
1365					fe1_out_be1: endpoint@1 {
1366						reg = <1>;
1367						remote-endpoint = <&be1_in_fe1>;
1368					};
1369				};
1370			};
1371		};
1372
1373		be1: display-backend@1e40000 {
1374			compatible = "allwinner,sun7i-a20-display-backend";
1375			reg = <0x01e40000 0x10000>;
1376			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1377			clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>,
1378				 <&ccu CLK_DRAM_DE_BE1>;
1379			clock-names = "ahb", "mod",
1380				      "ram";
1381			resets = <&ccu RST_DE_BE1>;
1382
1383			ports {
1384				#address-cells = <1>;
1385				#size-cells = <0>;
1386
1387				be1_in: port@0 {
1388					#address-cells = <1>;
1389					#size-cells = <0>;
1390					reg = <0>;
1391
1392					be1_in_fe0: endpoint@0 {
1393						reg = <0>;
1394						remote-endpoint = <&fe0_out_be1>;
1395					};
1396
1397					be1_in_fe1: endpoint@1 {
1398						reg = <1>;
1399						remote-endpoint = <&fe1_out_be1>;
1400					};
1401				};
1402
1403				be1_out: port@1 {
1404					#address-cells = <1>;
1405					#size-cells = <0>;
1406					reg = <1>;
1407
1408					be1_out_tcon0: endpoint@0 {
1409						reg = <0>;
1410						remote-endpoint = <&tcon0_in_be1>;
1411					};
1412
1413					be1_out_tcon1: endpoint@1 {
1414						reg = <1>;
1415						remote-endpoint = <&tcon1_in_be1>;
1416					};
1417				};
1418			};
1419		};
1420
1421		be0: display-backend@1e60000 {
1422			compatible = "allwinner,sun7i-a20-display-backend";
1423			reg = <0x01e60000 0x10000>;
1424			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1425			clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
1426				 <&ccu CLK_DRAM_DE_BE0>;
1427			clock-names = "ahb", "mod",
1428				      "ram";
1429			resets = <&ccu RST_DE_BE0>;
1430
1431			ports {
1432				#address-cells = <1>;
1433				#size-cells = <0>;
1434
1435				be0_in: port@0 {
1436					#address-cells = <1>;
1437					#size-cells = <0>;
1438					reg = <0>;
1439
1440					be0_in_fe0: endpoint@0 {
1441						reg = <0>;
1442						remote-endpoint = <&fe0_out_be0>;
1443					};
1444
1445					be0_in_fe1: endpoint@1 {
1446						reg = <1>;
1447						remote-endpoint = <&fe1_out_be0>;
1448					};
1449				};
1450
1451				be0_out: port@1 {
1452					#address-cells = <1>;
1453					#size-cells = <0>;
1454					reg = <1>;
1455
1456					be0_out_tcon0: endpoint@0 {
1457						reg = <0>;
1458						remote-endpoint = <&tcon0_in_be0>;
1459					};
1460
1461					be0_out_tcon1: endpoint@1 {
1462						reg = <1>;
1463						remote-endpoint = <&tcon1_in_be0>;
1464					};
1465				};
1466			};
1467		};
1468	};
1469};
1470