1/* 2 * Copyright 2013 Maxime Ripard 3 * 4 * Maxime Ripard <maxime.ripard@free-electrons.com> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include "skeleton.dtsi" 46 47#include <dt-bindings/interrupt-controller/arm-gic.h> 48#include <dt-bindings/thermal/thermal.h> 49 50#include <dt-bindings/clock/sun6i-a31-ccu.h> 51#include <dt-bindings/reset/sun6i-a31-ccu.h> 52 53/ { 54 interrupt-parent = <&gic>; 55 56 aliases { 57 ethernet0 = &gmac; 58 }; 59 60 chosen { 61 #address-cells = <1>; 62 #size-cells = <1>; 63 ranges; 64 65 simplefb_hdmi: framebuffer@0 { 66 compatible = "allwinner,simple-framebuffer", 67 "simple-framebuffer"; 68 allwinner,pipeline = "de_be0-lcd0-hdmi"; 69 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>, 70 <&ccu CLK_AHB1_HDMI>, <&ccu CLK_DRAM_BE0>, 71 <&ccu CLK_IEP_DRC0>, <&ccu CLK_BE0>, 72 <&ccu CLK_LCD0_CH1>, <&ccu CLK_HDMI>; 73 status = "disabled"; 74 }; 75 76 simplefb_lcd: framebuffer@1 { 77 compatible = "allwinner,simple-framebuffer", 78 "simple-framebuffer"; 79 allwinner,pipeline = "de_be0-lcd0"; 80 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>, 81 <&ccu CLK_DRAM_BE0>, <&ccu CLK_IEP_DRC0>, 82 <&ccu CLK_BE0>, <&ccu CLK_LCD0_CH0>; 83 status = "disabled"; 84 }; 85 }; 86 87 timer { 88 compatible = "arm,armv7-timer"; 89 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 90 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 91 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 92 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 93 clock-frequency = <24000000>; 94 arm,cpu-registers-not-fw-configured; 95 }; 96 97 cpus { 98 enable-method = "allwinner,sun6i-a31"; 99 #address-cells = <1>; 100 #size-cells = <0>; 101 102 cpu0: cpu@0 { 103 compatible = "arm,cortex-a7"; 104 device_type = "cpu"; 105 reg = <0>; 106 clocks = <&ccu CLK_CPU>; 107 clock-latency = <244144>; /* 8 32k periods */ 108 operating-points = < 109 /* kHz uV */ 110 1008000 1200000 111 864000 1200000 112 720000 1100000 113 480000 1000000 114 >; 115 #cooling-cells = <2>; 116 }; 117 118 cpu@1 { 119 compatible = "arm,cortex-a7"; 120 device_type = "cpu"; 121 reg = <1>; 122 clocks = <&ccu CLK_CPU>; 123 clock-latency = <244144>; /* 8 32k periods */ 124 operating-points = < 125 /* kHz uV */ 126 1008000 1200000 127 864000 1200000 128 720000 1100000 129 480000 1000000 130 >; 131 #cooling-cells = <2>; 132 }; 133 134 cpu@2 { 135 compatible = "arm,cortex-a7"; 136 device_type = "cpu"; 137 reg = <2>; 138 clocks = <&ccu CLK_CPU>; 139 clock-latency = <244144>; /* 8 32k periods */ 140 operating-points = < 141 /* kHz uV */ 142 1008000 1200000 143 864000 1200000 144 720000 1100000 145 480000 1000000 146 >; 147 #cooling-cells = <2>; 148 }; 149 150 cpu@3 { 151 compatible = "arm,cortex-a7"; 152 device_type = "cpu"; 153 reg = <3>; 154 clocks = <&ccu CLK_CPU>; 155 clock-latency = <244144>; /* 8 32k periods */ 156 operating-points = < 157 /* kHz uV */ 158 1008000 1200000 159 864000 1200000 160 720000 1100000 161 480000 1000000 162 >; 163 #cooling-cells = <2>; 164 }; 165 }; 166 167 thermal-zones { 168 cpu_thermal { 169 /* milliseconds */ 170 polling-delay-passive = <250>; 171 polling-delay = <1000>; 172 thermal-sensors = <&rtp>; 173 174 cooling-maps { 175 map0 { 176 trip = <&cpu_alert0>; 177 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 178 }; 179 }; 180 181 trips { 182 cpu_alert0: cpu_alert0 { 183 /* milliCelsius */ 184 temperature = <70000>; 185 hysteresis = <2000>; 186 type = "passive"; 187 }; 188 189 cpu_crit: cpu_crit { 190 /* milliCelsius */ 191 temperature = <100000>; 192 hysteresis = <2000>; 193 type = "critical"; 194 }; 195 }; 196 }; 197 }; 198 199 memory { 200 reg = <0x40000000 0x80000000>; 201 }; 202 203 pmu { 204 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu"; 205 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 208 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 209 }; 210 211 clocks { 212 #address-cells = <1>; 213 #size-cells = <1>; 214 ranges; 215 216 osc24M: osc24M { 217 #clock-cells = <0>; 218 compatible = "fixed-clock"; 219 clock-frequency = <24000000>; 220 }; 221 222 osc32k: clk@0 { 223 #clock-cells = <0>; 224 compatible = "fixed-clock"; 225 clock-frequency = <32768>; 226 clock-output-names = "osc32k"; 227 }; 228 229 /* 230 * The following two are dummy clocks, placeholders 231 * used in the gmac_tx clock. The gmac driver will 232 * choose one parent depending on the PHY interface 233 * mode, using clk_set_rate auto-reparenting. 234 * 235 * The actual TX clock rate is not controlled by the 236 * gmac_tx clock. 237 */ 238 mii_phy_tx_clk: clk@1 { 239 #clock-cells = <0>; 240 compatible = "fixed-clock"; 241 clock-frequency = <25000000>; 242 clock-output-names = "mii_phy_tx"; 243 }; 244 245 gmac_int_tx_clk: clk@2 { 246 #clock-cells = <0>; 247 compatible = "fixed-clock"; 248 clock-frequency = <125000000>; 249 clock-output-names = "gmac_int_tx"; 250 }; 251 252 gmac_tx_clk: clk@1c200d0 { 253 #clock-cells = <0>; 254 compatible = "allwinner,sun7i-a20-gmac-clk"; 255 reg = <0x01c200d0 0x4>; 256 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; 257 clock-output-names = "gmac_tx"; 258 }; 259 }; 260 261 de: display-engine { 262 compatible = "allwinner,sun6i-a31-display-engine"; 263 allwinner,pipelines = <&fe0>, <&fe1>; 264 status = "disabled"; 265 }; 266 267 soc@1c00000 { 268 compatible = "simple-bus"; 269 #address-cells = <1>; 270 #size-cells = <1>; 271 ranges; 272 273 dma: dma-controller@1c02000 { 274 compatible = "allwinner,sun6i-a31-dma"; 275 reg = <0x01c02000 0x1000>; 276 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 277 clocks = <&ccu CLK_AHB1_DMA>; 278 resets = <&ccu RST_AHB1_DMA>; 279 #dma-cells = <1>; 280 }; 281 282 tcon0: lcd-controller@1c0c000 { 283 compatible = "allwinner,sun6i-a31-tcon"; 284 reg = <0x01c0c000 0x1000>; 285 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 286 resets = <&ccu RST_AHB1_LCD0>; 287 reset-names = "lcd"; 288 clocks = <&ccu CLK_AHB1_LCD0>, 289 <&ccu CLK_LCD0_CH0>, 290 <&ccu CLK_LCD0_CH1>; 291 clock-names = "ahb", 292 "tcon-ch0", 293 "tcon-ch1"; 294 clock-output-names = "tcon0-pixel-clock"; 295 296 ports { 297 #address-cells = <1>; 298 #size-cells = <0>; 299 300 tcon0_in: port@0 { 301 #address-cells = <1>; 302 #size-cells = <0>; 303 reg = <0>; 304 305 tcon0_in_drc0: endpoint@0 { 306 reg = <0>; 307 remote-endpoint = <&drc0_out_tcon0>; 308 }; 309 310 tcon0_in_drc1: endpoint@1 { 311 reg = <1>; 312 remote-endpoint = <&drc1_out_tcon0>; 313 }; 314 }; 315 316 tcon0_out: port@1 { 317 #address-cells = <1>; 318 #size-cells = <0>; 319 reg = <1>; 320 321 tcon0_out_hdmi: endpoint@1 { 322 reg = <1>; 323 remote-endpoint = <&hdmi_in_tcon0>; 324 allwinner,tcon-channel = <1>; 325 }; 326 }; 327 }; 328 }; 329 330 tcon1: lcd-controller@1c0d000 { 331 compatible = "allwinner,sun6i-a31-tcon"; 332 reg = <0x01c0d000 0x1000>; 333 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 334 resets = <&ccu RST_AHB1_LCD1>; 335 reset-names = "lcd"; 336 clocks = <&ccu CLK_AHB1_LCD1>, 337 <&ccu CLK_LCD1_CH0>, 338 <&ccu CLK_LCD1_CH1>; 339 clock-names = "ahb", 340 "tcon-ch0", 341 "tcon-ch1"; 342 clock-output-names = "tcon1-pixel-clock"; 343 344 ports { 345 #address-cells = <1>; 346 #size-cells = <0>; 347 348 tcon1_in: port@0 { 349 #address-cells = <1>; 350 #size-cells = <0>; 351 reg = <0>; 352 353 tcon1_in_drc0: endpoint@0 { 354 reg = <0>; 355 remote-endpoint = <&drc0_out_tcon1>; 356 }; 357 358 tcon1_in_drc1: endpoint@1 { 359 reg = <1>; 360 remote-endpoint = <&drc1_out_tcon1>; 361 }; 362 }; 363 364 tcon1_out: port@1 { 365 #address-cells = <1>; 366 #size-cells = <0>; 367 reg = <1>; 368 369 tcon1_out_hdmi: endpoint@1 { 370 reg = <1>; 371 remote-endpoint = <&hdmi_in_tcon1>; 372 allwinner,tcon-channel = <1>; 373 }; 374 }; 375 }; 376 }; 377 378 mmc0: mmc@1c0f000 { 379 compatible = "allwinner,sun7i-a20-mmc"; 380 reg = <0x01c0f000 0x1000>; 381 clocks = <&ccu CLK_AHB1_MMC0>, 382 <&ccu CLK_MMC0>, 383 <&ccu CLK_MMC0_OUTPUT>, 384 <&ccu CLK_MMC0_SAMPLE>; 385 clock-names = "ahb", 386 "mmc", 387 "output", 388 "sample"; 389 resets = <&ccu RST_AHB1_MMC0>; 390 reset-names = "ahb"; 391 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 392 status = "disabled"; 393 #address-cells = <1>; 394 #size-cells = <0>; 395 }; 396 397 mmc1: mmc@1c10000 { 398 compatible = "allwinner,sun7i-a20-mmc"; 399 reg = <0x01c10000 0x1000>; 400 clocks = <&ccu CLK_AHB1_MMC1>, 401 <&ccu CLK_MMC1>, 402 <&ccu CLK_MMC1_OUTPUT>, 403 <&ccu CLK_MMC1_SAMPLE>; 404 clock-names = "ahb", 405 "mmc", 406 "output", 407 "sample"; 408 resets = <&ccu RST_AHB1_MMC1>; 409 reset-names = "ahb"; 410 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 411 status = "disabled"; 412 #address-cells = <1>; 413 #size-cells = <0>; 414 }; 415 416 mmc2: mmc@1c11000 { 417 compatible = "allwinner,sun7i-a20-mmc"; 418 reg = <0x01c11000 0x1000>; 419 clocks = <&ccu CLK_AHB1_MMC2>, 420 <&ccu CLK_MMC2>, 421 <&ccu CLK_MMC2_OUTPUT>, 422 <&ccu CLK_MMC2_SAMPLE>; 423 clock-names = "ahb", 424 "mmc", 425 "output", 426 "sample"; 427 resets = <&ccu RST_AHB1_MMC2>; 428 reset-names = "ahb"; 429 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 430 status = "disabled"; 431 #address-cells = <1>; 432 #size-cells = <0>; 433 }; 434 435 mmc3: mmc@1c12000 { 436 compatible = "allwinner,sun7i-a20-mmc"; 437 reg = <0x01c12000 0x1000>; 438 clocks = <&ccu CLK_AHB1_MMC3>, 439 <&ccu CLK_MMC3>, 440 <&ccu CLK_MMC3_OUTPUT>, 441 <&ccu CLK_MMC3_SAMPLE>; 442 clock-names = "ahb", 443 "mmc", 444 "output", 445 "sample"; 446 resets = <&ccu RST_AHB1_MMC3>; 447 reset-names = "ahb"; 448 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 449 status = "disabled"; 450 #address-cells = <1>; 451 #size-cells = <0>; 452 }; 453 454 hdmi: hdmi@1c16000 { 455 compatible = "allwinner,sun6i-a31-hdmi"; 456 reg = <0x01c16000 0x1000>; 457 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 458 clocks = <&ccu CLK_AHB1_HDMI>, <&ccu CLK_HDMI>, 459 <&ccu CLK_HDMI_DDC>, 460 <&ccu CLK_PLL_VIDEO0_2X>, 461 <&ccu CLK_PLL_VIDEO1_2X>; 462 clock-names = "ahb", "mod", "ddc", "pll-0", "pll-1"; 463 resets = <&ccu RST_AHB1_HDMI>; 464 reset-names = "ahb"; 465 dma-names = "ddc-tx", "ddc-rx", "audio-tx"; 466 dmas = <&dma 13>, <&dma 13>, <&dma 14>; 467 status = "disabled"; 468 469 ports { 470 #address-cells = <1>; 471 #size-cells = <0>; 472 473 hdmi_in: port@0 { 474 #address-cells = <1>; 475 #size-cells = <0>; 476 reg = <0>; 477 478 hdmi_in_tcon0: endpoint@0 { 479 reg = <0>; 480 remote-endpoint = <&tcon0_out_hdmi>; 481 }; 482 483 hdmi_in_tcon1: endpoint@1 { 484 reg = <1>; 485 remote-endpoint = <&tcon1_out_hdmi>; 486 }; 487 }; 488 489 hdmi_out: port@1 { 490 #address-cells = <1>; 491 #size-cells = <0>; 492 reg = <1>; 493 }; 494 }; 495 }; 496 497 usb_otg: usb@1c19000 { 498 compatible = "allwinner,sun6i-a31-musb"; 499 reg = <0x01c19000 0x0400>; 500 clocks = <&ccu CLK_AHB1_OTG>; 501 resets = <&ccu RST_AHB1_OTG>; 502 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 503 interrupt-names = "mc"; 504 phys = <&usbphy 0>; 505 phy-names = "usb"; 506 extcon = <&usbphy 0>; 507 status = "disabled"; 508 }; 509 510 usbphy: phy@1c19400 { 511 compatible = "allwinner,sun6i-a31-usb-phy"; 512 reg = <0x01c19400 0x10>, 513 <0x01c1a800 0x4>, 514 <0x01c1b800 0x4>; 515 reg-names = "phy_ctrl", 516 "pmu1", 517 "pmu2"; 518 clocks = <&ccu CLK_USB_PHY0>, 519 <&ccu CLK_USB_PHY1>, 520 <&ccu CLK_USB_PHY2>; 521 clock-names = "usb0_phy", 522 "usb1_phy", 523 "usb2_phy"; 524 resets = <&ccu RST_USB_PHY0>, 525 <&ccu RST_USB_PHY1>, 526 <&ccu RST_USB_PHY2>; 527 reset-names = "usb0_reset", 528 "usb1_reset", 529 "usb2_reset"; 530 status = "disabled"; 531 #phy-cells = <1>; 532 }; 533 534 ehci0: usb@1c1a000 { 535 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; 536 reg = <0x01c1a000 0x100>; 537 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 538 clocks = <&ccu CLK_AHB1_EHCI0>; 539 resets = <&ccu RST_AHB1_EHCI0>; 540 phys = <&usbphy 1>; 541 phy-names = "usb"; 542 status = "disabled"; 543 }; 544 545 ohci0: usb@1c1a400 { 546 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; 547 reg = <0x01c1a400 0x100>; 548 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 549 clocks = <&ccu CLK_AHB1_OHCI0>, <&ccu CLK_USB_OHCI0>; 550 resets = <&ccu RST_AHB1_OHCI0>; 551 phys = <&usbphy 1>; 552 phy-names = "usb"; 553 status = "disabled"; 554 }; 555 556 ehci1: usb@1c1b000 { 557 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; 558 reg = <0x01c1b000 0x100>; 559 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 560 clocks = <&ccu CLK_AHB1_EHCI1>; 561 resets = <&ccu RST_AHB1_EHCI1>; 562 phys = <&usbphy 2>; 563 phy-names = "usb"; 564 status = "disabled"; 565 }; 566 567 ohci1: usb@1c1b400 { 568 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; 569 reg = <0x01c1b400 0x100>; 570 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 571 clocks = <&ccu CLK_AHB1_OHCI1>, <&ccu CLK_USB_OHCI1>; 572 resets = <&ccu RST_AHB1_OHCI1>; 573 phys = <&usbphy 2>; 574 phy-names = "usb"; 575 status = "disabled"; 576 }; 577 578 ohci2: usb@1c1c400 { 579 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; 580 reg = <0x01c1c400 0x100>; 581 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 582 clocks = <&ccu CLK_AHB1_OHCI2>, <&ccu CLK_USB_OHCI2>; 583 resets = <&ccu RST_AHB1_OHCI2>; 584 status = "disabled"; 585 }; 586 587 ccu: clock@1c20000 { 588 compatible = "allwinner,sun6i-a31-ccu"; 589 reg = <0x01c20000 0x400>; 590 clocks = <&osc24M>, <&osc32k>; 591 clock-names = "hosc", "losc"; 592 #clock-cells = <1>; 593 #reset-cells = <1>; 594 }; 595 596 pio: pinctrl@1c20800 { 597 compatible = "allwinner,sun6i-a31-pinctrl"; 598 reg = <0x01c20800 0x400>; 599 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 603 clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&osc32k>; 604 clock-names = "apb", "hosc", "losc"; 605 gpio-controller; 606 interrupt-controller; 607 #interrupt-cells = <3>; 608 #gpio-cells = <3>; 609 610 gmac_pins_gmii_a: gmac_gmii@0 { 611 pins = "PA0", "PA1", "PA2", "PA3", 612 "PA4", "PA5", "PA6", "PA7", 613 "PA8", "PA9", "PA10", "PA11", 614 "PA12", "PA13", "PA14", "PA15", 615 "PA16", "PA17", "PA18", "PA19", 616 "PA20", "PA21", "PA22", "PA23", 617 "PA24", "PA25", "PA26", "PA27"; 618 function = "gmac"; 619 /* 620 * data lines in GMII mode run at 125MHz and 621 * might need a higher signal drive strength 622 */ 623 drive-strength = <30>; 624 }; 625 626 gmac_pins_mii_a: gmac_mii@0 { 627 pins = "PA0", "PA1", "PA2", "PA3", 628 "PA8", "PA9", "PA11", 629 "PA12", "PA13", "PA14", "PA19", 630 "PA20", "PA21", "PA22", "PA23", 631 "PA24", "PA26", "PA27"; 632 function = "gmac"; 633 }; 634 635 gmac_pins_rgmii_a: gmac_rgmii@0 { 636 pins = "PA0", "PA1", "PA2", "PA3", 637 "PA9", "PA10", "PA11", 638 "PA12", "PA13", "PA14", "PA19", 639 "PA20", "PA25", "PA26", "PA27"; 640 function = "gmac"; 641 /* 642 * data lines in RGMII mode use DDR mode 643 * and need a higher signal drive strength 644 */ 645 drive-strength = <40>; 646 }; 647 648 i2c0_pins_a: i2c0@0 { 649 pins = "PH14", "PH15"; 650 function = "i2c0"; 651 }; 652 653 i2c1_pins_a: i2c1@0 { 654 pins = "PH16", "PH17"; 655 function = "i2c1"; 656 }; 657 658 i2c2_pins_a: i2c2@0 { 659 pins = "PH18", "PH19"; 660 function = "i2c2"; 661 }; 662 663 lcd0_rgb888_pins: lcd0_rgb888 { 664 pins = "PD0", "PD1", "PD2", "PD3", 665 "PD4", "PD5", "PD6", "PD7", 666 "PD8", "PD9", "PD10", "PD11", 667 "PD12", "PD13", "PD14", "PD15", 668 "PD16", "PD17", "PD18", "PD19", 669 "PD20", "PD21", "PD22", "PD23", 670 "PD24", "PD25", "PD26", "PD27"; 671 function = "lcd0"; 672 }; 673 674 mmc0_pins_a: mmc0@0 { 675 pins = "PF0", "PF1", "PF2", 676 "PF3", "PF4", "PF5"; 677 function = "mmc0"; 678 drive-strength = <30>; 679 bias-pull-up; 680 }; 681 682 mmc1_pins_a: mmc1@0 { 683 pins = "PG0", "PG1", "PG2", "PG3", 684 "PG4", "PG5"; 685 function = "mmc1"; 686 drive-strength = <30>; 687 bias-pull-up; 688 }; 689 690 mmc2_pins_a: mmc2@0 { 691 pins = "PC6", "PC7", "PC8", "PC9", 692 "PC10", "PC11"; 693 function = "mmc2"; 694 drive-strength = <30>; 695 bias-pull-up; 696 }; 697 698 mmc2_8bit_emmc_pins: mmc2@1 { 699 pins = "PC6", "PC7", "PC8", "PC9", 700 "PC10", "PC11", "PC12", 701 "PC13", "PC14", "PC15", 702 "PC24"; 703 function = "mmc2"; 704 drive-strength = <30>; 705 bias-pull-up; 706 }; 707 708 mmc3_8bit_emmc_pins: mmc3@1 { 709 pins = "PC6", "PC7", "PC8", "PC9", 710 "PC10", "PC11", "PC12", 711 "PC13", "PC14", "PC15", 712 "PC24"; 713 function = "mmc3"; 714 drive-strength = <40>; 715 bias-pull-up; 716 }; 717 718 spdif_pins_a: spdif@0 { 719 pins = "PH28"; 720 function = "spdif"; 721 }; 722 723 uart0_pins_a: uart0@0 { 724 pins = "PH20", "PH21"; 725 function = "uart0"; 726 }; 727 }; 728 729 timer@1c20c00 { 730 compatible = "allwinner,sun4i-a10-timer"; 731 reg = <0x01c20c00 0xa0>; 732 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 737 clocks = <&osc24M>; 738 }; 739 740 wdt1: watchdog@1c20ca0 { 741 compatible = "allwinner,sun6i-a31-wdt"; 742 reg = <0x01c20ca0 0x20>; 743 }; 744 745 spdif: spdif@1c21000 { 746 #sound-dai-cells = <0>; 747 compatible = "allwinner,sun6i-a31-spdif"; 748 reg = <0x01c21000 0x400>; 749 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 750 clocks = <&ccu CLK_APB1_SPDIF>, <&ccu CLK_SPDIF>; 751 resets = <&ccu RST_APB1_SPDIF>; 752 clock-names = "apb", "spdif"; 753 dmas = <&dma 2>, <&dma 2>; 754 dma-names = "rx", "tx"; 755 status = "disabled"; 756 }; 757 758 i2s0: i2s@1c22000 { 759 #sound-dai-cells = <0>; 760 compatible = "allwinner,sun6i-a31-i2s"; 761 reg = <0x01c22000 0x400>; 762 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 763 clocks = <&ccu CLK_APB1_DAUDIO0>, <&ccu CLK_DAUDIO0>; 764 resets = <&ccu RST_APB1_DAUDIO0>; 765 clock-names = "apb", "mod"; 766 dmas = <&dma 3>, <&dma 3>; 767 dma-names = "rx", "tx"; 768 status = "disabled"; 769 }; 770 771 i2s1: i2s@1c22400 { 772 #sound-dai-cells = <0>; 773 compatible = "allwinner,sun6i-a31-i2s"; 774 reg = <0x01c22400 0x400>; 775 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 776 clocks = <&ccu CLK_APB1_DAUDIO1>, <&ccu CLK_DAUDIO1>; 777 resets = <&ccu RST_APB1_DAUDIO1>; 778 clock-names = "apb", "mod"; 779 dmas = <&dma 4>, <&dma 4>; 780 dma-names = "rx", "tx"; 781 status = "disabled"; 782 }; 783 784 lradc: lradc@1c22800 { 785 compatible = "allwinner,sun4i-a10-lradc-keys"; 786 reg = <0x01c22800 0x100>; 787 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 788 status = "disabled"; 789 }; 790 791 rtp: rtp@1c25000 { 792 compatible = "allwinner,sun6i-a31-ts"; 793 reg = <0x01c25000 0x100>; 794 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 795 #thermal-sensor-cells = <0>; 796 }; 797 798 uart0: serial@1c28000 { 799 compatible = "snps,dw-apb-uart"; 800 reg = <0x01c28000 0x400>; 801 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 802 reg-shift = <2>; 803 reg-io-width = <4>; 804 clocks = <&ccu CLK_APB2_UART0>; 805 resets = <&ccu RST_APB2_UART0>; 806 dmas = <&dma 6>, <&dma 6>; 807 dma-names = "rx", "tx"; 808 status = "disabled"; 809 }; 810 811 uart1: serial@1c28400 { 812 compatible = "snps,dw-apb-uart"; 813 reg = <0x01c28400 0x400>; 814 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 815 reg-shift = <2>; 816 reg-io-width = <4>; 817 clocks = <&ccu CLK_APB2_UART1>; 818 resets = <&ccu RST_APB2_UART1>; 819 dmas = <&dma 7>, <&dma 7>; 820 dma-names = "rx", "tx"; 821 status = "disabled"; 822 }; 823 824 uart2: serial@1c28800 { 825 compatible = "snps,dw-apb-uart"; 826 reg = <0x01c28800 0x400>; 827 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 828 reg-shift = <2>; 829 reg-io-width = <4>; 830 clocks = <&ccu CLK_APB2_UART2>; 831 resets = <&ccu RST_APB2_UART2>; 832 dmas = <&dma 8>, <&dma 8>; 833 dma-names = "rx", "tx"; 834 status = "disabled"; 835 }; 836 837 uart3: serial@1c28c00 { 838 compatible = "snps,dw-apb-uart"; 839 reg = <0x01c28c00 0x400>; 840 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 841 reg-shift = <2>; 842 reg-io-width = <4>; 843 clocks = <&ccu CLK_APB2_UART3>; 844 resets = <&ccu RST_APB2_UART3>; 845 dmas = <&dma 9>, <&dma 9>; 846 dma-names = "rx", "tx"; 847 status = "disabled"; 848 }; 849 850 uart4: serial@1c29000 { 851 compatible = "snps,dw-apb-uart"; 852 reg = <0x01c29000 0x400>; 853 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 854 reg-shift = <2>; 855 reg-io-width = <4>; 856 clocks = <&ccu CLK_APB2_UART4>; 857 resets = <&ccu RST_APB2_UART4>; 858 dmas = <&dma 10>, <&dma 10>; 859 dma-names = "rx", "tx"; 860 status = "disabled"; 861 }; 862 863 uart5: serial@1c29400 { 864 compatible = "snps,dw-apb-uart"; 865 reg = <0x01c29400 0x400>; 866 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 867 reg-shift = <2>; 868 reg-io-width = <4>; 869 clocks = <&ccu CLK_APB2_UART5>; 870 resets = <&ccu RST_APB2_UART5>; 871 dmas = <&dma 22>, <&dma 22>; 872 dma-names = "rx", "tx"; 873 status = "disabled"; 874 }; 875 876 i2c0: i2c@1c2ac00 { 877 compatible = "allwinner,sun6i-a31-i2c"; 878 reg = <0x01c2ac00 0x400>; 879 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 880 clocks = <&ccu CLK_APB2_I2C0>; 881 resets = <&ccu RST_APB2_I2C0>; 882 status = "disabled"; 883 #address-cells = <1>; 884 #size-cells = <0>; 885 }; 886 887 i2c1: i2c@1c2b000 { 888 compatible = "allwinner,sun6i-a31-i2c"; 889 reg = <0x01c2b000 0x400>; 890 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 891 clocks = <&ccu CLK_APB2_I2C1>; 892 resets = <&ccu RST_APB2_I2C1>; 893 status = "disabled"; 894 #address-cells = <1>; 895 #size-cells = <0>; 896 }; 897 898 i2c2: i2c@1c2b400 { 899 compatible = "allwinner,sun6i-a31-i2c"; 900 reg = <0x01c2b400 0x400>; 901 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 902 clocks = <&ccu CLK_APB2_I2C2>; 903 resets = <&ccu RST_APB2_I2C2>; 904 status = "disabled"; 905 #address-cells = <1>; 906 #size-cells = <0>; 907 }; 908 909 i2c3: i2c@1c2b800 { 910 compatible = "allwinner,sun6i-a31-i2c"; 911 reg = <0x01c2b800 0x400>; 912 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 913 clocks = <&ccu CLK_APB2_I2C3>; 914 resets = <&ccu RST_APB2_I2C3>; 915 status = "disabled"; 916 #address-cells = <1>; 917 #size-cells = <0>; 918 }; 919 920 gmac: ethernet@1c30000 { 921 compatible = "allwinner,sun7i-a20-gmac"; 922 reg = <0x01c30000 0x1054>; 923 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 924 interrupt-names = "macirq"; 925 clocks = <&ccu CLK_AHB1_EMAC>, <&gmac_tx_clk>; 926 clock-names = "stmmaceth", "allwinner_gmac_tx"; 927 resets = <&ccu RST_AHB1_EMAC>; 928 reset-names = "stmmaceth"; 929 snps,pbl = <2>; 930 snps,fixed-burst; 931 snps,force_sf_dma_mode; 932 status = "disabled"; 933 #address-cells = <1>; 934 #size-cells = <0>; 935 }; 936 937 crypto: crypto-engine@1c15000 { 938 compatible = "allwinner,sun6i-a31-crypto", 939 "allwinner,sun4i-a10-crypto"; 940 reg = <0x01c15000 0x1000>; 941 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 942 clocks = <&ccu CLK_AHB1_SS>, <&ccu CLK_SS>; 943 clock-names = "ahb", "mod"; 944 resets = <&ccu RST_AHB1_SS>; 945 reset-names = "ahb"; 946 }; 947 948 codec: codec@1c22c00 { 949 #sound-dai-cells = <0>; 950 compatible = "allwinner,sun6i-a31-codec"; 951 reg = <0x01c22c00 0x400>; 952 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 953 clocks = <&ccu CLK_APB1_CODEC>, <&ccu CLK_CODEC>; 954 clock-names = "apb", "codec"; 955 resets = <&ccu RST_APB1_CODEC>; 956 dmas = <&dma 15>, <&dma 15>; 957 dma-names = "rx", "tx"; 958 status = "disabled"; 959 }; 960 961 timer@1c60000 { 962 compatible = "allwinner,sun6i-a31-hstimer", 963 "allwinner,sun7i-a20-hstimer"; 964 reg = <0x01c60000 0x1000>; 965 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 966 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 967 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 968 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 969 clocks = <&ccu CLK_AHB1_HSTIMER>; 970 resets = <&ccu RST_AHB1_HSTIMER>; 971 }; 972 973 spi0: spi@1c68000 { 974 compatible = "allwinner,sun6i-a31-spi"; 975 reg = <0x01c68000 0x1000>; 976 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 977 clocks = <&ccu CLK_AHB1_SPI0>, <&ccu CLK_SPI0>; 978 clock-names = "ahb", "mod"; 979 dmas = <&dma 23>, <&dma 23>; 980 dma-names = "rx", "tx"; 981 resets = <&ccu RST_AHB1_SPI0>; 982 status = "disabled"; 983 }; 984 985 spi1: spi@1c69000 { 986 compatible = "allwinner,sun6i-a31-spi"; 987 reg = <0x01c69000 0x1000>; 988 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 989 clocks = <&ccu CLK_AHB1_SPI1>, <&ccu CLK_SPI1>; 990 clock-names = "ahb", "mod"; 991 dmas = <&dma 24>, <&dma 24>; 992 dma-names = "rx", "tx"; 993 resets = <&ccu RST_AHB1_SPI1>; 994 status = "disabled"; 995 }; 996 997 spi2: spi@1c6a000 { 998 compatible = "allwinner,sun6i-a31-spi"; 999 reg = <0x01c6a000 0x1000>; 1000 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 1001 clocks = <&ccu CLK_AHB1_SPI2>, <&ccu CLK_SPI2>; 1002 clock-names = "ahb", "mod"; 1003 dmas = <&dma 25>, <&dma 25>; 1004 dma-names = "rx", "tx"; 1005 resets = <&ccu RST_AHB1_SPI2>; 1006 status = "disabled"; 1007 }; 1008 1009 spi3: spi@1c6b000 { 1010 compatible = "allwinner,sun6i-a31-spi"; 1011 reg = <0x01c6b000 0x1000>; 1012 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 1013 clocks = <&ccu CLK_AHB1_SPI3>, <&ccu CLK_SPI3>; 1014 clock-names = "ahb", "mod"; 1015 dmas = <&dma 26>, <&dma 26>; 1016 dma-names = "rx", "tx"; 1017 resets = <&ccu RST_AHB1_SPI3>; 1018 status = "disabled"; 1019 }; 1020 1021 gic: interrupt-controller@1c81000 { 1022 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; 1023 reg = <0x01c81000 0x1000>, 1024 <0x01c82000 0x2000>, 1025 <0x01c84000 0x2000>, 1026 <0x01c86000 0x2000>; 1027 interrupt-controller; 1028 #interrupt-cells = <3>; 1029 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1030 }; 1031 1032 fe0: display-frontend@1e00000 { 1033 compatible = "allwinner,sun6i-a31-display-frontend"; 1034 reg = <0x01e00000 0x20000>; 1035 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1036 clocks = <&ccu CLK_AHB1_FE0>, <&ccu CLK_FE0>, 1037 <&ccu CLK_DRAM_FE0>; 1038 clock-names = "ahb", "mod", 1039 "ram"; 1040 resets = <&ccu RST_AHB1_FE0>; 1041 1042 ports { 1043 #address-cells = <1>; 1044 #size-cells = <0>; 1045 1046 fe0_out: port@1 { 1047 #address-cells = <1>; 1048 #size-cells = <0>; 1049 reg = <1>; 1050 1051 fe0_out_be0: endpoint@0 { 1052 reg = <0>; 1053 remote-endpoint = <&be0_in_fe0>; 1054 }; 1055 1056 fe0_out_be1: endpoint@1 { 1057 reg = <1>; 1058 remote-endpoint = <&be1_in_fe0>; 1059 }; 1060 }; 1061 }; 1062 }; 1063 1064 fe1: display-frontend@1e20000 { 1065 compatible = "allwinner,sun6i-a31-display-frontend"; 1066 reg = <0x01e20000 0x20000>; 1067 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 1068 clocks = <&ccu CLK_AHB1_FE1>, <&ccu CLK_FE1>, 1069 <&ccu CLK_DRAM_FE1>; 1070 clock-names = "ahb", "mod", 1071 "ram"; 1072 resets = <&ccu RST_AHB1_FE1>; 1073 1074 ports { 1075 #address-cells = <1>; 1076 #size-cells = <0>; 1077 1078 fe1_out: port@1 { 1079 #address-cells = <1>; 1080 #size-cells = <0>; 1081 reg = <1>; 1082 1083 fe1_out_be0: endpoint@0 { 1084 reg = <0>; 1085 remote-endpoint = <&be0_in_fe1>; 1086 }; 1087 1088 fe1_out_be1: endpoint@1 { 1089 reg = <1>; 1090 remote-endpoint = <&be1_in_fe1>; 1091 }; 1092 }; 1093 }; 1094 }; 1095 1096 be1: display-backend@1e40000 { 1097 compatible = "allwinner,sun6i-a31-display-backend"; 1098 reg = <0x01e40000 0x10000>; 1099 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1100 clocks = <&ccu CLK_AHB1_BE1>, <&ccu CLK_BE1>, 1101 <&ccu CLK_DRAM_BE1>; 1102 clock-names = "ahb", "mod", 1103 "ram"; 1104 resets = <&ccu RST_AHB1_BE1>; 1105 1106 assigned-clocks = <&ccu CLK_BE1>; 1107 assigned-clock-rates = <300000000>; 1108 1109 ports { 1110 #address-cells = <1>; 1111 #size-cells = <0>; 1112 1113 be1_in: port@0 { 1114 #address-cells = <1>; 1115 #size-cells = <0>; 1116 reg = <0>; 1117 1118 be1_in_fe0: endpoint@0 { 1119 reg = <0>; 1120 remote-endpoint = <&fe0_out_be1>; 1121 }; 1122 1123 be1_in_fe1: endpoint@1 { 1124 reg = <1>; 1125 remote-endpoint = <&fe1_out_be1>; 1126 }; 1127 }; 1128 1129 be1_out: port@1 { 1130 #address-cells = <1>; 1131 #size-cells = <0>; 1132 reg = <1>; 1133 1134 be1_out_drc1: endpoint@1 { 1135 reg = <1>; 1136 remote-endpoint = <&drc1_in_be1>; 1137 }; 1138 }; 1139 }; 1140 }; 1141 1142 drc1: drc@1e50000 { 1143 compatible = "allwinner,sun6i-a31-drc"; 1144 reg = <0x01e50000 0x10000>; 1145 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1146 clocks = <&ccu CLK_AHB1_DRC1>, <&ccu CLK_IEP_DRC1>, 1147 <&ccu CLK_DRAM_DRC1>; 1148 clock-names = "ahb", "mod", 1149 "ram"; 1150 resets = <&ccu RST_AHB1_DRC1>; 1151 1152 assigned-clocks = <&ccu CLK_IEP_DRC1>; 1153 assigned-clock-rates = <300000000>; 1154 1155 ports { 1156 #address-cells = <1>; 1157 #size-cells = <0>; 1158 1159 drc1_in: port@0 { 1160 #address-cells = <1>; 1161 #size-cells = <0>; 1162 reg = <0>; 1163 1164 drc1_in_be1: endpoint@1 { 1165 reg = <1>; 1166 remote-endpoint = <&be1_out_drc1>; 1167 }; 1168 }; 1169 1170 drc1_out: port@1 { 1171 #address-cells = <1>; 1172 #size-cells = <0>; 1173 reg = <1>; 1174 1175 drc1_out_tcon0: endpoint@0 { 1176 reg = <0>; 1177 remote-endpoint = <&tcon0_in_drc1>; 1178 }; 1179 1180 drc1_out_tcon1: endpoint@1 { 1181 reg = <1>; 1182 remote-endpoint = <&tcon1_in_drc1>; 1183 }; 1184 }; 1185 }; 1186 }; 1187 1188 be0: display-backend@1e60000 { 1189 compatible = "allwinner,sun6i-a31-display-backend"; 1190 reg = <0x01e60000 0x10000>; 1191 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1192 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_BE0>, 1193 <&ccu CLK_DRAM_BE0>; 1194 clock-names = "ahb", "mod", 1195 "ram"; 1196 resets = <&ccu RST_AHB1_BE0>; 1197 1198 assigned-clocks = <&ccu CLK_BE0>; 1199 assigned-clock-rates = <300000000>; 1200 1201 ports { 1202 #address-cells = <1>; 1203 #size-cells = <0>; 1204 1205 be0_in: port@0 { 1206 #address-cells = <1>; 1207 #size-cells = <0>; 1208 reg = <0>; 1209 1210 be0_in_fe0: endpoint@0 { 1211 reg = <0>; 1212 remote-endpoint = <&fe0_out_be0>; 1213 }; 1214 1215 be0_in_fe1: endpoint@1 { 1216 reg = <1>; 1217 remote-endpoint = <&fe1_out_be0>; 1218 }; 1219 }; 1220 1221 be0_out: port@1 { 1222 #address-cells = <1>; 1223 #size-cells = <0>; 1224 reg = <1>; 1225 1226 be0_out_drc0: endpoint@0 { 1227 reg = <0>; 1228 remote-endpoint = <&drc0_in_be0>; 1229 }; 1230 }; 1231 }; 1232 }; 1233 1234 drc0: drc@1e70000 { 1235 compatible = "allwinner,sun6i-a31-drc"; 1236 reg = <0x01e70000 0x10000>; 1237 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1238 clocks = <&ccu CLK_AHB1_DRC0>, <&ccu CLK_IEP_DRC0>, 1239 <&ccu CLK_DRAM_DRC0>; 1240 clock-names = "ahb", "mod", 1241 "ram"; 1242 resets = <&ccu RST_AHB1_DRC0>; 1243 1244 assigned-clocks = <&ccu CLK_IEP_DRC0>; 1245 assigned-clock-rates = <300000000>; 1246 1247 ports { 1248 #address-cells = <1>; 1249 #size-cells = <0>; 1250 1251 drc0_in: port@0 { 1252 #address-cells = <1>; 1253 #size-cells = <0>; 1254 reg = <0>; 1255 1256 drc0_in_be0: endpoint@0 { 1257 reg = <0>; 1258 remote-endpoint = <&be0_out_drc0>; 1259 }; 1260 }; 1261 1262 drc0_out: port@1 { 1263 #address-cells = <1>; 1264 #size-cells = <0>; 1265 reg = <1>; 1266 1267 drc0_out_tcon0: endpoint@0 { 1268 reg = <0>; 1269 remote-endpoint = <&tcon0_in_drc0>; 1270 }; 1271 1272 drc0_out_tcon1: endpoint@1 { 1273 reg = <1>; 1274 remote-endpoint = <&tcon1_in_drc0>; 1275 }; 1276 }; 1277 }; 1278 }; 1279 1280 rtc: rtc@1f00000 { 1281 compatible = "allwinner,sun6i-a31-rtc"; 1282 reg = <0x01f00000 0x54>; 1283 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1284 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1285 }; 1286 1287 nmi_intc: interrupt-controller@1f00c00 { 1288 compatible = "allwinner,sun6i-a31-r-intc"; 1289 interrupt-controller; 1290 #interrupt-cells = <2>; 1291 reg = <0x01f00c00 0x400>; 1292 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1293 }; 1294 1295 prcm@1f01400 { 1296 compatible = "allwinner,sun6i-a31-prcm"; 1297 reg = <0x01f01400 0x200>; 1298 1299 ar100: ar100_clk { 1300 compatible = "allwinner,sun6i-a31-ar100-clk"; 1301 #clock-cells = <0>; 1302 clocks = <&osc32k>, <&osc24M>, 1303 <&ccu CLK_PLL_PERIPH>, 1304 <&ccu CLK_PLL_PERIPH>; 1305 clock-output-names = "ar100"; 1306 }; 1307 1308 ahb0: ahb0_clk { 1309 compatible = "fixed-factor-clock"; 1310 #clock-cells = <0>; 1311 clock-div = <1>; 1312 clock-mult = <1>; 1313 clocks = <&ar100>; 1314 clock-output-names = "ahb0"; 1315 }; 1316 1317 apb0: apb0_clk { 1318 compatible = "allwinner,sun6i-a31-apb0-clk"; 1319 #clock-cells = <0>; 1320 clocks = <&ahb0>; 1321 clock-output-names = "apb0"; 1322 }; 1323 1324 apb0_gates: apb0_gates_clk { 1325 compatible = "allwinner,sun6i-a31-apb0-gates-clk"; 1326 #clock-cells = <1>; 1327 clocks = <&apb0>; 1328 clock-output-names = "apb0_pio", "apb0_ir", 1329 "apb0_timer", "apb0_p2wi", 1330 "apb0_uart", "apb0_1wire", 1331 "apb0_i2c"; 1332 }; 1333 1334 ir_clk: ir_clk { 1335 #clock-cells = <0>; 1336 compatible = "allwinner,sun4i-a10-mod0-clk"; 1337 clocks = <&osc32k>, <&osc24M>; 1338 clock-output-names = "ir"; 1339 }; 1340 1341 apb0_rst: apb0_rst { 1342 compatible = "allwinner,sun6i-a31-clock-reset"; 1343 #reset-cells = <1>; 1344 }; 1345 }; 1346 1347 cpucfg@1f01c00 { 1348 compatible = "allwinner,sun6i-a31-cpuconfig"; 1349 reg = <0x01f01c00 0x300>; 1350 }; 1351 1352 ir: ir@1f02000 { 1353 compatible = "allwinner,sun5i-a13-ir"; 1354 clocks = <&apb0_gates 1>, <&ir_clk>; 1355 clock-names = "apb", "ir"; 1356 resets = <&apb0_rst 1>; 1357 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1358 reg = <0x01f02000 0x40>; 1359 status = "disabled"; 1360 }; 1361 1362 r_pio: pinctrl@1f02c00 { 1363 compatible = "allwinner,sun6i-a31-r-pinctrl"; 1364 reg = <0x01f02c00 0x400>; 1365 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 1366 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 1367 clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>; 1368 clock-names = "apb", "hosc", "losc"; 1369 resets = <&apb0_rst 0>; 1370 gpio-controller; 1371 interrupt-controller; 1372 #interrupt-cells = <3>; 1373 #size-cells = <0>; 1374 #gpio-cells = <3>; 1375 1376 ir_pins_a: ir@0 { 1377 pins = "PL4"; 1378 function = "s_ir"; 1379 }; 1380 1381 p2wi_pins: p2wi { 1382 pins = "PL0", "PL1"; 1383 function = "s_p2wi"; 1384 }; 1385 }; 1386 1387 p2wi: i2c@1f03400 { 1388 compatible = "allwinner,sun6i-a31-p2wi"; 1389 reg = <0x01f03400 0x400>; 1390 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1391 clocks = <&apb0_gates 3>; 1392 clock-frequency = <100000>; 1393 resets = <&apb0_rst 3>; 1394 pinctrl-names = "default"; 1395 pinctrl-0 = <&p2wi_pins>; 1396 status = "disabled"; 1397 #address-cells = <1>; 1398 #size-cells = <0>; 1399 }; 1400 }; 1401}; 1402
