1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved 4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. 5 */ 6#include <dt-bindings/pinctrl/stm32-pinfunc.h> 7 8&pinctrl { 9 adc1_in6_pins_a: adc1-in6-0 { 10 pins { 11 pinmux = <STM32_PINMUX('F', 12, ANALOG)>; 12 }; 13 }; 14 15 adc12_ain_pins_a: adc12-ain-0 { 16 pins { 17 pinmux = <STM32_PINMUX('C', 3, ANALOG)>, /* ADC1 in13 */ 18 <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */ 19 <STM32_PINMUX('F', 13, ANALOG)>, /* ADC2 in2 */ 20 <STM32_PINMUX('F', 14, ANALOG)>; /* ADC2 in6 */ 21 }; 22 }; 23 24 adc12_ain_pins_b: adc12-ain-1 { 25 pins { 26 pinmux = <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */ 27 <STM32_PINMUX('F', 13, ANALOG)>; /* ADC2 in2 */ 28 }; 29 }; 30 31 adc12_usb_cc_pins_a: adc12-usb-cc-pins-0 { 32 pins { 33 pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* ADC12 in18 */ 34 <STM32_PINMUX('A', 5, ANALOG)>; /* ADC12 in19 */ 35 }; 36 }; 37 38 cec_pins_a: cec-0 { 39 pins { 40 pinmux = <STM32_PINMUX('A', 15, AF4)>; 41 bias-disable; 42 drive-open-drain; 43 slew-rate = <0>; 44 }; 45 }; 46 47 cec_sleep_pins_a: cec-sleep-0 { 48 pins { 49 pinmux = <STM32_PINMUX('A', 15, ANALOG)>; /* HDMI_CEC */ 50 }; 51 }; 52 53 cec_pins_b: cec-1 { 54 pins { 55 pinmux = <STM32_PINMUX('B', 6, AF5)>; 56 bias-disable; 57 drive-open-drain; 58 slew-rate = <0>; 59 }; 60 }; 61 62 cec_sleep_pins_b: cec-sleep-1 { 63 pins { 64 pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* HDMI_CEC */ 65 }; 66 }; 67 68 dac_ch1_pins_a: dac-ch1-0 { 69 pins { 70 pinmux = <STM32_PINMUX('A', 4, ANALOG)>; 71 }; 72 }; 73 74 dac_ch2_pins_a: dac-ch2-0 { 75 pins { 76 pinmux = <STM32_PINMUX('A', 5, ANALOG)>; 77 }; 78 }; 79 80 dcmi_pins_a: dcmi-0 { 81 pins { 82 pinmux = <STM32_PINMUX('H', 8, AF13)>,/* DCMI_HSYNC */ 83 <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */ 84 <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */ 85 <STM32_PINMUX('H', 9, AF13)>,/* DCMI_D0 */ 86 <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */ 87 <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */ 88 <STM32_PINMUX('H', 12, AF13)>,/* DCMI_D3 */ 89 <STM32_PINMUX('H', 14, AF13)>,/* DCMI_D4 */ 90 <STM32_PINMUX('I', 4, AF13)>,/* DCMI_D5 */ 91 <STM32_PINMUX('B', 8, AF13)>,/* DCMI_D6 */ 92 <STM32_PINMUX('E', 6, AF13)>,/* DCMI_D7 */ 93 <STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */ 94 <STM32_PINMUX('H', 7, AF13)>,/* DCMI_D9 */ 95 <STM32_PINMUX('I', 3, AF13)>,/* DCMI_D10 */ 96 <STM32_PINMUX('H', 15, AF13)>;/* DCMI_D11 */ 97 bias-disable; 98 }; 99 }; 100 101 dcmi_sleep_pins_a: dcmi-sleep-0 { 102 pins { 103 pinmux = <STM32_PINMUX('H', 8, ANALOG)>,/* DCMI_HSYNC */ 104 <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */ 105 <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */ 106 <STM32_PINMUX('H', 9, ANALOG)>,/* DCMI_D0 */ 107 <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */ 108 <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */ 109 <STM32_PINMUX('H', 12, ANALOG)>,/* DCMI_D3 */ 110 <STM32_PINMUX('H', 14, ANALOG)>,/* DCMI_D4 */ 111 <STM32_PINMUX('I', 4, ANALOG)>,/* DCMI_D5 */ 112 <STM32_PINMUX('B', 8, ANALOG)>,/* DCMI_D6 */ 113 <STM32_PINMUX('E', 6, ANALOG)>,/* DCMI_D7 */ 114 <STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */ 115 <STM32_PINMUX('H', 7, ANALOG)>,/* DCMI_D9 */ 116 <STM32_PINMUX('I', 3, ANALOG)>,/* DCMI_D10 */ 117 <STM32_PINMUX('H', 15, ANALOG)>;/* DCMI_D11 */ 118 }; 119 }; 120 121 dcmi_pins_b: dcmi-1 { 122 pins { 123 pinmux = <STM32_PINMUX('A', 4, AF13)>,/* DCMI_HSYNC */ 124 <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */ 125 <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */ 126 <STM32_PINMUX('C', 6, AF13)>,/* DCMI_D0 */ 127 <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */ 128 <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */ 129 <STM32_PINMUX('E', 1, AF13)>,/* DCMI_D3 */ 130 <STM32_PINMUX('E', 11, AF13)>,/* DCMI_D4 */ 131 <STM32_PINMUX('D', 3, AF13)>,/* DCMI_D5 */ 132 <STM32_PINMUX('E', 13, AF13)>,/* DCMI_D6 */ 133 <STM32_PINMUX('B', 9, AF13)>;/* DCMI_D7 */ 134 bias-disable; 135 }; 136 }; 137 138 dcmi_sleep_pins_b: dcmi-sleep-1 { 139 pins { 140 pinmux = <STM32_PINMUX('A', 4, ANALOG)>,/* DCMI_HSYNC */ 141 <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */ 142 <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */ 143 <STM32_PINMUX('C', 6, ANALOG)>,/* DCMI_D0 */ 144 <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */ 145 <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */ 146 <STM32_PINMUX('E', 1, ANALOG)>,/* DCMI_D3 */ 147 <STM32_PINMUX('E', 11, ANALOG)>,/* DCMI_D4 */ 148 <STM32_PINMUX('D', 3, ANALOG)>,/* DCMI_D5 */ 149 <STM32_PINMUX('E', 13, ANALOG)>,/* DCMI_D6 */ 150 <STM32_PINMUX('B', 9, ANALOG)>;/* DCMI_D7 */ 151 }; 152 }; 153 154 dcmi_pins_c: dcmi-2 { 155 pins { 156 pinmux = <STM32_PINMUX('A', 4, AF13)>,/* DCMI_HSYNC */ 157 <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */ 158 <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */ 159 <STM32_PINMUX('A', 9, AF13)>,/* DCMI_D0 */ 160 <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */ 161 <STM32_PINMUX('E', 0, AF13)>,/* DCMI_D2 */ 162 <STM32_PINMUX('E', 1, AF13)>,/* DCMI_D3 */ 163 <STM32_PINMUX('H', 14, AF13)>,/* DCMI_D4 */ 164 <STM32_PINMUX('I', 4, AF13)>,/* DCMI_D5 */ 165 <STM32_PINMUX('I', 6, AF13)>,/* DCMI_D6 */ 166 <STM32_PINMUX('E', 6, AF13)>,/* DCMI_D7 */ 167 <STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */ 168 <STM32_PINMUX('H', 7, AF13)>;/* DCMI_D9 */ 169 bias-pull-up; 170 }; 171 }; 172 173 dcmi_sleep_pins_c: dcmi-sleep-2 { 174 pins { 175 pinmux = <STM32_PINMUX('A', 4, ANALOG)>,/* DCMI_HSYNC */ 176 <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */ 177 <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */ 178 <STM32_PINMUX('A', 9, ANALOG)>,/* DCMI_D0 */ 179 <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */ 180 <STM32_PINMUX('E', 0, ANALOG)>,/* DCMI_D2 */ 181 <STM32_PINMUX('E', 1, ANALOG)>,/* DCMI_D3 */ 182 <STM32_PINMUX('H', 14, ANALOG)>,/* DCMI_D4 */ 183 <STM32_PINMUX('I', 4, ANALOG)>,/* DCMI_D5 */ 184 <STM32_PINMUX('I', 6, ANALOG)>,/* DCMI_D6 */ 185 <STM32_PINMUX('E', 6, ANALOG)>,/* DCMI_D7 */ 186 <STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */ 187 <STM32_PINMUX('H', 7, ANALOG)>;/* DCMI_D9 */ 188 }; 189 }; 190 191 ethernet0_rgmii_pins_a: rgmii-0 { 192 pins1 { 193 pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */ 194 <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */ 195 <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */ 196 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */ 197 <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */ 198 <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */ 199 <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */ 200 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */ 201 bias-disable; 202 drive-push-pull; 203 slew-rate = <2>; 204 }; 205 pins2 { 206 pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */ 207 bias-disable; 208 drive-push-pull; 209 slew-rate = <0>; 210 }; 211 pins3 { 212 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */ 213 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */ 214 <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */ 215 <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */ 216 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */ 217 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */ 218 bias-disable; 219 }; 220 }; 221 222 ethernet0_rgmii_sleep_pins_a: rgmii-sleep-0 { 223 pins1 { 224 pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */ 225 <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */ 226 <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */ 227 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */ 228 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */ 229 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */ 230 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */ 231 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */ 232 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */ 233 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */ 234 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */ 235 <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD2 */ 236 <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */ 237 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */ 238 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */ 239 }; 240 }; 241 242 ethernet0_rgmii_pins_b: rgmii-1 { 243 pins1 { 244 pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */ 245 <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */ 246 <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */ 247 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */ 248 <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */ 249 <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */ 250 <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */ 251 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */ 252 bias-disable; 253 drive-push-pull; 254 slew-rate = <2>; 255 }; 256 pins2 { 257 pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */ 258 bias-disable; 259 drive-push-pull; 260 slew-rate = <0>; 261 }; 262 pins3 { 263 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */ 264 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */ 265 <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */ 266 <STM32_PINMUX('H', 7, AF11)>, /* ETH_RGMII_RXD3 */ 267 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */ 268 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */ 269 bias-disable; 270 }; 271 }; 272 273 ethernet0_rgmii_sleep_pins_b: rgmii-sleep-1 { 274 pins1 { 275 pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */ 276 <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */ 277 <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */ 278 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */ 279 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */ 280 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */ 281 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */ 282 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */ 283 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */ 284 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */ 285 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */ 286 <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */ 287 <STM32_PINMUX('H', 7, ANALOG)>, /* ETH_RGMII_RXD3 */ 288 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */ 289 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */ 290 }; 291 }; 292 293 ethernet0_rgmii_pins_c: rgmii-2 { 294 pins1 { 295 pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */ 296 <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */ 297 <STM32_PINMUX('B', 12, AF11)>, /* ETH_RGMII_TXD0 */ 298 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */ 299 <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */ 300 <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */ 301 <STM32_PINMUX('G', 11, AF11)>, /* ETH_RGMII_TX_CTL */ 302 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */ 303 bias-disable; 304 drive-push-pull; 305 slew-rate = <2>; 306 }; 307 pins2 { 308 pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */ 309 bias-disable; 310 drive-push-pull; 311 slew-rate = <0>; 312 }; 313 pins3 { 314 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */ 315 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */ 316 <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */ 317 <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */ 318 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */ 319 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */ 320 bias-disable; 321 }; 322 }; 323 324 ethernet0_rgmii_sleep_pins_c: rgmii-sleep-2 { 325 pins1 { 326 pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */ 327 <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */ 328 <STM32_PINMUX('B', 12, ANALOG)>, /* ETH_RGMII_TXD0 */ 329 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */ 330 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */ 331 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */ 332 <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */ 333 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */ 334 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */ 335 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */ 336 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */ 337 <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */ 338 <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */ 339 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */ 340 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */ 341 }; 342 }; 343 344 ethernet0_rmii_pins_a: rmii-0 { 345 pins1 { 346 pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */ 347 <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */ 348 <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */ 349 <STM32_PINMUX('A', 1, AF0)>, /* ETH1_RMII_REF_CLK */ 350 <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */ 351 <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */ 352 bias-disable; 353 drive-push-pull; 354 slew-rate = <2>; 355 }; 356 pins2 { 357 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */ 358 <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */ 359 <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */ 360 bias-disable; 361 }; 362 }; 363 364 ethernet0_rmii_sleep_pins_a: rmii-sleep-0 { 365 pins1 { 366 pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */ 367 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */ 368 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */ 369 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */ 370 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */ 371 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */ 372 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */ 373 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */ 374 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */ 375 }; 376 }; 377 378 ethernet0_rmii_pins_b: rmii-1 { 379 pins1 { 380 pinmux = <STM32_PINMUX('B', 5, AF0)>, /* ETH1_CLK */ 381 <STM32_PINMUX('C', 1, AF11)>, /* ETH1_MDC */ 382 <STM32_PINMUX('G', 13, AF11)>, /* ETH1_TXD0 */ 383 <STM32_PINMUX('G', 14, AF11)>; /* ETH1_TXD1 */ 384 bias-disable; 385 drive-push-pull; 386 slew-rate = <1>; 387 }; 388 pins2 { 389 pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH1_MDIO */ 390 bias-disable; 391 drive-push-pull; 392 slew-rate = <0>; 393 }; 394 pins3 { 395 pinmux = <STM32_PINMUX('A', 7, AF11)>, /* ETH1_CRS_DV */ 396 <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RXD0 */ 397 <STM32_PINMUX('C', 5, AF11)>; /* ETH1_RXD1 */ 398 bias-disable; 399 }; 400 pins4 { 401 pinmux = <STM32_PINMUX('B', 11, AF11)>; /* ETH1_TX_EN */ 402 }; 403 }; 404 405 ethernet0_rmii_sleep_pins_b: rmii-sleep-1 { 406 pins1 { 407 pinmux = <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */ 408 <STM32_PINMUX('A', 7, ANALOG)>, /* ETH1_CRS_DV */ 409 <STM32_PINMUX('B', 5, ANALOG)>, /* ETH1_CLK */ 410 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_TX_EN */ 411 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */ 412 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RXD0 */ 413 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RXD1 */ 414 <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_TXD0 */ 415 <STM32_PINMUX('G', 14, ANALOG)>; /* ETH1_TXD1 */ 416 }; 417 }; 418 419 ethernet0_rmii_pins_c: rmii-2 { 420 pins1 { 421 pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */ 422 <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */ 423 <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */ 424 <STM32_PINMUX('A', 1, AF11)>, /* ETH1_RMII_REF_CLK */ 425 <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */ 426 <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */ 427 bias-disable; 428 drive-push-pull; 429 slew-rate = <2>; 430 }; 431 pins2 { 432 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */ 433 <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */ 434 <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */ 435 bias-disable; 436 }; 437 }; 438 439 ethernet0_rmii_sleep_pins_c: rmii-sleep-2 { 440 pins1 { 441 pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */ 442 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */ 443 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */ 444 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */ 445 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */ 446 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */ 447 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */ 448 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */ 449 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */ 450 }; 451 }; 452 453 fmc_pins_a: fmc-0 { 454 pins1 { 455 pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */ 456 <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */ 457 <STM32_PINMUX('D', 11, AF12)>, /* FMC_A16_FMC_CLE */ 458 <STM32_PINMUX('D', 12, AF12)>, /* FMC_A17_FMC_ALE */ 459 <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */ 460 <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */ 461 <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */ 462 <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */ 463 <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */ 464 <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */ 465 <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */ 466 <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */ 467 <STM32_PINMUX('G', 9, AF12)>; /* FMC_NE2_FMC_NCE */ 468 bias-disable; 469 drive-push-pull; 470 slew-rate = <1>; 471 }; 472 pins2 { 473 pinmux = <STM32_PINMUX('D', 6, AF12)>; /* FMC_NWAIT */ 474 bias-pull-up; 475 }; 476 }; 477 478 fmc_sleep_pins_a: fmc-sleep-0 { 479 pins { 480 pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */ 481 <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */ 482 <STM32_PINMUX('D', 11, ANALOG)>, /* FMC_A16_FMC_CLE */ 483 <STM32_PINMUX('D', 12, ANALOG)>, /* FMC_A17_FMC_ALE */ 484 <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */ 485 <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */ 486 <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */ 487 <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */ 488 <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */ 489 <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */ 490 <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */ 491 <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */ 492 <STM32_PINMUX('D', 6, ANALOG)>, /* FMC_NWAIT */ 493 <STM32_PINMUX('G', 9, ANALOG)>; /* FMC_NE2_FMC_NCE */ 494 }; 495 }; 496 497 fmc_pins_b: fmc-1 { 498 pins { 499 pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */ 500 <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */ 501 <STM32_PINMUX('B', 7, AF12)>, /* FMC_NL */ 502 <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */ 503 <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */ 504 <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */ 505 <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */ 506 <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */ 507 <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */ 508 <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */ 509 <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */ 510 <STM32_PINMUX('E', 11, AF12)>, /* FMC_D8 */ 511 <STM32_PINMUX('E', 12, AF12)>, /* FMC_D9 */ 512 <STM32_PINMUX('E', 13, AF12)>, /* FMC_D10 */ 513 <STM32_PINMUX('E', 14, AF12)>, /* FMC_D11 */ 514 <STM32_PINMUX('E', 15, AF12)>, /* FMC_D12 */ 515 <STM32_PINMUX('D', 8, AF12)>, /* FMC_D13 */ 516 <STM32_PINMUX('D', 9, AF12)>, /* FMC_D14 */ 517 <STM32_PINMUX('D', 10, AF12)>, /* FMC_D15 */ 518 <STM32_PINMUX('G', 9, AF12)>, /* FMC_NE2_FMC_NCE */ 519 <STM32_PINMUX('G', 12, AF12)>; /* FMC_NE4 */ 520 bias-disable; 521 drive-push-pull; 522 slew-rate = <3>; 523 }; 524 }; 525 526 fmc_sleep_pins_b: fmc-sleep-1 { 527 pins { 528 pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */ 529 <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */ 530 <STM32_PINMUX('B', 7, ANALOG)>, /* FMC_NL */ 531 <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */ 532 <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */ 533 <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */ 534 <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */ 535 <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */ 536 <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */ 537 <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */ 538 <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */ 539 <STM32_PINMUX('E', 11, ANALOG)>, /* FMC_D8 */ 540 <STM32_PINMUX('E', 12, ANALOG)>, /* FMC_D9 */ 541 <STM32_PINMUX('E', 13, ANALOG)>, /* FMC_D10 */ 542 <STM32_PINMUX('E', 14, ANALOG)>, /* FMC_D11 */ 543 <STM32_PINMUX('E', 15, ANALOG)>, /* FMC_D12 */ 544 <STM32_PINMUX('D', 8, ANALOG)>, /* FMC_D13 */ 545 <STM32_PINMUX('D', 9, ANALOG)>, /* FMC_D14 */ 546 <STM32_PINMUX('D', 10, ANALOG)>, /* FMC_D15 */ 547 <STM32_PINMUX('G', 9, ANALOG)>, /* FMC_NE2_FMC_NCE */ 548 <STM32_PINMUX('G', 12, ANALOG)>; /* FMC_NE4 */ 549 }; 550 }; 551 552 i2c1_pins_a: i2c1-0 { 553 pins { 554 pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */ 555 <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */ 556 bias-disable; 557 drive-open-drain; 558 slew-rate = <0>; 559 }; 560 }; 561 562 i2c1_sleep_pins_a: i2c1-sleep-0 { 563 pins { 564 pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */ 565 <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */ 566 }; 567 }; 568 569 i2c1_pins_b: i2c1-1 { 570 pins { 571 pinmux = <STM32_PINMUX('F', 14, AF5)>, /* I2C1_SCL */ 572 <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */ 573 bias-disable; 574 drive-open-drain; 575 slew-rate = <0>; 576 }; 577 }; 578 579 i2c1_sleep_pins_b: i2c1-sleep-1 { 580 pins { 581 pinmux = <STM32_PINMUX('F', 14, ANALOG)>, /* I2C1_SCL */ 582 <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */ 583 }; 584 }; 585 586 i2c2_pins_a: i2c2-0 { 587 pins { 588 pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */ 589 <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */ 590 bias-disable; 591 drive-open-drain; 592 slew-rate = <0>; 593 }; 594 }; 595 596 i2c2_sleep_pins_a: i2c2-sleep-0 { 597 pins { 598 pinmux = <STM32_PINMUX('H', 4, ANALOG)>, /* I2C2_SCL */ 599 <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */ 600 }; 601 }; 602 603 i2c2_pins_b1: i2c2-1 { 604 pins { 605 pinmux = <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */ 606 bias-disable; 607 drive-open-drain; 608 slew-rate = <0>; 609 }; 610 }; 611 612 i2c2_sleep_pins_b1: i2c2-sleep-1 { 613 pins { 614 pinmux = <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */ 615 }; 616 }; 617 618 i2c2_pins_c: i2c2-2 { 619 pins { 620 pinmux = <STM32_PINMUX('F', 1, AF4)>, /* I2C2_SCL */ 621 <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */ 622 bias-disable; 623 drive-open-drain; 624 slew-rate = <0>; 625 }; 626 }; 627 628 i2c2_pins_sleep_c: i2c2-sleep-2 { 629 pins { 630 pinmux = <STM32_PINMUX('F', 1, ANALOG)>, /* I2C2_SCL */ 631 <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */ 632 }; 633 }; 634 635 i2c5_pins_a: i2c5-0 { 636 pins { 637 pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */ 638 <STM32_PINMUX('A', 12, AF4)>; /* I2C5_SDA */ 639 bias-disable; 640 drive-open-drain; 641 slew-rate = <0>; 642 }; 643 }; 644 645 i2c5_sleep_pins_a: i2c5-sleep-0 { 646 pins { 647 pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* I2C5_SCL */ 648 <STM32_PINMUX('A', 12, ANALOG)>; /* I2C5_SDA */ 649 650 }; 651 }; 652 653 i2c5_pins_b: i2c5-1 { 654 pins { 655 pinmux = <STM32_PINMUX('D', 0, AF4)>, /* I2C5_SCL */ 656 <STM32_PINMUX('D', 1, AF4)>; /* I2C5_SDA */ 657 bias-disable; 658 drive-open-drain; 659 slew-rate = <0>; 660 }; 661 }; 662 663 i2c5_sleep_pins_b: i2c5-sleep-1 { 664 pins { 665 pinmux = <STM32_PINMUX('D', 0, ANALOG)>, /* I2C5_SCL */ 666 <STM32_PINMUX('D', 1, ANALOG)>; /* I2C5_SDA */ 667 }; 668 }; 669 670 i2s2_pins_a: i2s2-0 { 671 pins { 672 pinmux = <STM32_PINMUX('I', 3, AF5)>, /* I2S2_SDO */ 673 <STM32_PINMUX('B', 9, AF5)>, /* I2S2_WS */ 674 <STM32_PINMUX('A', 9, AF5)>; /* I2S2_CK */ 675 slew-rate = <1>; 676 drive-push-pull; 677 bias-disable; 678 }; 679 }; 680 681 i2s2_sleep_pins_a: i2s2-sleep-0 { 682 pins { 683 pinmux = <STM32_PINMUX('I', 3, ANALOG)>, /* I2S2_SDO */ 684 <STM32_PINMUX('B', 9, ANALOG)>, /* I2S2_WS */ 685 <STM32_PINMUX('A', 9, ANALOG)>; /* I2S2_CK */ 686 }; 687 }; 688 689 ltdc_pins_a: ltdc-0 { 690 pins { 691 pinmux = <STM32_PINMUX('G', 7, AF14)>, /* LCD_CLK */ 692 <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */ 693 <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */ 694 <STM32_PINMUX('F', 10, AF14)>, /* LCD_DE */ 695 <STM32_PINMUX('H', 2, AF14)>, /* LCD_R0 */ 696 <STM32_PINMUX('H', 3, AF14)>, /* LCD_R1 */ 697 <STM32_PINMUX('H', 8, AF14)>, /* LCD_R2 */ 698 <STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */ 699 <STM32_PINMUX('H', 10, AF14)>, /* LCD_R4 */ 700 <STM32_PINMUX('C', 0, AF14)>, /* LCD_R5 */ 701 <STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */ 702 <STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */ 703 <STM32_PINMUX('E', 5, AF14)>, /* LCD_G0 */ 704 <STM32_PINMUX('E', 6, AF14)>, /* LCD_G1 */ 705 <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */ 706 <STM32_PINMUX('H', 14, AF14)>, /* LCD_G3 */ 707 <STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */ 708 <STM32_PINMUX('I', 0, AF14)>, /* LCD_G5 */ 709 <STM32_PINMUX('I', 1, AF14)>, /* LCD_G6 */ 710 <STM32_PINMUX('I', 2, AF14)>, /* LCD_G7 */ 711 <STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */ 712 <STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */ 713 <STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */ 714 <STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */ 715 <STM32_PINMUX('I', 4, AF14)>, /* LCD_B4 */ 716 <STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */ 717 <STM32_PINMUX('B', 8, AF14)>, /* LCD_B6 */ 718 <STM32_PINMUX('D', 8, AF14)>; /* LCD_B7 */ 719 bias-disable; 720 drive-push-pull; 721 slew-rate = <1>; 722 }; 723 }; 724 725 ltdc_sleep_pins_a: ltdc-sleep-0 { 726 pins { 727 pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */ 728 <STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */ 729 <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */ 730 <STM32_PINMUX('F', 10, ANALOG)>, /* LCD_DE */ 731 <STM32_PINMUX('H', 2, ANALOG)>, /* LCD_R0 */ 732 <STM32_PINMUX('H', 3, ANALOG)>, /* LCD_R1 */ 733 <STM32_PINMUX('H', 8, ANALOG)>, /* LCD_R2 */ 734 <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */ 735 <STM32_PINMUX('H', 10, ANALOG)>, /* LCD_R4 */ 736 <STM32_PINMUX('C', 0, ANALOG)>, /* LCD_R5 */ 737 <STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */ 738 <STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */ 739 <STM32_PINMUX('E', 5, ANALOG)>, /* LCD_G0 */ 740 <STM32_PINMUX('E', 6, ANALOG)>, /* LCD_G1 */ 741 <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */ 742 <STM32_PINMUX('H', 14, ANALOG)>, /* LCD_G3 */ 743 <STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */ 744 <STM32_PINMUX('I', 0, ANALOG)>, /* LCD_G5 */ 745 <STM32_PINMUX('I', 1, ANALOG)>, /* LCD_G6 */ 746 <STM32_PINMUX('I', 2, ANALOG)>, /* LCD_G7 */ 747 <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */ 748 <STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */ 749 <STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */ 750 <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */ 751 <STM32_PINMUX('I', 4, ANALOG)>, /* LCD_B4 */ 752 <STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */ 753 <STM32_PINMUX('B', 8, ANALOG)>, /* LCD_B6 */ 754 <STM32_PINMUX('D', 8, ANALOG)>; /* LCD_B7 */ 755 }; 756 }; 757 758 ltdc_pins_b: ltdc-1 { 759 pins { 760 pinmux = <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */ 761 <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */ 762 <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */ 763 <STM32_PINMUX('K', 7, AF14)>, /* LCD_DE */ 764 <STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */ 765 <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */ 766 <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */ 767 <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */ 768 <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */ 769 <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */ 770 <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6 */ 771 <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */ 772 <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */ 773 <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */ 774 <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */ 775 <STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */ 776 <STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */ 777 <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */ 778 <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */ 779 <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */ 780 <STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */ 781 <STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */ 782 <STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */ 783 <STM32_PINMUX('J', 15, AF14)>, /* LCD_B3 */ 784 <STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */ 785 <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */ 786 <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */ 787 <STM32_PINMUX('K', 6, AF14)>; /* LCD_B7 */ 788 bias-disable; 789 drive-push-pull; 790 slew-rate = <1>; 791 }; 792 }; 793 794 ltdc_sleep_pins_b: ltdc-sleep-1 { 795 pins { 796 pinmux = <STM32_PINMUX('I', 14, ANALOG)>, /* LCD_CLK */ 797 <STM32_PINMUX('I', 12, ANALOG)>, /* LCD_HSYNC */ 798 <STM32_PINMUX('I', 13, ANALOG)>, /* LCD_VSYNC */ 799 <STM32_PINMUX('K', 7, ANALOG)>, /* LCD_DE */ 800 <STM32_PINMUX('I', 15, ANALOG)>, /* LCD_R0 */ 801 <STM32_PINMUX('J', 0, ANALOG)>, /* LCD_R1 */ 802 <STM32_PINMUX('J', 1, ANALOG)>, /* LCD_R2 */ 803 <STM32_PINMUX('J', 2, ANALOG)>, /* LCD_R3 */ 804 <STM32_PINMUX('J', 3, ANALOG)>, /* LCD_R4 */ 805 <STM32_PINMUX('J', 4, ANALOG)>, /* LCD_R5 */ 806 <STM32_PINMUX('J', 5, ANALOG)>, /* LCD_R6 */ 807 <STM32_PINMUX('J', 6, ANALOG)>, /* LCD_R7 */ 808 <STM32_PINMUX('J', 7, ANALOG)>, /* LCD_G0 */ 809 <STM32_PINMUX('J', 8, ANALOG)>, /* LCD_G1 */ 810 <STM32_PINMUX('J', 9, ANALOG)>, /* LCD_G2 */ 811 <STM32_PINMUX('J', 10, ANALOG)>, /* LCD_G3 */ 812 <STM32_PINMUX('J', 11, ANALOG)>, /* LCD_G4 */ 813 <STM32_PINMUX('K', 0, ANALOG)>, /* LCD_G5 */ 814 <STM32_PINMUX('K', 1, ANALOG)>, /* LCD_G6 */ 815 <STM32_PINMUX('K', 2, ANALOG)>, /* LCD_G7 */ 816 <STM32_PINMUX('J', 12, ANALOG)>, /* LCD_B0 */ 817 <STM32_PINMUX('J', 13, ANALOG)>, /* LCD_B1 */ 818 <STM32_PINMUX('J', 14, ANALOG)>, /* LCD_B2 */ 819 <STM32_PINMUX('J', 15, ANALOG)>, /* LCD_B3 */ 820 <STM32_PINMUX('K', 3, ANALOG)>, /* LCD_B4 */ 821 <STM32_PINMUX('K', 4, ANALOG)>, /* LCD_B5 */ 822 <STM32_PINMUX('K', 5, ANALOG)>, /* LCD_B6 */ 823 <STM32_PINMUX('K', 6, ANALOG)>; /* LCD_B7 */ 824 }; 825 }; 826 827 ltdc_pins_c: ltdc-2 { 828 pins1 { 829 pinmux = <STM32_PINMUX('B', 1, AF9)>, /* LTDC_R6 */ 830 <STM32_PINMUX('B', 9, AF14)>, /* LTDC_B7 */ 831 <STM32_PINMUX('C', 0, AF14)>, /* LTDC_R5 */ 832 <STM32_PINMUX('D', 3, AF14)>, /* LTDC_G7 */ 833 <STM32_PINMUX('D', 6, AF14)>, /* LTDC_B2 */ 834 <STM32_PINMUX('D', 10, AF14)>, /* LTDC_B3 */ 835 <STM32_PINMUX('E', 11, AF14)>, /* LTDC_G3 */ 836 <STM32_PINMUX('E', 12, AF14)>, /* LTDC_B4 */ 837 <STM32_PINMUX('E', 13, AF14)>, /* LTDC_DE */ 838 <STM32_PINMUX('E', 15, AF14)>, /* LTDC_R7 */ 839 <STM32_PINMUX('H', 4, AF9)>, /* LTDC_G5 */ 840 <STM32_PINMUX('H', 8, AF14)>, /* LTDC_R2 */ 841 <STM32_PINMUX('H', 9, AF14)>, /* LTDC_R3 */ 842 <STM32_PINMUX('H', 10, AF14)>, /* LTDC_R4 */ 843 <STM32_PINMUX('H', 13, AF14)>, /* LTDC_G2 */ 844 <STM32_PINMUX('H', 15, AF14)>, /* LTDC_G4 */ 845 <STM32_PINMUX('I', 1, AF14)>, /* LTDC_G6 */ 846 <STM32_PINMUX('I', 5, AF14)>, /* LTDC_B5 */ 847 <STM32_PINMUX('I', 6, AF14)>, /* LTDC_B6 */ 848 <STM32_PINMUX('I', 9, AF14)>, /* LTDC_VSYNC */ 849 <STM32_PINMUX('I', 10, AF14)>; /* LTDC_HSYNC */ 850 bias-disable; 851 drive-push-pull; 852 slew-rate = <0>; 853 }; 854 pins2 { 855 pinmux = <STM32_PINMUX('E', 14, AF14)>; /* LTDC_CLK */ 856 bias-disable; 857 drive-push-pull; 858 slew-rate = <1>; 859 }; 860 }; 861 862 ltdc_sleep_pins_c: ltdc-sleep-2 { 863 pins1 { 864 pinmux = <STM32_PINMUX('B', 1, ANALOG)>, /* LTDC_R6 */ 865 <STM32_PINMUX('B', 9, ANALOG)>, /* LTDC_B7 */ 866 <STM32_PINMUX('C', 0, ANALOG)>, /* LTDC_R5 */ 867 <STM32_PINMUX('D', 3, ANALOG)>, /* LTDC_G7 */ 868 <STM32_PINMUX('D', 6, ANALOG)>, /* LTDC_B2 */ 869 <STM32_PINMUX('D', 10, ANALOG)>, /* LTDC_B3 */ 870 <STM32_PINMUX('E', 11, ANALOG)>, /* LTDC_G3 */ 871 <STM32_PINMUX('E', 12, ANALOG)>, /* LTDC_B4 */ 872 <STM32_PINMUX('E', 13, ANALOG)>, /* LTDC_DE */ 873 <STM32_PINMUX('E', 15, ANALOG)>, /* LTDC_R7 */ 874 <STM32_PINMUX('H', 4, ANALOG)>, /* LTDC_G5 */ 875 <STM32_PINMUX('H', 8, ANALOG)>, /* LTDC_R2 */ 876 <STM32_PINMUX('H', 9, ANALOG)>, /* LTDC_R3 */ 877 <STM32_PINMUX('H', 10, ANALOG)>, /* LTDC_R4 */ 878 <STM32_PINMUX('H', 13, ANALOG)>, /* LTDC_G2 */ 879 <STM32_PINMUX('H', 15, ANALOG)>, /* LTDC_G4 */ 880 <STM32_PINMUX('I', 1, ANALOG)>, /* LTDC_G6 */ 881 <STM32_PINMUX('I', 5, ANALOG)>, /* LTDC_B5 */ 882 <STM32_PINMUX('I', 6, ANALOG)>, /* LTDC_B6 */ 883 <STM32_PINMUX('I', 9, ANALOG)>, /* LTDC_VSYNC */ 884 <STM32_PINMUX('I', 10, ANALOG)>, /* LTDC_HSYNC */ 885 <STM32_PINMUX('E', 14, ANALOG)>; /* LTDC_CLK */ 886 }; 887 }; 888 889 ltdc_pins_d: ltdc-3 { 890 pins1 { 891 pinmux = <STM32_PINMUX('G', 7, AF14)>; /* LCD_CLK */ 892 bias-disable; 893 drive-push-pull; 894 slew-rate = <3>; 895 }; 896 pins2 { 897 pinmux = <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */ 898 <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */ 899 <STM32_PINMUX('E', 13, AF14)>, /* LCD_DE */ 900 <STM32_PINMUX('G', 13, AF14)>, /* LCD_R0 */ 901 <STM32_PINMUX('H', 3, AF14)>, /* LCD_R1 */ 902 <STM32_PINMUX('H', 8, AF14)>, /* LCD_R2 */ 903 <STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */ 904 <STM32_PINMUX('A', 5, AF14)>, /* LCD_R4 */ 905 <STM32_PINMUX('H', 11, AF14)>, /* LCD_R5 */ 906 <STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */ 907 <STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */ 908 <STM32_PINMUX('E', 5, AF14)>, /* LCD_G0 */ 909 <STM32_PINMUX('B', 0, AF14)>, /* LCD_G1 */ 910 <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */ 911 <STM32_PINMUX('E', 11, AF14)>, /* LCD_G3 */ 912 <STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */ 913 <STM32_PINMUX('H', 4, AF9)>, /* LCD_G5 */ 914 <STM32_PINMUX('I', 11, AF9)>, /* LCD_G6 */ 915 <STM32_PINMUX('G', 8, AF14)>, /* LCD_G7 */ 916 <STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */ 917 <STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */ 918 <STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */ 919 <STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */ 920 <STM32_PINMUX('E', 12, AF14)>, /* LCD_B4 */ 921 <STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */ 922 <STM32_PINMUX('B', 8, AF14)>, /* LCD_B6 */ 923 <STM32_PINMUX('I', 7, AF14)>; /* LCD_B7 */ 924 bias-disable; 925 drive-push-pull; 926 slew-rate = <2>; 927 }; 928 }; 929 930 ltdc_sleep_pins_d: ltdc-sleep-3 { 931 pins { 932 pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */ 933 <STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */ 934 <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */ 935 <STM32_PINMUX('E', 13, ANALOG)>, /* LCD_DE */ 936 <STM32_PINMUX('G', 13, ANALOG)>, /* LCD_R0 */ 937 <STM32_PINMUX('H', 3, ANALOG)>, /* LCD_R1 */ 938 <STM32_PINMUX('H', 8, ANALOG)>, /* LCD_R2 */ 939 <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */ 940 <STM32_PINMUX('A', 5, ANALOG)>, /* LCD_R4 */ 941 <STM32_PINMUX('H', 11, ANALOG)>, /* LCD_R5 */ 942 <STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */ 943 <STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */ 944 <STM32_PINMUX('E', 5, ANALOG)>, /* LCD_G0 */ 945 <STM32_PINMUX('B', 0, ANALOG)>, /* LCD_G1 */ 946 <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */ 947 <STM32_PINMUX('E', 11, ANALOG)>, /* LCD_G3 */ 948 <STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */ 949 <STM32_PINMUX('H', 4, ANALOG)>, /* LCD_G5 */ 950 <STM32_PINMUX('I', 11, ANALOG)>, /* LCD_G6 */ 951 <STM32_PINMUX('G', 8, ANALOG)>, /* LCD_G7 */ 952 <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */ 953 <STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */ 954 <STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */ 955 <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */ 956 <STM32_PINMUX('E', 12, ANALOG)>, /* LCD_B4 */ 957 <STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */ 958 <STM32_PINMUX('B', 8, ANALOG)>, /* LCD_B6 */ 959 <STM32_PINMUX('I', 7, ANALOG)>; /* LCD_B7 */ 960 }; 961 }; 962 963 mco1_pins_a: mco1-0 { 964 pins { 965 pinmux = <STM32_PINMUX('A', 13, AF2)>; /* MCO1 */ 966 bias-disable; 967 drive-push-pull; 968 slew-rate = <1>; 969 }; 970 }; 971 972 mco1_sleep_pins_a: mco1-sleep-0 { 973 pins { 974 pinmux = <STM32_PINMUX('A', 13, ANALOG)>; /* MCO1 */ 975 }; 976 }; 977 978 mco2_pins_a: mco2-0 { 979 pins { 980 pinmux = <STM32_PINMUX('G', 2, AF1)>; /* MCO2 */ 981 bias-disable; 982 drive-push-pull; 983 slew-rate = <2>; 984 }; 985 }; 986 987 mco2_sleep_pins_a: mco2-sleep-0 { 988 pins { 989 pinmux = <STM32_PINMUX('G', 2, ANALOG)>; /* MCO2 */ 990 }; 991 }; 992 993 m_can1_pins_a: m-can1-0 { 994 pins1 { 995 pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */ 996 slew-rate = <1>; 997 drive-push-pull; 998 bias-disable; 999 }; 1000 pins2 { 1001 pinmux = <STM32_PINMUX('I', 9, AF9)>; /* CAN1_RX */ 1002 bias-disable; 1003 }; 1004 }; 1005 1006 m_can1_sleep_pins_a: m_can1-sleep-0 { 1007 pins { 1008 pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */ 1009 <STM32_PINMUX('I', 9, ANALOG)>; /* CAN1_RX */ 1010 }; 1011 }; 1012 1013 m_can1_pins_b: m-can1-1 { 1014 pins1 { 1015 pinmux = <STM32_PINMUX('A', 12, AF9)>; /* CAN1_TX */ 1016 slew-rate = <1>; 1017 drive-push-pull; 1018 bias-disable; 1019 }; 1020 pins2 { 1021 pinmux = <STM32_PINMUX('A', 11, AF9)>; /* CAN1_RX */ 1022 bias-disable; 1023 }; 1024 }; 1025 1026 m_can1_sleep_pins_b: m_can1-sleep-1 { 1027 pins { 1028 pinmux = <STM32_PINMUX('A', 12, ANALOG)>, /* CAN1_TX */ 1029 <STM32_PINMUX('A', 11, ANALOG)>; /* CAN1_RX */ 1030 }; 1031 }; 1032 1033 m_can1_pins_c: m-can1-2 { 1034 pins1 { 1035 pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */ 1036 slew-rate = <1>; 1037 drive-push-pull; 1038 bias-disable; 1039 }; 1040 pins2 { 1041 pinmux = <STM32_PINMUX('H', 14, AF9)>; /* CAN1_RX */ 1042 bias-disable; 1043 }; 1044 }; 1045 1046 m_can1_sleep_pins_c: m_can1-sleep-2 { 1047 pins { 1048 pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */ 1049 <STM32_PINMUX('H', 14, ANALOG)>; /* CAN1_RX */ 1050 }; 1051 }; 1052 1053 m_can2_pins_a: m-can2-0 { 1054 pins1 { 1055 pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */ 1056 slew-rate = <1>; 1057 drive-push-pull; 1058 bias-disable; 1059 }; 1060 pins2 { 1061 pinmux = <STM32_PINMUX('B', 5, AF9)>; /* CAN2_RX */ 1062 bias-disable; 1063 }; 1064 }; 1065 1066 m_can2_sleep_pins_a: m_can2-sleep-0 { 1067 pins { 1068 pinmux = <STM32_PINMUX('B', 13, ANALOG)>, /* CAN2_TX */ 1069 <STM32_PINMUX('B', 5, ANALOG)>; /* CAN2_RX */ 1070 }; 1071 }; 1072 1073 pwm1_pins_a: pwm1-0 { 1074 pins { 1075 pinmux = <STM32_PINMUX('E', 9, AF1)>, /* TIM1_CH1 */ 1076 <STM32_PINMUX('E', 11, AF1)>, /* TIM1_CH2 */ 1077 <STM32_PINMUX('E', 14, AF1)>; /* TIM1_CH4 */ 1078 bias-pull-down; 1079 drive-push-pull; 1080 slew-rate = <0>; 1081 }; 1082 }; 1083 1084 pwm1_sleep_pins_a: pwm1-sleep-0 { 1085 pins { 1086 pinmux = <STM32_PINMUX('E', 9, ANALOG)>, /* TIM1_CH1 */ 1087 <STM32_PINMUX('E', 11, ANALOG)>, /* TIM1_CH2 */ 1088 <STM32_PINMUX('E', 14, ANALOG)>; /* TIM1_CH4 */ 1089 }; 1090 }; 1091 1092 pwm1_pins_b: pwm1-1 { 1093 pins { 1094 pinmux = <STM32_PINMUX('E', 9, AF1)>; /* TIM1_CH1 */ 1095 bias-pull-down; 1096 drive-push-pull; 1097 slew-rate = <0>; 1098 }; 1099 }; 1100 1101 pwm1_sleep_pins_b: pwm1-sleep-1 { 1102 pins { 1103 pinmux = <STM32_PINMUX('E', 9, ANALOG)>; /* TIM1_CH1 */ 1104 }; 1105 }; 1106 1107 pwm2_pins_a: pwm2-0 { 1108 pins { 1109 pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */ 1110 bias-pull-down; 1111 drive-push-pull; 1112 slew-rate = <0>; 1113 }; 1114 }; 1115 1116 pwm2_sleep_pins_a: pwm2-sleep-0 { 1117 pins { 1118 pinmux = <STM32_PINMUX('A', 3, ANALOG)>; /* TIM2_CH4 */ 1119 }; 1120 }; 1121 1122 pwm3_pins_a: pwm3-0 { 1123 pins { 1124 pinmux = <STM32_PINMUX('C', 7, AF2)>; /* TIM3_CH2 */ 1125 bias-pull-down; 1126 drive-push-pull; 1127 slew-rate = <0>; 1128 }; 1129 }; 1130 1131 pwm3_sleep_pins_a: pwm3-sleep-0 { 1132 pins { 1133 pinmux = <STM32_PINMUX('C', 7, ANALOG)>; /* TIM3_CH2 */ 1134 }; 1135 }; 1136 1137 pwm3_pins_b: pwm3-1 { 1138 pins { 1139 pinmux = <STM32_PINMUX('B', 5, AF2)>; /* TIM3_CH2 */ 1140 bias-disable; 1141 drive-push-pull; 1142 slew-rate = <0>; 1143 }; 1144 }; 1145 1146 pwm3_sleep_pins_b: pwm3-sleep-1 { 1147 pins { 1148 pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* TIM3_CH2 */ 1149 }; 1150 }; 1151 1152 pwm4_pins_a: pwm4-0 { 1153 pins { 1154 pinmux = <STM32_PINMUX('D', 14, AF2)>, /* TIM4_CH3 */ 1155 <STM32_PINMUX('D', 15, AF2)>; /* TIM4_CH4 */ 1156 bias-pull-down; 1157 drive-push-pull; 1158 slew-rate = <0>; 1159 }; 1160 }; 1161 1162 pwm4_sleep_pins_a: pwm4-sleep-0 { 1163 pins { 1164 pinmux = <STM32_PINMUX('D', 14, ANALOG)>, /* TIM4_CH3 */ 1165 <STM32_PINMUX('D', 15, ANALOG)>; /* TIM4_CH4 */ 1166 }; 1167 }; 1168 1169 pwm4_pins_b: pwm4-1 { 1170 pins { 1171 pinmux = <STM32_PINMUX('D', 13, AF2)>; /* TIM4_CH2 */ 1172 bias-pull-down; 1173 drive-push-pull; 1174 slew-rate = <0>; 1175 }; 1176 }; 1177 1178 pwm4_sleep_pins_b: pwm4-sleep-1 { 1179 pins { 1180 pinmux = <STM32_PINMUX('D', 13, ANALOG)>; /* TIM4_CH2 */ 1181 }; 1182 }; 1183 1184 pwm5_pins_a: pwm5-0 { 1185 pins { 1186 pinmux = <STM32_PINMUX('H', 11, AF2)>; /* TIM5_CH2 */ 1187 bias-pull-down; 1188 drive-push-pull; 1189 slew-rate = <0>; 1190 }; 1191 }; 1192 1193 pwm5_sleep_pins_a: pwm5-sleep-0 { 1194 pins { 1195 pinmux = <STM32_PINMUX('H', 11, ANALOG)>; /* TIM5_CH2 */ 1196 }; 1197 }; 1198 1199 pwm5_pins_b: pwm5-1 { 1200 pins { 1201 pinmux = <STM32_PINMUX('H', 11, AF2)>, /* TIM5_CH2 */ 1202 <STM32_PINMUX('H', 12, AF2)>, /* TIM5_CH3 */ 1203 <STM32_PINMUX('I', 0, AF2)>; /* TIM5_CH4 */ 1204 bias-disable; 1205 drive-push-pull; 1206 slew-rate = <0>; 1207 }; 1208 }; 1209 1210 pwm5_sleep_pins_b: pwm5-sleep-1 { 1211 pins { 1212 pinmux = <STM32_PINMUX('H', 11, ANALOG)>, /* TIM5_CH2 */ 1213 <STM32_PINMUX('H', 12, ANALOG)>, /* TIM5_CH3 */ 1214 <STM32_PINMUX('I', 0, ANALOG)>; /* TIM5_CH4 */ 1215 }; 1216 }; 1217 1218 pwm8_pins_a: pwm8-0 { 1219 pins { 1220 pinmux = <STM32_PINMUX('I', 2, AF3)>; /* TIM8_CH4 */ 1221 bias-pull-down; 1222 drive-push-pull; 1223 slew-rate = <0>; 1224 }; 1225 }; 1226 1227 pwm8_sleep_pins_a: pwm8-sleep-0 { 1228 pins { 1229 pinmux = <STM32_PINMUX('I', 2, ANALOG)>; /* TIM8_CH4 */ 1230 }; 1231 }; 1232 1233 pwm12_pins_a: pwm12-0 { 1234 pins { 1235 pinmux = <STM32_PINMUX('H', 6, AF2)>; /* TIM12_CH1 */ 1236 bias-pull-down; 1237 drive-push-pull; 1238 slew-rate = <0>; 1239 }; 1240 }; 1241 1242 pwm12_sleep_pins_a: pwm12-sleep-0 { 1243 pins { 1244 pinmux = <STM32_PINMUX('H', 6, ANALOG)>; /* TIM12_CH1 */ 1245 }; 1246 }; 1247 1248 qspi_clk_pins_a: qspi-clk-0 { 1249 pins { 1250 pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */ 1251 bias-disable; 1252 drive-push-pull; 1253 slew-rate = <3>; 1254 }; 1255 }; 1256 1257 qspi_clk_sleep_pins_a: qspi-clk-sleep-0 { 1258 pins { 1259 pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */ 1260 }; 1261 }; 1262 1263 qspi_bk1_pins_a: qspi-bk1-0 { 1264 pins { 1265 pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */ 1266 <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */ 1267 <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */ 1268 <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */ 1269 bias-disable; 1270 drive-push-pull; 1271 slew-rate = <1>; 1272 }; 1273 }; 1274 1275 qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 { 1276 pins { 1277 pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */ 1278 <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */ 1279 <STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */ 1280 <STM32_PINMUX('F', 6, ANALOG)>; /* QSPI_BK1_IO3 */ 1281 }; 1282 }; 1283 1284 qspi_bk2_pins_a: qspi-bk2-0 { 1285 pins { 1286 pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */ 1287 <STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */ 1288 <STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */ 1289 <STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */ 1290 bias-disable; 1291 drive-push-pull; 1292 slew-rate = <1>; 1293 }; 1294 }; 1295 1296 qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 { 1297 pins { 1298 pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */ 1299 <STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */ 1300 <STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */ 1301 <STM32_PINMUX('G', 7, ANALOG)>; /* QSPI_BK2_IO3 */ 1302 }; 1303 }; 1304 1305 qspi_cs1_pins_a: qspi-cs1-0 { 1306 pins { 1307 pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */ 1308 bias-pull-up; 1309 drive-push-pull; 1310 slew-rate = <1>; 1311 }; 1312 }; 1313 1314 qspi_cs1_sleep_pins_a: qspi-cs1-sleep-0 { 1315 pins { 1316 pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */ 1317 }; 1318 }; 1319 1320 qspi_cs2_pins_a: qspi-cs2-0 { 1321 pins { 1322 pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */ 1323 bias-pull-up; 1324 drive-push-pull; 1325 slew-rate = <1>; 1326 }; 1327 }; 1328 1329 qspi_cs2_sleep_pins_a: qspi-cs2-sleep-0 { 1330 pins { 1331 pinmux = <STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */ 1332 }; 1333 }; 1334 1335 sai2a_pins_a: sai2a-0 { 1336 pins { 1337 pinmux = <STM32_PINMUX('I', 5, AF10)>, /* SAI2_SCK_A */ 1338 <STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */ 1339 <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */ 1340 <STM32_PINMUX('E', 0, AF10)>; /* SAI2_MCLK_A */ 1341 slew-rate = <0>; 1342 drive-push-pull; 1343 bias-disable; 1344 }; 1345 }; 1346 1347 sai2a_sleep_pins_a: sai2a-sleep-0 { 1348 pins { 1349 pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* SAI2_SCK_A */ 1350 <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */ 1351 <STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */ 1352 <STM32_PINMUX('E', 0, ANALOG)>; /* SAI2_MCLK_A */ 1353 }; 1354 }; 1355 1356 sai2a_pins_b: sai2a-1 { 1357 pins1 { 1358 pinmux = <STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */ 1359 <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */ 1360 <STM32_PINMUX('D', 13, AF10)>; /* SAI2_SCK_A */ 1361 slew-rate = <0>; 1362 drive-push-pull; 1363 bias-disable; 1364 }; 1365 }; 1366 1367 sai2a_sleep_pins_b: sai2a-sleep-1 { 1368 pins { 1369 pinmux = <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */ 1370 <STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */ 1371 <STM32_PINMUX('D', 13, ANALOG)>; /* SAI2_SCK_A */ 1372 }; 1373 }; 1374 1375 sai2a_pins_c: sai2a-2 { 1376 pins { 1377 pinmux = <STM32_PINMUX('D', 13, AF10)>, /* SAI2_SCK_A */ 1378 <STM32_PINMUX('D', 11, AF10)>, /* SAI2_SD_A */ 1379 <STM32_PINMUX('D', 12, AF10)>; /* SAI2_FS_A */ 1380 slew-rate = <0>; 1381 drive-push-pull; 1382 bias-disable; 1383 }; 1384 }; 1385 1386 sai2a_sleep_pins_c: sai2a-sleep-2 { 1387 pins { 1388 pinmux = <STM32_PINMUX('D', 13, ANALOG)>, /* SAI2_SCK_A */ 1389 <STM32_PINMUX('D', 11, ANALOG)>, /* SAI2_SD_A */ 1390 <STM32_PINMUX('D', 12, ANALOG)>; /* SAI2_FS_A */ 1391 }; 1392 }; 1393 1394 sai2b_pins_a: sai2b-0 { 1395 pins1 { 1396 pinmux = <STM32_PINMUX('E', 12, AF10)>, /* SAI2_SCK_B */ 1397 <STM32_PINMUX('E', 13, AF10)>, /* SAI2_FS_B */ 1398 <STM32_PINMUX('E', 14, AF10)>; /* SAI2_MCLK_B */ 1399 slew-rate = <0>; 1400 drive-push-pull; 1401 bias-disable; 1402 }; 1403 pins2 { 1404 pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */ 1405 bias-disable; 1406 }; 1407 }; 1408 1409 sai2b_sleep_pins_a: sai2b-sleep-0 { 1410 pins { 1411 pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* SAI2_SD_B */ 1412 <STM32_PINMUX('E', 12, ANALOG)>, /* SAI2_SCK_B */ 1413 <STM32_PINMUX('E', 13, ANALOG)>, /* SAI2_FS_B */ 1414 <STM32_PINMUX('E', 14, ANALOG)>; /* SAI2_MCLK_B */ 1415 }; 1416 }; 1417 1418 sai2b_pins_b: sai2b-1 { 1419 pins { 1420 pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */ 1421 bias-disable; 1422 }; 1423 }; 1424 1425 sai2b_sleep_pins_b: sai2b-sleep-1 { 1426 pins { 1427 pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */ 1428 }; 1429 }; 1430 1431 sai2b_pins_c: sai2b-2 { 1432 pins1 { 1433 pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */ 1434 bias-disable; 1435 }; 1436 }; 1437 1438 sai2b_sleep_pins_c: sai2b-sleep-2 { 1439 pins { 1440 pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */ 1441 }; 1442 }; 1443 1444 sai4a_pins_a: sai4a-0 { 1445 pins { 1446 pinmux = <STM32_PINMUX('B', 5, AF10)>; /* SAI4_SD_A */ 1447 slew-rate = <0>; 1448 drive-push-pull; 1449 bias-disable; 1450 }; 1451 }; 1452 1453 sai4a_sleep_pins_a: sai4a-sleep-0 { 1454 pins { 1455 pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* SAI4_SD_A */ 1456 }; 1457 }; 1458 1459 sdmmc1_b4_pins_a: sdmmc1-b4-0 { 1460 pins1 { 1461 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ 1462 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ 1463 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ 1464 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */ 1465 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ 1466 slew-rate = <1>; 1467 drive-push-pull; 1468 bias-disable; 1469 }; 1470 pins2 { 1471 pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */ 1472 slew-rate = <2>; 1473 drive-push-pull; 1474 bias-disable; 1475 }; 1476 }; 1477 1478 sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { 1479 pins1 { 1480 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ 1481 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ 1482 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ 1483 <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */ 1484 slew-rate = <1>; 1485 drive-push-pull; 1486 bias-disable; 1487 }; 1488 pins2 { 1489 pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */ 1490 slew-rate = <2>; 1491 drive-push-pull; 1492 bias-disable; 1493 }; 1494 pins3 { 1495 pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ 1496 slew-rate = <1>; 1497 drive-open-drain; 1498 bias-disable; 1499 }; 1500 }; 1501 1502 sdmmc1_b4_init_pins_a: sdmmc1-b4-init-0 { 1503 pins1 { 1504 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ 1505 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ 1506 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ 1507 <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */ 1508 slew-rate = <1>; 1509 drive-push-pull; 1510 bias-disable; 1511 }; 1512 }; 1513 1514 sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { 1515 pins { 1516 pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */ 1517 <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */ 1518 <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */ 1519 <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */ 1520 <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */ 1521 <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */ 1522 }; 1523 }; 1524 1525 sdmmc1_dir_pins_a: sdmmc1-dir-0 { 1526 pins1 { 1527 pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */ 1528 <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */ 1529 <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */ 1530 slew-rate = <1>; 1531 drive-push-pull; 1532 bias-pull-up; 1533 }; 1534 pins2{ 1535 pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */ 1536 bias-pull-up; 1537 }; 1538 }; 1539 1540 sdmmc1_dir_init_pins_a: sdmmc1-dir-init-0 { 1541 pins1 { 1542 pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */ 1543 <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */ 1544 <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */ 1545 slew-rate = <1>; 1546 drive-push-pull; 1547 bias-pull-up; 1548 }; 1549 }; 1550 1551 sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 { 1552 pins { 1553 pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */ 1554 <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */ 1555 <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */ 1556 <STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */ 1557 }; 1558 }; 1559 1560 sdmmc1_dir_pins_b: sdmmc1-dir-1 { 1561 pins1 { 1562 pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */ 1563 <STM32_PINMUX('E', 14, AF11)>, /* SDMMC1_D123DIR */ 1564 <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */ 1565 slew-rate = <1>; 1566 drive-push-pull; 1567 bias-pull-up; 1568 }; 1569 pins2{ 1570 pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */ 1571 bias-pull-up; 1572 }; 1573 }; 1574 1575 sdmmc1_dir_sleep_pins_b: sdmmc1-dir-sleep-1 { 1576 pins { 1577 pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */ 1578 <STM32_PINMUX('E', 14, ANALOG)>, /* SDMMC1_D123DIR */ 1579 <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */ 1580 <STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */ 1581 }; 1582 }; 1583 1584 sdmmc2_b4_pins_a: sdmmc2-b4-0 { 1585 pins1 { 1586 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ 1587 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */ 1588 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ 1589 <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */ 1590 <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ 1591 slew-rate = <1>; 1592 drive-push-pull; 1593 bias-pull-up; 1594 }; 1595 pins2 { 1596 pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */ 1597 slew-rate = <2>; 1598 drive-push-pull; 1599 bias-pull-up; 1600 }; 1601 }; 1602 1603 sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 { 1604 pins1 { 1605 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ 1606 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */ 1607 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ 1608 <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */ 1609 slew-rate = <1>; 1610 drive-push-pull; 1611 bias-pull-up; 1612 }; 1613 pins2 { 1614 pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */ 1615 slew-rate = <2>; 1616 drive-push-pull; 1617 bias-pull-up; 1618 }; 1619 pins3 { 1620 pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ 1621 slew-rate = <1>; 1622 drive-open-drain; 1623 bias-pull-up; 1624 }; 1625 }; 1626 1627 sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 { 1628 pins { 1629 pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */ 1630 <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC2_D1 */ 1631 <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */ 1632 <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */ 1633 <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */ 1634 <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */ 1635 }; 1636 }; 1637 1638 sdmmc2_b4_pins_b: sdmmc2-b4-1 { 1639 pins1 { 1640 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ 1641 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */ 1642 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ 1643 <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */ 1644 <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ 1645 slew-rate = <1>; 1646 drive-push-pull; 1647 bias-disable; 1648 }; 1649 pins2 { 1650 pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */ 1651 slew-rate = <2>; 1652 drive-push-pull; 1653 bias-disable; 1654 }; 1655 }; 1656 1657 sdmmc2_b4_od_pins_b: sdmmc2-b4-od-1 { 1658 pins1 { 1659 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ 1660 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */ 1661 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ 1662 <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */ 1663 slew-rate = <1>; 1664 drive-push-pull; 1665 bias-disable; 1666 }; 1667 pins2 { 1668 pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */ 1669 slew-rate = <2>; 1670 drive-push-pull; 1671 bias-disable; 1672 }; 1673 pins3 { 1674 pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ 1675 slew-rate = <1>; 1676 drive-open-drain; 1677 bias-disable; 1678 }; 1679 }; 1680 1681 sdmmc2_d47_pins_a: sdmmc2-d47-0 { 1682 pins { 1683 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ 1684 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ 1685 <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */ 1686 <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */ 1687 slew-rate = <1>; 1688 drive-push-pull; 1689 bias-pull-up; 1690 }; 1691 }; 1692 1693 sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 { 1694 pins { 1695 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */ 1696 <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */ 1697 <STM32_PINMUX('E', 5, ANALOG)>, /* SDMMC2_D6 */ 1698 <STM32_PINMUX('D', 3, ANALOG)>; /* SDMMC2_D7 */ 1699 }; 1700 }; 1701 1702 sdmmc2_d47_pins_b: sdmmc2-d47-1 { 1703 pins { 1704 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ 1705 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ 1706 <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */ 1707 <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */ 1708 slew-rate = <1>; 1709 drive-push-pull; 1710 bias-disable; 1711 }; 1712 }; 1713 1714 sdmmc2_d47_sleep_pins_b: sdmmc2-d47-sleep-1 { 1715 pins { 1716 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */ 1717 <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */ 1718 <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */ 1719 <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */ 1720 }; 1721 }; 1722 1723 sdmmc2_d47_pins_c: sdmmc2-d47-2 { 1724 pins { 1725 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ 1726 <STM32_PINMUX('A', 15, AF9)>, /* SDMMC2_D5 */ 1727 <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */ 1728 <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */ 1729 slew-rate = <1>; 1730 drive-push-pull; 1731 bias-pull-up; 1732 }; 1733 }; 1734 1735 sdmmc2_d47_sleep_pins_c: sdmmc2-d47-sleep-2 { 1736 pins { 1737 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */ 1738 <STM32_PINMUX('A', 15, ANALOG)>, /* SDMMC2_D5 */ 1739 <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */ 1740 <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */ 1741 }; 1742 }; 1743 1744 sdmmc2_d47_pins_d: sdmmc2-d47-3 { 1745 pins { 1746 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ 1747 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ 1748 <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */ 1749 <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */ 1750 }; 1751 }; 1752 1753 sdmmc2_d47_sleep_pins_d: sdmmc2-d47-sleep-3 { 1754 pins { 1755 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */ 1756 <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */ 1757 <STM32_PINMUX('E', 5, ANALOG)>, /* SDMMC2_D6 */ 1758 <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */ 1759 }; 1760 }; 1761 1762 sdmmc3_b4_pins_a: sdmmc3-b4-0 { 1763 pins1 { 1764 pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */ 1765 <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */ 1766 <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */ 1767 <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */ 1768 <STM32_PINMUX('F', 1, AF9)>; /* SDMMC3_CMD */ 1769 slew-rate = <1>; 1770 drive-push-pull; 1771 bias-pull-up; 1772 }; 1773 pins2 { 1774 pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */ 1775 slew-rate = <2>; 1776 drive-push-pull; 1777 bias-pull-up; 1778 }; 1779 }; 1780 1781 sdmmc3_b4_od_pins_a: sdmmc3-b4-od-0 { 1782 pins1 { 1783 pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */ 1784 <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */ 1785 <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */ 1786 <STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */ 1787 slew-rate = <1>; 1788 drive-push-pull; 1789 bias-pull-up; 1790 }; 1791 pins2 { 1792 pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */ 1793 slew-rate = <2>; 1794 drive-push-pull; 1795 bias-pull-up; 1796 }; 1797 pins3 { 1798 pinmux = <STM32_PINMUX('F', 1, AF9)>; /* SDMMC2_CMD */ 1799 slew-rate = <1>; 1800 drive-open-drain; 1801 bias-pull-up; 1802 }; 1803 }; 1804 1805 sdmmc3_b4_sleep_pins_a: sdmmc3-b4-sleep-0 { 1806 pins { 1807 pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC3_D0 */ 1808 <STM32_PINMUX('F', 4, ANALOG)>, /* SDMMC3_D1 */ 1809 <STM32_PINMUX('F', 5, ANALOG)>, /* SDMMC3_D2 */ 1810 <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */ 1811 <STM32_PINMUX('G', 15, ANALOG)>, /* SDMMC3_CK */ 1812 <STM32_PINMUX('F', 1, ANALOG)>; /* SDMMC3_CMD */ 1813 }; 1814 }; 1815 1816 sdmmc3_b4_pins_b: sdmmc3-b4-1 { 1817 pins1 { 1818 pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */ 1819 <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */ 1820 <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */ 1821 <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */ 1822 <STM32_PINMUX('D', 0, AF10)>; /* SDMMC3_CMD */ 1823 slew-rate = <1>; 1824 drive-push-pull; 1825 bias-pull-up; 1826 }; 1827 pins2 { 1828 pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */ 1829 slew-rate = <2>; 1830 drive-push-pull; 1831 bias-pull-up; 1832 }; 1833 }; 1834 1835 sdmmc3_b4_od_pins_b: sdmmc3-b4-od-1 { 1836 pins1 { 1837 pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */ 1838 <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */ 1839 <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */ 1840 <STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */ 1841 slew-rate = <1>; 1842 drive-push-pull; 1843 bias-pull-up; 1844 }; 1845 pins2 { 1846 pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */ 1847 slew-rate = <2>; 1848 drive-push-pull; 1849 bias-pull-up; 1850 }; 1851 pins3 { 1852 pinmux = <STM32_PINMUX('D', 0, AF10)>; /* SDMMC2_CMD */ 1853 slew-rate = <1>; 1854 drive-open-drain; 1855 bias-pull-up; 1856 }; 1857 }; 1858 1859 sdmmc3_b4_sleep_pins_b: sdmmc3-b4-sleep-1 { 1860 pins { 1861 pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC3_D0 */ 1862 <STM32_PINMUX('F', 4, ANALOG)>, /* SDMMC3_D1 */ 1863 <STM32_PINMUX('D', 5, ANALOG)>, /* SDMMC3_D2 */ 1864 <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */ 1865 <STM32_PINMUX('G', 15, ANALOG)>, /* SDMMC3_CK */ 1866 <STM32_PINMUX('D', 0, ANALOG)>; /* SDMMC3_CMD */ 1867 }; 1868 }; 1869 1870 spdifrx_pins_a: spdifrx-0 { 1871 pins { 1872 pinmux = <STM32_PINMUX('G', 12, AF8)>; /* SPDIF_IN1 */ 1873 bias-disable; 1874 }; 1875 }; 1876 1877 spdifrx_sleep_pins_a: spdifrx-sleep-0 { 1878 pins { 1879 pinmux = <STM32_PINMUX('G', 12, ANALOG)>; /* SPDIF_IN1 */ 1880 }; 1881 }; 1882 1883 spi2_pins_a: spi2-0 { 1884 pins1 { 1885 pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI2_SCK */ 1886 <STM32_PINMUX('I', 3, AF5)>; /* SPI2_MOSI */ 1887 bias-disable; 1888 drive-push-pull; 1889 slew-rate = <1>; 1890 }; 1891 1892 pins2 { 1893 pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI2_MISO */ 1894 bias-disable; 1895 }; 1896 }; 1897 1898 spi2_pins_b: spi2-1 { 1899 pins1 { 1900 pinmux = <STM32_PINMUX('I', 1, AF5)>, /* SPI2_SCK */ 1901 <STM32_PINMUX('I', 3, AF5)>; /* SPI2_MOSI */ 1902 bias-disable; 1903 drive-push-pull; 1904 slew-rate = <1>; 1905 }; 1906 1907 pins2 { 1908 pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI2_MISO */ 1909 bias-disable; 1910 }; 1911 }; 1912 1913 spi4_pins_a: spi4-0 { 1914 pins { 1915 pinmux = <STM32_PINMUX('E', 12, AF5)>, /* SPI4_SCK */ 1916 <STM32_PINMUX('E', 6, AF5)>; /* SPI4_MOSI */ 1917 bias-disable; 1918 drive-push-pull; 1919 slew-rate = <1>; 1920 }; 1921 pins2 { 1922 pinmux = <STM32_PINMUX('E', 13, AF5)>; /* SPI4_MISO */ 1923 bias-disable; 1924 }; 1925 }; 1926 1927 stusb1600_pins_a: stusb1600-0 { 1928 pins { 1929 pinmux = <STM32_PINMUX('I', 11, GPIO)>; 1930 bias-pull-up; 1931 }; 1932 }; 1933 1934 uart4_pins_a: uart4-0 { 1935 pins1 { 1936 pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */ 1937 bias-disable; 1938 drive-push-pull; 1939 slew-rate = <0>; 1940 }; 1941 pins2 { 1942 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ 1943 bias-disable; 1944 }; 1945 }; 1946 1947 uart4_idle_pins_a: uart4-idle-0 { 1948 pins1 { 1949 pinmux = <STM32_PINMUX('G', 11, ANALOG)>; /* UART4_TX */ 1950 }; 1951 pins2 { 1952 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ 1953 bias-disable; 1954 }; 1955 }; 1956 1957 uart4_sleep_pins_a: uart4-sleep-0 { 1958 pins { 1959 pinmux = <STM32_PINMUX('G', 11, ANALOG)>, /* UART4_TX */ 1960 <STM32_PINMUX('B', 2, ANALOG)>; /* UART4_RX */ 1961 }; 1962 }; 1963 1964 uart4_pins_b: uart4-1 { 1965 pins1 { 1966 pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */ 1967 bias-disable; 1968 drive-push-pull; 1969 slew-rate = <0>; 1970 }; 1971 pins2 { 1972 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ 1973 bias-disable; 1974 }; 1975 }; 1976 1977 uart4_pins_c: uart4-2 { 1978 pins1 { 1979 pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */ 1980 bias-disable; 1981 drive-push-pull; 1982 slew-rate = <0>; 1983 }; 1984 pins2 { 1985 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ 1986 bias-disable; 1987 }; 1988 }; 1989 1990 uart4_pins_d: uart4-3 { 1991 pins1 { 1992 pinmux = <STM32_PINMUX('A', 13, AF8)>; /* UART4_TX */ 1993 bias-disable; 1994 drive-push-pull; 1995 slew-rate = <0>; 1996 }; 1997 pins2 { 1998 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ 1999 bias-disable; 2000 }; 2001 }; 2002 2003 uart4_idle_pins_d: uart4-idle-3 { 2004 pins1 { 2005 pinmux = <STM32_PINMUX('A', 13, ANALOG)>; /* UART4_TX */ 2006 }; 2007 pins2 { 2008 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ 2009 bias-disable; 2010 }; 2011 }; 2012 2013 uart4_sleep_pins_d: uart4-sleep-3 { 2014 pins { 2015 pinmux = <STM32_PINMUX('A', 13, ANALOG)>, /* UART4_TX */ 2016 <STM32_PINMUX('B', 2, ANALOG)>; /* UART4_RX */ 2017 }; 2018 }; 2019 2020 uart5_pins_a: uart5-0 { 2021 pins1 { 2022 pinmux = <STM32_PINMUX('B', 13, AF14)>; /* UART5_TX */ 2023 bias-disable; 2024 drive-push-pull; 2025 slew-rate = <0>; 2026 }; 2027 pins2 { 2028 pinmux = <STM32_PINMUX('B', 5, AF12)>; /* UART5_RX */ 2029 bias-disable; 2030 }; 2031 }; 2032 2033 uart7_pins_a: uart7-0 { 2034 pins1 { 2035 pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */ 2036 bias-disable; 2037 drive-push-pull; 2038 slew-rate = <0>; 2039 }; 2040 pins2 { 2041 pinmux = <STM32_PINMUX('E', 7, AF7)>, /* UART7_RX */ 2042 <STM32_PINMUX('E', 10, AF7)>, /* UART7_CTS */ 2043 <STM32_PINMUX('E', 9, AF7)>; /* UART7_RTS */ 2044 bias-disable; 2045 }; 2046 }; 2047 2048 uart7_pins_b: uart7-1 { 2049 pins1 { 2050 pinmux = <STM32_PINMUX('F', 7, AF7)>; /* UART7_TX */ 2051 bias-disable; 2052 drive-push-pull; 2053 slew-rate = <0>; 2054 }; 2055 pins2 { 2056 pinmux = <STM32_PINMUX('F', 6, AF7)>; /* UART7_RX */ 2057 bias-disable; 2058 }; 2059 }; 2060 2061 uart7_pins_c: uart7-2 { 2062 pins1 { 2063 pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */ 2064 bias-disable; 2065 drive-push-pull; 2066 slew-rate = <0>; 2067 }; 2068 pins2 { 2069 pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */ 2070 bias-pull-up; 2071 }; 2072 }; 2073 2074 uart7_idle_pins_c: uart7-idle-2 { 2075 pins1 { 2076 pinmux = <STM32_PINMUX('E', 8, ANALOG)>; /* UART7_TX */ 2077 }; 2078 pins2 { 2079 pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */ 2080 bias-pull-up; 2081 }; 2082 }; 2083 2084 uart7_sleep_pins_c: uart7-sleep-2 { 2085 pins { 2086 pinmux = <STM32_PINMUX('E', 8, ANALOG)>, /* UART7_TX */ 2087 <STM32_PINMUX('E', 7, ANALOG)>; /* UART7_RX */ 2088 }; 2089 }; 2090 2091 uart8_pins_a: uart8-0 { 2092 pins1 { 2093 pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */ 2094 bias-disable; 2095 drive-push-pull; 2096 slew-rate = <0>; 2097 }; 2098 pins2 { 2099 pinmux = <STM32_PINMUX('E', 0, AF8)>; /* UART8_RX */ 2100 bias-disable; 2101 }; 2102 }; 2103 2104 uart8_rtscts_pins_a: uart8rtscts-0 { 2105 pins { 2106 pinmux = <STM32_PINMUX('G', 7, AF8)>, /* UART8_RTS */ 2107 <STM32_PINMUX('G', 10, AF8)>; /* UART8_CTS */ 2108 bias-disable; 2109 }; 2110 }; 2111 2112 usart2_pins_a: usart2-0 { 2113 pins1 { 2114 pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */ 2115 <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */ 2116 bias-disable; 2117 drive-push-pull; 2118 slew-rate = <0>; 2119 }; 2120 pins2 { 2121 pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */ 2122 <STM32_PINMUX('D', 3, AF7)>; /* USART2_CTS_NSS */ 2123 bias-disable; 2124 }; 2125 }; 2126 2127 usart2_sleep_pins_a: usart2-sleep-0 { 2128 pins { 2129 pinmux = <STM32_PINMUX('F', 5, ANALOG)>, /* USART2_TX */ 2130 <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */ 2131 <STM32_PINMUX('D', 6, ANALOG)>, /* USART2_RX */ 2132 <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */ 2133 }; 2134 }; 2135 2136 usart2_pins_b: usart2-1 { 2137 pins1 { 2138 pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */ 2139 <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */ 2140 bias-disable; 2141 drive-push-pull; 2142 slew-rate = <0>; 2143 }; 2144 pins2 { 2145 pinmux = <STM32_PINMUX('F', 4, AF7)>, /* USART2_RX */ 2146 <STM32_PINMUX('E', 15, AF7)>; /* USART2_CTS_NSS */ 2147 bias-disable; 2148 }; 2149 }; 2150 2151 usart2_sleep_pins_b: usart2-sleep-1 { 2152 pins { 2153 pinmux = <STM32_PINMUX('F', 5, ANALOG)>, /* USART2_TX */ 2154 <STM32_PINMUX('A', 1, ANALOG)>, /* USART2_RTS */ 2155 <STM32_PINMUX('F', 4, ANALOG)>, /* USART2_RX */ 2156 <STM32_PINMUX('E', 15, ANALOG)>; /* USART2_CTS_NSS */ 2157 }; 2158 }; 2159 2160 usart2_pins_c: usart2-2 { 2161 pins1 { 2162 pinmux = <STM32_PINMUX('D', 5, AF7)>, /* USART2_TX */ 2163 <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */ 2164 bias-disable; 2165 drive-push-pull; 2166 slew-rate = <3>; 2167 }; 2168 pins2 { 2169 pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */ 2170 <STM32_PINMUX('D', 3, AF7)>; /* USART2_CTS_NSS */ 2171 bias-disable; 2172 }; 2173 }; 2174 2175 usart2_idle_pins_c: usart2-idle-2 { 2176 pins1 { 2177 pinmux = <STM32_PINMUX('D', 5, ANALOG)>, /* USART2_TX */ 2178 <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */ 2179 }; 2180 pins2 { 2181 pinmux = <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */ 2182 bias-disable; 2183 drive-push-pull; 2184 slew-rate = <3>; 2185 }; 2186 pins3 { 2187 pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */ 2188 bias-disable; 2189 }; 2190 }; 2191 2192 usart2_sleep_pins_c: usart2-sleep-2 { 2193 pins { 2194 pinmux = <STM32_PINMUX('D', 5, ANALOG)>, /* USART2_TX */ 2195 <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */ 2196 <STM32_PINMUX('D', 6, ANALOG)>, /* USART2_RX */ 2197 <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */ 2198 }; 2199 }; 2200 2201 usart3_pins_a: usart3-0 { 2202 pins1 { 2203 pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */ 2204 bias-disable; 2205 drive-push-pull; 2206 slew-rate = <0>; 2207 }; 2208 pins2 { 2209 pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */ 2210 bias-disable; 2211 }; 2212 }; 2213 2214 usart3_pins_b: usart3-1 { 2215 pins1 { 2216 pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ 2217 <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ 2218 bias-disable; 2219 drive-push-pull; 2220 slew-rate = <0>; 2221 }; 2222 pins2 { 2223 pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */ 2224 <STM32_PINMUX('I', 10, AF8)>; /* USART3_CTS_NSS */ 2225 bias-pull-up; 2226 }; 2227 }; 2228 2229 usart3_idle_pins_b: usart3-idle-1 { 2230 pins1 { 2231 pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ 2232 <STM32_PINMUX('I', 10, ANALOG)>; /* USART3_CTS_NSS */ 2233 }; 2234 pins2 { 2235 pinmux = <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ 2236 bias-disable; 2237 drive-push-pull; 2238 slew-rate = <0>; 2239 }; 2240 pins3 { 2241 pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */ 2242 bias-pull-up; 2243 }; 2244 }; 2245 2246 usart3_sleep_pins_b: usart3-sleep-1 { 2247 pins { 2248 pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ 2249 <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */ 2250 <STM32_PINMUX('I', 10, ANALOG)>, /* USART3_CTS_NSS */ 2251 <STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */ 2252 }; 2253 }; 2254 2255 usart3_pins_c: usart3-2 { 2256 pins1 { 2257 pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ 2258 <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ 2259 bias-disable; 2260 drive-push-pull; 2261 slew-rate = <0>; 2262 }; 2263 pins2 { 2264 pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */ 2265 <STM32_PINMUX('B', 13, AF7)>; /* USART3_CTS_NSS */ 2266 bias-pull-up; 2267 }; 2268 }; 2269 2270 usart3_idle_pins_c: usart3-idle-2 { 2271 pins1 { 2272 pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ 2273 <STM32_PINMUX('B', 13, ANALOG)>; /* USART3_CTS_NSS */ 2274 }; 2275 pins2 { 2276 pinmux = <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ 2277 bias-disable; 2278 drive-push-pull; 2279 slew-rate = <0>; 2280 }; 2281 pins3 { 2282 pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */ 2283 bias-pull-up; 2284 }; 2285 }; 2286 2287 usart3_sleep_pins_c: usart3-sleep-2 { 2288 pins { 2289 pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ 2290 <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */ 2291 <STM32_PINMUX('B', 13, ANALOG)>, /* USART3_CTS_NSS */ 2292 <STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */ 2293 }; 2294 }; 2295 2296 usart3_pins_d: usart3-3 { 2297 pins1 { 2298 pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ 2299 <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ 2300 bias-disable; 2301 drive-push-pull; 2302 slew-rate = <0>; 2303 }; 2304 pins2 { 2305 pinmux = <STM32_PINMUX('D', 9, AF7)>, /* USART3_RX */ 2306 <STM32_PINMUX('D', 11, AF7)>; /* USART3_CTS_NSS */ 2307 bias-disable; 2308 }; 2309 }; 2310 2311 usart3_idle_pins_d: usart3-idle-3 { 2312 pins1 { 2313 pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ 2314 <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */ 2315 <STM32_PINMUX('D', 11, ANALOG)>; /* USART3_CTS_NSS */ 2316 }; 2317 pins2 { 2318 pinmux = <STM32_PINMUX('D', 9, AF7)>; /* USART3_RX */ 2319 bias-disable; 2320 }; 2321 }; 2322 2323 usart3_sleep_pins_d: usart3-sleep-3 { 2324 pins { 2325 pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ 2326 <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */ 2327 <STM32_PINMUX('D', 11, ANALOG)>, /* USART3_CTS_NSS */ 2328 <STM32_PINMUX('D', 9, ANALOG)>; /* USART3_RX */ 2329 }; 2330 }; 2331 2332 usart3_pins_e: usart3-4 { 2333 pins1 { 2334 pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ 2335 <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ 2336 bias-disable; 2337 drive-push-pull; 2338 slew-rate = <0>; 2339 }; 2340 pins2 { 2341 pinmux = <STM32_PINMUX('B', 11, AF7)>, /* USART3_RX */ 2342 <STM32_PINMUX('D', 11, AF7)>; /* USART3_CTS_NSS */ 2343 bias-pull-up; 2344 }; 2345 }; 2346 2347 usart3_idle_pins_e: usart3-idle-4 { 2348 pins1 { 2349 pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ 2350 <STM32_PINMUX('D', 11, ANALOG)>; /* USART3_CTS_NSS */ 2351 }; 2352 pins2 { 2353 pinmux = <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ 2354 bias-disable; 2355 drive-push-pull; 2356 slew-rate = <0>; 2357 }; 2358 pins3 { 2359 pinmux = <STM32_PINMUX('B', 11, AF7)>; /* USART3_RX */ 2360 bias-pull-up; 2361 }; 2362 }; 2363 2364 usart3_sleep_pins_e: usart3-sleep-4 { 2365 pins { 2366 pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ 2367 <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */ 2368 <STM32_PINMUX('D', 11, ANALOG)>, /* USART3_CTS_NSS */ 2369 <STM32_PINMUX('B', 11, ANALOG)>; /* USART3_RX */ 2370 }; 2371 }; 2372 2373 usbotg_hs_pins_a: usbotg-hs-0 { 2374 pins { 2375 pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */ 2376 }; 2377 }; 2378 2379 usbotg_fs_dp_dm_pins_a: usbotg-fs-dp-dm-0 { 2380 pins { 2381 pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* OTG_FS_DM */ 2382 <STM32_PINMUX('A', 12, ANALOG)>; /* OTG_FS_DP */ 2383 }; 2384 }; 2385}; 2386 2387&pinctrl_z { 2388 i2c2_pins_b2: i2c2-0 { 2389 pins { 2390 pinmux = <STM32_PINMUX('Z', 0, AF3)>; /* I2C2_SCL */ 2391 bias-disable; 2392 drive-open-drain; 2393 slew-rate = <0>; 2394 }; 2395 }; 2396 2397 i2c2_sleep_pins_b2: i2c2-sleep-0 { 2398 pins { 2399 pinmux = <STM32_PINMUX('Z', 0, ANALOG)>; /* I2C2_SCL */ 2400 }; 2401 }; 2402 2403 i2c4_pins_a: i2c4-0 { 2404 pins { 2405 pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */ 2406 <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */ 2407 bias-disable; 2408 drive-open-drain; 2409 slew-rate = <0>; 2410 }; 2411 }; 2412 2413 i2c4_sleep_pins_a: i2c4-sleep-0 { 2414 pins { 2415 pinmux = <STM32_PINMUX('Z', 4, ANALOG)>, /* I2C4_SCL */ 2416 <STM32_PINMUX('Z', 5, ANALOG)>; /* I2C4_SDA */ 2417 }; 2418 }; 2419 2420 i2c6_pins_a: i2c6-0 { 2421 pins { 2422 pinmux = <STM32_PINMUX('Z', 6, AF2)>, /* I2C6_SCL */ 2423 <STM32_PINMUX('Z', 7, AF2)>; /* I2C6_SDA */ 2424 bias-disable; 2425 drive-open-drain; 2426 slew-rate = <0>; 2427 }; 2428 }; 2429 2430 i2c6_sleep_pins_a: i2c6-sleep-0 { 2431 pins { 2432 pinmux = <STM32_PINMUX('Z', 6, ANALOG)>, /* I2C6_SCL */ 2433 <STM32_PINMUX('Z', 7, ANALOG)>; /* I2C6_SDA */ 2434 }; 2435 }; 2436 2437 spi1_pins_a: spi1-0 { 2438 pins1 { 2439 pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */ 2440 <STM32_PINMUX('Z', 2, AF5)>; /* SPI1_MOSI */ 2441 bias-disable; 2442 drive-push-pull; 2443 slew-rate = <1>; 2444 }; 2445 2446 pins2 { 2447 pinmux = <STM32_PINMUX('Z', 1, AF5)>; /* SPI1_MISO */ 2448 bias-disable; 2449 }; 2450 }; 2451 2452 spi1_pins_b: spi1-1 { 2453 pins1 { 2454 pinmux = <STM32_PINMUX('A', 5, AF5)>, /* SPI1_SCK */ 2455 <STM32_PINMUX('B', 5, AF5)>; /* SPI1_MOSI */ 2456 bias-disable; 2457 drive-push-pull; 2458 slew-rate = <1>; 2459 }; 2460 2461 pins2 { 2462 pinmux = <STM32_PINMUX('A', 6, AF5)>; /* SPI1_MISO */ 2463 bias-disable; 2464 }; 2465 }; 2466}; 2467
