1/* 2 * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com> 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This file is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This file is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43#include "skeleton.dtsi" 44#include "armv7-m.dtsi" 45#include <dt-bindings/clock/stm32h7-clks.h> 46#include <dt-bindings/mfd/stm32h7-rcc.h> 47#include <dt-bindings/interrupt-controller/irq.h> 48 49/ { 50 clocks { 51 clk_hse: clk-hse { 52 #clock-cells = <0>; 53 compatible = "fixed-clock"; 54 clock-frequency = <0>; 55 }; 56 57 clk_lse: clk-lse { 58 #clock-cells = <0>; 59 compatible = "fixed-clock"; 60 clock-frequency = <32768>; 61 }; 62 63 clk_i2s: i2s_ckin { 64 #clock-cells = <0>; 65 compatible = "fixed-clock"; 66 clock-frequency = <0>; 67 }; 68 }; 69 70 soc { 71 timer5: timer@40000c00 { 72 compatible = "st,stm32-timer"; 73 reg = <0x40000c00 0x400>; 74 interrupts = <50>; 75 clocks = <&rcc TIM5_CK>; 76 }; 77 78 lptimer1: timer@40002400 { 79 #address-cells = <1>; 80 #size-cells = <0>; 81 compatible = "st,stm32-lptimer"; 82 reg = <0x40002400 0x400>; 83 clocks = <&rcc LPTIM1_CK>; 84 clock-names = "mux"; 85 status = "disabled"; 86 87 pwm { 88 compatible = "st,stm32-pwm-lp"; 89 #pwm-cells = <3>; 90 status = "disabled"; 91 }; 92 93 trigger@0 { 94 compatible = "st,stm32-lptimer-trigger"; 95 reg = <0>; 96 status = "disabled"; 97 }; 98 99 counter { 100 compatible = "st,stm32-lptimer-counter"; 101 status = "disabled"; 102 }; 103 }; 104 105 spi2: spi@40003800 { 106 #address-cells = <1>; 107 #size-cells = <0>; 108 compatible = "st,stm32h7-spi"; 109 reg = <0x40003800 0x400>; 110 interrupts = <36>; 111 clocks = <&rcc SPI2_CK>; 112 status = "disabled"; 113 114 }; 115 116 spi3: spi@40003c00 { 117 #address-cells = <1>; 118 #size-cells = <0>; 119 compatible = "st,stm32h7-spi"; 120 reg = <0x40003c00 0x400>; 121 interrupts = <51>; 122 clocks = <&rcc SPI3_CK>; 123 status = "disabled"; 124 }; 125 126 usart2: serial@40004400 { 127 compatible = "st,stm32f7-uart"; 128 reg = <0x40004400 0x400>; 129 interrupts = <38>; 130 status = "disabled"; 131 clocks = <&rcc USART2_CK>; 132 }; 133 134 i2c1: i2c@40005400 { 135 compatible = "st,stm32f7-i2c"; 136 #address-cells = <1>; 137 #size-cells = <0>; 138 reg = <0x40005400 0x400>; 139 interrupts = <31>, 140 <32>; 141 resets = <&rcc STM32H7_APB1L_RESET(I2C1)>; 142 clocks = <&rcc I2C1_CK>; 143 status = "disabled"; 144 }; 145 146 i2c2: i2c@40005800 { 147 compatible = "st,stm32f7-i2c"; 148 #address-cells = <1>; 149 #size-cells = <0>; 150 reg = <0x40005800 0x400>; 151 interrupts = <33>, 152 <34>; 153 resets = <&rcc STM32H7_APB1L_RESET(I2C2)>; 154 clocks = <&rcc I2C2_CK>; 155 status = "disabled"; 156 }; 157 158 i2c3: i2c@40005C00 { 159 compatible = "st,stm32f7-i2c"; 160 #address-cells = <1>; 161 #size-cells = <0>; 162 reg = <0x40005C00 0x400>; 163 interrupts = <72>, 164 <73>; 165 resets = <&rcc STM32H7_APB1L_RESET(I2C3)>; 166 clocks = <&rcc I2C3_CK>; 167 status = "disabled"; 168 }; 169 170 dac: dac@40007400 { 171 compatible = "st,stm32h7-dac-core"; 172 reg = <0x40007400 0x400>; 173 clocks = <&rcc DAC12_CK>; 174 clock-names = "pclk"; 175 #address-cells = <1>; 176 #size-cells = <0>; 177 status = "disabled"; 178 179 dac1: dac@1 { 180 compatible = "st,stm32-dac"; 181 #io-channels-cells = <1>; 182 reg = <1>; 183 status = "disabled"; 184 }; 185 186 dac2: dac@2 { 187 compatible = "st,stm32-dac"; 188 #io-channels-cells = <1>; 189 reg = <2>; 190 status = "disabled"; 191 }; 192 }; 193 194 usart1: serial@40011000 { 195 compatible = "st,stm32f7-uart"; 196 reg = <0x40011000 0x400>; 197 interrupts = <37>; 198 status = "disabled"; 199 clocks = <&rcc USART1_CK>; 200 }; 201 202 spi1: spi@40013000 { 203 #address-cells = <1>; 204 #size-cells = <0>; 205 compatible = "st,stm32h7-spi"; 206 reg = <0x40013000 0x400>; 207 interrupts = <35>; 208 clocks = <&rcc SPI1_CK>; 209 status = "disabled"; 210 }; 211 212 spi4: spi@40013400 { 213 #address-cells = <1>; 214 #size-cells = <0>; 215 compatible = "st,stm32h7-spi"; 216 reg = <0x40013400 0x400>; 217 interrupts = <84>; 218 clocks = <&rcc SPI4_CK>; 219 status = "disabled"; 220 }; 221 222 spi5: spi@40015000 { 223 #address-cells = <1>; 224 #size-cells = <0>; 225 compatible = "st,stm32h7-spi"; 226 reg = <0x40015000 0x400>; 227 interrupts = <85>; 228 clocks = <&rcc SPI5_CK>; 229 status = "disabled"; 230 }; 231 232 dma1: dma@40020000 { 233 compatible = "st,stm32-dma"; 234 reg = <0x40020000 0x400>; 235 interrupts = <11>, 236 <12>, 237 <13>, 238 <14>, 239 <15>, 240 <16>, 241 <17>, 242 <47>; 243 clocks = <&rcc DMA1_CK>; 244 #dma-cells = <4>; 245 st,mem2mem; 246 dma-requests = <8>; 247 status = "disabled"; 248 }; 249 250 dma2: dma@40020400 { 251 compatible = "st,stm32-dma"; 252 reg = <0x40020400 0x400>; 253 interrupts = <56>, 254 <57>, 255 <58>, 256 <59>, 257 <60>, 258 <68>, 259 <69>, 260 <70>; 261 clocks = <&rcc DMA2_CK>; 262 #dma-cells = <4>; 263 st,mem2mem; 264 dma-requests = <8>; 265 status = "disabled"; 266 }; 267 268 dmamux1: dma-router@40020800 { 269 compatible = "st,stm32h7-dmamux"; 270 reg = <0x40020800 0x1c>; 271 #dma-cells = <3>; 272 dma-channels = <16>; 273 dma-requests = <128>; 274 dma-masters = <&dma1 &dma2>; 275 clocks = <&rcc DMA1_CK>; 276 }; 277 278 adc_12: adc@40022000 { 279 compatible = "st,stm32h7-adc-core"; 280 reg = <0x40022000 0x400>; 281 interrupts = <18>; 282 clocks = <&rcc ADC12_CK>; 283 clock-names = "bus"; 284 interrupt-controller; 285 #interrupt-cells = <1>; 286 #address-cells = <1>; 287 #size-cells = <0>; 288 status = "disabled"; 289 290 adc1: adc@0 { 291 compatible = "st,stm32h7-adc"; 292 #io-channel-cells = <1>; 293 reg = <0x0>; 294 interrupt-parent = <&adc_12>; 295 interrupts = <0>; 296 status = "disabled"; 297 }; 298 299 adc2: adc@100 { 300 compatible = "st,stm32h7-adc"; 301 #io-channel-cells = <1>; 302 reg = <0x100>; 303 interrupt-parent = <&adc_12>; 304 interrupts = <1>; 305 status = "disabled"; 306 }; 307 }; 308 309 usbotg_hs: usb@40040000 { 310 compatible = "st,stm32f7-hsotg"; 311 reg = <0x40040000 0x40000>; 312 interrupts = <77>; 313 clocks = <&rcc USB1OTG_CK>; 314 clock-names = "otg"; 315 g-rx-fifo-size = <256>; 316 g-np-tx-fifo-size = <32>; 317 g-tx-fifo-size = <128 128 64 64 64 64 32 32>; 318 status = "disabled"; 319 }; 320 321 usbotg_fs: usb@40080000 { 322 compatible = "st,stm32f4x9-fsotg"; 323 reg = <0x40080000 0x40000>; 324 interrupts = <101>; 325 clocks = <&rcc USB2OTG_CK>; 326 clock-names = "otg"; 327 status = "disabled"; 328 }; 329 330 mdma1: dma@52000000 { 331 compatible = "st,stm32h7-mdma"; 332 reg = <0x52000000 0x1000>; 333 interrupts = <122>; 334 clocks = <&rcc MDMA_CK>; 335 #dma-cells = <5>; 336 dma-channels = <16>; 337 dma-requests = <32>; 338 }; 339 340 exti: interrupt-controller@58000000 { 341 compatible = "st,stm32h7-exti"; 342 interrupt-controller; 343 #interrupt-cells = <2>; 344 reg = <0x58000000 0x400>; 345 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <62>, <76>; 346 }; 347 348 syscfg: system-config@58000400 { 349 compatible = "syscon"; 350 reg = <0x58000400 0x400>; 351 }; 352 353 spi6: spi@58001400 { 354 #address-cells = <1>; 355 #size-cells = <0>; 356 compatible = "st,stm32h7-spi"; 357 reg = <0x58001400 0x400>; 358 interrupts = <86>; 359 clocks = <&rcc SPI6_CK>; 360 status = "disabled"; 361 }; 362 363 i2c4: i2c@58001C00 { 364 compatible = "st,stm32f7-i2c"; 365 #address-cells = <1>; 366 #size-cells = <0>; 367 reg = <0x58001C00 0x400>; 368 interrupts = <95>, 369 <96>; 370 resets = <&rcc STM32H7_APB4_RESET(I2C4)>; 371 clocks = <&rcc I2C4_CK>; 372 status = "disabled"; 373 }; 374 375 lptimer2: timer@58002400 { 376 #address-cells = <1>; 377 #size-cells = <0>; 378 compatible = "st,stm32-lptimer"; 379 reg = <0x58002400 0x400>; 380 clocks = <&rcc LPTIM2_CK>; 381 clock-names = "mux"; 382 status = "disabled"; 383 384 pwm { 385 compatible = "st,stm32-pwm-lp"; 386 #pwm-cells = <3>; 387 status = "disabled"; 388 }; 389 390 trigger@1 { 391 compatible = "st,stm32-lptimer-trigger"; 392 reg = <1>; 393 status = "disabled"; 394 }; 395 396 counter { 397 compatible = "st,stm32-lptimer-counter"; 398 status = "disabled"; 399 }; 400 }; 401 402 lptimer3: timer@58002800 { 403 #address-cells = <1>; 404 #size-cells = <0>; 405 compatible = "st,stm32-lptimer"; 406 reg = <0x58002800 0x400>; 407 clocks = <&rcc LPTIM3_CK>; 408 clock-names = "mux"; 409 status = "disabled"; 410 411 pwm { 412 compatible = "st,stm32-pwm-lp"; 413 #pwm-cells = <3>; 414 status = "disabled"; 415 }; 416 417 trigger@2 { 418 compatible = "st,stm32-lptimer-trigger"; 419 reg = <2>; 420 status = "disabled"; 421 }; 422 }; 423 424 lptimer4: timer@58002c00 { 425 #address-cells = <1>; 426 #size-cells = <0>; 427 compatible = "st,stm32-lptimer"; 428 reg = <0x58002c00 0x400>; 429 clocks = <&rcc LPTIM4_CK>; 430 clock-names = "mux"; 431 status = "disabled"; 432 433 pwm { 434 compatible = "st,stm32-pwm-lp"; 435 #pwm-cells = <3>; 436 status = "disabled"; 437 }; 438 }; 439 440 lptimer5: timer@58003000 { 441 #address-cells = <1>; 442 #size-cells = <0>; 443 compatible = "st,stm32-lptimer"; 444 reg = <0x58003000 0x400>; 445 clocks = <&rcc LPTIM5_CK>; 446 clock-names = "mux"; 447 status = "disabled"; 448 449 pwm { 450 compatible = "st,stm32-pwm-lp"; 451 #pwm-cells = <3>; 452 status = "disabled"; 453 }; 454 }; 455 456 vrefbuf: regulator@58003c00 { 457 compatible = "st,stm32-vrefbuf"; 458 reg = <0x58003C00 0x8>; 459 clocks = <&rcc VREF_CK>; 460 regulator-min-microvolt = <1500000>; 461 regulator-max-microvolt = <2500000>; 462 status = "disabled"; 463 }; 464 465 rtc: rtc@58004000 { 466 compatible = "st,stm32h7-rtc"; 467 reg = <0x58004000 0x400>; 468 clocks = <&rcc RTCAPB_CK>, <&rcc RTC_CK>; 469 clock-names = "pclk", "rtc_ck"; 470 assigned-clocks = <&rcc RTC_CK>; 471 assigned-clock-parents = <&rcc LSE_CK>; 472 interrupt-parent = <&exti>; 473 interrupts = <17 IRQ_TYPE_EDGE_RISING>; 474 interrupt-names = "alarm"; 475 st,syscfg = <&pwrcfg>; 476 status = "disabled"; 477 }; 478 479 rcc: reset-clock-controller@58024400 { 480 compatible = "st,stm32h743-rcc", "st,stm32-rcc"; 481 reg = <0x58024400 0x400>; 482 #clock-cells = <1>; 483 #reset-cells = <1>; 484 clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>; 485 st,syscfg = <&pwrcfg>; 486 }; 487 488 pwrcfg: power-config@58024800 { 489 compatible = "syscon"; 490 reg = <0x58024800 0x400>; 491 }; 492 493 adc_3: adc@58026000 { 494 compatible = "st,stm32h7-adc-core"; 495 reg = <0x58026000 0x400>; 496 interrupts = <127>; 497 clocks = <&rcc ADC3_CK>; 498 clock-names = "bus"; 499 interrupt-controller; 500 #interrupt-cells = <1>; 501 #address-cells = <1>; 502 #size-cells = <0>; 503 status = "disabled"; 504 505 adc3: adc@0 { 506 compatible = "st,stm32h7-adc"; 507 #io-channel-cells = <1>; 508 reg = <0x0>; 509 interrupt-parent = <&adc_3>; 510 interrupts = <0>; 511 status = "disabled"; 512 }; 513 }; 514 }; 515}; 516 517&systick { 518 clock-frequency = <250000000>; 519 status = "okay"; 520}; 521
