1/* 2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com> 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This file is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This file is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43#include "armv7-m.dtsi" 44#include <dt-bindings/clock/stm32fx-clock.h> 45#include <dt-bindings/mfd/stm32f7-rcc.h> 46 47/ { 48 #address-cells = <1>; 49 #size-cells = <1>; 50 51 clocks { 52 clk_hse: clk-hse { 53 #clock-cells = <0>; 54 compatible = "fixed-clock"; 55 clock-frequency = <0>; 56 }; 57 58 clk-lse { 59 #clock-cells = <0>; 60 compatible = "fixed-clock"; 61 clock-frequency = <32768>; 62 }; 63 64 clk-lsi { 65 #clock-cells = <0>; 66 compatible = "fixed-clock"; 67 clock-frequency = <32000>; 68 }; 69 70 clk_i2s_ckin: clk-i2s-ckin { 71 #clock-cells = <0>; 72 compatible = "fixed-clock"; 73 clock-frequency = <48000000>; 74 }; 75 }; 76 77 soc { 78 timer2: timer@40000000 { 79 compatible = "st,stm32-timer"; 80 reg = <0x40000000 0x400>; 81 interrupts = <28>; 82 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>; 83 status = "disabled"; 84 }; 85 86 timers2: timers@40000000 { 87 #address-cells = <1>; 88 #size-cells = <0>; 89 compatible = "st,stm32-timers"; 90 reg = <0x40000000 0x400>; 91 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>; 92 clock-names = "int"; 93 status = "disabled"; 94 95 pwm { 96 compatible = "st,stm32-pwm"; 97 #pwm-cells = <3>; 98 status = "disabled"; 99 }; 100 101 timer@1 { 102 compatible = "st,stm32-timer-trigger"; 103 reg = <1>; 104 status = "disabled"; 105 }; 106 }; 107 108 timer3: timer@40000400 { 109 compatible = "st,stm32-timer"; 110 reg = <0x40000400 0x400>; 111 interrupts = <29>; 112 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>; 113 status = "disabled"; 114 }; 115 116 timers3: timers@40000400 { 117 #address-cells = <1>; 118 #size-cells = <0>; 119 compatible = "st,stm32-timers"; 120 reg = <0x40000400 0x400>; 121 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>; 122 clock-names = "int"; 123 status = "disabled"; 124 125 pwm { 126 compatible = "st,stm32-pwm"; 127 #pwm-cells = <3>; 128 status = "disabled"; 129 }; 130 131 timer@2 { 132 compatible = "st,stm32-timer-trigger"; 133 reg = <2>; 134 status = "disabled"; 135 }; 136 }; 137 138 timer4: timer@40000800 { 139 compatible = "st,stm32-timer"; 140 reg = <0x40000800 0x400>; 141 interrupts = <30>; 142 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>; 143 status = "disabled"; 144 }; 145 146 timers4: timers@40000800 { 147 #address-cells = <1>; 148 #size-cells = <0>; 149 compatible = "st,stm32-timers"; 150 reg = <0x40000800 0x400>; 151 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>; 152 clock-names = "int"; 153 status = "disabled"; 154 155 pwm { 156 compatible = "st,stm32-pwm"; 157 #pwm-cells = <3>; 158 status = "disabled"; 159 }; 160 161 timer@3 { 162 compatible = "st,stm32-timer-trigger"; 163 reg = <3>; 164 status = "disabled"; 165 }; 166 }; 167 168 timer5: timer@40000c00 { 169 compatible = "st,stm32-timer"; 170 reg = <0x40000c00 0x400>; 171 interrupts = <50>; 172 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>; 173 }; 174 175 timers5: timers@40000c00 { 176 #address-cells = <1>; 177 #size-cells = <0>; 178 compatible = "st,stm32-timers"; 179 reg = <0x40000C00 0x400>; 180 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>; 181 clock-names = "int"; 182 status = "disabled"; 183 184 pwm { 185 compatible = "st,stm32-pwm"; 186 #pwm-cells = <3>; 187 status = "disabled"; 188 }; 189 190 timer@4 { 191 compatible = "st,stm32-timer-trigger"; 192 reg = <4>; 193 status = "disabled"; 194 }; 195 }; 196 197 timer6: timer@40001000 { 198 compatible = "st,stm32-timer"; 199 reg = <0x40001000 0x400>; 200 interrupts = <54>; 201 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>; 202 status = "disabled"; 203 }; 204 205 timers6: timers@40001000 { 206 #address-cells = <1>; 207 #size-cells = <0>; 208 compatible = "st,stm32-timers"; 209 reg = <0x40001000 0x400>; 210 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>; 211 clock-names = "int"; 212 status = "disabled"; 213 214 timer@5 { 215 compatible = "st,stm32-timer-trigger"; 216 reg = <5>; 217 status = "disabled"; 218 }; 219 }; 220 221 timer7: timer@40001400 { 222 compatible = "st,stm32-timer"; 223 reg = <0x40001400 0x400>; 224 interrupts = <55>; 225 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>; 226 status = "disabled"; 227 }; 228 229 timers7: timers@40001400 { 230 #address-cells = <1>; 231 #size-cells = <0>; 232 compatible = "st,stm32-timers"; 233 reg = <0x40001400 0x400>; 234 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>; 235 clock-names = "int"; 236 status = "disabled"; 237 238 timer@6 { 239 compatible = "st,stm32-timer-trigger"; 240 reg = <6>; 241 status = "disabled"; 242 }; 243 }; 244 245 timers12: timers@40001800 { 246 #address-cells = <1>; 247 #size-cells = <0>; 248 compatible = "st,stm32-timers"; 249 reg = <0x40001800 0x400>; 250 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>; 251 clock-names = "int"; 252 status = "disabled"; 253 254 pwm { 255 compatible = "st,stm32-pwm"; 256 #pwm-cells = <3>; 257 status = "disabled"; 258 }; 259 260 timer@11 { 261 compatible = "st,stm32-timer-trigger"; 262 reg = <11>; 263 status = "disabled"; 264 }; 265 }; 266 267 timers13: timers@40001c00 { 268 #address-cells = <1>; 269 #size-cells = <0>; 270 compatible = "st,stm32-timers"; 271 reg = <0x40001C00 0x400>; 272 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>; 273 clock-names = "int"; 274 status = "disabled"; 275 276 pwm { 277 compatible = "st,stm32-pwm"; 278 #pwm-cells = <3>; 279 status = "disabled"; 280 }; 281 }; 282 283 timers14: timers@40002000 { 284 #address-cells = <1>; 285 #size-cells = <0>; 286 compatible = "st,stm32-timers"; 287 reg = <0x40002000 0x400>; 288 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>; 289 clock-names = "int"; 290 status = "disabled"; 291 292 pwm { 293 compatible = "st,stm32-pwm"; 294 #pwm-cells = <3>; 295 status = "disabled"; 296 }; 297 }; 298 299 rtc: rtc@40002800 { 300 compatible = "st,stm32-rtc"; 301 reg = <0x40002800 0x400>; 302 clocks = <&rcc 1 CLK_RTC>; 303 clock-names = "ck_rtc"; 304 assigned-clocks = <&rcc 1 CLK_RTC>; 305 assigned-clock-parents = <&rcc 1 CLK_LSE>; 306 interrupt-parent = <&exti>; 307 interrupts = <17 1>; 308 interrupt-names = "alarm"; 309 st,syscfg = <&pwrcfg 0x00 0x100>; 310 status = "disabled"; 311 }; 312 313 usart2: serial@40004400 { 314 compatible = "st,stm32f7-uart"; 315 reg = <0x40004400 0x400>; 316 interrupts = <38>; 317 clocks = <&rcc 1 CLK_USART2>; 318 status = "disabled"; 319 }; 320 321 usart3: serial@40004800 { 322 compatible = "st,stm32f7-uart"; 323 reg = <0x40004800 0x400>; 324 interrupts = <39>; 325 clocks = <&rcc 1 CLK_USART3>; 326 status = "disabled"; 327 }; 328 329 usart4: serial@40004c00 { 330 compatible = "st,stm32f7-uart"; 331 reg = <0x40004c00 0x400>; 332 interrupts = <52>; 333 clocks = <&rcc 1 CLK_UART4>; 334 status = "disabled"; 335 }; 336 337 usart5: serial@40005000 { 338 compatible = "st,stm32f7-uart"; 339 reg = <0x40005000 0x400>; 340 interrupts = <53>; 341 clocks = <&rcc 1 CLK_UART5>; 342 status = "disabled"; 343 }; 344 345 i2c1: i2c@40005400 { 346 compatible = "st,stm32f7-i2c"; 347 reg = <0x40005400 0x400>; 348 interrupts = <31>, 349 <32>; 350 resets = <&rcc STM32F7_APB1_RESET(I2C1)>; 351 clocks = <&rcc 1 CLK_I2C1>; 352 #address-cells = <1>; 353 #size-cells = <0>; 354 status = "disabled"; 355 }; 356 357 i2c2: i2c@40005800 { 358 compatible = "st,stm32f7-i2c"; 359 reg = <0x40005800 0x400>; 360 interrupts = <33>, 361 <34>; 362 resets = <&rcc STM32F7_APB1_RESET(I2C2)>; 363 clocks = <&rcc 1 CLK_I2C2>; 364 #address-cells = <1>; 365 #size-cells = <0>; 366 status = "disabled"; 367 }; 368 369 i2c3: i2c@40005C00 { 370 compatible = "st,stm32f7-i2c"; 371 reg = <0x40005C00 0x400>; 372 interrupts = <72>, 373 <73>; 374 resets = <&rcc STM32F7_APB1_RESET(I2C3)>; 375 clocks = <&rcc 1 CLK_I2C3>; 376 #address-cells = <1>; 377 #size-cells = <0>; 378 status = "disabled"; 379 }; 380 381 i2c4: i2c@40006000 { 382 compatible = "st,stm32f7-i2c"; 383 reg = <0x40006000 0x400>; 384 interrupts = <95>, 385 <96>; 386 resets = <&rcc STM32F7_APB1_RESET(I2C4)>; 387 clocks = <&rcc 1 CLK_I2C4>; 388 #address-cells = <1>; 389 #size-cells = <0>; 390 status = "disabled"; 391 }; 392 393 cec: cec@40006c00 { 394 compatible = "st,stm32-cec"; 395 reg = <0x40006C00 0x400>; 396 interrupts = <94>; 397 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>; 398 clock-names = "cec", "hdmi-cec"; 399 status = "disabled"; 400 }; 401 402 usart7: serial@40007800 { 403 compatible = "st,stm32f7-uart"; 404 reg = <0x40007800 0x400>; 405 interrupts = <82>; 406 clocks = <&rcc 1 CLK_UART7>; 407 status = "disabled"; 408 }; 409 410 usart8: serial@40007c00 { 411 compatible = "st,stm32f7-uart"; 412 reg = <0x40007c00 0x400>; 413 interrupts = <83>; 414 clocks = <&rcc 1 CLK_UART8>; 415 status = "disabled"; 416 }; 417 418 timers1: timers@40010000 { 419 #address-cells = <1>; 420 #size-cells = <0>; 421 compatible = "st,stm32-timers"; 422 reg = <0x40010000 0x400>; 423 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>; 424 clock-names = "int"; 425 status = "disabled"; 426 427 pwm { 428 compatible = "st,stm32-pwm"; 429 #pwm-cells = <3>; 430 status = "disabled"; 431 }; 432 433 timer@0 { 434 compatible = "st,stm32-timer-trigger"; 435 reg = <0>; 436 status = "disabled"; 437 }; 438 }; 439 440 timers8: timers@40010400 { 441 #address-cells = <1>; 442 #size-cells = <0>; 443 compatible = "st,stm32-timers"; 444 reg = <0x40010400 0x400>; 445 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>; 446 clock-names = "int"; 447 status = "disabled"; 448 449 pwm { 450 compatible = "st,stm32-pwm"; 451 #pwm-cells = <3>; 452 status = "disabled"; 453 }; 454 455 timer@7 { 456 compatible = "st,stm32-timer-trigger"; 457 reg = <7>; 458 status = "disabled"; 459 }; 460 }; 461 462 usart1: serial@40011000 { 463 compatible = "st,stm32f7-uart"; 464 reg = <0x40011000 0x400>; 465 interrupts = <37>; 466 clocks = <&rcc 1 CLK_USART1>; 467 status = "disabled"; 468 }; 469 470 usart6: serial@40011400 { 471 compatible = "st,stm32f7-uart"; 472 reg = <0x40011400 0x400>; 473 interrupts = <71>; 474 clocks = <&rcc 1 CLK_USART6>; 475 status = "disabled"; 476 }; 477 478 sdio2: sdio2@40011c00 { 479 compatible = "arm,pl180", "arm,primecell"; 480 arm,primecell-periphid = <0x00880180>; 481 reg = <0x40011c00 0x400>; 482 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>; 483 clock-names = "apb_pclk"; 484 interrupts = <103>; 485 max-frequency = <48000000>; 486 status = "disabled"; 487 }; 488 489 sdio1: sdio1@40012c00 { 490 compatible = "arm,pl180", "arm,primecell"; 491 arm,primecell-periphid = <0x00880180>; 492 reg = <0x40012c00 0x400>; 493 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>; 494 clock-names = "apb_pclk"; 495 interrupts = <49>; 496 max-frequency = <48000000>; 497 status = "disabled"; 498 }; 499 500 syscfg: system-config@40013800 { 501 compatible = "syscon"; 502 reg = <0x40013800 0x400>; 503 }; 504 505 exti: interrupt-controller@40013c00 { 506 compatible = "st,stm32-exti"; 507 interrupt-controller; 508 #interrupt-cells = <2>; 509 reg = <0x40013C00 0x400>; 510 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>; 511 }; 512 513 timers9: timers@40014000 { 514 #address-cells = <1>; 515 #size-cells = <0>; 516 compatible = "st,stm32-timers"; 517 reg = <0x40014000 0x400>; 518 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>; 519 clock-names = "int"; 520 status = "disabled"; 521 522 pwm { 523 compatible = "st,stm32-pwm"; 524 #pwm-cells = <3>; 525 status = "disabled"; 526 }; 527 528 timer@8 { 529 compatible = "st,stm32-timer-trigger"; 530 reg = <8>; 531 status = "disabled"; 532 }; 533 }; 534 535 timers10: timers@40014400 { 536 #address-cells = <1>; 537 #size-cells = <0>; 538 compatible = "st,stm32-timers"; 539 reg = <0x40014400 0x400>; 540 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>; 541 clock-names = "int"; 542 status = "disabled"; 543 544 pwm { 545 compatible = "st,stm32-pwm"; 546 #pwm-cells = <3>; 547 status = "disabled"; 548 }; 549 }; 550 551 timers11: timers@40014800 { 552 #address-cells = <1>; 553 #size-cells = <0>; 554 compatible = "st,stm32-timers"; 555 reg = <0x40014800 0x400>; 556 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>; 557 clock-names = "int"; 558 status = "disabled"; 559 560 pwm { 561 compatible = "st,stm32-pwm"; 562 #pwm-cells = <3>; 563 status = "disabled"; 564 }; 565 }; 566 567 pwrcfg: power-config@40007000 { 568 compatible = "syscon"; 569 reg = <0x40007000 0x400>; 570 }; 571 572 crc: crc@40023000 { 573 compatible = "st,stm32f7-crc"; 574 reg = <0x40023000 0x400>; 575 clocks = <&rcc 0 12>; 576 status = "disabled"; 577 }; 578 579 rcc: rcc@40023800 { 580 #reset-cells = <1>; 581 #clock-cells = <2>; 582 compatible = "st,stm32f746-rcc", "st,stm32-rcc"; 583 reg = <0x40023800 0x400>; 584 clocks = <&clk_hse>, <&clk_i2s_ckin>; 585 st,syscfg = <&pwrcfg>; 586 assigned-clocks = <&rcc 1 CLK_HSE_RTC>; 587 assigned-clock-rates = <1000000>; 588 }; 589 590 dma1: dma@40026000 { 591 compatible = "st,stm32-dma"; 592 reg = <0x40026000 0x400>; 593 interrupts = <11>, 594 <12>, 595 <13>, 596 <14>, 597 <15>, 598 <16>, 599 <17>, 600 <47>; 601 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>; 602 #dma-cells = <4>; 603 status = "disabled"; 604 }; 605 606 dma2: dma@40026400 { 607 compatible = "st,stm32-dma"; 608 reg = <0x40026400 0x400>; 609 interrupts = <56>, 610 <57>, 611 <58>, 612 <59>, 613 <60>, 614 <68>, 615 <69>, 616 <70>; 617 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>; 618 #dma-cells = <4>; 619 st,mem2mem; 620 status = "disabled"; 621 }; 622 623 usbotg_hs: usb@40040000 { 624 compatible = "st,stm32f7-hsotg"; 625 reg = <0x40040000 0x40000>; 626 interrupts = <77>; 627 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>; 628 clock-names = "otg"; 629 g-rx-fifo-size = <256>; 630 g-np-tx-fifo-size = <32>; 631 g-tx-fifo-size = <128 128 64 64 64 64 32 32>; 632 status = "disabled"; 633 }; 634 635 usbotg_fs: usb@50000000 { 636 compatible = "st,stm32f4x9-fsotg"; 637 reg = <0x50000000 0x40000>; 638 interrupts = <67>; 639 clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>; 640 clock-names = "otg"; 641 status = "disabled"; 642 }; 643 }; 644}; 645 646&systick { 647 clocks = <&rcc 1 0>; 648 status = "okay"; 649}; 650
