1/* 2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com> 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This file is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This file is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public 20 * License along with this file; if not, write to the Free 21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, 22 * MA 02110-1301 USA 23 * 24 * Or, alternatively, 25 * 26 * b) Permission is hereby granted, free of charge, to any person 27 * obtaining a copy of this software and associated documentation 28 * files (the "Software"), to deal in the Software without 29 * restriction, including without limitation the rights to use, 30 * copy, modify, merge, publish, distribute, sublicense, and/or 31 * sell copies of the Software, and to permit persons to whom the 32 * Software is furnished to do so, subject to the following 33 * conditions: 34 * 35 * The above copyright notice and this permission notice shall be 36 * included in all copies or substantial portions of the Software. 37 * 38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 45 * OTHER DEALINGS IN THE SOFTWARE. 46 */ 47 48#include "skeleton.dtsi" 49#include "armv7-m.dtsi" 50#include <dt-bindings/clock/stm32fx-clock.h> 51#include <dt-bindings/mfd/stm32f4-rcc.h> 52 53/ { 54 clocks { 55 clk_hse: clk-hse { 56 #clock-cells = <0>; 57 compatible = "fixed-clock"; 58 clock-frequency = <0>; 59 }; 60 61 clk-lse { 62 #clock-cells = <0>; 63 compatible = "fixed-clock"; 64 clock-frequency = <32768>; 65 }; 66 67 clk_lsi: clk-lsi { 68 #clock-cells = <0>; 69 compatible = "fixed-clock"; 70 clock-frequency = <32000>; 71 }; 72 73 clk_i2s_ckin: i2s-ckin { 74 #clock-cells = <0>; 75 compatible = "fixed-clock"; 76 clock-frequency = <0>; 77 }; 78 }; 79 80 soc { 81 timer2: timer@40000000 { 82 compatible = "st,stm32-timer"; 83 reg = <0x40000000 0x400>; 84 interrupts = <28>; 85 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>; 86 status = "disabled"; 87 }; 88 89 timers2: timers@40000000 { 90 #address-cells = <1>; 91 #size-cells = <0>; 92 compatible = "st,stm32-timers"; 93 reg = <0x40000000 0x400>; 94 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>; 95 clock-names = "int"; 96 status = "disabled"; 97 98 pwm { 99 compatible = "st,stm32-pwm"; 100 status = "disabled"; 101 }; 102 103 timer@1 { 104 compatible = "st,stm32-timer-trigger"; 105 reg = <1>; 106 status = "disabled"; 107 }; 108 }; 109 110 timer3: timer@40000400 { 111 compatible = "st,stm32-timer"; 112 reg = <0x40000400 0x400>; 113 interrupts = <29>; 114 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>; 115 status = "disabled"; 116 }; 117 118 timers3: timers@40000400 { 119 #address-cells = <1>; 120 #size-cells = <0>; 121 compatible = "st,stm32-timers"; 122 reg = <0x40000400 0x400>; 123 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>; 124 clock-names = "int"; 125 status = "disabled"; 126 127 pwm { 128 compatible = "st,stm32-pwm"; 129 status = "disabled"; 130 }; 131 132 timer@2 { 133 compatible = "st,stm32-timer-trigger"; 134 reg = <2>; 135 status = "disabled"; 136 }; 137 }; 138 139 timer4: timer@40000800 { 140 compatible = "st,stm32-timer"; 141 reg = <0x40000800 0x400>; 142 interrupts = <30>; 143 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>; 144 status = "disabled"; 145 }; 146 147 timers4: timers@40000800 { 148 #address-cells = <1>; 149 #size-cells = <0>; 150 compatible = "st,stm32-timers"; 151 reg = <0x40000800 0x400>; 152 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>; 153 clock-names = "int"; 154 status = "disabled"; 155 156 pwm { 157 compatible = "st,stm32-pwm"; 158 status = "disabled"; 159 }; 160 161 timer@3 { 162 compatible = "st,stm32-timer-trigger"; 163 reg = <3>; 164 status = "disabled"; 165 }; 166 }; 167 168 timer5: timer@40000c00 { 169 compatible = "st,stm32-timer"; 170 reg = <0x40000c00 0x400>; 171 interrupts = <50>; 172 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>; 173 }; 174 175 timers5: timers@40000c00 { 176 #address-cells = <1>; 177 #size-cells = <0>; 178 compatible = "st,stm32-timers"; 179 reg = <0x40000C00 0x400>; 180 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>; 181 clock-names = "int"; 182 status = "disabled"; 183 184 pwm { 185 compatible = "st,stm32-pwm"; 186 status = "disabled"; 187 }; 188 189 timer@4 { 190 compatible = "st,stm32-timer-trigger"; 191 reg = <4>; 192 status = "disabled"; 193 }; 194 }; 195 196 timer6: timer@40001000 { 197 compatible = "st,stm32-timer"; 198 reg = <0x40001000 0x400>; 199 interrupts = <54>; 200 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>; 201 status = "disabled"; 202 }; 203 204 timers6: timers@40001000 { 205 #address-cells = <1>; 206 #size-cells = <0>; 207 compatible = "st,stm32-timers"; 208 reg = <0x40001000 0x400>; 209 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>; 210 clock-names = "int"; 211 status = "disabled"; 212 213 timer@5 { 214 compatible = "st,stm32-timer-trigger"; 215 reg = <5>; 216 status = "disabled"; 217 }; 218 }; 219 220 timer7: timer@40001400 { 221 compatible = "st,stm32-timer"; 222 reg = <0x40001400 0x400>; 223 interrupts = <55>; 224 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>; 225 status = "disabled"; 226 }; 227 228 timers7: timers@40001400 { 229 #address-cells = <1>; 230 #size-cells = <0>; 231 compatible = "st,stm32-timers"; 232 reg = <0x40001400 0x400>; 233 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>; 234 clock-names = "int"; 235 status = "disabled"; 236 237 timer@6 { 238 compatible = "st,stm32-timer-trigger"; 239 reg = <6>; 240 status = "disabled"; 241 }; 242 }; 243 244 timers12: timers@40001800 { 245 #address-cells = <1>; 246 #size-cells = <0>; 247 compatible = "st,stm32-timers"; 248 reg = <0x40001800 0x400>; 249 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>; 250 clock-names = "int"; 251 status = "disabled"; 252 253 pwm { 254 compatible = "st,stm32-pwm"; 255 status = "disabled"; 256 }; 257 258 timer@11 { 259 compatible = "st,stm32-timer-trigger"; 260 reg = <11>; 261 status = "disabled"; 262 }; 263 }; 264 265 timers13: timers@40001c00 { 266 #address-cells = <1>; 267 #size-cells = <0>; 268 compatible = "st,stm32-timers"; 269 reg = <0x40001C00 0x400>; 270 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>; 271 clock-names = "int"; 272 status = "disabled"; 273 274 pwm { 275 compatible = "st,stm32-pwm"; 276 status = "disabled"; 277 }; 278 }; 279 280 timers14: timers@40002000 { 281 #address-cells = <1>; 282 #size-cells = <0>; 283 compatible = "st,stm32-timers"; 284 reg = <0x40002000 0x400>; 285 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>; 286 clock-names = "int"; 287 status = "disabled"; 288 289 pwm { 290 compatible = "st,stm32-pwm"; 291 status = "disabled"; 292 }; 293 }; 294 295 rtc: rtc@40002800 { 296 compatible = "st,stm32-rtc"; 297 reg = <0x40002800 0x400>; 298 clocks = <&rcc 1 CLK_RTC>; 299 clock-names = "ck_rtc"; 300 assigned-clocks = <&rcc 1 CLK_RTC>; 301 assigned-clock-parents = <&rcc 1 CLK_LSE>; 302 interrupt-parent = <&exti>; 303 interrupts = <17 1>; 304 interrupt-names = "alarm"; 305 st,syscfg = <&pwrcfg 0x00 0x100>; 306 status = "disabled"; 307 }; 308 309 iwdg: watchdog@40003000 { 310 compatible = "st,stm32-iwdg"; 311 reg = <0x40003000 0x400>; 312 clocks = <&clk_lsi>; 313 clock-names = "lsi"; 314 status = "disabled"; 315 }; 316 317 usart2: serial@40004400 { 318 compatible = "st,stm32-uart"; 319 reg = <0x40004400 0x400>; 320 interrupts = <38>; 321 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>; 322 status = "disabled"; 323 }; 324 325 usart3: serial@40004800 { 326 compatible = "st,stm32-uart"; 327 reg = <0x40004800 0x400>; 328 interrupts = <39>; 329 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>; 330 status = "disabled"; 331 dmas = <&dma1 1 4 0x400 0x0>, 332 <&dma1 3 4 0x400 0x0>; 333 dma-names = "rx", "tx"; 334 }; 335 336 usart4: serial@40004c00 { 337 compatible = "st,stm32-uart"; 338 reg = <0x40004c00 0x400>; 339 interrupts = <52>; 340 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>; 341 status = "disabled"; 342 }; 343 344 usart5: serial@40005000 { 345 compatible = "st,stm32-uart"; 346 reg = <0x40005000 0x400>; 347 interrupts = <53>; 348 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>; 349 status = "disabled"; 350 }; 351 352 i2c1: i2c@40005400 { 353 compatible = "st,stm32f4-i2c"; 354 reg = <0x40005400 0x400>; 355 interrupts = <31>, 356 <32>; 357 resets = <&rcc STM32F4_APB1_RESET(I2C1)>; 358 clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>; 359 #address-cells = <1>; 360 #size-cells = <0>; 361 status = "disabled"; 362 }; 363 364 dac: dac@40007400 { 365 compatible = "st,stm32f4-dac-core"; 366 reg = <0x40007400 0x400>; 367 resets = <&rcc STM32F4_APB1_RESET(DAC)>; 368 clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>; 369 clock-names = "pclk"; 370 #address-cells = <1>; 371 #size-cells = <0>; 372 status = "disabled"; 373 374 dac1: dac@1 { 375 compatible = "st,stm32-dac"; 376 #io-channels-cells = <1>; 377 reg = <1>; 378 status = "disabled"; 379 }; 380 381 dac2: dac@2 { 382 compatible = "st,stm32-dac"; 383 #io-channels-cells = <1>; 384 reg = <2>; 385 status = "disabled"; 386 }; 387 }; 388 389 usart7: serial@40007800 { 390 compatible = "st,stm32-uart"; 391 reg = <0x40007800 0x400>; 392 interrupts = <82>; 393 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>; 394 status = "disabled"; 395 }; 396 397 usart8: serial@40007c00 { 398 compatible = "st,stm32-uart"; 399 reg = <0x40007c00 0x400>; 400 interrupts = <83>; 401 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>; 402 status = "disabled"; 403 }; 404 405 timers1: timers@40010000 { 406 #address-cells = <1>; 407 #size-cells = <0>; 408 compatible = "st,stm32-timers"; 409 reg = <0x40010000 0x400>; 410 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>; 411 clock-names = "int"; 412 status = "disabled"; 413 414 pwm { 415 compatible = "st,stm32-pwm"; 416 status = "disabled"; 417 }; 418 419 timer@0 { 420 compatible = "st,stm32-timer-trigger"; 421 reg = <0>; 422 status = "disabled"; 423 }; 424 }; 425 426 timers8: timers@40010400 { 427 #address-cells = <1>; 428 #size-cells = <0>; 429 compatible = "st,stm32-timers"; 430 reg = <0x40010400 0x400>; 431 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>; 432 clock-names = "int"; 433 status = "disabled"; 434 435 pwm { 436 compatible = "st,stm32-pwm"; 437 status = "disabled"; 438 }; 439 440 timer@7 { 441 compatible = "st,stm32-timer-trigger"; 442 reg = <7>; 443 status = "disabled"; 444 }; 445 }; 446 447 usart1: serial@40011000 { 448 compatible = "st,stm32-uart"; 449 reg = <0x40011000 0x400>; 450 interrupts = <37>; 451 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>; 452 status = "disabled"; 453 dmas = <&dma2 2 4 0x400 0x0>, 454 <&dma2 7 4 0x400 0x0>; 455 dma-names = "rx", "tx"; 456 }; 457 458 usart6: serial@40011400 { 459 compatible = "st,stm32-uart"; 460 reg = <0x40011400 0x400>; 461 interrupts = <71>; 462 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>; 463 status = "disabled"; 464 }; 465 466 adc: adc@40012000 { 467 compatible = "st,stm32f4-adc-core"; 468 reg = <0x40012000 0x400>; 469 interrupts = <18>; 470 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>; 471 clock-names = "adc"; 472 interrupt-controller; 473 #interrupt-cells = <1>; 474 #address-cells = <1>; 475 #size-cells = <0>; 476 status = "disabled"; 477 478 adc1: adc@0 { 479 compatible = "st,stm32f4-adc"; 480 #io-channel-cells = <1>; 481 reg = <0x0>; 482 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>; 483 interrupt-parent = <&adc>; 484 interrupts = <0>; 485 dmas = <&dma2 0 0 0x400 0x0>; 486 dma-names = "rx"; 487 status = "disabled"; 488 }; 489 490 adc2: adc@100 { 491 compatible = "st,stm32f4-adc"; 492 #io-channel-cells = <1>; 493 reg = <0x100>; 494 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>; 495 interrupt-parent = <&adc>; 496 interrupts = <1>; 497 dmas = <&dma2 3 1 0x400 0x0>; 498 dma-names = "rx"; 499 status = "disabled"; 500 }; 501 502 adc3: adc@200 { 503 compatible = "st,stm32f4-adc"; 504 #io-channel-cells = <1>; 505 reg = <0x200>; 506 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>; 507 interrupt-parent = <&adc>; 508 interrupts = <2>; 509 dmas = <&dma2 1 2 0x400 0x0>; 510 dma-names = "rx"; 511 status = "disabled"; 512 }; 513 }; 514 515 sdio: sdio@40012c00 { 516 compatible = "arm,pl180", "arm,primecell"; 517 arm,primecell-periphid = <0x00880180>; 518 reg = <0x40012c00 0x400>; 519 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>; 520 clock-names = "apb_pclk"; 521 interrupts = <49>; 522 max-frequency = <48000000>; 523 status = "disabled"; 524 }; 525 526 syscfg: system-config@40013800 { 527 compatible = "syscon"; 528 reg = <0x40013800 0x400>; 529 }; 530 531 exti: interrupt-controller@40013c00 { 532 compatible = "st,stm32-exti"; 533 interrupt-controller; 534 #interrupt-cells = <2>; 535 reg = <0x40013C00 0x400>; 536 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>; 537 }; 538 539 timers9: timers@40014000 { 540 #address-cells = <1>; 541 #size-cells = <0>; 542 compatible = "st,stm32-timers"; 543 reg = <0x40014000 0x400>; 544 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>; 545 clock-names = "int"; 546 status = "disabled"; 547 548 pwm { 549 compatible = "st,stm32-pwm"; 550 status = "disabled"; 551 }; 552 553 timer@8 { 554 compatible = "st,stm32-timer-trigger"; 555 reg = <8>; 556 status = "disabled"; 557 }; 558 }; 559 560 timers10: timers@40014400 { 561 #address-cells = <1>; 562 #size-cells = <0>; 563 compatible = "st,stm32-timers"; 564 reg = <0x40014400 0x400>; 565 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>; 566 clock-names = "int"; 567 status = "disabled"; 568 569 pwm { 570 compatible = "st,stm32-pwm"; 571 status = "disabled"; 572 }; 573 }; 574 575 timers11: timers@40014800 { 576 #address-cells = <1>; 577 #size-cells = <0>; 578 compatible = "st,stm32-timers"; 579 reg = <0x40014800 0x400>; 580 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>; 581 clock-names = "int"; 582 status = "disabled"; 583 584 pwm { 585 compatible = "st,stm32-pwm"; 586 status = "disabled"; 587 }; 588 }; 589 590 pwrcfg: power-config@40007000 { 591 compatible = "syscon"; 592 reg = <0x40007000 0x400>; 593 }; 594 595 ltdc: display-controller@40016800 { 596 compatible = "st,stm32-ltdc"; 597 reg = <0x40016800 0x200>; 598 interrupts = <88>, <89>; 599 resets = <&rcc STM32F4_APB2_RESET(LTDC)>; 600 clocks = <&rcc 1 CLK_LCD>; 601 clock-names = "lcd"; 602 status = "disabled"; 603 }; 604 605 crc: crc@40023000 { 606 compatible = "st,stm32f4-crc"; 607 reg = <0x40023000 0x400>; 608 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>; 609 status = "disabled"; 610 }; 611 612 rcc: rcc@40023810 { 613 #reset-cells = <1>; 614 #clock-cells = <2>; 615 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; 616 reg = <0x40023800 0x400>; 617 clocks = <&clk_hse>, <&clk_i2s_ckin>; 618 st,syscfg = <&pwrcfg>; 619 assigned-clocks = <&rcc 1 CLK_HSE_RTC>; 620 assigned-clock-rates = <1000000>; 621 }; 622 623 dma1: dma-controller@40026000 { 624 compatible = "st,stm32-dma"; 625 reg = <0x40026000 0x400>; 626 interrupts = <11>, 627 <12>, 628 <13>, 629 <14>, 630 <15>, 631 <16>, 632 <17>, 633 <47>; 634 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>; 635 #dma-cells = <4>; 636 }; 637 638 dma2: dma-controller@40026400 { 639 compatible = "st,stm32-dma"; 640 reg = <0x40026400 0x400>; 641 interrupts = <56>, 642 <57>, 643 <58>, 644 <59>, 645 <60>, 646 <68>, 647 <69>, 648 <70>; 649 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>; 650 #dma-cells = <4>; 651 st,mem2mem; 652 }; 653 654 mac: ethernet@40028000 { 655 compatible = "st,stm32-dwmac", "snps,dwmac-3.50a"; 656 reg = <0x40028000 0x8000>; 657 reg-names = "stmmaceth"; 658 interrupts = <61>; 659 interrupt-names = "macirq"; 660 clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx"; 661 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>, 662 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>, 663 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>; 664 st,syscon = <&syscfg 0x4>; 665 snps,pbl = <8>; 666 snps,mixed-burst; 667 status = "disabled"; 668 }; 669 670 usbotg_hs: usb@40040000 { 671 compatible = "snps,dwc2"; 672 reg = <0x40040000 0x40000>; 673 interrupts = <77>; 674 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>; 675 clock-names = "otg"; 676 status = "disabled"; 677 }; 678 679 usbotg_fs: usb@50000000 { 680 compatible = "st,stm32f4x9-fsotg"; 681 reg = <0x50000000 0x40000>; 682 interrupts = <67>; 683 clocks = <&rcc 0 39>; 684 clock-names = "otg"; 685 status = "disabled"; 686 }; 687 688 dcmi: dcmi@50050000 { 689 compatible = "st,stm32-dcmi"; 690 reg = <0x50050000 0x400>; 691 interrupts = <78>; 692 resets = <&rcc STM32F4_AHB2_RESET(DCMI)>; 693 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>; 694 clock-names = "mclk"; 695 pinctrl-names = "default"; 696 pinctrl-0 = <&dcmi_pins>; 697 dmas = <&dma2 1 1 0x414 0x3>; 698 dma-names = "tx"; 699 status = "disabled"; 700 }; 701 702 rng: rng@50060800 { 703 compatible = "st,stm32-rng"; 704 reg = <0x50060800 0x400>; 705 interrupts = <80>; 706 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>; 707 708 }; 709 }; 710}; 711 712&systick { 713 clocks = <&rcc 1 SYSTICK>; 714 status = "okay"; 715}; 716
