1 /*
2 * Xtfpga I2S controller driver
3 *
4 * Copyright (c) 2014 Cadence Design Systems Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #include <linux/clk.h>
12 #include <linux/io.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <sound/pcm_params.h>
18 #include <sound/soc.h>
19
20 #define DRV_NAME "xtfpga-i2s"
21
22 #define XTFPGA_I2S_VERSION 0x00
23 #define XTFPGA_I2S_CONFIG 0x04
24 #define XTFPGA_I2S_INT_MASK 0x08
25 #define XTFPGA_I2S_INT_STATUS 0x0c
26 #define XTFPGA_I2S_CHAN0_DATA 0x10
27 #define XTFPGA_I2S_CHAN1_DATA 0x14
28 #define XTFPGA_I2S_CHAN2_DATA 0x18
29 #define XTFPGA_I2S_CHAN3_DATA 0x1c
30
31 #define XTFPGA_I2S_CONFIG_TX_ENABLE 0x1
32 #define XTFPGA_I2S_CONFIG_INT_ENABLE 0x2
33 #define XTFPGA_I2S_CONFIG_LEFT 0x4
34 #define XTFPGA_I2S_CONFIG_RATIO_BASE 8
35 #define XTFPGA_I2S_CONFIG_RATIO_MASK 0x0000ff00
36 #define XTFPGA_I2S_CONFIG_RES_BASE 16
37 #define XTFPGA_I2S_CONFIG_RES_MASK 0x003f0000
38 #define XTFPGA_I2S_CONFIG_LEVEL_BASE 24
39 #define XTFPGA_I2S_CONFIG_LEVEL_MASK 0x0f000000
40 #define XTFPGA_I2S_CONFIG_CHANNEL_BASE 28
41
42 #define XTFPGA_I2S_INT_UNDERRUN 0x1
43 #define XTFPGA_I2S_INT_LEVEL 0x2
44 #define XTFPGA_I2S_INT_VALID 0x3
45
46 #define XTFPGA_I2S_FIFO_SIZE 8192
47
48 /*
49 * I2S controller operation:
50 *
51 * Enabling TX: output 1 period of zeros (starting with left channel)
52 * and then queued data.
53 *
54 * Level status and interrupt: whenever FIFO level is below FIFO trigger,
55 * level status is 1 and an IRQ is asserted (if enabled).
56 *
57 * Underrun status and interrupt: whenever FIFO is empty, underrun status
58 * is 1 and an IRQ is asserted (if enabled).
59 */
60 struct xtfpga_i2s {
61 struct device *dev;
62 struct clk *clk;
63 struct regmap *regmap;
64 void __iomem *regs;
65
66 /* current playback substream. NULL if not playing.
67 *
68 * Access to that field is synchronized between the interrupt handler
69 * and userspace through RCU.
70 *
71 * Interrupt handler (threaded part) does PIO on substream data in RCU
72 * read-side critical section. Trigger callback sets and clears the
73 * pointer when the playback is started and stopped with
74 * rcu_assign_pointer. When userspace is about to free the playback
75 * stream in the pcm_close callback it synchronizes with the interrupt
76 * handler by means of synchronize_rcu call.
77 */
78 struct snd_pcm_substream __rcu *tx_substream;
79 unsigned (*tx_fn)(struct xtfpga_i2s *i2s,
80 struct snd_pcm_runtime *runtime,
81 unsigned tx_ptr);
82 unsigned tx_ptr; /* next frame index in the sample buffer */
83
84 /* current fifo level estimate.
85 * Doesn't have to be perfectly accurate, but must be not less than
86 * the actual FIFO level in order to avoid stall on push attempt.
87 */
88 unsigned tx_fifo_level;
89
90 /* FIFO level at which level interrupt occurs */
91 unsigned tx_fifo_low;
92
93 /* maximal FIFO level */
94 unsigned tx_fifo_high;
95 };
96
xtfpga_i2s_wr_reg(struct device * dev,unsigned int reg)97 static bool xtfpga_i2s_wr_reg(struct device *dev, unsigned int reg)
98 {
99 return reg >= XTFPGA_I2S_CONFIG;
100 }
101
xtfpga_i2s_rd_reg(struct device * dev,unsigned int reg)102 static bool xtfpga_i2s_rd_reg(struct device *dev, unsigned int reg)
103 {
104 return reg < XTFPGA_I2S_CHAN0_DATA;
105 }
106
xtfpga_i2s_volatile_reg(struct device * dev,unsigned int reg)107 static bool xtfpga_i2s_volatile_reg(struct device *dev, unsigned int reg)
108 {
109 return reg == XTFPGA_I2S_INT_STATUS;
110 }
111
112 static const struct regmap_config xtfpga_i2s_regmap_config = {
113 .reg_bits = 32,
114 .reg_stride = 4,
115 .val_bits = 32,
116 .max_register = XTFPGA_I2S_CHAN3_DATA,
117 .writeable_reg = xtfpga_i2s_wr_reg,
118 .readable_reg = xtfpga_i2s_rd_reg,
119 .volatile_reg = xtfpga_i2s_volatile_reg,
120 .cache_type = REGCACHE_FLAT,
121 };
122
123 /* Generate functions that do PIO from TX DMA area to FIFO for all supported
124 * stream formats.
125 * Functions will be called xtfpga_pcm_tx_<channels>x<sample bits>, e.g.
126 * xtfpga_pcm_tx_2x16 for 16-bit stereo.
127 *
128 * FIFO consists of 32-bit words, one word per channel, always 2 channels.
129 * If I2S interface is configured with smaller sample resolution, only
130 * the LSB of each word is used.
131 */
132 #define xtfpga_pcm_tx_fn(channels, sample_bits) \
133 static unsigned xtfpga_pcm_tx_##channels##x##sample_bits( \
134 struct xtfpga_i2s *i2s, struct snd_pcm_runtime *runtime, \
135 unsigned tx_ptr) \
136 { \
137 const u##sample_bits (*p)[channels] = \
138 (void *)runtime->dma_area; \
139 \
140 for (; i2s->tx_fifo_level < i2s->tx_fifo_high; \
141 i2s->tx_fifo_level += 2) { \
142 iowrite32(p[tx_ptr][0], \
143 i2s->regs + XTFPGA_I2S_CHAN0_DATA); \
144 iowrite32(p[tx_ptr][channels - 1], \
145 i2s->regs + XTFPGA_I2S_CHAN0_DATA); \
146 if (++tx_ptr >= runtime->buffer_size) \
147 tx_ptr = 0; \
148 } \
149 return tx_ptr; \
150 }
151
152 xtfpga_pcm_tx_fn(1, 16)
153 xtfpga_pcm_tx_fn(2, 16)
154 xtfpga_pcm_tx_fn(1, 32)
155 xtfpga_pcm_tx_fn(2, 32)
156
157 #undef xtfpga_pcm_tx_fn
158
xtfpga_pcm_push_tx(struct xtfpga_i2s * i2s)159 static bool xtfpga_pcm_push_tx(struct xtfpga_i2s *i2s)
160 {
161 struct snd_pcm_substream *tx_substream;
162 bool tx_active;
163
164 rcu_read_lock();
165 tx_substream = rcu_dereference(i2s->tx_substream);
166 tx_active = tx_substream && snd_pcm_running(tx_substream);
167 if (tx_active) {
168 unsigned tx_ptr = READ_ONCE(i2s->tx_ptr);
169 unsigned new_tx_ptr = i2s->tx_fn(i2s, tx_substream->runtime,
170 tx_ptr);
171
172 cmpxchg(&i2s->tx_ptr, tx_ptr, new_tx_ptr);
173 }
174 rcu_read_unlock();
175
176 return tx_active;
177 }
178
xtfpga_pcm_refill_fifo(struct xtfpga_i2s * i2s)179 static void xtfpga_pcm_refill_fifo(struct xtfpga_i2s *i2s)
180 {
181 unsigned int_status;
182 unsigned i;
183
184 regmap_read(i2s->regmap, XTFPGA_I2S_INT_STATUS,
185 &int_status);
186
187 for (i = 0; i < 2; ++i) {
188 bool tx_active = xtfpga_pcm_push_tx(i2s);
189
190 regmap_write(i2s->regmap, XTFPGA_I2S_INT_STATUS,
191 XTFPGA_I2S_INT_VALID);
192 if (tx_active)
193 regmap_read(i2s->regmap, XTFPGA_I2S_INT_STATUS,
194 &int_status);
195
196 if (!tx_active ||
197 !(int_status & XTFPGA_I2S_INT_LEVEL))
198 break;
199
200 /* After the push the level IRQ is still asserted,
201 * means FIFO level is below tx_fifo_low. Estimate
202 * it as tx_fifo_low.
203 */
204 i2s->tx_fifo_level = i2s->tx_fifo_low;
205 }
206
207 if (!(int_status & XTFPGA_I2S_INT_LEVEL))
208 regmap_write(i2s->regmap, XTFPGA_I2S_INT_MASK,
209 XTFPGA_I2S_INT_VALID);
210 else if (!(int_status & XTFPGA_I2S_INT_UNDERRUN))
211 regmap_write(i2s->regmap, XTFPGA_I2S_INT_MASK,
212 XTFPGA_I2S_INT_UNDERRUN);
213
214 if (!(int_status & XTFPGA_I2S_INT_UNDERRUN))
215 regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
216 XTFPGA_I2S_CONFIG_INT_ENABLE |
217 XTFPGA_I2S_CONFIG_TX_ENABLE,
218 XTFPGA_I2S_CONFIG_INT_ENABLE |
219 XTFPGA_I2S_CONFIG_TX_ENABLE);
220 else
221 regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
222 XTFPGA_I2S_CONFIG_INT_ENABLE |
223 XTFPGA_I2S_CONFIG_TX_ENABLE, 0);
224 }
225
xtfpga_i2s_threaded_irq_handler(int irq,void * dev_id)226 static irqreturn_t xtfpga_i2s_threaded_irq_handler(int irq, void *dev_id)
227 {
228 struct xtfpga_i2s *i2s = dev_id;
229 struct snd_pcm_substream *tx_substream;
230 unsigned config, int_status, int_mask;
231
232 regmap_read(i2s->regmap, XTFPGA_I2S_CONFIG, &config);
233 regmap_read(i2s->regmap, XTFPGA_I2S_INT_MASK, &int_mask);
234 regmap_read(i2s->regmap, XTFPGA_I2S_INT_STATUS, &int_status);
235
236 if (!(config & XTFPGA_I2S_CONFIG_INT_ENABLE) ||
237 !(int_status & int_mask & XTFPGA_I2S_INT_VALID))
238 return IRQ_NONE;
239
240 /* Update FIFO level estimate in accordance with interrupt status
241 * register.
242 */
243 if (int_status & XTFPGA_I2S_INT_UNDERRUN) {
244 i2s->tx_fifo_level = 0;
245 regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
246 XTFPGA_I2S_CONFIG_TX_ENABLE, 0);
247 } else {
248 /* The FIFO isn't empty, but is below tx_fifo_low. Estimate
249 * it as tx_fifo_low.
250 */
251 i2s->tx_fifo_level = i2s->tx_fifo_low;
252 }
253
254 rcu_read_lock();
255 tx_substream = rcu_dereference(i2s->tx_substream);
256
257 if (tx_substream && snd_pcm_running(tx_substream)) {
258 snd_pcm_period_elapsed(tx_substream);
259 if (int_status & XTFPGA_I2S_INT_UNDERRUN)
260 dev_dbg_ratelimited(i2s->dev, "%s: underrun\n",
261 __func__);
262 }
263 rcu_read_unlock();
264
265 /* Refill FIFO, update allowed IRQ reasons, enable IRQ if FIFO is
266 * not empty.
267 */
268 xtfpga_pcm_refill_fifo(i2s);
269
270 return IRQ_HANDLED;
271 }
272
xtfpga_i2s_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)273 static int xtfpga_i2s_startup(struct snd_pcm_substream *substream,
274 struct snd_soc_dai *dai)
275 {
276 struct xtfpga_i2s *i2s = snd_soc_dai_get_drvdata(dai);
277
278 snd_soc_dai_set_dma_data(dai, substream, i2s);
279 return 0;
280 }
281
xtfpga_i2s_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)282 static int xtfpga_i2s_hw_params(struct snd_pcm_substream *substream,
283 struct snd_pcm_hw_params *params,
284 struct snd_soc_dai *dai)
285 {
286 struct xtfpga_i2s *i2s = snd_soc_dai_get_drvdata(dai);
287 unsigned srate = params_rate(params);
288 unsigned channels = params_channels(params);
289 unsigned period_size = params_period_size(params);
290 unsigned sample_size = snd_pcm_format_width(params_format(params));
291 unsigned freq, ratio, level;
292 int err;
293
294 regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
295 XTFPGA_I2S_CONFIG_RES_MASK,
296 sample_size << XTFPGA_I2S_CONFIG_RES_BASE);
297
298 freq = 256 * srate;
299 err = clk_set_rate(i2s->clk, freq);
300 if (err < 0)
301 return err;
302
303 /* ratio field of the config register controls MCLK->I2S clock
304 * derivation: I2S clock = MCLK / (2 * (ratio + 2)).
305 *
306 * So with MCLK = 256 * sample rate ratio is 0 for 32 bit stereo
307 * and 2 for 16 bit stereo.
308 */
309 ratio = (freq - (srate * sample_size * 8)) /
310 (srate * sample_size * 4);
311
312 regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
313 XTFPGA_I2S_CONFIG_RATIO_MASK,
314 ratio << XTFPGA_I2S_CONFIG_RATIO_BASE);
315
316 i2s->tx_fifo_low = XTFPGA_I2S_FIFO_SIZE / 2;
317
318 /* period_size * 2: FIFO always gets 2 samples per frame */
319 for (level = 1;
320 i2s->tx_fifo_low / 2 >= period_size * 2 &&
321 level < (XTFPGA_I2S_CONFIG_LEVEL_MASK >>
322 XTFPGA_I2S_CONFIG_LEVEL_BASE); ++level)
323 i2s->tx_fifo_low /= 2;
324
325 i2s->tx_fifo_high = 2 * i2s->tx_fifo_low;
326
327 regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
328 XTFPGA_I2S_CONFIG_LEVEL_MASK,
329 level << XTFPGA_I2S_CONFIG_LEVEL_BASE);
330
331 dev_dbg(i2s->dev,
332 "%s srate: %u, channels: %u, sample_size: %u, period_size: %u\n",
333 __func__, srate, channels, sample_size, period_size);
334 dev_dbg(i2s->dev, "%s freq: %u, ratio: %u, level: %u\n",
335 __func__, freq, ratio, level);
336
337 return 0;
338 }
339
xtfpga_i2s_set_fmt(struct snd_soc_dai * cpu_dai,unsigned int fmt)340 static int xtfpga_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
341 unsigned int fmt)
342 {
343 if ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF)
344 return -EINVAL;
345 if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS)
346 return -EINVAL;
347 if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) != SND_SOC_DAIFMT_I2S)
348 return -EINVAL;
349
350 return 0;
351 }
352
353 /* PCM */
354
355 static const struct snd_pcm_hardware xtfpga_pcm_hardware = {
356 .info = SNDRV_PCM_INFO_INTERLEAVED |
357 SNDRV_PCM_INFO_MMAP_VALID |
358 SNDRV_PCM_INFO_BLOCK_TRANSFER,
359 .formats = SNDRV_PCM_FMTBIT_S16_LE |
360 SNDRV_PCM_FMTBIT_S32_LE,
361 .channels_min = 1,
362 .channels_max = 2,
363 .period_bytes_min = 2,
364 .period_bytes_max = XTFPGA_I2S_FIFO_SIZE / 2 * 8,
365 .periods_min = 2,
366 .periods_max = XTFPGA_I2S_FIFO_SIZE * 8 / 2,
367 .buffer_bytes_max = XTFPGA_I2S_FIFO_SIZE * 8,
368 .fifo_size = 16,
369 };
370
xtfpga_pcm_open(struct snd_pcm_substream * substream)371 static int xtfpga_pcm_open(struct snd_pcm_substream *substream)
372 {
373 struct snd_pcm_runtime *runtime = substream->runtime;
374 struct snd_soc_pcm_runtime *rtd = substream->private_data;
375 void *p;
376
377 snd_soc_set_runtime_hwparams(substream, &xtfpga_pcm_hardware);
378 p = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
379 runtime->private_data = p;
380
381 return 0;
382 }
383
xtfpga_pcm_close(struct snd_pcm_substream * substream)384 static int xtfpga_pcm_close(struct snd_pcm_substream *substream)
385 {
386 synchronize_rcu();
387 return 0;
388 }
389
xtfpga_pcm_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * hw_params)390 static int xtfpga_pcm_hw_params(struct snd_pcm_substream *substream,
391 struct snd_pcm_hw_params *hw_params)
392 {
393 int ret;
394 struct snd_pcm_runtime *runtime = substream->runtime;
395 struct xtfpga_i2s *i2s = runtime->private_data;
396 unsigned channels = params_channels(hw_params);
397
398 switch (channels) {
399 case 1:
400 case 2:
401 break;
402
403 default:
404 return -EINVAL;
405
406 }
407
408 switch (params_format(hw_params)) {
409 case SNDRV_PCM_FORMAT_S16_LE:
410 i2s->tx_fn = (channels == 1) ?
411 xtfpga_pcm_tx_1x16 :
412 xtfpga_pcm_tx_2x16;
413 break;
414
415 case SNDRV_PCM_FORMAT_S32_LE:
416 i2s->tx_fn = (channels == 1) ?
417 xtfpga_pcm_tx_1x32 :
418 xtfpga_pcm_tx_2x32;
419 break;
420
421 default:
422 return -EINVAL;
423 }
424
425 ret = snd_pcm_lib_malloc_pages(substream,
426 params_buffer_bytes(hw_params));
427 return ret;
428 }
429
xtfpga_pcm_trigger(struct snd_pcm_substream * substream,int cmd)430 static int xtfpga_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
431 {
432 int ret = 0;
433 struct snd_pcm_runtime *runtime = substream->runtime;
434 struct xtfpga_i2s *i2s = runtime->private_data;
435
436 switch (cmd) {
437 case SNDRV_PCM_TRIGGER_START:
438 case SNDRV_PCM_TRIGGER_RESUME:
439 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
440 WRITE_ONCE(i2s->tx_ptr, 0);
441 rcu_assign_pointer(i2s->tx_substream, substream);
442 xtfpga_pcm_refill_fifo(i2s);
443 break;
444
445 case SNDRV_PCM_TRIGGER_STOP:
446 case SNDRV_PCM_TRIGGER_SUSPEND:
447 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
448 rcu_assign_pointer(i2s->tx_substream, NULL);
449 break;
450
451 default:
452 ret = -EINVAL;
453 break;
454 }
455 return ret;
456 }
457
xtfpga_pcm_pointer(struct snd_pcm_substream * substream)458 static snd_pcm_uframes_t xtfpga_pcm_pointer(struct snd_pcm_substream *substream)
459 {
460 struct snd_pcm_runtime *runtime = substream->runtime;
461 struct xtfpga_i2s *i2s = runtime->private_data;
462 snd_pcm_uframes_t pos = READ_ONCE(i2s->tx_ptr);
463
464 return pos < runtime->buffer_size ? pos : 0;
465 }
466
xtfpga_pcm_new(struct snd_soc_pcm_runtime * rtd)467 static int xtfpga_pcm_new(struct snd_soc_pcm_runtime *rtd)
468 {
469 struct snd_card *card = rtd->card->snd_card;
470 size_t size = xtfpga_pcm_hardware.buffer_bytes_max;
471
472 return snd_pcm_lib_preallocate_pages_for_all(rtd->pcm,
473 SNDRV_DMA_TYPE_DEV,
474 card->dev, size, size);
475 }
476
477 static const struct snd_pcm_ops xtfpga_pcm_ops = {
478 .open = xtfpga_pcm_open,
479 .close = xtfpga_pcm_close,
480 .ioctl = snd_pcm_lib_ioctl,
481 .hw_params = xtfpga_pcm_hw_params,
482 .trigger = xtfpga_pcm_trigger,
483 .pointer = xtfpga_pcm_pointer,
484 };
485
486 static const struct snd_soc_component_driver xtfpga_i2s_component = {
487 .name = DRV_NAME,
488 .pcm_new = xtfpga_pcm_new,
489 .ops = &xtfpga_pcm_ops,
490 };
491
492 static const struct snd_soc_dai_ops xtfpga_i2s_dai_ops = {
493 .startup = xtfpga_i2s_startup,
494 .hw_params = xtfpga_i2s_hw_params,
495 .set_fmt = xtfpga_i2s_set_fmt,
496 };
497
498 static struct snd_soc_dai_driver xtfpga_i2s_dai[] = {
499 {
500 .name = "xtfpga-i2s",
501 .id = 0,
502 .playback = {
503 .channels_min = 1,
504 .channels_max = 2,
505 .rates = SNDRV_PCM_RATE_8000_96000,
506 .formats = SNDRV_PCM_FMTBIT_S16_LE |
507 SNDRV_PCM_FMTBIT_S32_LE,
508 },
509 .ops = &xtfpga_i2s_dai_ops,
510 },
511 };
512
xtfpga_i2s_runtime_suspend(struct device * dev)513 static int xtfpga_i2s_runtime_suspend(struct device *dev)
514 {
515 struct xtfpga_i2s *i2s = dev_get_drvdata(dev);
516
517 clk_disable_unprepare(i2s->clk);
518 return 0;
519 }
520
xtfpga_i2s_runtime_resume(struct device * dev)521 static int xtfpga_i2s_runtime_resume(struct device *dev)
522 {
523 struct xtfpga_i2s *i2s = dev_get_drvdata(dev);
524 int ret;
525
526 ret = clk_prepare_enable(i2s->clk);
527 if (ret) {
528 dev_err(dev, "clk_prepare_enable failed: %d\n", ret);
529 return ret;
530 }
531 return 0;
532 }
533
xtfpga_i2s_probe(struct platform_device * pdev)534 static int xtfpga_i2s_probe(struct platform_device *pdev)
535 {
536 struct xtfpga_i2s *i2s;
537 struct resource *mem;
538 int err, irq;
539
540 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
541 if (!i2s) {
542 err = -ENOMEM;
543 goto err;
544 }
545 platform_set_drvdata(pdev, i2s);
546 i2s->dev = &pdev->dev;
547 dev_dbg(&pdev->dev, "dev: %p, i2s: %p\n", &pdev->dev, i2s);
548
549 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
550 i2s->regs = devm_ioremap_resource(&pdev->dev, mem);
551 if (IS_ERR(i2s->regs)) {
552 err = PTR_ERR(i2s->regs);
553 goto err;
554 }
555
556 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, i2s->regs,
557 &xtfpga_i2s_regmap_config);
558 if (IS_ERR(i2s->regmap)) {
559 dev_err(&pdev->dev, "regmap init failed\n");
560 err = PTR_ERR(i2s->regmap);
561 goto err;
562 }
563
564 i2s->clk = devm_clk_get(&pdev->dev, NULL);
565 if (IS_ERR(i2s->clk)) {
566 dev_err(&pdev->dev, "couldn't get clock\n");
567 err = PTR_ERR(i2s->clk);
568 goto err;
569 }
570
571 regmap_write(i2s->regmap, XTFPGA_I2S_CONFIG,
572 (0x1 << XTFPGA_I2S_CONFIG_CHANNEL_BASE));
573 regmap_write(i2s->regmap, XTFPGA_I2S_INT_STATUS, XTFPGA_I2S_INT_VALID);
574 regmap_write(i2s->regmap, XTFPGA_I2S_INT_MASK, XTFPGA_I2S_INT_UNDERRUN);
575
576 irq = platform_get_irq(pdev, 0);
577 if (irq < 0) {
578 dev_err(&pdev->dev, "No IRQ resource\n");
579 err = irq;
580 goto err;
581 }
582 err = devm_request_threaded_irq(&pdev->dev, irq, NULL,
583 xtfpga_i2s_threaded_irq_handler,
584 IRQF_SHARED | IRQF_ONESHOT,
585 pdev->name, i2s);
586 if (err < 0) {
587 dev_err(&pdev->dev, "request_irq failed\n");
588 goto err;
589 }
590
591 err = devm_snd_soc_register_component(&pdev->dev,
592 &xtfpga_i2s_component,
593 xtfpga_i2s_dai,
594 ARRAY_SIZE(xtfpga_i2s_dai));
595 if (err < 0) {
596 dev_err(&pdev->dev, "couldn't register component\n");
597 goto err;
598 }
599
600 pm_runtime_enable(&pdev->dev);
601 if (!pm_runtime_enabled(&pdev->dev)) {
602 err = xtfpga_i2s_runtime_resume(&pdev->dev);
603 if (err)
604 goto err_pm_disable;
605 }
606 return 0;
607
608 err_pm_disable:
609 pm_runtime_disable(&pdev->dev);
610 err:
611 dev_err(&pdev->dev, "%s: err = %d\n", __func__, err);
612 return err;
613 }
614
xtfpga_i2s_remove(struct platform_device * pdev)615 static int xtfpga_i2s_remove(struct platform_device *pdev)
616 {
617 struct xtfpga_i2s *i2s = dev_get_drvdata(&pdev->dev);
618
619 if (i2s->regmap && !IS_ERR(i2s->regmap)) {
620 regmap_write(i2s->regmap, XTFPGA_I2S_CONFIG, 0);
621 regmap_write(i2s->regmap, XTFPGA_I2S_INT_MASK, 0);
622 regmap_write(i2s->regmap, XTFPGA_I2S_INT_STATUS,
623 XTFPGA_I2S_INT_VALID);
624 }
625 pm_runtime_disable(&pdev->dev);
626 if (!pm_runtime_status_suspended(&pdev->dev))
627 xtfpga_i2s_runtime_suspend(&pdev->dev);
628 return 0;
629 }
630
631 #ifdef CONFIG_OF
632 static const struct of_device_id xtfpga_i2s_of_match[] = {
633 { .compatible = "cdns,xtfpga-i2s", },
634 {},
635 };
636 MODULE_DEVICE_TABLE(of, xtfpga_i2s_of_match);
637 #endif
638
639 static const struct dev_pm_ops xtfpga_i2s_pm_ops = {
640 SET_RUNTIME_PM_OPS(xtfpga_i2s_runtime_suspend,
641 xtfpga_i2s_runtime_resume, NULL)
642 };
643
644 static struct platform_driver xtfpga_i2s_driver = {
645 .probe = xtfpga_i2s_probe,
646 .remove = xtfpga_i2s_remove,
647 .driver = {
648 .name = "xtfpga-i2s",
649 .of_match_table = of_match_ptr(xtfpga_i2s_of_match),
650 .pm = &xtfpga_i2s_pm_ops,
651 },
652 };
653
654 module_platform_driver(xtfpga_i2s_driver);
655
656 MODULE_AUTHOR("Max Filippov <jcmvbkbc@gmail.com>");
657 MODULE_DESCRIPTION("xtfpga I2S controller driver");
658 MODULE_LICENSE("GPL v2");
659
