1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/bitops.h>
7 #include <linux/device.h>
8 #include <linux/gpio/consumer.h>
9 #include <linux/init.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/of_gpio.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/printk.h>
15 #include <linux/regmap.h>
16 #include <linux/regulator/consumer.h>
17 #include <linux/slab.h>
18 #include <linux/soundwire/sdw.h>
19 #include <linux/soundwire/sdw_registers.h>
20 #include <linux/soundwire/sdw_type.h>
21 #include <sound/pcm.h>
22 #include <sound/pcm_params.h>
23 #include <sound/soc-dapm.h>
24 #include <sound/soc.h>
25 #include <sound/tlv.h>
26
27 #define WSA883X_BASE 0x3000
28 #define WSA883X_ANA_BG_TSADC_BASE (WSA883X_BASE + 0x00000001)
29 #define WSA883X_REF_CTRL (WSA883X_ANA_BG_TSADC_BASE + 0x0000)
30 #define WSA883X_TEST_CTL_0 (WSA883X_ANA_BG_TSADC_BASE + 0x0001)
31 #define WSA883X_BIAS_0 (WSA883X_ANA_BG_TSADC_BASE + 0x0002)
32 #define WSA883X_OP_CTL (WSA883X_ANA_BG_TSADC_BASE + 0x0003)
33 #define WSA883X_IREF_CTL (WSA883X_ANA_BG_TSADC_BASE + 0x0004)
34 #define WSA883X_ISENS_CTL (WSA883X_ANA_BG_TSADC_BASE + 0x0005)
35 #define WSA883X_CLK_CTL (WSA883X_ANA_BG_TSADC_BASE + 0x0006)
36 #define WSA883X_TEST_CTL_1 (WSA883X_ANA_BG_TSADC_BASE + 0x0007)
37 #define WSA883X_BIAS_1 (WSA883X_ANA_BG_TSADC_BASE + 0x0008)
38 #define WSA883X_ADC_CTL (WSA883X_ANA_BG_TSADC_BASE + 0x0009)
39 #define WSA883X_DOUT_MSB (WSA883X_ANA_BG_TSADC_BASE + 0x000A)
40 #define WSA883X_DOUT_LSB (WSA883X_ANA_BG_TSADC_BASE + 0x000B)
41 #define WSA883X_VBAT_SNS (WSA883X_ANA_BG_TSADC_BASE + 0x000C)
42 #define WSA883X_ITRIM_CODE (WSA883X_ANA_BG_TSADC_BASE + 0x000D)
43
44 #define WSA883X_ANA_IVSENSE_BASE (WSA883X_BASE + 0x0000000F)
45 #define WSA883X_EN (WSA883X_ANA_IVSENSE_BASE + 0x0000)
46 #define WSA883X_OVERRIDE1 (WSA883X_ANA_IVSENSE_BASE + 0x0001)
47 #define WSA883X_OVERRIDE2 (WSA883X_ANA_IVSENSE_BASE + 0x0002)
48 #define WSA883X_VSENSE1 (WSA883X_ANA_IVSENSE_BASE + 0x0003)
49 #define WSA883X_ISENSE1 (WSA883X_ANA_IVSENSE_BASE + 0x0004)
50 #define WSA883X_ISENSE2 (WSA883X_ANA_IVSENSE_BASE + 0x0005)
51 #define WSA883X_ISENSE_CAL (WSA883X_ANA_IVSENSE_BASE + 0x0006)
52 #define WSA883X_MISC (WSA883X_ANA_IVSENSE_BASE + 0x0007)
53 #define WSA883X_ADC_0 (WSA883X_ANA_IVSENSE_BASE + 0x0008)
54 #define WSA883X_ADC_1 (WSA883X_ANA_IVSENSE_BASE + 0x0009)
55 #define WSA883X_ADC_2 (WSA883X_ANA_IVSENSE_BASE + 0x000A)
56 #define WSA883X_ADC_3 (WSA883X_ANA_IVSENSE_BASE + 0x000B)
57 #define WSA883X_ADC_4 (WSA883X_ANA_IVSENSE_BASE + 0x000C)
58 #define WSA883X_ADC_5 (WSA883X_ANA_IVSENSE_BASE + 0x000D)
59 #define WSA883X_ADC_6 (WSA883X_ANA_IVSENSE_BASE + 0x000E)
60 #define WSA883X_ADC_7 (WSA883X_ANA_IVSENSE_BASE + 0x000F)
61 #define WSA883X_STATUS (WSA883X_ANA_IVSENSE_BASE + 0x0010)
62
63 #define WSA883X_ANA_SPK_TOP_BASE (WSA883X_BASE + 0x00000025)
64 #define WSA883X_DAC_CTRL_REG (WSA883X_ANA_SPK_TOP_BASE + 0x0000)
65 #define WSA883X_DAC_EN_DEBUG_REG (WSA883X_ANA_SPK_TOP_BASE + 0x0001)
66 #define WSA883X_DAC_OPAMP_BIAS1_REG (WSA883X_ANA_SPK_TOP_BASE + 0x0002)
67 #define WSA883X_DAC_OPAMP_BIAS2_REG (WSA883X_ANA_SPK_TOP_BASE + 0x0003)
68 #define WSA883X_DAC_VCM_CTRL_REG (WSA883X_ANA_SPK_TOP_BASE + 0x0004)
69 #define WSA883X_DAC_VOLTAGE_CTRL_REG (WSA883X_ANA_SPK_TOP_BASE + 0x0005)
70 #define WSA883X_ATEST1_REG (WSA883X_ANA_SPK_TOP_BASE + 0x0006)
71 #define WSA883X_ATEST2_REG (WSA883X_ANA_SPK_TOP_BASE + 0x0007)
72 #define WSA883X_SPKR_TOP_BIAS_REG1 (WSA883X_ANA_SPK_TOP_BASE + 0x0008)
73 #define WSA883X_SPKR_TOP_BIAS_REG2 (WSA883X_ANA_SPK_TOP_BASE + 0x0009)
74 #define WSA883X_SPKR_TOP_BIAS_REG3 (WSA883X_ANA_SPK_TOP_BASE + 0x000A)
75 #define WSA883X_SPKR_TOP_BIAS_REG4 (WSA883X_ANA_SPK_TOP_BASE + 0x000B)
76 #define WSA883X_SPKR_CLIP_DET_REG (WSA883X_ANA_SPK_TOP_BASE + 0x000C)
77 #define WSA883X_SPKR_DRV_LF_BLK_EN (WSA883X_ANA_SPK_TOP_BASE + 0x000D)
78 #define WSA883X_SPKR_DRV_LF_EN (WSA883X_ANA_SPK_TOP_BASE + 0x000E)
79 #define WSA883X_SPKR_DRV_LF_MASK_DCC_CTL (WSA883X_ANA_SPK_TOP_BASE + 0x000F)
80 #define WSA883X_SPKR_DRV_LF_MISC_CTL (WSA883X_ANA_SPK_TOP_BASE + 0x0010)
81 #define WSA883X_SPKR_DRV_LF_REG_GAIN (WSA883X_ANA_SPK_TOP_BASE + 0x0011)
82 #define WSA883X_SPKR_DRV_OS_CAL_CTL (WSA883X_ANA_SPK_TOP_BASE + 0x0012)
83 #define WSA883X_SPKR_DRV_OS_CAL_CTL1 (WSA883X_ANA_SPK_TOP_BASE + 0x0013)
84 #define WSA883X_SPKR_PWM_CLK_CTL (WSA883X_ANA_SPK_TOP_BASE + 0x0014)
85 #define WSA883X_SPKR_PWM_FREQ_SEL_MASK BIT(3)
86 #define WSA883X_SPKR_PWM_FREQ_F300KHZ 0
87 #define WSA883X_SPKR_PWM_FREQ_F600KHZ 1
88 #define WSA883X_SPKR_PDRV_HS_CTL (WSA883X_ANA_SPK_TOP_BASE + 0x0015)
89 #define WSA883X_SPKR_PDRV_LS_CTL (WSA883X_ANA_SPK_TOP_BASE + 0x0016)
90 #define WSA883X_SPKR_PWRSTG_DBG (WSA883X_ANA_SPK_TOP_BASE + 0x0017)
91 #define WSA883X_SPKR_OCP_CTL (WSA883X_ANA_SPK_TOP_BASE + 0x0018)
92 #define WSA883X_SPKR_BBM_CTL (WSA883X_ANA_SPK_TOP_BASE + 0x0019)
93 #define WSA883X_PA_STATUS0 (WSA883X_ANA_SPK_TOP_BASE + 0x001A)
94 #define WSA883X_PA_STATUS1 (WSA883X_ANA_SPK_TOP_BASE + 0x001B)
95 #define WSA883X_PA_STATUS2 (WSA883X_ANA_SPK_TOP_BASE + 0x001C)
96
97 #define WSA883X_ANA_BOOST_BASE (WSA883X_BASE + 0x00000043)
98 #define WSA883X_EN_CTRL (WSA883X_ANA_BOOST_BASE + 0x0000)
99 #define WSA883X_CURRENT_LIMIT (WSA883X_ANA_BOOST_BASE + 0x0001)
100 #define WSA883X_IBIAS1 (WSA883X_ANA_BOOST_BASE + 0x0002)
101 #define WSA883X_IBIAS2 (WSA883X_ANA_BOOST_BASE + 0x0003)
102 #define WSA883X_IBIAS3 (WSA883X_ANA_BOOST_BASE + 0x0004)
103 #define WSA883X_LDO_PROG (WSA883X_ANA_BOOST_BASE + 0x0005)
104 #define WSA883X_STABILITY_CTRL1 (WSA883X_ANA_BOOST_BASE + 0x0006)
105 #define WSA883X_STABILITY_CTRL2 (WSA883X_ANA_BOOST_BASE + 0x0007)
106 #define WSA883X_PWRSTAGE_CTRL1 (WSA883X_ANA_BOOST_BASE + 0x0008)
107 #define WSA883X_PWRSTAGE_CTRL2 (WSA883X_ANA_BOOST_BASE + 0x0009)
108 #define WSA883X_BYPASS_1 (WSA883X_ANA_BOOST_BASE + 0x000A)
109 #define WSA883X_BYPASS_2 (WSA883X_ANA_BOOST_BASE + 0x000B)
110 #define WSA883X_ZX_CTRL_1 (WSA883X_ANA_BOOST_BASE + 0x000C)
111 #define WSA883X_ZX_CTRL_2 (WSA883X_ANA_BOOST_BASE + 0x000D)
112 #define WSA883X_MISC1 (WSA883X_ANA_BOOST_BASE + 0x000E)
113 #define WSA883X_MISC2 (WSA883X_ANA_BOOST_BASE + 0x000F)
114 #define WSA883X_GMAMP_SUP1 (WSA883X_ANA_BOOST_BASE + 0x0010)
115 #define WSA883X_PWRSTAGE_CTRL3 (WSA883X_ANA_BOOST_BASE + 0x0011)
116 #define WSA883X_PWRSTAGE_CTRL4 (WSA883X_ANA_BOOST_BASE + 0x0012)
117 #define WSA883X_TEST1 (WSA883X_ANA_BOOST_BASE + 0x0013)
118 #define WSA883X_SPARE1 (WSA883X_ANA_BOOST_BASE + 0x0014)
119 #define WSA883X_SPARE2 (WSA883X_ANA_BOOST_BASE + 0x0015)
120
121 #define WSA883X_ANA_PON_LDOL_BASE (WSA883X_BASE + 0x00000059)
122 #define WSA883X_PON_CTL_0 (WSA883X_ANA_PON_LDOL_BASE + 0x0000)
123 #define WSA883X_PON_CLT_1 (WSA883X_ANA_PON_LDOL_BASE + 0x0001)
124 #define WSA883X_PON_CTL_2 (WSA883X_ANA_PON_LDOL_BASE + 0x0002)
125 #define WSA883X_PON_CTL_3 (WSA883X_ANA_PON_LDOL_BASE + 0x0003)
126 #define WSA883X_CKWD_CTL_0 (WSA883X_ANA_PON_LDOL_BASE + 0x0004)
127 #define WSA883X_CKWD_CTL_1 (WSA883X_ANA_PON_LDOL_BASE + 0x0005)
128 #define WSA883X_CKWD_CTL_2 (WSA883X_ANA_PON_LDOL_BASE + 0x0006)
129 #define WSA883X_CKSK_CTL_0 (WSA883X_ANA_PON_LDOL_BASE + 0x0007)
130 #define WSA883X_PADSW_CTL_0 (WSA883X_ANA_PON_LDOL_BASE + 0x0008)
131 #define WSA883X_TEST_0 (WSA883X_ANA_PON_LDOL_BASE + 0x0009)
132 #define WSA883X_TEST_1 (WSA883X_ANA_PON_LDOL_BASE + 0x000A)
133 #define WSA883X_STATUS_0 (WSA883X_ANA_PON_LDOL_BASE + 0x000B)
134 #define WSA883X_STATUS_1 (WSA883X_ANA_PON_LDOL_BASE + 0x000C)
135
136 #define WSA883X_DIG_CTRL_BASE (WSA883X_BASE + 0x00000400)
137 #define WSA883X_CHIP_ID0 (WSA883X_DIG_CTRL_BASE + 0x0001)
138 #define WSA883X_CHIP_ID1 (WSA883X_DIG_CTRL_BASE + 0x0002)
139 #define WSA883X_CHIP_ID2 (WSA883X_DIG_CTRL_BASE + 0x0003)
140 #define WSA883X_CHIP_ID3 (WSA883X_DIG_CTRL_BASE + 0x0004)
141 #define WSA883X_BUS_ID (WSA883X_DIG_CTRL_BASE + 0x0005)
142 #define WSA883X_CDC_RST_CTL (WSA883X_DIG_CTRL_BASE + 0x0006)
143 #define WSA883X_TOP_CLK_CFG (WSA883X_DIG_CTRL_BASE + 0x0007)
144 #define WSA883X_CDC_PATH_MODE (WSA883X_DIG_CTRL_BASE + 0x0008)
145 #define WSA883X_RXD_MODE_MASK BIT(1)
146 #define WSA883X_RXD_MODE_NORMAL 0
147 #define WSA883X_RXD_MODE_HIFI 1
148 #define WSA883X_CDC_CLK_CTL (WSA883X_DIG_CTRL_BASE + 0x0009)
149 #define WSA883X_SWR_RESET_EN (WSA883X_DIG_CTRL_BASE + 0x000A)
150 #define WSA883X_RESET_CTL (WSA883X_DIG_CTRL_BASE + 0x000B)
151 #define WSA883X_PA_FSM_CTL (WSA883X_DIG_CTRL_BASE + 0x0010)
152 #define WSA883X_GLOBAL_PA_EN_MASK BIT(0)
153 #define WSA883X_GLOBAL_PA_ENABLE 1
154 #define WSA883X_PA_FSM_TIMER0 (WSA883X_DIG_CTRL_BASE + 0x0011)
155 #define WSA883X_PA_FSM_TIMER1 (WSA883X_DIG_CTRL_BASE + 0x0012)
156 #define WSA883X_PA_FSM_STA (WSA883X_DIG_CTRL_BASE + 0x0013)
157 #define WSA883X_PA_FSM_ERR_COND (WSA883X_DIG_CTRL_BASE + 0x0014)
158 #define WSA883X_PA_FSM_MSK (WSA883X_DIG_CTRL_BASE + 0x0015)
159 #define WSA883X_PA_FSM_BYP (WSA883X_DIG_CTRL_BASE + 0x0016)
160 #define WSA883X_PA_FSM_DBG (WSA883X_DIG_CTRL_BASE + 0x0017)
161 #define WSA883X_TADC_VALUE_CTL (WSA883X_DIG_CTRL_BASE + 0x0020)
162 #define WSA883X_TEMP_DETECT_CTL (WSA883X_DIG_CTRL_BASE + 0x0021)
163 #define WSA883X_TEMP_MSB (WSA883X_DIG_CTRL_BASE + 0x0022)
164 #define WSA883X_TEMP_LSB (WSA883X_DIG_CTRL_BASE + 0x0023)
165 #define WSA883X_TEMP_CONFIG0 (WSA883X_DIG_CTRL_BASE + 0x0024)
166 #define WSA883X_TEMP_CONFIG1 (WSA883X_DIG_CTRL_BASE + 0x0025)
167 #define WSA883X_VBAT_ADC_FLT_CTL (WSA883X_DIG_CTRL_BASE + 0x0026)
168 #define WSA883X_VBAT_ADC_FLT_EN_MASK BIT(0)
169 #define WSA883X_VBAT_ADC_COEF_SEL_MASK GENMASK(3, 1)
170 #define WSA883X_VBAT_ADC_COEF_F_1DIV2 0x0
171 #define WSA883X_VBAT_ADC_COEF_F_1DIV16 0x3
172 #define WSA883X_VBAT_DIN_MSB (WSA883X_DIG_CTRL_BASE + 0x0027)
173 #define WSA883X_VBAT_DIN_LSB (WSA883X_DIG_CTRL_BASE + 0x0028)
174 #define WSA883X_VBAT_DOUT (WSA883X_DIG_CTRL_BASE + 0x0029)
175 #define WSA883X_SDM_PDM9_LSB (WSA883X_DIG_CTRL_BASE + 0x002A)
176 #define WSA883X_SDM_PDM9_MSB (WSA883X_DIG_CTRL_BASE + 0x002B)
177 #define WSA883X_CDC_RX_CTL (WSA883X_DIG_CTRL_BASE + 0x0030)
178 #define WSA883X_CDC_SPK_DSM_A1_0 (WSA883X_DIG_CTRL_BASE + 0x0031)
179 #define WSA883X_CDC_SPK_DSM_A1_1 (WSA883X_DIG_CTRL_BASE + 0x0032)
180 #define WSA883X_CDC_SPK_DSM_A2_0 (WSA883X_DIG_CTRL_BASE + 0x0033)
181 #define WSA883X_CDC_SPK_DSM_A2_1 (WSA883X_DIG_CTRL_BASE + 0x0034)
182 #define WSA883X_CDC_SPK_DSM_A3_0 (WSA883X_DIG_CTRL_BASE + 0x0035)
183 #define WSA883X_CDC_SPK_DSM_A3_1 (WSA883X_DIG_CTRL_BASE + 0x0036)
184 #define WSA883X_CDC_SPK_DSM_A4_0 (WSA883X_DIG_CTRL_BASE + 0x0037)
185 #define WSA883X_CDC_SPK_DSM_A4_1 (WSA883X_DIG_CTRL_BASE + 0x0038)
186 #define WSA883X_CDC_SPK_DSM_A5_0 (WSA883X_DIG_CTRL_BASE + 0x0039)
187 #define WSA883X_CDC_SPK_DSM_A5_1 (WSA883X_DIG_CTRL_BASE + 0x003A)
188 #define WSA883X_CDC_SPK_DSM_A6_0 (WSA883X_DIG_CTRL_BASE + 0x003B)
189 #define WSA883X_CDC_SPK_DSM_A7_0 (WSA883X_DIG_CTRL_BASE + 0x003C)
190 #define WSA883X_CDC_SPK_DSM_C_0 (WSA883X_DIG_CTRL_BASE + 0x003D)
191 #define WSA883X_CDC_SPK_DSM_C_1 (WSA883X_DIG_CTRL_BASE + 0x003E)
192 #define WSA883X_CDC_SPK_DSM_C_2 (WSA883X_DIG_CTRL_BASE + 0x003F)
193 #define WSA883X_CDC_SPK_DSM_C_3 (WSA883X_DIG_CTRL_BASE + 0x0040)
194 #define WSA883X_CDC_SPK_DSM_R1 (WSA883X_DIG_CTRL_BASE + 0x0041)
195 #define WSA883X_CDC_SPK_DSM_R2 (WSA883X_DIG_CTRL_BASE + 0x0042)
196 #define WSA883X_CDC_SPK_DSM_R3 (WSA883X_DIG_CTRL_BASE + 0x0043)
197 #define WSA883X_CDC_SPK_DSM_R4 (WSA883X_DIG_CTRL_BASE + 0x0044)
198 #define WSA883X_CDC_SPK_DSM_R5 (WSA883X_DIG_CTRL_BASE + 0x0045)
199 #define WSA883X_CDC_SPK_DSM_R6 (WSA883X_DIG_CTRL_BASE + 0x0046)
200 #define WSA883X_CDC_SPK_DSM_R7 (WSA883X_DIG_CTRL_BASE + 0x0047)
201 #define WSA883X_CDC_SPK_GAIN_PDM_0 (WSA883X_DIG_CTRL_BASE + 0x0048)
202 #define WSA883X_CDC_SPK_GAIN_PDM_1 (WSA883X_DIG_CTRL_BASE + 0x0049)
203 #define WSA883X_CDC_SPK_GAIN_PDM_2 (WSA883X_DIG_CTRL_BASE + 0x004A)
204 #define WSA883X_PDM_WD_CTL (WSA883X_DIG_CTRL_BASE + 0x004B)
205 #define WSA883X_PDM_EN_MASK BIT(0)
206 #define WSA883X_PDM_ENABLE BIT(0)
207 #define WSA883X_DEM_BYPASS_DATA0 (WSA883X_DIG_CTRL_BASE + 0x004C)
208 #define WSA883X_DEM_BYPASS_DATA1 (WSA883X_DIG_CTRL_BASE + 0x004D)
209 #define WSA883X_DEM_BYPASS_DATA2 (WSA883X_DIG_CTRL_BASE + 0x004E)
210 #define WSA883X_DEM_BYPASS_DATA3 (WSA883X_DIG_CTRL_BASE + 0x004F)
211 #define WSA883X_WAVG_CTL (WSA883X_DIG_CTRL_BASE + 0x0050)
212 #define WSA883X_WAVG_LRA_PER_0 (WSA883X_DIG_CTRL_BASE + 0x0051)
213 #define WSA883X_WAVG_LRA_PER_1 (WSA883X_DIG_CTRL_BASE + 0x0052)
214 #define WSA883X_WAVG_DELTA_THETA_0 (WSA883X_DIG_CTRL_BASE + 0x0053)
215 #define WSA883X_WAVG_DELTA_THETA_1 (WSA883X_DIG_CTRL_BASE + 0x0054)
216 #define WSA883X_WAVG_DIRECT_AMP_0 (WSA883X_DIG_CTRL_BASE + 0x0055)
217 #define WSA883X_WAVG_DIRECT_AMP_1 (WSA883X_DIG_CTRL_BASE + 0x0056)
218 #define WSA883X_WAVG_PTRN_AMP0_0 (WSA883X_DIG_CTRL_BASE + 0x0057)
219 #define WSA883X_WAVG_PTRN_AMP0_1 (WSA883X_DIG_CTRL_BASE + 0x0058)
220 #define WSA883X_WAVG_PTRN_AMP1_0 (WSA883X_DIG_CTRL_BASE + 0x0059)
221 #define WSA883X_WAVG_PTRN_AMP1_1 (WSA883X_DIG_CTRL_BASE + 0x005A)
222 #define WSA883X_WAVG_PTRN_AMP2_0 (WSA883X_DIG_CTRL_BASE + 0x005B)
223 #define WSA883X_WAVG_PTRN_AMP2_1 (WSA883X_DIG_CTRL_BASE + 0x005C)
224 #define WSA883X_WAVG_PTRN_AMP3_0 (WSA883X_DIG_CTRL_BASE + 0x005D)
225 #define WSA883X_WAVG_PTRN_AMP3_1 (WSA883X_DIG_CTRL_BASE + 0x005E)
226 #define WSA883X_WAVG_PTRN_AMP4_0 (WSA883X_DIG_CTRL_BASE + 0x005F)
227 #define WSA883X_WAVG_PTRN_AMP4_1 (WSA883X_DIG_CTRL_BASE + 0x0060)
228 #define WSA883X_WAVG_PTRN_AMP5_0 (WSA883X_DIG_CTRL_BASE + 0x0061)
229 #define WSA883X_WAVG_PTRN_AMP5_1 (WSA883X_DIG_CTRL_BASE + 0x0062)
230 #define WSA883X_WAVG_PTRN_AMP6_0 (WSA883X_DIG_CTRL_BASE + 0x0063)
231 #define WSA883X_WAVG_PTRN_AMP6_1 (WSA883X_DIG_CTRL_BASE + 0x0064)
232 #define WSA883X_WAVG_PTRN_AMP7_0 (WSA883X_DIG_CTRL_BASE + 0x0065)
233 #define WSA883X_WAVG_PTRN_AMP7_1 (WSA883X_DIG_CTRL_BASE + 0x0066)
234 #define WSA883X_WAVG_PER_0_1 (WSA883X_DIG_CTRL_BASE + 0x0067)
235 #define WSA883X_WAVG_PER_2_3 (WSA883X_DIG_CTRL_BASE + 0x0068)
236 #define WSA883X_WAVG_PER_4_5 (WSA883X_DIG_CTRL_BASE + 0x0069)
237 #define WSA883X_WAVG_PER_6_7 (WSA883X_DIG_CTRL_BASE + 0x006A)
238 #define WSA883X_WAVG_STA (WSA883X_DIG_CTRL_BASE + 0x006B)
239 #define WSA883X_DRE_CTL_0 (WSA883X_DIG_CTRL_BASE + 0x006C)
240 #define WSA883X_DRE_OFFSET_MASK GENMASK(2, 0)
241 #define WSA883X_DRE_PROG_DELAY_MASK GENMASK(7, 4)
242 #define WSA883X_DRE_CTL_1 (WSA883X_DIG_CTRL_BASE + 0x006D)
243 #define WSA883X_DRE_GAIN_EN_MASK BIT(0)
244 #define WSA883X_DRE_GAIN_FROM_CSR 1
245 #define WSA883X_DRE_IDLE_DET_CTL (WSA883X_DIG_CTRL_BASE + 0x006E)
246 #define WSA883X_CLSH_CTL_0 (WSA883X_DIG_CTRL_BASE + 0x0070)
247 #define WSA883X_CLSH_CTL_1 (WSA883X_DIG_CTRL_BASE + 0x0071)
248 #define WSA883X_CLSH_V_HD_PA (WSA883X_DIG_CTRL_BASE + 0x0072)
249 #define WSA883X_CLSH_V_PA_MIN (WSA883X_DIG_CTRL_BASE + 0x0073)
250 #define WSA883X_CLSH_OVRD_VAL (WSA883X_DIG_CTRL_BASE + 0x0074)
251 #define WSA883X_CLSH_HARD_MAX (WSA883X_DIG_CTRL_BASE + 0x0075)
252 #define WSA883X_CLSH_SOFT_MAX (WSA883X_DIG_CTRL_BASE + 0x0076)
253 #define WSA883X_CLSH_SIG_DP (WSA883X_DIG_CTRL_BASE + 0x0077)
254 #define WSA883X_TAGC_CTL (WSA883X_DIG_CTRL_BASE + 0x0078)
255 #define WSA883X_TAGC_TIME (WSA883X_DIG_CTRL_BASE + 0x0079)
256 #define WSA883X_TAGC_E2E_GAIN (WSA883X_DIG_CTRL_BASE + 0x007A)
257 #define WSA883X_TAGC_FORCE_VAL (WSA883X_DIG_CTRL_BASE + 0x007B)
258 #define WSA883X_VAGC_CTL (WSA883X_DIG_CTRL_BASE + 0x007C)
259 #define WSA883X_VAGC_TIME (WSA883X_DIG_CTRL_BASE + 0x007D)
260 #define WSA883X_VAGC_ATTN_LVL_1_2 (WSA883X_DIG_CTRL_BASE + 0x007E)
261 #define WSA883X_VAGC_ATTN_LVL_3 (WSA883X_DIG_CTRL_BASE + 0x007F)
262 #define WSA883X_INTR_MODE (WSA883X_DIG_CTRL_BASE + 0x0080)
263 #define WSA883X_INTR_MASK0 (WSA883X_DIG_CTRL_BASE + 0x0081)
264 #define WSA883X_INTR_MASK1 (WSA883X_DIG_CTRL_BASE + 0x0082)
265 #define WSA883X_INTR_STATUS0 (WSA883X_DIG_CTRL_BASE + 0x0083)
266 #define WSA883X_INTR_STATUS1 (WSA883X_DIG_CTRL_BASE + 0x0084)
267 #define WSA883X_INTR_CLEAR0 (WSA883X_DIG_CTRL_BASE + 0x0085)
268 #define WSA883X_INTR_CLEAR1 (WSA883X_DIG_CTRL_BASE + 0x0086)
269 #define WSA883X_INTR_LEVEL0 (WSA883X_DIG_CTRL_BASE + 0x0087)
270 #define WSA883X_INTR_LEVEL1 (WSA883X_DIG_CTRL_BASE + 0x0088)
271 #define WSA883X_INTR_SET0 (WSA883X_DIG_CTRL_BASE + 0x0089)
272 #define WSA883X_INTR_SET1 (WSA883X_DIG_CTRL_BASE + 0x008A)
273 #define WSA883X_INTR_TEST0 (WSA883X_DIG_CTRL_BASE + 0x008B)
274 #define WSA883X_INTR_TEST1 (WSA883X_DIG_CTRL_BASE + 0x008C)
275 #define WSA883X_OTP_CTRL0 (WSA883X_DIG_CTRL_BASE + 0x0090)
276 #define WSA883X_OTP_CTRL1 (WSA883X_DIG_CTRL_BASE + 0x0091)
277 #define WSA883X_HDRIVE_CTL_GROUP1 (WSA883X_DIG_CTRL_BASE + 0x0092)
278 #define WSA883X_PIN_CTL (WSA883X_DIG_CTRL_BASE + 0x0093)
279 #define WSA883X_PIN_CTL_OE (WSA883X_DIG_CTRL_BASE + 0x0094)
280 #define WSA883X_PIN_WDATA_IOPAD (WSA883X_DIG_CTRL_BASE + 0x0095)
281 #define WSA883X_PIN_STATUS (WSA883X_DIG_CTRL_BASE + 0x0096)
282 #define WSA883X_I2C_SLAVE_CTL (WSA883X_DIG_CTRL_BASE + 0x0097)
283 #define WSA883X_PDM_TEST_MODE (WSA883X_DIG_CTRL_BASE + 0x00A0)
284 #define WSA883X_ATE_TEST_MODE (WSA883X_DIG_CTRL_BASE + 0x00A1)
285 #define WSA883X_DIG_DEBUG_MODE (WSA883X_DIG_CTRL_BASE + 0x00A3)
286 #define WSA883X_DIG_DEBUG_SEL (WSA883X_DIG_CTRL_BASE + 0x00A4)
287 #define WSA883X_DIG_DEBUG_EN (WSA883X_DIG_CTRL_BASE + 0x00A5)
288 #define WSA883X_SWR_HM_TEST0 (WSA883X_DIG_CTRL_BASE + 0x00A6)
289 #define WSA883X_SWR_HM_TEST1 (WSA883X_DIG_CTRL_BASE + 0x00A7)
290 #define WSA883X_SWR_PAD_CTL (WSA883X_DIG_CTRL_BASE + 0x00A8)
291 #define WSA883X_TADC_DETECT_DBG_CTL (WSA883X_DIG_CTRL_BASE + 0x00A9)
292 #define WSA883X_TADC_DEBUG_MSB (WSA883X_DIG_CTRL_BASE + 0x00AA)
293 #define WSA883X_TADC_DEBUG_LSB (WSA883X_DIG_CTRL_BASE + 0x00AB)
294 #define WSA883X_SAMPLE_EDGE_SEL (WSA883X_DIG_CTRL_BASE + 0x00AC)
295 #define WSA883X_SWR_EDGE_SEL (WSA883X_DIG_CTRL_BASE + 0x00AD)
296 #define WSA883X_TEST_MODE_CTL (WSA883X_DIG_CTRL_BASE + 0x00AE)
297 #define WSA883X_IOPAD_CTL (WSA883X_DIG_CTRL_BASE + 0x00AF)
298 #define WSA883X_ANA_CSR_DBG_ADD (WSA883X_DIG_CTRL_BASE + 0x00B0)
299 #define WSA883X_ANA_CSR_DBG_CTL (WSA883X_DIG_CTRL_BASE + 0x00B1)
300 #define WSA883X_SPARE_R (WSA883X_DIG_CTRL_BASE + 0x00BC)
301 #define WSA883X_SPARE_0 (WSA883X_DIG_CTRL_BASE + 0x00BD)
302 #define WSA883X_SPARE_1 (WSA883X_DIG_CTRL_BASE + 0x00BE)
303 #define WSA883X_SPARE_2 (WSA883X_DIG_CTRL_BASE + 0x00BF)
304 #define WSA883X_SCODE (WSA883X_DIG_CTRL_BASE + 0x00C0)
305
306 #define WSA883X_DIG_TRIM_BASE (WSA883X_BASE + 0x00000500)
307 #define WSA883X_OTP_REG_0 (WSA883X_DIG_TRIM_BASE + 0x0080)
308 #define WSA883X_ID_MASK GENMASK(3, 0)
309 #define WSA883X_OTP_REG_1 (WSA883X_DIG_TRIM_BASE + 0x0081)
310 #define WSA883X_OTP_REG_2 (WSA883X_DIG_TRIM_BASE + 0x0082)
311 #define WSA883X_OTP_REG_3 (WSA883X_DIG_TRIM_BASE + 0x0083)
312 #define WSA883X_OTP_REG_4 (WSA883X_DIG_TRIM_BASE + 0x0084)
313 #define WSA883X_OTP_REG_5 (WSA883X_DIG_TRIM_BASE + 0x0085)
314 #define WSA883X_OTP_REG_6 (WSA883X_DIG_TRIM_BASE + 0x0086)
315 #define WSA883X_OTP_REG_7 (WSA883X_DIG_TRIM_BASE + 0x0087)
316 #define WSA883X_OTP_REG_8 (WSA883X_DIG_TRIM_BASE + 0x0088)
317 #define WSA883X_OTP_REG_9 (WSA883X_DIG_TRIM_BASE + 0x0089)
318 #define WSA883X_OTP_REG_10 (WSA883X_DIG_TRIM_BASE + 0x008A)
319 #define WSA883X_OTP_REG_11 (WSA883X_DIG_TRIM_BASE + 0x008B)
320 #define WSA883X_OTP_REG_12 (WSA883X_DIG_TRIM_BASE + 0x008C)
321 #define WSA883X_OTP_REG_13 (WSA883X_DIG_TRIM_BASE + 0x008D)
322 #define WSA883X_OTP_REG_14 (WSA883X_DIG_TRIM_BASE + 0x008E)
323 #define WSA883X_OTP_REG_15 (WSA883X_DIG_TRIM_BASE + 0x008F)
324 #define WSA883X_OTP_REG_16 (WSA883X_DIG_TRIM_BASE + 0x0090)
325 #define WSA883X_OTP_REG_17 (WSA883X_DIG_TRIM_BASE + 0x0091)
326 #define WSA883X_OTP_REG_18 (WSA883X_DIG_TRIM_BASE + 0x0092)
327 #define WSA883X_OTP_REG_19 (WSA883X_DIG_TRIM_BASE + 0x0093)
328 #define WSA883X_OTP_REG_20 (WSA883X_DIG_TRIM_BASE + 0x0094)
329 #define WSA883X_OTP_REG_21 (WSA883X_DIG_TRIM_BASE + 0x0095)
330 #define WSA883X_OTP_REG_22 (WSA883X_DIG_TRIM_BASE + 0x0096)
331 #define WSA883X_OTP_REG_23 (WSA883X_DIG_TRIM_BASE + 0x0097)
332 #define WSA883X_OTP_REG_24 (WSA883X_DIG_TRIM_BASE + 0x0098)
333 #define WSA883X_OTP_REG_25 (WSA883X_DIG_TRIM_BASE + 0x0099)
334 #define WSA883X_OTP_REG_26 (WSA883X_DIG_TRIM_BASE + 0x009A)
335 #define WSA883X_OTP_REG_27 (WSA883X_DIG_TRIM_BASE + 0x009B)
336 #define WSA883X_OTP_REG_28 (WSA883X_DIG_TRIM_BASE + 0x009C)
337 #define WSA883X_OTP_REG_29 (WSA883X_DIG_TRIM_BASE + 0x009D)
338 #define WSA883X_OTP_REG_30 (WSA883X_DIG_TRIM_BASE + 0x009E)
339 #define WSA883X_OTP_REG_31 (WSA883X_DIG_TRIM_BASE + 0x009F)
340 #define WSA883X_OTP_REG_32 (WSA883X_DIG_TRIM_BASE + 0x00A0)
341 #define WSA883X_OTP_REG_33 (WSA883X_DIG_TRIM_BASE + 0x00A1)
342 #define WSA883X_OTP_REG_34 (WSA883X_DIG_TRIM_BASE + 0x00A2)
343 #define WSA883X_OTP_REG_35 (WSA883X_DIG_TRIM_BASE + 0x00A3)
344 #define WSA883X_OTP_REG_63 (WSA883X_DIG_TRIM_BASE + 0x00BF)
345
346 #define WSA883X_DIG_EMEM_BASE (WSA883X_BASE + 0x000005C0)
347 #define WSA883X_EMEM_0 (WSA883X_DIG_EMEM_BASE + 0x0000)
348 #define WSA883X_EMEM_1 (WSA883X_DIG_EMEM_BASE + 0x0001)
349 #define WSA883X_EMEM_2 (WSA883X_DIG_EMEM_BASE + 0x0002)
350 #define WSA883X_EMEM_3 (WSA883X_DIG_EMEM_BASE + 0x0003)
351 #define WSA883X_EMEM_4 (WSA883X_DIG_EMEM_BASE + 0x0004)
352 #define WSA883X_EMEM_5 (WSA883X_DIG_EMEM_BASE + 0x0005)
353 #define WSA883X_EMEM_6 (WSA883X_DIG_EMEM_BASE + 0x0006)
354 #define WSA883X_EMEM_7 (WSA883X_DIG_EMEM_BASE + 0x0007)
355 #define WSA883X_EMEM_8 (WSA883X_DIG_EMEM_BASE + 0x0008)
356 #define WSA883X_EMEM_9 (WSA883X_DIG_EMEM_BASE + 0x0009)
357 #define WSA883X_EMEM_10 (WSA883X_DIG_EMEM_BASE + 0x000A)
358 #define WSA883X_EMEM_11 (WSA883X_DIG_EMEM_BASE + 0x000B)
359 #define WSA883X_EMEM_12 (WSA883X_DIG_EMEM_BASE + 0x000C)
360 #define WSA883X_EMEM_13 (WSA883X_DIG_EMEM_BASE + 0x000D)
361 #define WSA883X_EMEM_14 (WSA883X_DIG_EMEM_BASE + 0x000E)
362 #define WSA883X_EMEM_15 (WSA883X_DIG_EMEM_BASE + 0x000F)
363 #define WSA883X_EMEM_16 (WSA883X_DIG_EMEM_BASE + 0x0010)
364 #define WSA883X_EMEM_17 (WSA883X_DIG_EMEM_BASE + 0x0011)
365 #define WSA883X_EMEM_18 (WSA883X_DIG_EMEM_BASE + 0x0012)
366 #define WSA883X_EMEM_19 (WSA883X_DIG_EMEM_BASE + 0x0013)
367 #define WSA883X_EMEM_20 (WSA883X_DIG_EMEM_BASE + 0x0014)
368 #define WSA883X_EMEM_21 (WSA883X_DIG_EMEM_BASE + 0x0015)
369 #define WSA883X_EMEM_22 (WSA883X_DIG_EMEM_BASE + 0x0016)
370 #define WSA883X_EMEM_23 (WSA883X_DIG_EMEM_BASE + 0x0017)
371 #define WSA883X_EMEM_24 (WSA883X_DIG_EMEM_BASE + 0x0018)
372 #define WSA883X_EMEM_25 (WSA883X_DIG_EMEM_BASE + 0x0019)
373 #define WSA883X_EMEM_26 (WSA883X_DIG_EMEM_BASE + 0x001A)
374 #define WSA883X_EMEM_27 (WSA883X_DIG_EMEM_BASE + 0x001B)
375 #define WSA883X_EMEM_28 (WSA883X_DIG_EMEM_BASE + 0x001C)
376 #define WSA883X_EMEM_29 (WSA883X_DIG_EMEM_BASE + 0x001D)
377 #define WSA883X_EMEM_30 (WSA883X_DIG_EMEM_BASE + 0x001E)
378 #define WSA883X_EMEM_31 (WSA883X_DIG_EMEM_BASE + 0x001F)
379 #define WSA883X_EMEM_32 (WSA883X_DIG_EMEM_BASE + 0x0020)
380 #define WSA883X_EMEM_33 (WSA883X_DIG_EMEM_BASE + 0x0021)
381 #define WSA883X_EMEM_34 (WSA883X_DIG_EMEM_BASE + 0x0022)
382 #define WSA883X_EMEM_35 (WSA883X_DIG_EMEM_BASE + 0x0023)
383 #define WSA883X_EMEM_36 (WSA883X_DIG_EMEM_BASE + 0x0024)
384 #define WSA883X_EMEM_37 (WSA883X_DIG_EMEM_BASE + 0x0025)
385 #define WSA883X_EMEM_38 (WSA883X_DIG_EMEM_BASE + 0x0026)
386 #define WSA883X_EMEM_39 (WSA883X_DIG_EMEM_BASE + 0x0027)
387 #define WSA883X_EMEM_40 (WSA883X_DIG_EMEM_BASE + 0x0028)
388 #define WSA883X_EMEM_41 (WSA883X_DIG_EMEM_BASE + 0x0029)
389 #define WSA883X_EMEM_42 (WSA883X_DIG_EMEM_BASE + 0x002A)
390 #define WSA883X_EMEM_43 (WSA883X_DIG_EMEM_BASE + 0x002B)
391 #define WSA883X_EMEM_44 (WSA883X_DIG_EMEM_BASE + 0x002C)
392 #define WSA883X_EMEM_45 (WSA883X_DIG_EMEM_BASE + 0x002D)
393 #define WSA883X_EMEM_46 (WSA883X_DIG_EMEM_BASE + 0x002E)
394 #define WSA883X_EMEM_47 (WSA883X_DIG_EMEM_BASE + 0x002F)
395 #define WSA883X_EMEM_48 (WSA883X_DIG_EMEM_BASE + 0x0030)
396 #define WSA883X_EMEM_49 (WSA883X_DIG_EMEM_BASE + 0x0031)
397 #define WSA883X_EMEM_50 (WSA883X_DIG_EMEM_BASE + 0x0032)
398 #define WSA883X_EMEM_51 (WSA883X_DIG_EMEM_BASE + 0x0033)
399 #define WSA883X_EMEM_52 (WSA883X_DIG_EMEM_BASE + 0x0034)
400 #define WSA883X_EMEM_53 (WSA883X_DIG_EMEM_BASE + 0x0035)
401 #define WSA883X_EMEM_54 (WSA883X_DIG_EMEM_BASE + 0x0036)
402 #define WSA883X_EMEM_55 (WSA883X_DIG_EMEM_BASE + 0x0037)
403 #define WSA883X_EMEM_56 (WSA883X_DIG_EMEM_BASE + 0x0038)
404 #define WSA883X_EMEM_57 (WSA883X_DIG_EMEM_BASE + 0x0039)
405 #define WSA883X_EMEM_58 (WSA883X_DIG_EMEM_BASE + 0x003A)
406 #define WSA883X_EMEM_59 (WSA883X_DIG_EMEM_BASE + 0x003B)
407 #define WSA883X_EMEM_60 (WSA883X_DIG_EMEM_BASE + 0x003C)
408 #define WSA883X_EMEM_61 (WSA883X_DIG_EMEM_BASE + 0x003D)
409 #define WSA883X_EMEM_62 (WSA883X_DIG_EMEM_BASE + 0x003E)
410 #define WSA883X_EMEM_63 (WSA883X_DIG_EMEM_BASE + 0x003F)
411
412 #define WSA883X_NUM_REGISTERS (WSA883X_EMEM_63 + 1)
413 #define WSA883X_MAX_REGISTER (WSA883X_NUM_REGISTERS - 1)
414
415 #define WSA883X_VERSION_1_0 0
416 #define WSA883X_VERSION_1_1 1
417
418 #define WSA883X_MAX_SWR_PORTS 4
419 #define WSA883X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
420 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
421 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
422 SNDRV_PCM_RATE_384000)
423 /* Fractional Rates */
424 #define WSA883X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
425 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
426
427 #define WSA883X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
428 SNDRV_PCM_FMTBIT_S24_LE |\
429 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
430
431 struct wsa883x_priv {
432 struct regmap *regmap;
433 struct device *dev;
434 struct regulator *vdd;
435 struct sdw_slave *slave;
436 struct sdw_stream_config sconfig;
437 struct sdw_stream_runtime *sruntime;
438 struct sdw_port_config port_config[WSA883X_MAX_SWR_PORTS];
439 struct gpio_desc *sd_n;
440 bool port_prepared[WSA883X_MAX_SWR_PORTS];
441 bool port_enable[WSA883X_MAX_SWR_PORTS];
442 int version;
443 int variant;
444 int active_ports;
445 int dev_mode;
446 int comp_offset;
447 };
448
449 enum {
450 WSA8830 = 0,
451 WSA8835,
452 WSA8832,
453 WSA8835_V2 = 5,
454 };
455
456 enum {
457 COMP_OFFSET0,
458 COMP_OFFSET1,
459 COMP_OFFSET2,
460 COMP_OFFSET3,
461 COMP_OFFSET4,
462 };
463
464 enum wsa_port_ids {
465 WSA883X_PORT_DAC,
466 WSA883X_PORT_COMP,
467 WSA883X_PORT_BOOST,
468 WSA883X_PORT_VISENSE,
469 };
470
471 static const char * const wsa_dev_mode_text[] = {
472 "Speaker", "Receiver", "Ultrasound"
473 };
474
475 enum {
476 SPEAKER,
477 RECEIVER,
478 ULTRASOUND,
479 };
480
481 static const struct soc_enum wsa_dev_mode_enum =
482 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(wsa_dev_mode_text), wsa_dev_mode_text);
483
484 /* 4 ports */
485 static struct sdw_dpn_prop wsa_sink_dpn_prop[WSA883X_MAX_SWR_PORTS] = {
486 {
487 /* DAC */
488 .num = 1,
489 .type = SDW_DPN_SIMPLE,
490 .min_ch = 1,
491 .max_ch = 1,
492 .simple_ch_prep_sm = true,
493 .read_only_wordlength = true,
494 }, {
495 /* COMP */
496 .num = 2,
497 .type = SDW_DPN_SIMPLE,
498 .min_ch = 1,
499 .max_ch = 1,
500 .simple_ch_prep_sm = true,
501 .read_only_wordlength = true,
502 }, {
503 /* BOOST */
504 .num = 3,
505 .type = SDW_DPN_SIMPLE,
506 .min_ch = 1,
507 .max_ch = 1,
508 .simple_ch_prep_sm = true,
509 .read_only_wordlength = true,
510 }, {
511 /* VISENSE */
512 .num = 4,
513 .type = SDW_DPN_SIMPLE,
514 .min_ch = 1,
515 .max_ch = 1,
516 .simple_ch_prep_sm = true,
517 .read_only_wordlength = true,
518 }
519 };
520
521 static const struct sdw_port_config wsa883x_pconfig[WSA883X_MAX_SWR_PORTS] = {
522 {
523 .num = 1,
524 .ch_mask = 0x1,
525 }, {
526 .num = 2,
527 .ch_mask = 0xf,
528 }, {
529 .num = 3,
530 .ch_mask = 0x3,
531 }, { /* IV feedback */
532 .num = 4,
533 .ch_mask = 0x3,
534 },
535 };
536
537 static struct reg_default wsa883x_defaults[] = {
538 { WSA883X_REF_CTRL, 0xD5 },
539 { WSA883X_TEST_CTL_0, 0x06 },
540 { WSA883X_BIAS_0, 0xD2 },
541 { WSA883X_OP_CTL, 0xE0 },
542 { WSA883X_IREF_CTL, 0x57 },
543 { WSA883X_ISENS_CTL, 0x47 },
544 { WSA883X_CLK_CTL, 0x87 },
545 { WSA883X_TEST_CTL_1, 0x00 },
546 { WSA883X_BIAS_1, 0x51 },
547 { WSA883X_ADC_CTL, 0x01 },
548 { WSA883X_DOUT_MSB, 0x00 },
549 { WSA883X_DOUT_LSB, 0x00 },
550 { WSA883X_VBAT_SNS, 0x40 },
551 { WSA883X_ITRIM_CODE, 0x9F },
552 { WSA883X_EN, 0x20 },
553 { WSA883X_OVERRIDE1, 0x00 },
554 { WSA883X_OVERRIDE2, 0x08 },
555 { WSA883X_VSENSE1, 0xD3 },
556 { WSA883X_ISENSE1, 0xD4 },
557 { WSA883X_ISENSE2, 0x20 },
558 { WSA883X_ISENSE_CAL, 0x00 },
559 { WSA883X_MISC, 0x08 },
560 { WSA883X_ADC_0, 0x00 },
561 { WSA883X_ADC_1, 0x00 },
562 { WSA883X_ADC_2, 0x40 },
563 { WSA883X_ADC_3, 0x80 },
564 { WSA883X_ADC_4, 0x25 },
565 { WSA883X_ADC_5, 0x25 },
566 { WSA883X_ADC_6, 0x08 },
567 { WSA883X_ADC_7, 0x81 },
568 { WSA883X_STATUS, 0x00 },
569 { WSA883X_DAC_CTRL_REG, 0x53 },
570 { WSA883X_DAC_EN_DEBUG_REG, 0x00 },
571 { WSA883X_DAC_OPAMP_BIAS1_REG, 0x48 },
572 { WSA883X_DAC_OPAMP_BIAS2_REG, 0x48 },
573 { WSA883X_DAC_VCM_CTRL_REG, 0x88 },
574 { WSA883X_DAC_VOLTAGE_CTRL_REG, 0xA5 },
575 { WSA883X_ATEST1_REG, 0x00 },
576 { WSA883X_ATEST2_REG, 0x00 },
577 { WSA883X_SPKR_TOP_BIAS_REG1, 0x6A },
578 { WSA883X_SPKR_TOP_BIAS_REG2, 0x65 },
579 { WSA883X_SPKR_TOP_BIAS_REG3, 0x55 },
580 { WSA883X_SPKR_TOP_BIAS_REG4, 0xA9 },
581 { WSA883X_SPKR_CLIP_DET_REG, 0x9C },
582 { WSA883X_SPKR_DRV_LF_BLK_EN, 0x0F },
583 { WSA883X_SPKR_DRV_LF_EN, 0x0A },
584 { WSA883X_SPKR_DRV_LF_MASK_DCC_CTL, 0x00 },
585 { WSA883X_SPKR_DRV_LF_MISC_CTL, 0x3A },
586 { WSA883X_SPKR_DRV_LF_REG_GAIN, 0x00 },
587 { WSA883X_SPKR_DRV_OS_CAL_CTL, 0x00 },
588 { WSA883X_SPKR_DRV_OS_CAL_CTL1, 0x90 },
589 { WSA883X_SPKR_PWM_CLK_CTL, 0x00 },
590 { WSA883X_SPKR_PDRV_HS_CTL, 0x52 },
591 { WSA883X_SPKR_PDRV_LS_CTL, 0x48 },
592 { WSA883X_SPKR_PWRSTG_DBG, 0x08 },
593 { WSA883X_SPKR_OCP_CTL, 0xE2 },
594 { WSA883X_SPKR_BBM_CTL, 0x92 },
595 { WSA883X_PA_STATUS0, 0x00 },
596 { WSA883X_PA_STATUS1, 0x00 },
597 { WSA883X_PA_STATUS2, 0x80 },
598 { WSA883X_EN_CTRL, 0x44 },
599 { WSA883X_CURRENT_LIMIT, 0xCC },
600 { WSA883X_IBIAS1, 0x00 },
601 { WSA883X_IBIAS2, 0x00 },
602 { WSA883X_IBIAS3, 0x00 },
603 { WSA883X_LDO_PROG, 0x02 },
604 { WSA883X_STABILITY_CTRL1, 0x8E },
605 { WSA883X_STABILITY_CTRL2, 0x10 },
606 { WSA883X_PWRSTAGE_CTRL1, 0x06 },
607 { WSA883X_PWRSTAGE_CTRL2, 0x00 },
608 { WSA883X_BYPASS_1, 0x19 },
609 { WSA883X_BYPASS_2, 0x13 },
610 { WSA883X_ZX_CTRL_1, 0xF0 },
611 { WSA883X_ZX_CTRL_2, 0x04 },
612 { WSA883X_MISC1, 0x06 },
613 { WSA883X_MISC2, 0xA0 },
614 { WSA883X_GMAMP_SUP1, 0x82 },
615 { WSA883X_PWRSTAGE_CTRL3, 0x39 },
616 { WSA883X_PWRSTAGE_CTRL4, 0x5F },
617 { WSA883X_TEST1, 0x00 },
618 { WSA883X_SPARE1, 0x00 },
619 { WSA883X_SPARE2, 0x00 },
620 { WSA883X_PON_CTL_0, 0x10 },
621 { WSA883X_PON_CLT_1, 0xE0 },
622 { WSA883X_PON_CTL_2, 0x90 },
623 { WSA883X_PON_CTL_3, 0x70 },
624 { WSA883X_CKWD_CTL_0, 0x34 },
625 { WSA883X_CKWD_CTL_1, 0x0F },
626 { WSA883X_CKWD_CTL_2, 0x00 },
627 { WSA883X_CKSK_CTL_0, 0x00 },
628 { WSA883X_PADSW_CTL_0, 0x00 },
629 { WSA883X_TEST_0, 0x00 },
630 { WSA883X_TEST_1, 0x00 },
631 { WSA883X_STATUS_0, 0x00 },
632 { WSA883X_STATUS_1, 0x00 },
633 { WSA883X_CHIP_ID0, 0x00 },
634 { WSA883X_CHIP_ID1, 0x00 },
635 { WSA883X_CHIP_ID2, 0x02 },
636 { WSA883X_CHIP_ID3, 0x02 },
637 { WSA883X_BUS_ID, 0x00 },
638 { WSA883X_CDC_RST_CTL, 0x01 },
639 { WSA883X_TOP_CLK_CFG, 0x00 },
640 { WSA883X_CDC_PATH_MODE, 0x00 },
641 { WSA883X_CDC_CLK_CTL, 0xFF },
642 { WSA883X_SWR_RESET_EN, 0x00 },
643 { WSA883X_RESET_CTL, 0x00 },
644 { WSA883X_PA_FSM_CTL, 0x00 },
645 { WSA883X_PA_FSM_TIMER0, 0x80 },
646 { WSA883X_PA_FSM_TIMER1, 0x80 },
647 { WSA883X_PA_FSM_STA, 0x00 },
648 { WSA883X_PA_FSM_ERR_COND, 0x00 },
649 { WSA883X_PA_FSM_MSK, 0x00 },
650 { WSA883X_PA_FSM_BYP, 0x01 },
651 { WSA883X_PA_FSM_DBG, 0x00 },
652 { WSA883X_TADC_VALUE_CTL, 0x03 },
653 { WSA883X_TEMP_DETECT_CTL, 0x01 },
654 { WSA883X_TEMP_MSB, 0x00 },
655 { WSA883X_TEMP_LSB, 0x00 },
656 { WSA883X_TEMP_CONFIG0, 0x00 },
657 { WSA883X_TEMP_CONFIG1, 0x00 },
658 { WSA883X_VBAT_ADC_FLT_CTL, 0x00 },
659 { WSA883X_VBAT_DIN_MSB, 0x00 },
660 { WSA883X_VBAT_DIN_LSB, 0x00 },
661 { WSA883X_VBAT_DOUT, 0x00 },
662 { WSA883X_SDM_PDM9_LSB, 0x00 },
663 { WSA883X_SDM_PDM9_MSB, 0x00 },
664 { WSA883X_CDC_RX_CTL, 0xFE },
665 { WSA883X_CDC_SPK_DSM_A1_0, 0x00 },
666 { WSA883X_CDC_SPK_DSM_A1_1, 0x01 },
667 { WSA883X_CDC_SPK_DSM_A2_0, 0x96 },
668 { WSA883X_CDC_SPK_DSM_A2_1, 0x09 },
669 { WSA883X_CDC_SPK_DSM_A3_0, 0xAB },
670 { WSA883X_CDC_SPK_DSM_A3_1, 0x05 },
671 { WSA883X_CDC_SPK_DSM_A4_0, 0x1C },
672 { WSA883X_CDC_SPK_DSM_A4_1, 0x02 },
673 { WSA883X_CDC_SPK_DSM_A5_0, 0x17 },
674 { WSA883X_CDC_SPK_DSM_A5_1, 0x02 },
675 { WSA883X_CDC_SPK_DSM_A6_0, 0xAA },
676 { WSA883X_CDC_SPK_DSM_A7_0, 0xE3 },
677 { WSA883X_CDC_SPK_DSM_C_0, 0x69 },
678 { WSA883X_CDC_SPK_DSM_C_1, 0x54 },
679 { WSA883X_CDC_SPK_DSM_C_2, 0x02 },
680 { WSA883X_CDC_SPK_DSM_C_3, 0x15 },
681 { WSA883X_CDC_SPK_DSM_R1, 0xA4 },
682 { WSA883X_CDC_SPK_DSM_R2, 0xB5 },
683 { WSA883X_CDC_SPK_DSM_R3, 0x86 },
684 { WSA883X_CDC_SPK_DSM_R4, 0x85 },
685 { WSA883X_CDC_SPK_DSM_R5, 0xAA },
686 { WSA883X_CDC_SPK_DSM_R6, 0xE2 },
687 { WSA883X_CDC_SPK_DSM_R7, 0x62 },
688 { WSA883X_CDC_SPK_GAIN_PDM_0, 0x00 },
689 { WSA883X_CDC_SPK_GAIN_PDM_1, 0xFC },
690 { WSA883X_CDC_SPK_GAIN_PDM_2, 0x05 },
691 { WSA883X_PDM_WD_CTL, 0x00 },
692 { WSA883X_DEM_BYPASS_DATA0, 0x00 },
693 { WSA883X_DEM_BYPASS_DATA1, 0x00 },
694 { WSA883X_DEM_BYPASS_DATA2, 0x00 },
695 { WSA883X_DEM_BYPASS_DATA3, 0x00 },
696 { WSA883X_WAVG_CTL, 0x06 },
697 { WSA883X_WAVG_LRA_PER_0, 0xD1 },
698 { WSA883X_WAVG_LRA_PER_1, 0x00 },
699 { WSA883X_WAVG_DELTA_THETA_0, 0xE6 },
700 { WSA883X_WAVG_DELTA_THETA_1, 0x04 },
701 { WSA883X_WAVG_DIRECT_AMP_0, 0x50 },
702 { WSA883X_WAVG_DIRECT_AMP_1, 0x00 },
703 { WSA883X_WAVG_PTRN_AMP0_0, 0x50 },
704 { WSA883X_WAVG_PTRN_AMP0_1, 0x00 },
705 { WSA883X_WAVG_PTRN_AMP1_0, 0x50 },
706 { WSA883X_WAVG_PTRN_AMP1_1, 0x00 },
707 { WSA883X_WAVG_PTRN_AMP2_0, 0x50 },
708 { WSA883X_WAVG_PTRN_AMP2_1, 0x00 },
709 { WSA883X_WAVG_PTRN_AMP3_0, 0x50 },
710 { WSA883X_WAVG_PTRN_AMP3_1, 0x00 },
711 { WSA883X_WAVG_PTRN_AMP4_0, 0x50 },
712 { WSA883X_WAVG_PTRN_AMP4_1, 0x00 },
713 { WSA883X_WAVG_PTRN_AMP5_0, 0x50 },
714 { WSA883X_WAVG_PTRN_AMP5_1, 0x00 },
715 { WSA883X_WAVG_PTRN_AMP6_0, 0x50 },
716 { WSA883X_WAVG_PTRN_AMP6_1, 0x00 },
717 { WSA883X_WAVG_PTRN_AMP7_0, 0x50 },
718 { WSA883X_WAVG_PTRN_AMP7_1, 0x00 },
719 { WSA883X_WAVG_PER_0_1, 0x88 },
720 { WSA883X_WAVG_PER_2_3, 0x88 },
721 { WSA883X_WAVG_PER_4_5, 0x88 },
722 { WSA883X_WAVG_PER_6_7, 0x88 },
723 { WSA883X_WAVG_STA, 0x00 },
724 { WSA883X_DRE_CTL_0, 0x70 },
725 { WSA883X_DRE_CTL_1, 0x08 },
726 { WSA883X_DRE_IDLE_DET_CTL, 0x1F },
727 { WSA883X_CLSH_CTL_0, 0x37 },
728 { WSA883X_CLSH_CTL_1, 0x81 },
729 { WSA883X_CLSH_V_HD_PA, 0x0F },
730 { WSA883X_CLSH_V_PA_MIN, 0x00 },
731 { WSA883X_CLSH_OVRD_VAL, 0x00 },
732 { WSA883X_CLSH_HARD_MAX, 0xFF },
733 { WSA883X_CLSH_SOFT_MAX, 0xF5 },
734 { WSA883X_CLSH_SIG_DP, 0x00 },
735 { WSA883X_TAGC_CTL, 0x10 },
736 { WSA883X_TAGC_TIME, 0x20 },
737 { WSA883X_TAGC_E2E_GAIN, 0x02 },
738 { WSA883X_TAGC_FORCE_VAL, 0x00 },
739 { WSA883X_VAGC_CTL, 0x00 },
740 { WSA883X_VAGC_TIME, 0x08 },
741 { WSA883X_VAGC_ATTN_LVL_1_2, 0x21 },
742 { WSA883X_VAGC_ATTN_LVL_3, 0x03 },
743 { WSA883X_INTR_MODE, 0x00 },
744 { WSA883X_INTR_MASK0, 0x90 },
745 { WSA883X_INTR_MASK1, 0x00 },
746 { WSA883X_INTR_STATUS0, 0x00 },
747 { WSA883X_INTR_STATUS1, 0x00 },
748 { WSA883X_INTR_CLEAR0, 0x00 },
749 { WSA883X_INTR_CLEAR1, 0x00 },
750 { WSA883X_INTR_LEVEL0, 0x00 },
751 { WSA883X_INTR_LEVEL1, 0x00 },
752 { WSA883X_INTR_SET0, 0x00 },
753 { WSA883X_INTR_SET1, 0x00 },
754 { WSA883X_INTR_TEST0, 0x00 },
755 { WSA883X_INTR_TEST1, 0x00 },
756 { WSA883X_OTP_CTRL0, 0x00 },
757 { WSA883X_OTP_CTRL1, 0x00 },
758 { WSA883X_HDRIVE_CTL_GROUP1, 0x00 },
759 { WSA883X_PIN_CTL, 0x04 },
760 { WSA883X_PIN_CTL_OE, 0x00 },
761 { WSA883X_PIN_WDATA_IOPAD, 0x00 },
762 { WSA883X_PIN_STATUS, 0x00 },
763 { WSA883X_I2C_SLAVE_CTL, 0x00 },
764 { WSA883X_PDM_TEST_MODE, 0x00 },
765 { WSA883X_ATE_TEST_MODE, 0x00 },
766 { WSA883X_DIG_DEBUG_MODE, 0x00 },
767 { WSA883X_DIG_DEBUG_SEL, 0x00 },
768 { WSA883X_DIG_DEBUG_EN, 0x00 },
769 { WSA883X_SWR_HM_TEST0, 0x08 },
770 { WSA883X_SWR_HM_TEST1, 0x00 },
771 { WSA883X_SWR_PAD_CTL, 0x37 },
772 { WSA883X_TADC_DETECT_DBG_CTL, 0x00 },
773 { WSA883X_TADC_DEBUG_MSB, 0x00 },
774 { WSA883X_TADC_DEBUG_LSB, 0x00 },
775 { WSA883X_SAMPLE_EDGE_SEL, 0x7F },
776 { WSA883X_SWR_EDGE_SEL, 0x00 },
777 { WSA883X_TEST_MODE_CTL, 0x04 },
778 { WSA883X_IOPAD_CTL, 0x00 },
779 { WSA883X_ANA_CSR_DBG_ADD, 0x00 },
780 { WSA883X_ANA_CSR_DBG_CTL, 0x12 },
781 { WSA883X_SPARE_R, 0x00 },
782 { WSA883X_SPARE_0, 0x00 },
783 { WSA883X_SPARE_1, 0x00 },
784 { WSA883X_SPARE_2, 0x00 },
785 { WSA883X_SCODE, 0x00 },
786 { WSA883X_OTP_REG_0, 0x05 },
787 { WSA883X_OTP_REG_1, 0xFF },
788 { WSA883X_OTP_REG_2, 0xC0 },
789 { WSA883X_OTP_REG_3, 0xFF },
790 { WSA883X_OTP_REG_4, 0xC0 },
791 { WSA883X_OTP_REG_5, 0xFF },
792 { WSA883X_OTP_REG_6, 0xFF },
793 { WSA883X_OTP_REG_7, 0xFF },
794 { WSA883X_OTP_REG_8, 0xFF },
795 { WSA883X_OTP_REG_9, 0xFF },
796 { WSA883X_OTP_REG_10, 0xFF },
797 { WSA883X_OTP_REG_11, 0xFF },
798 { WSA883X_OTP_REG_12, 0xFF },
799 { WSA883X_OTP_REG_13, 0xFF },
800 { WSA883X_OTP_REG_14, 0xFF },
801 { WSA883X_OTP_REG_15, 0xFF },
802 { WSA883X_OTP_REG_16, 0xFF },
803 { WSA883X_OTP_REG_17, 0xFF },
804 { WSA883X_OTP_REG_18, 0xFF },
805 { WSA883X_OTP_REG_19, 0xFF },
806 { WSA883X_OTP_REG_20, 0xFF },
807 { WSA883X_OTP_REG_21, 0xFF },
808 { WSA883X_OTP_REG_22, 0xFF },
809 { WSA883X_OTP_REG_23, 0xFF },
810 { WSA883X_OTP_REG_24, 0x37 },
811 { WSA883X_OTP_REG_25, 0x3F },
812 { WSA883X_OTP_REG_26, 0x03 },
813 { WSA883X_OTP_REG_27, 0x00 },
814 { WSA883X_OTP_REG_28, 0x00 },
815 { WSA883X_OTP_REG_29, 0x00 },
816 { WSA883X_OTP_REG_30, 0x00 },
817 { WSA883X_OTP_REG_31, 0x03 },
818 { WSA883X_OTP_REG_32, 0x00 },
819 { WSA883X_OTP_REG_33, 0xFF },
820 { WSA883X_OTP_REG_34, 0x00 },
821 { WSA883X_OTP_REG_35, 0x00 },
822 { WSA883X_OTP_REG_63, 0x40 },
823 { WSA883X_EMEM_0, 0x00 },
824 { WSA883X_EMEM_1, 0x00 },
825 { WSA883X_EMEM_2, 0x00 },
826 { WSA883X_EMEM_3, 0x00 },
827 { WSA883X_EMEM_4, 0x00 },
828 { WSA883X_EMEM_5, 0x00 },
829 { WSA883X_EMEM_6, 0x00 },
830 { WSA883X_EMEM_7, 0x00 },
831 { WSA883X_EMEM_8, 0x00 },
832 { WSA883X_EMEM_9, 0x00 },
833 { WSA883X_EMEM_10, 0x00 },
834 { WSA883X_EMEM_11, 0x00 },
835 { WSA883X_EMEM_12, 0x00 },
836 { WSA883X_EMEM_13, 0x00 },
837 { WSA883X_EMEM_14, 0x00 },
838 { WSA883X_EMEM_15, 0x00 },
839 { WSA883X_EMEM_16, 0x00 },
840 { WSA883X_EMEM_17, 0x00 },
841 { WSA883X_EMEM_18, 0x00 },
842 { WSA883X_EMEM_19, 0x00 },
843 { WSA883X_EMEM_20, 0x00 },
844 { WSA883X_EMEM_21, 0x00 },
845 { WSA883X_EMEM_22, 0x00 },
846 { WSA883X_EMEM_23, 0x00 },
847 { WSA883X_EMEM_24, 0x00 },
848 { WSA883X_EMEM_25, 0x00 },
849 { WSA883X_EMEM_26, 0x00 },
850 { WSA883X_EMEM_27, 0x00 },
851 { WSA883X_EMEM_28, 0x00 },
852 { WSA883X_EMEM_29, 0x00 },
853 { WSA883X_EMEM_30, 0x00 },
854 { WSA883X_EMEM_31, 0x00 },
855 { WSA883X_EMEM_32, 0x00 },
856 { WSA883X_EMEM_33, 0x00 },
857 { WSA883X_EMEM_34, 0x00 },
858 { WSA883X_EMEM_35, 0x00 },
859 { WSA883X_EMEM_36, 0x00 },
860 { WSA883X_EMEM_37, 0x00 },
861 { WSA883X_EMEM_38, 0x00 },
862 { WSA883X_EMEM_39, 0x00 },
863 { WSA883X_EMEM_40, 0x00 },
864 { WSA883X_EMEM_41, 0x00 },
865 { WSA883X_EMEM_42, 0x00 },
866 { WSA883X_EMEM_43, 0x00 },
867 { WSA883X_EMEM_44, 0x00 },
868 { WSA883X_EMEM_45, 0x00 },
869 { WSA883X_EMEM_46, 0x00 },
870 { WSA883X_EMEM_47, 0x00 },
871 { WSA883X_EMEM_48, 0x00 },
872 { WSA883X_EMEM_49, 0x00 },
873 { WSA883X_EMEM_50, 0x00 },
874 { WSA883X_EMEM_51, 0x00 },
875 { WSA883X_EMEM_52, 0x00 },
876 { WSA883X_EMEM_53, 0x00 },
877 { WSA883X_EMEM_54, 0x00 },
878 { WSA883X_EMEM_55, 0x00 },
879 { WSA883X_EMEM_56, 0x00 },
880 { WSA883X_EMEM_57, 0x00 },
881 { WSA883X_EMEM_58, 0x00 },
882 { WSA883X_EMEM_59, 0x00 },
883 { WSA883X_EMEM_60, 0x00 },
884 { WSA883X_EMEM_61, 0x00 },
885 { WSA883X_EMEM_62, 0x00 },
886 { WSA883X_EMEM_63, 0x00 },
887 };
888
wsa883x_readonly_register(struct device * dev,unsigned int reg)889 static bool wsa883x_readonly_register(struct device *dev, unsigned int reg)
890 {
891 switch (reg) {
892 case WSA883X_DOUT_MSB:
893 case WSA883X_DOUT_LSB:
894 case WSA883X_STATUS:
895 case WSA883X_PA_STATUS0:
896 case WSA883X_PA_STATUS1:
897 case WSA883X_PA_STATUS2:
898 case WSA883X_STATUS_0:
899 case WSA883X_STATUS_1:
900 case WSA883X_CHIP_ID0:
901 case WSA883X_CHIP_ID1:
902 case WSA883X_CHIP_ID2:
903 case WSA883X_CHIP_ID3:
904 case WSA883X_BUS_ID:
905 case WSA883X_PA_FSM_STA:
906 case WSA883X_PA_FSM_ERR_COND:
907 case WSA883X_TEMP_MSB:
908 case WSA883X_TEMP_LSB:
909 case WSA883X_VBAT_DIN_MSB:
910 case WSA883X_VBAT_DIN_LSB:
911 case WSA883X_VBAT_DOUT:
912 case WSA883X_SDM_PDM9_LSB:
913 case WSA883X_SDM_PDM9_MSB:
914 case WSA883X_WAVG_STA:
915 case WSA883X_INTR_STATUS0:
916 case WSA883X_INTR_STATUS1:
917 case WSA883X_OTP_CTRL1:
918 case WSA883X_PIN_STATUS:
919 case WSA883X_ATE_TEST_MODE:
920 case WSA883X_SWR_HM_TEST1:
921 case WSA883X_SPARE_R:
922 case WSA883X_OTP_REG_0:
923 return true;
924 }
925 return false;
926 }
927
wsa883x_writeable_register(struct device * dev,unsigned int reg)928 static bool wsa883x_writeable_register(struct device *dev, unsigned int reg)
929 {
930 return !wsa883x_readonly_register(dev, reg);
931 }
932
wsa883x_volatile_register(struct device * dev,unsigned int reg)933 static bool wsa883x_volatile_register(struct device *dev, unsigned int reg)
934 {
935 return wsa883x_readonly_register(dev, reg);
936 }
937
938 static struct regmap_config wsa883x_regmap_config = {
939 .reg_bits = 32,
940 .val_bits = 8,
941 .cache_type = REGCACHE_MAPLE,
942 .reg_defaults = wsa883x_defaults,
943 .max_register = WSA883X_MAX_REGISTER,
944 .num_reg_defaults = ARRAY_SIZE(wsa883x_defaults),
945 .volatile_reg = wsa883x_volatile_register,
946 .writeable_reg = wsa883x_writeable_register,
947 .reg_format_endian = REGMAP_ENDIAN_NATIVE,
948 .val_format_endian = REGMAP_ENDIAN_NATIVE,
949 .use_single_read = true,
950 };
951
952 static const struct reg_sequence reg_init[] = {
953 {WSA883X_PA_FSM_BYP, 0x00},
954 {WSA883X_ADC_6, 0x02},
955 {WSA883X_CDC_SPK_DSM_A2_0, 0x0A},
956 {WSA883X_CDC_SPK_DSM_A2_1, 0x08},
957 {WSA883X_CDC_SPK_DSM_A3_0, 0xF3},
958 {WSA883X_CDC_SPK_DSM_A3_1, 0x07},
959 {WSA883X_CDC_SPK_DSM_A4_0, 0x79},
960 {WSA883X_CDC_SPK_DSM_A4_1, 0x02},
961 {WSA883X_CDC_SPK_DSM_A5_0, 0x0B},
962 {WSA883X_CDC_SPK_DSM_A5_1, 0x02},
963 {WSA883X_CDC_SPK_DSM_A6_0, 0x8A},
964 {WSA883X_CDC_SPK_DSM_A7_0, 0x9B},
965 {WSA883X_CDC_SPK_DSM_C_0, 0x68},
966 {WSA883X_CDC_SPK_DSM_C_1, 0x54},
967 {WSA883X_CDC_SPK_DSM_C_2, 0xF2},
968 {WSA883X_CDC_SPK_DSM_C_3, 0x20},
969 {WSA883X_CDC_SPK_DSM_R1, 0x83},
970 {WSA883X_CDC_SPK_DSM_R2, 0x7F},
971 {WSA883X_CDC_SPK_DSM_R3, 0x9D},
972 {WSA883X_CDC_SPK_DSM_R4, 0x82},
973 {WSA883X_CDC_SPK_DSM_R5, 0x8B},
974 {WSA883X_CDC_SPK_DSM_R6, 0x9B},
975 {WSA883X_CDC_SPK_DSM_R7, 0x3F},
976 {WSA883X_VBAT_SNS, 0x20},
977 {WSA883X_DRE_CTL_0, 0x92},
978 {WSA883X_DRE_IDLE_DET_CTL, 0x0F},
979 {WSA883X_CURRENT_LIMIT, 0xC4},
980 {WSA883X_VAGC_TIME, 0x0F},
981 {WSA883X_VAGC_ATTN_LVL_1_2, 0x00},
982 {WSA883X_VAGC_ATTN_LVL_3, 0x01},
983 {WSA883X_VAGC_CTL, 0x01},
984 {WSA883X_TAGC_CTL, 0x1A},
985 {WSA883X_TAGC_TIME, 0x2C},
986 {WSA883X_TEMP_CONFIG0, 0x02},
987 {WSA883X_TEMP_CONFIG1, 0x02},
988 {WSA883X_OTP_REG_1, 0x49},
989 {WSA883X_OTP_REG_2, 0x80},
990 {WSA883X_OTP_REG_3, 0xC9},
991 {WSA883X_OTP_REG_4, 0x40},
992 {WSA883X_TAGC_CTL, 0x1B},
993 {WSA883X_ADC_2, 0x00},
994 {WSA883X_ADC_7, 0x85},
995 {WSA883X_ADC_7, 0x87},
996 {WSA883X_CKWD_CTL_0, 0x14},
997 {WSA883X_CKWD_CTL_1, 0x1B},
998 {WSA883X_GMAMP_SUP1, 0xE2},
999 };
1000
wsa883x_init(struct wsa883x_priv * wsa883x)1001 static void wsa883x_init(struct wsa883x_priv *wsa883x)
1002 {
1003 struct regmap *regmap = wsa883x->regmap;
1004 int variant, version;
1005
1006 regmap_read(regmap, WSA883X_OTP_REG_0, &variant);
1007 wsa883x->variant = variant & WSA883X_ID_MASK;
1008
1009 regmap_read(regmap, WSA883X_CHIP_ID0, &version);
1010 wsa883x->version = version;
1011
1012 switch (wsa883x->variant) {
1013 case WSA8830:
1014 dev_info(wsa883x->dev, "WSA883X Version 1_%d, Variant: WSA8830\n",
1015 wsa883x->version);
1016 break;
1017 case WSA8835:
1018 dev_info(wsa883x->dev, "WSA883X Version 1_%d, Variant: WSA8835\n",
1019 wsa883x->version);
1020 break;
1021 case WSA8832:
1022 dev_info(wsa883x->dev, "WSA883X Version 1_%d, Variant: WSA8832\n",
1023 wsa883x->version);
1024 break;
1025 case WSA8835_V2:
1026 dev_info(wsa883x->dev, "WSA883X Version 1_%d, Variant: WSA8835_V2\n",
1027 wsa883x->version);
1028 break;
1029 default:
1030 break;
1031 }
1032
1033 wsa883x->comp_offset = COMP_OFFSET2;
1034
1035 /* Initial settings */
1036 regmap_multi_reg_write(regmap, reg_init, ARRAY_SIZE(reg_init));
1037
1038 if (wsa883x->variant == WSA8830 || wsa883x->variant == WSA8832) {
1039 wsa883x->comp_offset = COMP_OFFSET3;
1040 regmap_update_bits(regmap, WSA883X_DRE_CTL_0,
1041 WSA883X_DRE_OFFSET_MASK,
1042 wsa883x->comp_offset);
1043 }
1044 }
1045
wsa883x_update_status(struct sdw_slave * slave,enum sdw_slave_status status)1046 static int wsa883x_update_status(struct sdw_slave *slave,
1047 enum sdw_slave_status status)
1048 {
1049 struct wsa883x_priv *wsa883x = dev_get_drvdata(&slave->dev);
1050
1051 if (status == SDW_SLAVE_ATTACHED && slave->dev_num > 0)
1052 wsa883x_init(wsa883x);
1053
1054 return 0;
1055 }
1056
wsa883x_port_prep(struct sdw_slave * slave,struct sdw_prepare_ch * prepare_ch,enum sdw_port_prep_ops state)1057 static int wsa883x_port_prep(struct sdw_slave *slave,
1058 struct sdw_prepare_ch *prepare_ch,
1059 enum sdw_port_prep_ops state)
1060 {
1061 struct wsa883x_priv *wsa883x = dev_get_drvdata(&slave->dev);
1062
1063 if (state == SDW_OPS_PORT_POST_PREP)
1064 wsa883x->port_prepared[prepare_ch->num - 1] = true;
1065 else
1066 wsa883x->port_prepared[prepare_ch->num - 1] = false;
1067
1068 return 0;
1069 }
1070
1071 static const struct sdw_slave_ops wsa883x_slave_ops = {
1072 .update_status = wsa883x_update_status,
1073 .port_prep = wsa883x_port_prep,
1074 };
1075
wsa_dev_mode_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1076 static int wsa_dev_mode_get(struct snd_kcontrol *kcontrol,
1077 struct snd_ctl_elem_value *ucontrol)
1078 {
1079 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1080 struct wsa883x_priv *wsa883x = snd_soc_component_get_drvdata(component);
1081
1082 ucontrol->value.enumerated.item[0] = wsa883x->dev_mode;
1083
1084 return 0;
1085 }
1086
wsa_dev_mode_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1087 static int wsa_dev_mode_put(struct snd_kcontrol *kcontrol,
1088 struct snd_ctl_elem_value *ucontrol)
1089 {
1090 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1091 struct wsa883x_priv *wsa883x = snd_soc_component_get_drvdata(component);
1092
1093 if (wsa883x->dev_mode == ucontrol->value.enumerated.item[0])
1094 return 0;
1095
1096 wsa883x->dev_mode = ucontrol->value.enumerated.item[0];
1097
1098 return 1;
1099 }
1100
1101 static const DECLARE_TLV_DB_SCALE(pa_gain, -300, 150, -300);
1102
wsa883x_get_swr_port(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1103 static int wsa883x_get_swr_port(struct snd_kcontrol *kcontrol,
1104 struct snd_ctl_elem_value *ucontrol)
1105 {
1106 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
1107 struct wsa883x_priv *data = snd_soc_component_get_drvdata(comp);
1108 struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value;
1109 int portidx = mixer->reg;
1110
1111 ucontrol->value.integer.value[0] = data->port_enable[portidx];
1112
1113 return 0;
1114 }
1115
wsa883x_set_swr_port(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1116 static int wsa883x_set_swr_port(struct snd_kcontrol *kcontrol,
1117 struct snd_ctl_elem_value *ucontrol)
1118 {
1119 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
1120 struct wsa883x_priv *data = snd_soc_component_get_drvdata(comp);
1121 struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value;
1122 int portidx = mixer->reg;
1123
1124 if (ucontrol->value.integer.value[0]) {
1125 if (data->port_enable[portidx])
1126 return 0;
1127
1128 data->port_enable[portidx] = true;
1129 } else {
1130 if (!data->port_enable[portidx])
1131 return 0;
1132
1133 data->port_enable[portidx] = false;
1134 }
1135
1136 return 1;
1137 }
1138
wsa883x_get_comp_offset(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1139 static int wsa883x_get_comp_offset(struct snd_kcontrol *kcontrol,
1140 struct snd_ctl_elem_value *ucontrol)
1141 {
1142 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1143 struct wsa883x_priv *wsa883x = snd_soc_component_get_drvdata(component);
1144
1145 ucontrol->value.integer.value[0] = wsa883x->comp_offset;
1146
1147 return 0;
1148 }
1149
wsa883x_set_comp_offset(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1150 static int wsa883x_set_comp_offset(struct snd_kcontrol *kcontrol,
1151 struct snd_ctl_elem_value *ucontrol)
1152 {
1153 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1154 struct wsa883x_priv *wsa883x = snd_soc_component_get_drvdata(component);
1155
1156 if (wsa883x->comp_offset == ucontrol->value.integer.value[0])
1157 return 0;
1158
1159 wsa883x->comp_offset = ucontrol->value.integer.value[0];
1160
1161 return 1;
1162 }
1163
wsa883x_codec_probe(struct snd_soc_component * comp)1164 static int wsa883x_codec_probe(struct snd_soc_component *comp)
1165 {
1166 struct wsa883x_priv *wsa883x = snd_soc_component_get_drvdata(comp);
1167
1168 snd_soc_component_init_regmap(comp, wsa883x->regmap);
1169
1170 return 0;
1171 }
1172
wsa883x_spkr_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1173 static int wsa883x_spkr_event(struct snd_soc_dapm_widget *w,
1174 struct snd_kcontrol *kcontrol, int event)
1175 {
1176 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1177 struct wsa883x_priv *wsa883x = snd_soc_component_get_drvdata(component);
1178
1179 switch (event) {
1180 case SND_SOC_DAPM_POST_PMU:
1181 switch (wsa883x->dev_mode) {
1182 case RECEIVER:
1183 snd_soc_component_write_field(component, WSA883X_CDC_PATH_MODE,
1184 WSA883X_RXD_MODE_MASK,
1185 WSA883X_RXD_MODE_HIFI);
1186 snd_soc_component_write_field(component, WSA883X_SPKR_PWM_CLK_CTL,
1187 WSA883X_SPKR_PWM_FREQ_SEL_MASK,
1188 WSA883X_SPKR_PWM_FREQ_F600KHZ);
1189 snd_soc_component_write_field(component, WSA883X_DRE_CTL_0,
1190 WSA883X_DRE_PROG_DELAY_MASK, 0x0);
1191 break;
1192 case SPEAKER:
1193 snd_soc_component_write_field(component, WSA883X_CDC_PATH_MODE,
1194 WSA883X_RXD_MODE_MASK,
1195 WSA883X_RXD_MODE_NORMAL);
1196 snd_soc_component_write_field(component, WSA883X_SPKR_PWM_CLK_CTL,
1197 WSA883X_SPKR_PWM_FREQ_SEL_MASK,
1198 WSA883X_SPKR_PWM_FREQ_F300KHZ);
1199 snd_soc_component_write_field(component, WSA883X_DRE_CTL_0,
1200 WSA883X_DRE_PROG_DELAY_MASK, 0x9);
1201 break;
1202 default:
1203 break;
1204 }
1205
1206 snd_soc_component_write_field(component, WSA883X_DRE_CTL_1,
1207 WSA883X_DRE_GAIN_EN_MASK,
1208 WSA883X_DRE_GAIN_FROM_CSR);
1209 if (wsa883x->port_enable[WSA883X_PORT_COMP])
1210 snd_soc_component_write_field(component, WSA883X_DRE_CTL_0,
1211 WSA883X_DRE_OFFSET_MASK,
1212 wsa883x->comp_offset);
1213 snd_soc_component_write_field(component, WSA883X_VBAT_ADC_FLT_CTL,
1214 WSA883X_VBAT_ADC_COEF_SEL_MASK,
1215 WSA883X_VBAT_ADC_COEF_F_1DIV16);
1216 snd_soc_component_write_field(component, WSA883X_VBAT_ADC_FLT_CTL,
1217 WSA883X_VBAT_ADC_FLT_EN_MASK, 0x1);
1218 snd_soc_component_write_field(component, WSA883X_PDM_WD_CTL,
1219 WSA883X_PDM_EN_MASK,
1220 WSA883X_PDM_ENABLE);
1221 snd_soc_component_write_field(component, WSA883X_PA_FSM_CTL,
1222 WSA883X_GLOBAL_PA_EN_MASK,
1223 WSA883X_GLOBAL_PA_ENABLE);
1224
1225 break;
1226 case SND_SOC_DAPM_PRE_PMD:
1227 snd_soc_component_write_field(component, WSA883X_VBAT_ADC_FLT_CTL,
1228 WSA883X_VBAT_ADC_FLT_EN_MASK, 0x0);
1229 snd_soc_component_write_field(component, WSA883X_VBAT_ADC_FLT_CTL,
1230 WSA883X_VBAT_ADC_COEF_SEL_MASK,
1231 WSA883X_VBAT_ADC_COEF_F_1DIV2);
1232 snd_soc_component_write_field(component, WSA883X_PA_FSM_CTL,
1233 WSA883X_GLOBAL_PA_EN_MASK, 0);
1234 snd_soc_component_write_field(component, WSA883X_PDM_WD_CTL,
1235 WSA883X_PDM_EN_MASK, 0);
1236 break;
1237 }
1238 return 0;
1239 }
1240
1241 static const struct snd_soc_dapm_widget wsa883x_dapm_widgets[] = {
1242 SND_SOC_DAPM_INPUT("IN"),
1243 SND_SOC_DAPM_SPK("SPKR", wsa883x_spkr_event),
1244 };
1245
1246 static const struct snd_kcontrol_new wsa883x_snd_controls[] = {
1247 SOC_SINGLE_RANGE_TLV("PA Volume", WSA883X_DRE_CTL_1, 1,
1248 0x0, 0x1f, 1, pa_gain),
1249 SOC_ENUM_EXT("WSA MODE", wsa_dev_mode_enum,
1250 wsa_dev_mode_get, wsa_dev_mode_put),
1251 SOC_SINGLE_EXT("COMP Offset", SND_SOC_NOPM, 0, 4, 0,
1252 wsa883x_get_comp_offset, wsa883x_set_comp_offset),
1253 SOC_SINGLE_EXT("DAC Switch", WSA883X_PORT_DAC, 0, 1, 0,
1254 wsa883x_get_swr_port, wsa883x_set_swr_port),
1255 SOC_SINGLE_EXT("COMP Switch", WSA883X_PORT_COMP, 0, 1, 0,
1256 wsa883x_get_swr_port, wsa883x_set_swr_port),
1257 SOC_SINGLE_EXT("BOOST Switch", WSA883X_PORT_BOOST, 0, 1, 0,
1258 wsa883x_get_swr_port, wsa883x_set_swr_port),
1259 SOC_SINGLE_EXT("VISENSE Switch", WSA883X_PORT_VISENSE, 0, 1, 0,
1260 wsa883x_get_swr_port, wsa883x_set_swr_port),
1261 };
1262
1263 static const struct snd_soc_dapm_route wsa883x_audio_map[] = {
1264 {"SPKR", NULL, "IN"},
1265 };
1266
1267 static const struct snd_soc_component_driver wsa883x_component_drv = {
1268 .name = "WSA883x",
1269 .probe = wsa883x_codec_probe,
1270 .controls = wsa883x_snd_controls,
1271 .num_controls = ARRAY_SIZE(wsa883x_snd_controls),
1272 .dapm_widgets = wsa883x_dapm_widgets,
1273 .num_dapm_widgets = ARRAY_SIZE(wsa883x_dapm_widgets),
1274 .dapm_routes = wsa883x_audio_map,
1275 .num_dapm_routes = ARRAY_SIZE(wsa883x_audio_map),
1276 };
1277
wsa883x_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)1278 static int wsa883x_hw_params(struct snd_pcm_substream *substream,
1279 struct snd_pcm_hw_params *params,
1280 struct snd_soc_dai *dai)
1281 {
1282 struct wsa883x_priv *wsa883x = dev_get_drvdata(dai->dev);
1283 int i;
1284
1285 wsa883x->active_ports = 0;
1286 for (i = 0; i < WSA883X_MAX_SWR_PORTS; i++) {
1287 if (!wsa883x->port_enable[i])
1288 continue;
1289
1290 wsa883x->port_config[wsa883x->active_ports] = wsa883x_pconfig[i];
1291 wsa883x->active_ports++;
1292 }
1293
1294 wsa883x->sconfig.frame_rate = params_rate(params);
1295
1296 return sdw_stream_add_slave(wsa883x->slave, &wsa883x->sconfig,
1297 wsa883x->port_config, wsa883x->active_ports,
1298 wsa883x->sruntime);
1299 }
1300
wsa883x_hw_free(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)1301 static int wsa883x_hw_free(struct snd_pcm_substream *substream,
1302 struct snd_soc_dai *dai)
1303 {
1304 struct wsa883x_priv *wsa883x = dev_get_drvdata(dai->dev);
1305
1306 sdw_stream_remove_slave(wsa883x->slave, wsa883x->sruntime);
1307
1308 return 0;
1309 }
1310
wsa883x_set_sdw_stream(struct snd_soc_dai * dai,void * stream,int direction)1311 static int wsa883x_set_sdw_stream(struct snd_soc_dai *dai,
1312 void *stream, int direction)
1313 {
1314 struct wsa883x_priv *wsa883x = dev_get_drvdata(dai->dev);
1315
1316 wsa883x->sruntime = stream;
1317
1318 return 0;
1319 }
1320
wsa883x_digital_mute(struct snd_soc_dai * dai,int mute,int stream)1321 static int wsa883x_digital_mute(struct snd_soc_dai *dai, int mute, int stream)
1322 {
1323 struct snd_soc_component *component = dai->component;
1324
1325 if (mute) {
1326 snd_soc_component_write_field(component, WSA883X_DRE_CTL_1,
1327 WSA883X_DRE_GAIN_EN_MASK, 0);
1328 snd_soc_component_write_field(component, WSA883X_PA_FSM_CTL,
1329 WSA883X_GLOBAL_PA_EN_MASK, 0);
1330
1331 } else {
1332 snd_soc_component_write_field(component, WSA883X_DRE_CTL_1,
1333 WSA883X_DRE_GAIN_EN_MASK,
1334 WSA883X_DRE_GAIN_FROM_CSR);
1335 snd_soc_component_write_field(component, WSA883X_PA_FSM_CTL,
1336 WSA883X_GLOBAL_PA_EN_MASK,
1337 WSA883X_GLOBAL_PA_ENABLE);
1338
1339 }
1340
1341 return 0;
1342 }
1343
1344 static const struct snd_soc_dai_ops wsa883x_dai_ops = {
1345 .hw_params = wsa883x_hw_params,
1346 .hw_free = wsa883x_hw_free,
1347 .mute_stream = wsa883x_digital_mute,
1348 .set_stream = wsa883x_set_sdw_stream,
1349 };
1350
1351 static struct snd_soc_dai_driver wsa883x_dais[] = {
1352 {
1353 .name = "SPKR",
1354 .playback = {
1355 .stream_name = "SPKR Playback",
1356 .rates = WSA883X_RATES | WSA883X_FRAC_RATES,
1357 .formats = WSA883X_FORMATS,
1358 .rate_min = 8000,
1359 .rate_max = 352800,
1360 .channels_min = 1,
1361 .channels_max = 1,
1362 },
1363 .ops = &wsa883x_dai_ops,
1364 },
1365 };
1366
wsa883x_probe(struct sdw_slave * pdev,const struct sdw_device_id * id)1367 static int wsa883x_probe(struct sdw_slave *pdev,
1368 const struct sdw_device_id *id)
1369 {
1370 struct wsa883x_priv *wsa883x;
1371 struct device *dev = &pdev->dev;
1372 int ret;
1373
1374 wsa883x = devm_kzalloc(dev, sizeof(*wsa883x), GFP_KERNEL);
1375 if (!wsa883x)
1376 return -ENOMEM;
1377
1378 wsa883x->vdd = devm_regulator_get(dev, "vdd");
1379 if (IS_ERR(wsa883x->vdd))
1380 return dev_err_probe(dev, PTR_ERR(wsa883x->vdd),
1381 "No vdd regulator found\n");
1382
1383 ret = regulator_enable(wsa883x->vdd);
1384 if (ret)
1385 return dev_err_probe(dev, ret, "Failed to enable vdd regulator\n");
1386
1387 wsa883x->sd_n = devm_gpiod_get_optional(dev, "powerdown",
1388 GPIOD_FLAGS_BIT_NONEXCLUSIVE | GPIOD_OUT_HIGH);
1389 if (IS_ERR(wsa883x->sd_n)) {
1390 ret = dev_err_probe(dev, PTR_ERR(wsa883x->sd_n),
1391 "Shutdown Control GPIO not found\n");
1392 goto err;
1393 }
1394
1395 dev_set_drvdata(dev, wsa883x);
1396 wsa883x->slave = pdev;
1397 wsa883x->dev = dev;
1398 wsa883x->sconfig.ch_count = 1;
1399 wsa883x->sconfig.bps = 1;
1400 wsa883x->sconfig.direction = SDW_DATA_DIR_RX;
1401 wsa883x->sconfig.type = SDW_STREAM_PDM;
1402
1403 pdev->prop.sink_ports = GENMASK(WSA883X_MAX_SWR_PORTS, 0);
1404 pdev->prop.simple_clk_stop_capable = true;
1405 pdev->prop.sink_dpn_prop = wsa_sink_dpn_prop;
1406 pdev->prop.scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
1407 gpiod_direction_output(wsa883x->sd_n, 0);
1408
1409 wsa883x->regmap = devm_regmap_init_sdw(pdev, &wsa883x_regmap_config);
1410 if (IS_ERR(wsa883x->regmap)) {
1411 gpiod_direction_output(wsa883x->sd_n, 1);
1412 ret = dev_err_probe(dev, PTR_ERR(wsa883x->regmap),
1413 "regmap_init failed\n");
1414 goto err;
1415 }
1416 pm_runtime_set_autosuspend_delay(dev, 3000);
1417 pm_runtime_use_autosuspend(dev);
1418 pm_runtime_mark_last_busy(dev);
1419 pm_runtime_set_active(dev);
1420 pm_runtime_enable(dev);
1421
1422 ret = devm_snd_soc_register_component(dev,
1423 &wsa883x_component_drv,
1424 wsa883x_dais,
1425 ARRAY_SIZE(wsa883x_dais));
1426 err:
1427 if (ret)
1428 regulator_disable(wsa883x->vdd);
1429
1430 return ret;
1431
1432 }
1433
wsa883x_runtime_suspend(struct device * dev)1434 static int __maybe_unused wsa883x_runtime_suspend(struct device *dev)
1435 {
1436 struct regmap *regmap = dev_get_regmap(dev, NULL);
1437
1438 regcache_cache_only(regmap, true);
1439 regcache_mark_dirty(regmap);
1440
1441 return 0;
1442 }
1443
wsa883x_runtime_resume(struct device * dev)1444 static int __maybe_unused wsa883x_runtime_resume(struct device *dev)
1445 {
1446 struct regmap *regmap = dev_get_regmap(dev, NULL);
1447
1448 regcache_cache_only(regmap, false);
1449 regcache_sync(regmap);
1450
1451 return 0;
1452 }
1453
1454 static const struct dev_pm_ops wsa883x_pm_ops = {
1455 SET_RUNTIME_PM_OPS(wsa883x_runtime_suspend, wsa883x_runtime_resume, NULL)
1456 };
1457
1458 static const struct sdw_device_id wsa883x_swr_id[] = {
1459 SDW_SLAVE_ENTRY(0x0217, 0x0202, 0),
1460 {},
1461 };
1462
1463 MODULE_DEVICE_TABLE(sdw, wsa883x_swr_id);
1464
1465 static struct sdw_driver wsa883x_codec_driver = {
1466 .driver = {
1467 .name = "wsa883x-codec",
1468 .pm = &wsa883x_pm_ops,
1469 .suppress_bind_attrs = true,
1470 },
1471 .probe = wsa883x_probe,
1472 .ops = &wsa883x_slave_ops,
1473 .id_table = wsa883x_swr_id,
1474 };
1475
1476 module_sdw_driver(wsa883x_codec_driver);
1477
1478 MODULE_DESCRIPTION("WSA883x codec driver");
1479 MODULE_LICENSE("GPL");
1480
