1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
3
4 #include <linux/module.h>
5 #include <linux/init.h>
6 #include <linux/clk.h>
7 #include <linux/io.h>
8 #include <linux/platform_device.h>
9 #include <linux/pm_runtime.h>
10 #include <linux/regmap.h>
11 #include <sound/soc.h>
12 #include <sound/soc-dapm.h>
13 #include <sound/tlv.h>
14 #include <linux/of_clk.h>
15 #include <linux/clk-provider.h>
16
17 #include "lpass-macro-common.h"
18
19 #define CDC_TX_CLK_RST_CTRL_MCLK_CONTROL (0x0000)
20 #define CDC_TX_MCLK_EN_MASK BIT(0)
21 #define CDC_TX_MCLK_ENABLE BIT(0)
22 #define CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL (0x0004)
23 #define CDC_TX_FS_CNT_EN_MASK BIT(0)
24 #define CDC_TX_FS_CNT_ENABLE BIT(0)
25 #define CDC_TX_CLK_RST_CTRL_SWR_CONTROL (0x0008)
26 #define CDC_TX_SWR_RESET_MASK BIT(1)
27 #define CDC_TX_SWR_RESET_ENABLE BIT(1)
28 #define CDC_TX_SWR_CLK_EN_MASK BIT(0)
29 #define CDC_TX_SWR_CLK_ENABLE BIT(0)
30 #define CDC_TX_TOP_CSR_TOP_CFG0 (0x0080)
31 #define CDC_TX_TOP_CSR_ANC_CFG (0x0084)
32 #define CDC_TX_TOP_CSR_SWR_CTRL (0x0088)
33 #define CDC_TX_TOP_CSR_FREQ_MCLK (0x0090)
34 #define CDC_TX_TOP_CSR_DEBUG_BUS (0x0094)
35 #define CDC_TX_TOP_CSR_DEBUG_EN (0x0098)
36 #define CDC_TX_TOP_CSR_TX_I2S_CTL (0x00A4)
37 #define CDC_TX_TOP_CSR_I2S_CLK (0x00A8)
38 #define CDC_TX_TOP_CSR_I2S_RESET (0x00AC)
39 #define CDC_TX_TOP_CSR_SWR_DMICn_CTL(n) (0x00C0 + n * 0x4)
40 #define CDC_TX_TOP_CSR_SWR_DMIC0_CTL (0x00C0)
41 #define CDC_TX_SWR_DMIC_CLK_SEL_MASK GENMASK(3, 1)
42 #define CDC_TX_TOP_CSR_SWR_DMIC1_CTL (0x00C4)
43 #define CDC_TX_TOP_CSR_SWR_DMIC2_CTL (0x00C8)
44 #define CDC_TX_TOP_CSR_SWR_DMIC3_CTL (0x00CC)
45 #define CDC_TX_TOP_CSR_SWR_AMIC0_CTL (0x00D0)
46 #define CDC_TX_TOP_CSR_SWR_AMIC1_CTL (0x00D4)
47 #define CDC_TX_INP_MUX_ADC_MUXn_CFG0(n) (0x0100 + 0x8 * n)
48 #define CDC_TX_MACRO_SWR_MIC_MUX_SEL_MASK GENMASK(3, 0)
49 #define CDC_TX_INP_MUX_ADC_MUX0_CFG0 (0x0100)
50 #define CDC_TX_INP_MUX_ADC_MUXn_CFG1(n) (0x0104 + 0x8 * n)
51 #define CDC_TX_INP_MUX_ADC_MUX0_CFG1 (0x0104)
52 #define CDC_TX_INP_MUX_ADC_MUX1_CFG0 (0x0108)
53 #define CDC_TX_INP_MUX_ADC_MUX1_CFG1 (0x010C)
54 #define CDC_TX_INP_MUX_ADC_MUX2_CFG0 (0x0110)
55 #define CDC_TX_INP_MUX_ADC_MUX2_CFG1 (0x0114)
56 #define CDC_TX_INP_MUX_ADC_MUX3_CFG0 (0x0118)
57 #define CDC_TX_INP_MUX_ADC_MUX3_CFG1 (0x011C)
58 #define CDC_TX_INP_MUX_ADC_MUX4_CFG0 (0x0120)
59 #define CDC_TX_INP_MUX_ADC_MUX4_CFG1 (0x0124)
60 #define CDC_TX_INP_MUX_ADC_MUX5_CFG0 (0x0128)
61 #define CDC_TX_INP_MUX_ADC_MUX5_CFG1 (0x012C)
62 #define CDC_TX_INP_MUX_ADC_MUX6_CFG0 (0x0130)
63 #define CDC_TX_INP_MUX_ADC_MUX6_CFG1 (0x0134)
64 #define CDC_TX_INP_MUX_ADC_MUX7_CFG0 (0x0138)
65 #define CDC_TX_INP_MUX_ADC_MUX7_CFG1 (0x013C)
66 #define CDC_TX_ANC0_CLK_RESET_CTL (0x0200)
67 #define CDC_TX_ANC0_MODE_1_CTL (0x0204)
68 #define CDC_TX_ANC0_MODE_2_CTL (0x0208)
69 #define CDC_TX_ANC0_FF_SHIFT (0x020C)
70 #define CDC_TX_ANC0_FB_SHIFT (0x0210)
71 #define CDC_TX_ANC0_LPF_FF_A_CTL (0x0214)
72 #define CDC_TX_ANC0_LPF_FF_B_CTL (0x0218)
73 #define CDC_TX_ANC0_LPF_FB_CTL (0x021C)
74 #define CDC_TX_ANC0_SMLPF_CTL (0x0220)
75 #define CDC_TX_ANC0_DCFLT_SHIFT_CTL (0x0224)
76 #define CDC_TX_ANC0_IIR_ADAPT_CTL (0x0228)
77 #define CDC_TX_ANC0_IIR_COEFF_1_CTL (0x022C)
78 #define CDC_TX_ANC0_IIR_COEFF_2_CTL (0x0230)
79 #define CDC_TX_ANC0_FF_A_GAIN_CTL (0x0234)
80 #define CDC_TX_ANC0_FF_B_GAIN_CTL (0x0238)
81 #define CDC_TX_ANC0_FB_GAIN_CTL (0x023C)
82 #define CDC_TXn_TX_PATH_CTL(n) (0x0400 + 0x80 * n)
83 #define CDC_TXn_PCM_RATE_MASK GENMASK(3, 0)
84 #define CDC_TXn_PGA_MUTE_MASK BIT(4)
85 #define CDC_TXn_CLK_EN_MASK BIT(5)
86 #define CDC_TX0_TX_PATH_CTL (0x0400)
87 #define CDC_TXn_TX_PATH_CFG0(n) (0x0404 + 0x80 * n)
88 #define CDC_TX0_TX_PATH_CFG0 (0x0404)
89 #define CDC_TXn_PH_EN_MASK BIT(0)
90 #define CDC_TXn_ADC_MODE_MASK GENMASK(2, 1)
91 #define CDC_TXn_HPF_CUT_FREQ_MASK GENMASK(6, 5)
92 #define CDC_TXn_ADC_DMIC_SEL_MASK BIT(7)
93 #define CDC_TX0_TX_PATH_CFG1 (0x0408)
94 #define CDC_TXn_TX_VOL_CTL(n) (0x040C + 0x80 * n)
95 #define CDC_TX0_TX_VOL_CTL (0x040C)
96 #define CDC_TX0_TX_PATH_SEC0 (0x0410)
97 #define CDC_TX0_TX_PATH_SEC1 (0x0414)
98 #define CDC_TXn_TX_PATH_SEC2(n) (0x0418 + 0x80 * n)
99 #define CDC_TXn_HPF_F_CHANGE_MASK BIT(1)
100 #define CDC_TXn_HPF_ZERO_GATE_MASK BIT(0)
101 #define CDC_TX0_TX_PATH_SEC2 (0x0418)
102 #define CDC_TX0_TX_PATH_SEC3 (0x041C)
103 #define CDC_TX0_TX_PATH_SEC4 (0x0420)
104 #define CDC_TX0_TX_PATH_SEC5 (0x0424)
105 #define CDC_TX0_TX_PATH_SEC6 (0x0428)
106 #define CDC_TX0_TX_PATH_SEC7 (0x042C)
107 #define CDC_TX0_MBHC_CTL_EN_MASK BIT(6)
108 #define CDC_TX1_TX_PATH_CTL (0x0480)
109 #define CDC_TX1_TX_PATH_CFG0 (0x0484)
110 #define CDC_TX1_TX_PATH_CFG1 (0x0488)
111 #define CDC_TX1_TX_VOL_CTL (0x048C)
112 #define CDC_TX1_TX_PATH_SEC0 (0x0490)
113 #define CDC_TX1_TX_PATH_SEC1 (0x0494)
114 #define CDC_TX1_TX_PATH_SEC2 (0x0498)
115 #define CDC_TX1_TX_PATH_SEC3 (0x049C)
116 #define CDC_TX1_TX_PATH_SEC4 (0x04A0)
117 #define CDC_TX1_TX_PATH_SEC5 (0x04A4)
118 #define CDC_TX1_TX_PATH_SEC6 (0x04A8)
119 #define CDC_TX2_TX_PATH_CTL (0x0500)
120 #define CDC_TX2_TX_PATH_CFG0 (0x0504)
121 #define CDC_TX2_TX_PATH_CFG1 (0x0508)
122 #define CDC_TX2_TX_VOL_CTL (0x050C)
123 #define CDC_TX2_TX_PATH_SEC0 (0x0510)
124 #define CDC_TX2_TX_PATH_SEC1 (0x0514)
125 #define CDC_TX2_TX_PATH_SEC2 (0x0518)
126 #define CDC_TX2_TX_PATH_SEC3 (0x051C)
127 #define CDC_TX2_TX_PATH_SEC4 (0x0520)
128 #define CDC_TX2_TX_PATH_SEC5 (0x0524)
129 #define CDC_TX2_TX_PATH_SEC6 (0x0528)
130 #define CDC_TX3_TX_PATH_CTL (0x0580)
131 #define CDC_TX3_TX_PATH_CFG0 (0x0584)
132 #define CDC_TX3_TX_PATH_CFG1 (0x0588)
133 #define CDC_TX3_TX_VOL_CTL (0x058C)
134 #define CDC_TX3_TX_PATH_SEC0 (0x0590)
135 #define CDC_TX3_TX_PATH_SEC1 (0x0594)
136 #define CDC_TX3_TX_PATH_SEC2 (0x0598)
137 #define CDC_TX3_TX_PATH_SEC3 (0x059C)
138 #define CDC_TX3_TX_PATH_SEC4 (0x05A0)
139 #define CDC_TX3_TX_PATH_SEC5 (0x05A4)
140 #define CDC_TX3_TX_PATH_SEC6 (0x05A8)
141 #define CDC_TX4_TX_PATH_CTL (0x0600)
142 #define CDC_TX4_TX_PATH_CFG0 (0x0604)
143 #define CDC_TX4_TX_PATH_CFG1 (0x0608)
144 #define CDC_TX4_TX_VOL_CTL (0x060C)
145 #define CDC_TX4_TX_PATH_SEC0 (0x0610)
146 #define CDC_TX4_TX_PATH_SEC1 (0x0614)
147 #define CDC_TX4_TX_PATH_SEC2 (0x0618)
148 #define CDC_TX4_TX_PATH_SEC3 (0x061C)
149 #define CDC_TX4_TX_PATH_SEC4 (0x0620)
150 #define CDC_TX4_TX_PATH_SEC5 (0x0624)
151 #define CDC_TX4_TX_PATH_SEC6 (0x0628)
152 #define CDC_TX5_TX_PATH_CTL (0x0680)
153 #define CDC_TX5_TX_PATH_CFG0 (0x0684)
154 #define CDC_TX5_TX_PATH_CFG1 (0x0688)
155 #define CDC_TX5_TX_VOL_CTL (0x068C)
156 #define CDC_TX5_TX_PATH_SEC0 (0x0690)
157 #define CDC_TX5_TX_PATH_SEC1 (0x0694)
158 #define CDC_TX5_TX_PATH_SEC2 (0x0698)
159 #define CDC_TX5_TX_PATH_SEC3 (0x069C)
160 #define CDC_TX5_TX_PATH_SEC4 (0x06A0)
161 #define CDC_TX5_TX_PATH_SEC5 (0x06A4)
162 #define CDC_TX5_TX_PATH_SEC6 (0x06A8)
163 #define CDC_TX6_TX_PATH_CTL (0x0700)
164 #define CDC_TX6_TX_PATH_CFG0 (0x0704)
165 #define CDC_TX6_TX_PATH_CFG1 (0x0708)
166 #define CDC_TX6_TX_VOL_CTL (0x070C)
167 #define CDC_TX6_TX_PATH_SEC0 (0x0710)
168 #define CDC_TX6_TX_PATH_SEC1 (0x0714)
169 #define CDC_TX6_TX_PATH_SEC2 (0x0718)
170 #define CDC_TX6_TX_PATH_SEC3 (0x071C)
171 #define CDC_TX6_TX_PATH_SEC4 (0x0720)
172 #define CDC_TX6_TX_PATH_SEC5 (0x0724)
173 #define CDC_TX6_TX_PATH_SEC6 (0x0728)
174 #define CDC_TX7_TX_PATH_CTL (0x0780)
175 #define CDC_TX7_TX_PATH_CFG0 (0x0784)
176 #define CDC_TX7_TX_PATH_CFG1 (0x0788)
177 #define CDC_TX7_TX_VOL_CTL (0x078C)
178 #define CDC_TX7_TX_PATH_SEC0 (0x0790)
179 #define CDC_TX7_TX_PATH_SEC1 (0x0794)
180 #define CDC_TX7_TX_PATH_SEC2 (0x0798)
181 #define CDC_TX7_TX_PATH_SEC3 (0x079C)
182 #define CDC_TX7_TX_PATH_SEC4 (0x07A0)
183 #define CDC_TX7_TX_PATH_SEC5 (0x07A4)
184 #define CDC_TX7_TX_PATH_SEC6 (0x07A8)
185 #define TX_MAX_OFFSET (0x07A8)
186
187 #define TX_MACRO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
188 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
189 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
190 #define TX_MACRO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
191 SNDRV_PCM_FMTBIT_S24_LE |\
192 SNDRV_PCM_FMTBIT_S24_3LE)
193
194 #define CF_MIN_3DB_4HZ 0x0
195 #define CF_MIN_3DB_75HZ 0x1
196 #define CF_MIN_3DB_150HZ 0x2
197 #define TX_ADC_MAX 5
198 #define TX_ADC_TO_DMIC(n) ((n - TX_ADC_MAX)/2)
199 #define NUM_DECIMATORS 8
200 #define TX_NUM_CLKS_MAX 5
201 #define TX_MACRO_DMIC_UNMUTE_DELAY_MS 40
202 #define TX_MACRO_AMIC_UNMUTE_DELAY_MS 100
203 #define TX_MACRO_DMIC_HPF_DELAY_MS 300
204 #define TX_MACRO_AMIC_HPF_DELAY_MS 300
205 #define MCLK_FREQ 9600000
206
207 enum {
208 TX_MACRO_AIF_INVALID = 0,
209 TX_MACRO_AIF1_CAP,
210 TX_MACRO_AIF2_CAP,
211 TX_MACRO_AIF3_CAP,
212 TX_MACRO_MAX_DAIS
213 };
214
215 enum {
216 TX_MACRO_DEC0,
217 TX_MACRO_DEC1,
218 TX_MACRO_DEC2,
219 TX_MACRO_DEC3,
220 TX_MACRO_DEC4,
221 TX_MACRO_DEC5,
222 TX_MACRO_DEC6,
223 TX_MACRO_DEC7,
224 TX_MACRO_DEC_MAX,
225 };
226
227 enum {
228 TX_MACRO_CLK_DIV_2,
229 TX_MACRO_CLK_DIV_3,
230 TX_MACRO_CLK_DIV_4,
231 TX_MACRO_CLK_DIV_6,
232 TX_MACRO_CLK_DIV_8,
233 TX_MACRO_CLK_DIV_16,
234 };
235
236 enum {
237 MSM_DMIC,
238 SWR_MIC,
239 ANC_FB_TUNE1
240 };
241
242 struct tx_mute_work {
243 struct tx_macro *tx;
244 u32 decimator;
245 struct delayed_work dwork;
246 };
247
248 struct hpf_work {
249 struct tx_macro *tx;
250 u8 decimator;
251 u8 hpf_cut_off_freq;
252 struct delayed_work dwork;
253 };
254
255 struct tx_macro {
256 struct device *dev;
257 struct snd_soc_component *component;
258 struct hpf_work tx_hpf_work[NUM_DECIMATORS];
259 struct tx_mute_work tx_mute_dwork[NUM_DECIMATORS];
260 unsigned long active_ch_mask[TX_MACRO_MAX_DAIS];
261 unsigned long active_ch_cnt[TX_MACRO_MAX_DAIS];
262 int active_decimator[TX_MACRO_MAX_DAIS];
263 struct regmap *regmap;
264 struct clk *mclk;
265 struct clk *npl;
266 struct clk *macro;
267 struct clk *dcodec;
268 struct clk *fsgen;
269 struct clk_hw hw;
270 bool dec_active[NUM_DECIMATORS];
271 int tx_mclk_users;
272 u16 dmic_clk_div;
273 bool bcs_enable;
274 int dec_mode[NUM_DECIMATORS];
275 struct lpass_macro *pds;
276 bool bcs_clk_en;
277 };
278 #define to_tx_macro(_hw) container_of(_hw, struct tx_macro, hw)
279
280 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
281
282 static struct reg_default tx_defaults[] = {
283 /* TX Macro */
284 { CDC_TX_CLK_RST_CTRL_MCLK_CONTROL, 0x00 },
285 { CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00 },
286 { CDC_TX_CLK_RST_CTRL_SWR_CONTROL, 0x00},
287 { CDC_TX_TOP_CSR_TOP_CFG0, 0x00},
288 { CDC_TX_TOP_CSR_ANC_CFG, 0x00},
289 { CDC_TX_TOP_CSR_SWR_CTRL, 0x00},
290 { CDC_TX_TOP_CSR_FREQ_MCLK, 0x00},
291 { CDC_TX_TOP_CSR_DEBUG_BUS, 0x00},
292 { CDC_TX_TOP_CSR_DEBUG_EN, 0x00},
293 { CDC_TX_TOP_CSR_TX_I2S_CTL, 0x0C},
294 { CDC_TX_TOP_CSR_I2S_CLK, 0x00},
295 { CDC_TX_TOP_CSR_I2S_RESET, 0x00},
296 { CDC_TX_TOP_CSR_SWR_DMIC0_CTL, 0x00},
297 { CDC_TX_TOP_CSR_SWR_DMIC1_CTL, 0x00},
298 { CDC_TX_TOP_CSR_SWR_DMIC2_CTL, 0x00},
299 { CDC_TX_TOP_CSR_SWR_DMIC3_CTL, 0x00},
300 { CDC_TX_TOP_CSR_SWR_AMIC0_CTL, 0x00},
301 { CDC_TX_TOP_CSR_SWR_AMIC1_CTL, 0x00},
302 { CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0x00},
303 { CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0x00},
304 { CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0x00},
305 { CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0x00},
306 { CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0x00},
307 { CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0x00},
308 { CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0x00},
309 { CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0x00},
310 { CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0x00},
311 { CDC_TX_INP_MUX_ADC_MUX4_CFG1, 0x00},
312 { CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0x00},
313 { CDC_TX_INP_MUX_ADC_MUX5_CFG1, 0x00},
314 { CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0x00},
315 { CDC_TX_INP_MUX_ADC_MUX6_CFG1, 0x00},
316 { CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0x00},
317 { CDC_TX_INP_MUX_ADC_MUX7_CFG1, 0x00},
318 { CDC_TX_ANC0_CLK_RESET_CTL, 0x00},
319 { CDC_TX_ANC0_MODE_1_CTL, 0x00},
320 { CDC_TX_ANC0_MODE_2_CTL, 0x00},
321 { CDC_TX_ANC0_FF_SHIFT, 0x00},
322 { CDC_TX_ANC0_FB_SHIFT, 0x00},
323 { CDC_TX_ANC0_LPF_FF_A_CTL, 0x00},
324 { CDC_TX_ANC0_LPF_FF_B_CTL, 0x00},
325 { CDC_TX_ANC0_LPF_FB_CTL, 0x00},
326 { CDC_TX_ANC0_SMLPF_CTL, 0x00},
327 { CDC_TX_ANC0_DCFLT_SHIFT_CTL, 0x00},
328 { CDC_TX_ANC0_IIR_ADAPT_CTL, 0x00},
329 { CDC_TX_ANC0_IIR_COEFF_1_CTL, 0x00},
330 { CDC_TX_ANC0_IIR_COEFF_2_CTL, 0x00},
331 { CDC_TX_ANC0_FF_A_GAIN_CTL, 0x00},
332 { CDC_TX_ANC0_FF_B_GAIN_CTL, 0x00},
333 { CDC_TX_ANC0_FB_GAIN_CTL, 0x00},
334 { CDC_TX0_TX_PATH_CTL, 0x04},
335 { CDC_TX0_TX_PATH_CFG0, 0x10},
336 { CDC_TX0_TX_PATH_CFG1, 0x0B},
337 { CDC_TX0_TX_VOL_CTL, 0x00},
338 { CDC_TX0_TX_PATH_SEC0, 0x00},
339 { CDC_TX0_TX_PATH_SEC1, 0x00},
340 { CDC_TX0_TX_PATH_SEC2, 0x01},
341 { CDC_TX0_TX_PATH_SEC3, 0x3C},
342 { CDC_TX0_TX_PATH_SEC4, 0x20},
343 { CDC_TX0_TX_PATH_SEC5, 0x00},
344 { CDC_TX0_TX_PATH_SEC6, 0x00},
345 { CDC_TX0_TX_PATH_SEC7, 0x25},
346 { CDC_TX1_TX_PATH_CTL, 0x04},
347 { CDC_TX1_TX_PATH_CFG0, 0x10},
348 { CDC_TX1_TX_PATH_CFG1, 0x0B},
349 { CDC_TX1_TX_VOL_CTL, 0x00},
350 { CDC_TX1_TX_PATH_SEC0, 0x00},
351 { CDC_TX1_TX_PATH_SEC1, 0x00},
352 { CDC_TX1_TX_PATH_SEC2, 0x01},
353 { CDC_TX1_TX_PATH_SEC3, 0x3C},
354 { CDC_TX1_TX_PATH_SEC4, 0x20},
355 { CDC_TX1_TX_PATH_SEC5, 0x00},
356 { CDC_TX1_TX_PATH_SEC6, 0x00},
357 { CDC_TX2_TX_PATH_CTL, 0x04},
358 { CDC_TX2_TX_PATH_CFG0, 0x10},
359 { CDC_TX2_TX_PATH_CFG1, 0x0B},
360 { CDC_TX2_TX_VOL_CTL, 0x00},
361 { CDC_TX2_TX_PATH_SEC0, 0x00},
362 { CDC_TX2_TX_PATH_SEC1, 0x00},
363 { CDC_TX2_TX_PATH_SEC2, 0x01},
364 { CDC_TX2_TX_PATH_SEC3, 0x3C},
365 { CDC_TX2_TX_PATH_SEC4, 0x20},
366 { CDC_TX2_TX_PATH_SEC5, 0x00},
367 { CDC_TX2_TX_PATH_SEC6, 0x00},
368 { CDC_TX3_TX_PATH_CTL, 0x04},
369 { CDC_TX3_TX_PATH_CFG0, 0x10},
370 { CDC_TX3_TX_PATH_CFG1, 0x0B},
371 { CDC_TX3_TX_VOL_CTL, 0x00},
372 { CDC_TX3_TX_PATH_SEC0, 0x00},
373 { CDC_TX3_TX_PATH_SEC1, 0x00},
374 { CDC_TX3_TX_PATH_SEC2, 0x01},
375 { CDC_TX3_TX_PATH_SEC3, 0x3C},
376 { CDC_TX3_TX_PATH_SEC4, 0x20},
377 { CDC_TX3_TX_PATH_SEC5, 0x00},
378 { CDC_TX3_TX_PATH_SEC6, 0x00},
379 { CDC_TX4_TX_PATH_CTL, 0x04},
380 { CDC_TX4_TX_PATH_CFG0, 0x10},
381 { CDC_TX4_TX_PATH_CFG1, 0x0B},
382 { CDC_TX4_TX_VOL_CTL, 0x00},
383 { CDC_TX4_TX_PATH_SEC0, 0x00},
384 { CDC_TX4_TX_PATH_SEC1, 0x00},
385 { CDC_TX4_TX_PATH_SEC2, 0x01},
386 { CDC_TX4_TX_PATH_SEC3, 0x3C},
387 { CDC_TX4_TX_PATH_SEC4, 0x20},
388 { CDC_TX4_TX_PATH_SEC5, 0x00},
389 { CDC_TX4_TX_PATH_SEC6, 0x00},
390 { CDC_TX5_TX_PATH_CTL, 0x04},
391 { CDC_TX5_TX_PATH_CFG0, 0x10},
392 { CDC_TX5_TX_PATH_CFG1, 0x0B},
393 { CDC_TX5_TX_VOL_CTL, 0x00},
394 { CDC_TX5_TX_PATH_SEC0, 0x00},
395 { CDC_TX5_TX_PATH_SEC1, 0x00},
396 { CDC_TX5_TX_PATH_SEC2, 0x01},
397 { CDC_TX5_TX_PATH_SEC3, 0x3C},
398 { CDC_TX5_TX_PATH_SEC4, 0x20},
399 { CDC_TX5_TX_PATH_SEC5, 0x00},
400 { CDC_TX5_TX_PATH_SEC6, 0x00},
401 { CDC_TX6_TX_PATH_CTL, 0x04},
402 { CDC_TX6_TX_PATH_CFG0, 0x10},
403 { CDC_TX6_TX_PATH_CFG1, 0x0B},
404 { CDC_TX6_TX_VOL_CTL, 0x00},
405 { CDC_TX6_TX_PATH_SEC0, 0x00},
406 { CDC_TX6_TX_PATH_SEC1, 0x00},
407 { CDC_TX6_TX_PATH_SEC2, 0x01},
408 { CDC_TX6_TX_PATH_SEC3, 0x3C},
409 { CDC_TX6_TX_PATH_SEC4, 0x20},
410 { CDC_TX6_TX_PATH_SEC5, 0x00},
411 { CDC_TX6_TX_PATH_SEC6, 0x00},
412 { CDC_TX7_TX_PATH_CTL, 0x04},
413 { CDC_TX7_TX_PATH_CFG0, 0x10},
414 { CDC_TX7_TX_PATH_CFG1, 0x0B},
415 { CDC_TX7_TX_VOL_CTL, 0x00},
416 { CDC_TX7_TX_PATH_SEC0, 0x00},
417 { CDC_TX7_TX_PATH_SEC1, 0x00},
418 { CDC_TX7_TX_PATH_SEC2, 0x01},
419 { CDC_TX7_TX_PATH_SEC3, 0x3C},
420 { CDC_TX7_TX_PATH_SEC4, 0x20},
421 { CDC_TX7_TX_PATH_SEC5, 0x00},
422 { CDC_TX7_TX_PATH_SEC6, 0x00},
423 };
424
tx_is_volatile_register(struct device * dev,unsigned int reg)425 static bool tx_is_volatile_register(struct device *dev, unsigned int reg)
426 {
427 /* Update volatile list for tx/tx macros */
428 switch (reg) {
429 case CDC_TX_TOP_CSR_SWR_DMIC0_CTL:
430 case CDC_TX_TOP_CSR_SWR_DMIC1_CTL:
431 case CDC_TX_TOP_CSR_SWR_DMIC2_CTL:
432 case CDC_TX_TOP_CSR_SWR_DMIC3_CTL:
433 return true;
434 }
435 return false;
436 }
437
tx_is_rw_register(struct device * dev,unsigned int reg)438 static bool tx_is_rw_register(struct device *dev, unsigned int reg)
439 {
440 switch (reg) {
441 case CDC_TX_CLK_RST_CTRL_MCLK_CONTROL:
442 case CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL:
443 case CDC_TX_CLK_RST_CTRL_SWR_CONTROL:
444 case CDC_TX_TOP_CSR_TOP_CFG0:
445 case CDC_TX_TOP_CSR_ANC_CFG:
446 case CDC_TX_TOP_CSR_SWR_CTRL:
447 case CDC_TX_TOP_CSR_FREQ_MCLK:
448 case CDC_TX_TOP_CSR_DEBUG_BUS:
449 case CDC_TX_TOP_CSR_DEBUG_EN:
450 case CDC_TX_TOP_CSR_TX_I2S_CTL:
451 case CDC_TX_TOP_CSR_I2S_CLK:
452 case CDC_TX_TOP_CSR_I2S_RESET:
453 case CDC_TX_TOP_CSR_SWR_DMIC0_CTL:
454 case CDC_TX_TOP_CSR_SWR_DMIC1_CTL:
455 case CDC_TX_TOP_CSR_SWR_DMIC2_CTL:
456 case CDC_TX_TOP_CSR_SWR_DMIC3_CTL:
457 case CDC_TX_TOP_CSR_SWR_AMIC0_CTL:
458 case CDC_TX_TOP_CSR_SWR_AMIC1_CTL:
459 case CDC_TX_ANC0_CLK_RESET_CTL:
460 case CDC_TX_ANC0_MODE_1_CTL:
461 case CDC_TX_ANC0_MODE_2_CTL:
462 case CDC_TX_ANC0_FF_SHIFT:
463 case CDC_TX_ANC0_FB_SHIFT:
464 case CDC_TX_ANC0_LPF_FF_A_CTL:
465 case CDC_TX_ANC0_LPF_FF_B_CTL:
466 case CDC_TX_ANC0_LPF_FB_CTL:
467 case CDC_TX_ANC0_SMLPF_CTL:
468 case CDC_TX_ANC0_DCFLT_SHIFT_CTL:
469 case CDC_TX_ANC0_IIR_ADAPT_CTL:
470 case CDC_TX_ANC0_IIR_COEFF_1_CTL:
471 case CDC_TX_ANC0_IIR_COEFF_2_CTL:
472 case CDC_TX_ANC0_FF_A_GAIN_CTL:
473 case CDC_TX_ANC0_FF_B_GAIN_CTL:
474 case CDC_TX_ANC0_FB_GAIN_CTL:
475 case CDC_TX_INP_MUX_ADC_MUX0_CFG0:
476 case CDC_TX_INP_MUX_ADC_MUX0_CFG1:
477 case CDC_TX_INP_MUX_ADC_MUX1_CFG0:
478 case CDC_TX_INP_MUX_ADC_MUX1_CFG1:
479 case CDC_TX_INP_MUX_ADC_MUX2_CFG0:
480 case CDC_TX_INP_MUX_ADC_MUX2_CFG1:
481 case CDC_TX_INP_MUX_ADC_MUX3_CFG0:
482 case CDC_TX_INP_MUX_ADC_MUX3_CFG1:
483 case CDC_TX_INP_MUX_ADC_MUX4_CFG0:
484 case CDC_TX_INP_MUX_ADC_MUX4_CFG1:
485 case CDC_TX_INP_MUX_ADC_MUX5_CFG0:
486 case CDC_TX_INP_MUX_ADC_MUX5_CFG1:
487 case CDC_TX_INP_MUX_ADC_MUX6_CFG0:
488 case CDC_TX_INP_MUX_ADC_MUX6_CFG1:
489 case CDC_TX_INP_MUX_ADC_MUX7_CFG0:
490 case CDC_TX_INP_MUX_ADC_MUX7_CFG1:
491 case CDC_TX0_TX_PATH_CTL:
492 case CDC_TX0_TX_PATH_CFG0:
493 case CDC_TX0_TX_PATH_CFG1:
494 case CDC_TX0_TX_VOL_CTL:
495 case CDC_TX0_TX_PATH_SEC0:
496 case CDC_TX0_TX_PATH_SEC1:
497 case CDC_TX0_TX_PATH_SEC2:
498 case CDC_TX0_TX_PATH_SEC3:
499 case CDC_TX0_TX_PATH_SEC4:
500 case CDC_TX0_TX_PATH_SEC5:
501 case CDC_TX0_TX_PATH_SEC6:
502 case CDC_TX0_TX_PATH_SEC7:
503 case CDC_TX1_TX_PATH_CTL:
504 case CDC_TX1_TX_PATH_CFG0:
505 case CDC_TX1_TX_PATH_CFG1:
506 case CDC_TX1_TX_VOL_CTL:
507 case CDC_TX1_TX_PATH_SEC0:
508 case CDC_TX1_TX_PATH_SEC1:
509 case CDC_TX1_TX_PATH_SEC2:
510 case CDC_TX1_TX_PATH_SEC3:
511 case CDC_TX1_TX_PATH_SEC4:
512 case CDC_TX1_TX_PATH_SEC5:
513 case CDC_TX1_TX_PATH_SEC6:
514 case CDC_TX2_TX_PATH_CTL:
515 case CDC_TX2_TX_PATH_CFG0:
516 case CDC_TX2_TX_PATH_CFG1:
517 case CDC_TX2_TX_VOL_CTL:
518 case CDC_TX2_TX_PATH_SEC0:
519 case CDC_TX2_TX_PATH_SEC1:
520 case CDC_TX2_TX_PATH_SEC2:
521 case CDC_TX2_TX_PATH_SEC3:
522 case CDC_TX2_TX_PATH_SEC4:
523 case CDC_TX2_TX_PATH_SEC5:
524 case CDC_TX2_TX_PATH_SEC6:
525 case CDC_TX3_TX_PATH_CTL:
526 case CDC_TX3_TX_PATH_CFG0:
527 case CDC_TX3_TX_PATH_CFG1:
528 case CDC_TX3_TX_VOL_CTL:
529 case CDC_TX3_TX_PATH_SEC0:
530 case CDC_TX3_TX_PATH_SEC1:
531 case CDC_TX3_TX_PATH_SEC2:
532 case CDC_TX3_TX_PATH_SEC3:
533 case CDC_TX3_TX_PATH_SEC4:
534 case CDC_TX3_TX_PATH_SEC5:
535 case CDC_TX3_TX_PATH_SEC6:
536 case CDC_TX4_TX_PATH_CTL:
537 case CDC_TX4_TX_PATH_CFG0:
538 case CDC_TX4_TX_PATH_CFG1:
539 case CDC_TX4_TX_VOL_CTL:
540 case CDC_TX4_TX_PATH_SEC0:
541 case CDC_TX4_TX_PATH_SEC1:
542 case CDC_TX4_TX_PATH_SEC2:
543 case CDC_TX4_TX_PATH_SEC3:
544 case CDC_TX4_TX_PATH_SEC4:
545 case CDC_TX4_TX_PATH_SEC5:
546 case CDC_TX4_TX_PATH_SEC6:
547 case CDC_TX5_TX_PATH_CTL:
548 case CDC_TX5_TX_PATH_CFG0:
549 case CDC_TX5_TX_PATH_CFG1:
550 case CDC_TX5_TX_VOL_CTL:
551 case CDC_TX5_TX_PATH_SEC0:
552 case CDC_TX5_TX_PATH_SEC1:
553 case CDC_TX5_TX_PATH_SEC2:
554 case CDC_TX5_TX_PATH_SEC3:
555 case CDC_TX5_TX_PATH_SEC4:
556 case CDC_TX5_TX_PATH_SEC5:
557 case CDC_TX5_TX_PATH_SEC6:
558 case CDC_TX6_TX_PATH_CTL:
559 case CDC_TX6_TX_PATH_CFG0:
560 case CDC_TX6_TX_PATH_CFG1:
561 case CDC_TX6_TX_VOL_CTL:
562 case CDC_TX6_TX_PATH_SEC0:
563 case CDC_TX6_TX_PATH_SEC1:
564 case CDC_TX6_TX_PATH_SEC2:
565 case CDC_TX6_TX_PATH_SEC3:
566 case CDC_TX6_TX_PATH_SEC4:
567 case CDC_TX6_TX_PATH_SEC5:
568 case CDC_TX6_TX_PATH_SEC6:
569 case CDC_TX7_TX_PATH_CTL:
570 case CDC_TX7_TX_PATH_CFG0:
571 case CDC_TX7_TX_PATH_CFG1:
572 case CDC_TX7_TX_VOL_CTL:
573 case CDC_TX7_TX_PATH_SEC0:
574 case CDC_TX7_TX_PATH_SEC1:
575 case CDC_TX7_TX_PATH_SEC2:
576 case CDC_TX7_TX_PATH_SEC3:
577 case CDC_TX7_TX_PATH_SEC4:
578 case CDC_TX7_TX_PATH_SEC5:
579 case CDC_TX7_TX_PATH_SEC6:
580 return true;
581 }
582
583 return false;
584 }
585
586 static const struct regmap_config tx_regmap_config = {
587 .name = "tx_macro",
588 .reg_bits = 16,
589 .val_bits = 32,
590 .reg_stride = 4,
591 .cache_type = REGCACHE_FLAT,
592 .max_register = TX_MAX_OFFSET,
593 .reg_defaults = tx_defaults,
594 .num_reg_defaults = ARRAY_SIZE(tx_defaults),
595 .writeable_reg = tx_is_rw_register,
596 .volatile_reg = tx_is_volatile_register,
597 .readable_reg = tx_is_rw_register,
598 };
599
tx_macro_mclk_enable(struct tx_macro * tx,bool mclk_enable)600 static int tx_macro_mclk_enable(struct tx_macro *tx,
601 bool mclk_enable)
602 {
603 struct regmap *regmap = tx->regmap;
604
605 if (mclk_enable) {
606 if (tx->tx_mclk_users == 0) {
607 /* 9.6MHz MCLK, set value 0x00 if other frequency */
608 regmap_update_bits(regmap, CDC_TX_TOP_CSR_FREQ_MCLK, 0x01, 0x01);
609 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_MCLK_CONTROL,
610 CDC_TX_MCLK_EN_MASK,
611 CDC_TX_MCLK_ENABLE);
612 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL,
613 CDC_TX_FS_CNT_EN_MASK,
614 CDC_TX_FS_CNT_ENABLE);
615 regcache_mark_dirty(regmap);
616 regcache_sync(regmap);
617 }
618 tx->tx_mclk_users++;
619 } else {
620 if (tx->tx_mclk_users <= 0) {
621 dev_err(tx->dev, "clock already disabled\n");
622 tx->tx_mclk_users = 0;
623 goto exit;
624 }
625 tx->tx_mclk_users--;
626 if (tx->tx_mclk_users == 0) {
627 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL,
628 CDC_TX_FS_CNT_EN_MASK, 0x0);
629 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_MCLK_CONTROL,
630 CDC_TX_MCLK_EN_MASK, 0x0);
631 }
632 }
633 exit:
634 return 0;
635 }
636
is_amic_enabled(struct snd_soc_component * component,int decimator)637 static bool is_amic_enabled(struct snd_soc_component *component, int decimator)
638 {
639 u16 adc_mux_reg, adc_reg, adc_n;
640
641 adc_mux_reg = CDC_TX_INP_MUX_ADC_MUXn_CFG1(decimator);
642
643 if (snd_soc_component_read(component, adc_mux_reg) & SWR_MIC) {
644 adc_reg = CDC_TX_INP_MUX_ADC_MUXn_CFG0(decimator);
645 adc_n = snd_soc_component_read_field(component, adc_reg,
646 CDC_TX_MACRO_SWR_MIC_MUX_SEL_MASK);
647 if (adc_n < TX_ADC_MAX)
648 return true;
649 }
650
651 return false;
652 }
653
tx_macro_tx_hpf_corner_freq_callback(struct work_struct * work)654 static void tx_macro_tx_hpf_corner_freq_callback(struct work_struct *work)
655 {
656 struct delayed_work *hpf_delayed_work;
657 struct hpf_work *hpf_work;
658 struct tx_macro *tx;
659 struct snd_soc_component *component;
660 u16 dec_cfg_reg, hpf_gate_reg;
661 u8 hpf_cut_off_freq;
662
663 hpf_delayed_work = to_delayed_work(work);
664 hpf_work = container_of(hpf_delayed_work, struct hpf_work, dwork);
665 tx = hpf_work->tx;
666 component = tx->component;
667 hpf_cut_off_freq = hpf_work->hpf_cut_off_freq;
668
669 dec_cfg_reg = CDC_TXn_TX_PATH_CFG0(hpf_work->decimator);
670 hpf_gate_reg = CDC_TXn_TX_PATH_SEC2(hpf_work->decimator);
671
672 if (is_amic_enabled(component, hpf_work->decimator)) {
673 snd_soc_component_write_field(component,
674 dec_cfg_reg,
675 CDC_TXn_HPF_CUT_FREQ_MASK,
676 hpf_cut_off_freq);
677 snd_soc_component_update_bits(component, hpf_gate_reg,
678 CDC_TXn_HPF_F_CHANGE_MASK |
679 CDC_TXn_HPF_ZERO_GATE_MASK,
680 0x02);
681 snd_soc_component_update_bits(component, hpf_gate_reg,
682 CDC_TXn_HPF_F_CHANGE_MASK |
683 CDC_TXn_HPF_ZERO_GATE_MASK,
684 0x01);
685 } else {
686 snd_soc_component_write_field(component, dec_cfg_reg,
687 CDC_TXn_HPF_CUT_FREQ_MASK,
688 hpf_cut_off_freq);
689 snd_soc_component_write_field(component, hpf_gate_reg,
690 CDC_TXn_HPF_F_CHANGE_MASK, 0x1);
691 /* Minimum 1 clk cycle delay is required as per HW spec */
692 usleep_range(1000, 1010);
693 snd_soc_component_write_field(component, hpf_gate_reg,
694 CDC_TXn_HPF_F_CHANGE_MASK, 0x0);
695 }
696 }
697
tx_macro_mute_update_callback(struct work_struct * work)698 static void tx_macro_mute_update_callback(struct work_struct *work)
699 {
700 struct tx_mute_work *tx_mute_dwork;
701 struct snd_soc_component *component;
702 struct tx_macro *tx;
703 struct delayed_work *delayed_work;
704 u8 decimator;
705
706 delayed_work = to_delayed_work(work);
707 tx_mute_dwork = container_of(delayed_work, struct tx_mute_work, dwork);
708 tx = tx_mute_dwork->tx;
709 component = tx->component;
710 decimator = tx_mute_dwork->decimator;
711
712 snd_soc_component_write_field(component, CDC_TXn_TX_PATH_CTL(decimator),
713 CDC_TXn_PGA_MUTE_MASK, 0x0);
714 }
715
tx_macro_mclk_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)716 static int tx_macro_mclk_event(struct snd_soc_dapm_widget *w,
717 struct snd_kcontrol *kcontrol, int event)
718 {
719 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
720 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
721
722 switch (event) {
723 case SND_SOC_DAPM_PRE_PMU:
724 tx_macro_mclk_enable(tx, true);
725 break;
726 case SND_SOC_DAPM_POST_PMD:
727 tx_macro_mclk_enable(tx, false);
728 break;
729 default:
730 break;
731 }
732
733 return 0;
734 }
735
tx_macro_put_dec_enum(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)736 static int tx_macro_put_dec_enum(struct snd_kcontrol *kcontrol,
737 struct snd_ctl_elem_value *ucontrol)
738 {
739 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol);
740 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm);
741 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
742 unsigned int val, dmic;
743 u16 mic_sel_reg;
744 u16 dmic_clk_reg;
745 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
746
747 val = ucontrol->value.enumerated.item[0];
748
749 switch (e->reg) {
750 case CDC_TX_INP_MUX_ADC_MUX0_CFG0:
751 mic_sel_reg = CDC_TX0_TX_PATH_CFG0;
752 break;
753 case CDC_TX_INP_MUX_ADC_MUX1_CFG0:
754 mic_sel_reg = CDC_TX1_TX_PATH_CFG0;
755 break;
756 case CDC_TX_INP_MUX_ADC_MUX2_CFG0:
757 mic_sel_reg = CDC_TX2_TX_PATH_CFG0;
758 break;
759 case CDC_TX_INP_MUX_ADC_MUX3_CFG0:
760 mic_sel_reg = CDC_TX3_TX_PATH_CFG0;
761 break;
762 case CDC_TX_INP_MUX_ADC_MUX4_CFG0:
763 mic_sel_reg = CDC_TX4_TX_PATH_CFG0;
764 break;
765 case CDC_TX_INP_MUX_ADC_MUX5_CFG0:
766 mic_sel_reg = CDC_TX5_TX_PATH_CFG0;
767 break;
768 case CDC_TX_INP_MUX_ADC_MUX6_CFG0:
769 mic_sel_reg = CDC_TX6_TX_PATH_CFG0;
770 break;
771 case CDC_TX_INP_MUX_ADC_MUX7_CFG0:
772 mic_sel_reg = CDC_TX7_TX_PATH_CFG0;
773 break;
774 }
775
776 if (val != 0) {
777 if (val < 5) {
778 snd_soc_component_write_field(component, mic_sel_reg,
779 CDC_TXn_ADC_DMIC_SEL_MASK, 0);
780 } else {
781 snd_soc_component_write_field(component, mic_sel_reg,
782 CDC_TXn_ADC_DMIC_SEL_MASK, 1);
783 dmic = TX_ADC_TO_DMIC(val);
784 dmic_clk_reg = CDC_TX_TOP_CSR_SWR_DMICn_CTL(dmic);
785 snd_soc_component_write_field(component, dmic_clk_reg,
786 CDC_TX_SWR_DMIC_CLK_SEL_MASK,
787 tx->dmic_clk_div);
788 }
789 }
790
791 return snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
792 }
793
tx_macro_tx_mixer_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)794 static int tx_macro_tx_mixer_get(struct snd_kcontrol *kcontrol,
795 struct snd_ctl_elem_value *ucontrol)
796 {
797 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol);
798 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm);
799 struct soc_mixer_control *mc = (struct soc_mixer_control *)kcontrol->private_value;
800 u32 dai_id = widget->shift;
801 u32 dec_id = mc->shift;
802 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
803
804 if (test_bit(dec_id, &tx->active_ch_mask[dai_id]))
805 ucontrol->value.integer.value[0] = 1;
806 else
807 ucontrol->value.integer.value[0] = 0;
808
809 return 0;
810 }
811
tx_macro_tx_mixer_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)812 static int tx_macro_tx_mixer_put(struct snd_kcontrol *kcontrol,
813 struct snd_ctl_elem_value *ucontrol)
814 {
815 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol);
816 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm);
817 struct snd_soc_dapm_update *update = NULL;
818 struct soc_mixer_control *mc = (struct soc_mixer_control *)kcontrol->private_value;
819 u32 dai_id = widget->shift;
820 u32 dec_id = mc->shift;
821 u32 enable = ucontrol->value.integer.value[0];
822 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
823
824 if (enable) {
825 if (tx->active_decimator[dai_id] == dec_id)
826 return 0;
827
828 set_bit(dec_id, &tx->active_ch_mask[dai_id]);
829 tx->active_ch_cnt[dai_id]++;
830 tx->active_decimator[dai_id] = dec_id;
831 } else {
832 if (tx->active_decimator[dai_id] == -1)
833 return 0;
834
835 tx->active_ch_cnt[dai_id]--;
836 clear_bit(dec_id, &tx->active_ch_mask[dai_id]);
837 tx->active_decimator[dai_id] = -1;
838 }
839 snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, enable, update);
840
841 return 1;
842 }
843
tx_macro_enable_dec(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)844 static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w,
845 struct snd_kcontrol *kcontrol, int event)
846 {
847 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
848 unsigned int decimator;
849 u16 tx_vol_ctl_reg, dec_cfg_reg, hpf_gate_reg, tx_gain_ctl_reg;
850 u8 hpf_cut_off_freq;
851 int hpf_delay = TX_MACRO_DMIC_HPF_DELAY_MS;
852 int unmute_delay = TX_MACRO_DMIC_UNMUTE_DELAY_MS;
853 u16 adc_mux_reg, adc_reg, adc_n, dmic;
854 u16 dmic_clk_reg;
855 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
856
857 decimator = w->shift;
858 tx_vol_ctl_reg = CDC_TXn_TX_PATH_CTL(decimator);
859 hpf_gate_reg = CDC_TXn_TX_PATH_SEC2(decimator);
860 dec_cfg_reg = CDC_TXn_TX_PATH_CFG0(decimator);
861 tx_gain_ctl_reg = CDC_TXn_TX_VOL_CTL(decimator);
862
863 switch (event) {
864 case SND_SOC_DAPM_PRE_PMU:
865 adc_mux_reg = CDC_TX_INP_MUX_ADC_MUXn_CFG1(decimator);
866 if (snd_soc_component_read(component, adc_mux_reg) & SWR_MIC) {
867 adc_reg = CDC_TX_INP_MUX_ADC_MUXn_CFG0(decimator);
868 adc_n = snd_soc_component_read(component, adc_reg) &
869 CDC_TX_MACRO_SWR_MIC_MUX_SEL_MASK;
870 if (adc_n >= TX_ADC_MAX) {
871 dmic = TX_ADC_TO_DMIC(adc_n);
872 dmic_clk_reg = CDC_TX_TOP_CSR_SWR_DMICn_CTL(dmic);
873
874 snd_soc_component_write_field(component, dmic_clk_reg,
875 CDC_TX_SWR_DMIC_CLK_SEL_MASK,
876 tx->dmic_clk_div);
877 }
878 }
879 snd_soc_component_write_field(component, dec_cfg_reg,
880 CDC_TXn_ADC_MODE_MASK,
881 tx->dec_mode[decimator]);
882 /* Enable TX PGA Mute */
883 snd_soc_component_write_field(component, tx_vol_ctl_reg,
884 CDC_TXn_PGA_MUTE_MASK, 0x1);
885 break;
886 case SND_SOC_DAPM_POST_PMU:
887 snd_soc_component_write_field(component, tx_vol_ctl_reg,
888 CDC_TXn_CLK_EN_MASK, 0x1);
889 if (!is_amic_enabled(component, decimator)) {
890 snd_soc_component_update_bits(component, hpf_gate_reg, 0x01, 0x00);
891 /* Minimum 1 clk cycle delay is required as per HW spec */
892 usleep_range(1000, 1010);
893 }
894 hpf_cut_off_freq = snd_soc_component_read_field(component, dec_cfg_reg,
895 CDC_TXn_HPF_CUT_FREQ_MASK);
896
897 tx->tx_hpf_work[decimator].hpf_cut_off_freq =
898 hpf_cut_off_freq;
899
900 if (hpf_cut_off_freq != CF_MIN_3DB_150HZ)
901 snd_soc_component_write_field(component, dec_cfg_reg,
902 CDC_TXn_HPF_CUT_FREQ_MASK,
903 CF_MIN_3DB_150HZ);
904
905 if (is_amic_enabled(component, decimator)) {
906 hpf_delay = TX_MACRO_AMIC_HPF_DELAY_MS;
907 unmute_delay = TX_MACRO_AMIC_UNMUTE_DELAY_MS;
908 }
909 /* schedule work queue to Remove Mute */
910 queue_delayed_work(system_freezable_wq,
911 &tx->tx_mute_dwork[decimator].dwork,
912 msecs_to_jiffies(unmute_delay));
913 if (tx->tx_hpf_work[decimator].hpf_cut_off_freq != CF_MIN_3DB_150HZ) {
914 queue_delayed_work(system_freezable_wq,
915 &tx->tx_hpf_work[decimator].dwork,
916 msecs_to_jiffies(hpf_delay));
917 snd_soc_component_update_bits(component, hpf_gate_reg,
918 CDC_TXn_HPF_F_CHANGE_MASK |
919 CDC_TXn_HPF_ZERO_GATE_MASK,
920 0x02);
921 if (!is_amic_enabled(component, decimator))
922 snd_soc_component_update_bits(component, hpf_gate_reg,
923 CDC_TXn_HPF_F_CHANGE_MASK |
924 CDC_TXn_HPF_ZERO_GATE_MASK,
925 0x00);
926 snd_soc_component_update_bits(component, hpf_gate_reg,
927 CDC_TXn_HPF_F_CHANGE_MASK |
928 CDC_TXn_HPF_ZERO_GATE_MASK,
929 0x01);
930
931 /*
932 * 6ms delay is required as per HW spec
933 */
934 usleep_range(6000, 6010);
935 }
936 /* apply gain after decimator is enabled */
937 snd_soc_component_write(component, tx_gain_ctl_reg,
938 snd_soc_component_read(component,
939 tx_gain_ctl_reg));
940 if (tx->bcs_enable) {
941 snd_soc_component_update_bits(component, dec_cfg_reg,
942 0x01, 0x01);
943 tx->bcs_clk_en = true;
944 }
945 break;
946 case SND_SOC_DAPM_PRE_PMD:
947 hpf_cut_off_freq =
948 tx->tx_hpf_work[decimator].hpf_cut_off_freq;
949 snd_soc_component_write_field(component, tx_vol_ctl_reg,
950 CDC_TXn_PGA_MUTE_MASK, 0x1);
951 if (cancel_delayed_work_sync(
952 &tx->tx_hpf_work[decimator].dwork)) {
953 if (hpf_cut_off_freq != CF_MIN_3DB_150HZ) {
954 snd_soc_component_write_field(
955 component, dec_cfg_reg,
956 CDC_TXn_HPF_CUT_FREQ_MASK,
957 hpf_cut_off_freq);
958 if (is_amic_enabled(component, decimator))
959 snd_soc_component_update_bits(component,
960 hpf_gate_reg,
961 CDC_TXn_HPF_F_CHANGE_MASK |
962 CDC_TXn_HPF_ZERO_GATE_MASK,
963 0x02);
964 else
965 snd_soc_component_update_bits(component,
966 hpf_gate_reg,
967 CDC_TXn_HPF_F_CHANGE_MASK |
968 CDC_TXn_HPF_ZERO_GATE_MASK,
969 0x03);
970
971 /*
972 * Minimum 1 clk cycle delay is required
973 * as per HW spec
974 */
975 usleep_range(1000, 1010);
976 snd_soc_component_update_bits(component, hpf_gate_reg,
977 CDC_TXn_HPF_F_CHANGE_MASK |
978 CDC_TXn_HPF_ZERO_GATE_MASK,
979 0x1);
980 }
981 }
982 cancel_delayed_work_sync(&tx->tx_mute_dwork[decimator].dwork);
983 break;
984 case SND_SOC_DAPM_POST_PMD:
985 snd_soc_component_write_field(component, tx_vol_ctl_reg,
986 CDC_TXn_CLK_EN_MASK, 0x0);
987 snd_soc_component_write_field(component, dec_cfg_reg,
988 CDC_TXn_ADC_MODE_MASK, 0x0);
989 snd_soc_component_write_field(component, tx_vol_ctl_reg,
990 CDC_TXn_PGA_MUTE_MASK, 0x0);
991 if (tx->bcs_enable) {
992 snd_soc_component_write_field(component, dec_cfg_reg,
993 CDC_TXn_PH_EN_MASK, 0x0);
994 snd_soc_component_write_field(component,
995 CDC_TX0_TX_PATH_SEC7,
996 CDC_TX0_MBHC_CTL_EN_MASK,
997 0x0);
998 tx->bcs_clk_en = false;
999 }
1000 break;
1001 }
1002 return 0;
1003 }
1004
tx_macro_dec_mode_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1005 static int tx_macro_dec_mode_get(struct snd_kcontrol *kcontrol,
1006 struct snd_ctl_elem_value *ucontrol)
1007 {
1008 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1009 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
1010 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1011 int path = e->shift_l;
1012
1013 ucontrol->value.integer.value[0] = tx->dec_mode[path];
1014
1015 return 0;
1016 }
1017
tx_macro_dec_mode_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1018 static int tx_macro_dec_mode_put(struct snd_kcontrol *kcontrol,
1019 struct snd_ctl_elem_value *ucontrol)
1020 {
1021 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1022 int value = ucontrol->value.integer.value[0];
1023 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1024 int path = e->shift_l;
1025 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
1026
1027 if (tx->dec_mode[path] == value)
1028 return 0;
1029
1030 tx->dec_mode[path] = value;
1031
1032 return 1;
1033 }
1034
tx_macro_get_bcs(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1035 static int tx_macro_get_bcs(struct snd_kcontrol *kcontrol,
1036 struct snd_ctl_elem_value *ucontrol)
1037 {
1038 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1039 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
1040
1041 ucontrol->value.integer.value[0] = tx->bcs_enable;
1042
1043 return 0;
1044 }
1045
tx_macro_set_bcs(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1046 static int tx_macro_set_bcs(struct snd_kcontrol *kcontrol,
1047 struct snd_ctl_elem_value *ucontrol)
1048 {
1049 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1050 int value = ucontrol->value.integer.value[0];
1051 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
1052
1053 tx->bcs_enable = value;
1054
1055 return 0;
1056 }
1057
tx_macro_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)1058 static int tx_macro_hw_params(struct snd_pcm_substream *substream,
1059 struct snd_pcm_hw_params *params,
1060 struct snd_soc_dai *dai)
1061 {
1062 struct snd_soc_component *component = dai->component;
1063 u32 decimator, sample_rate;
1064 int tx_fs_rate;
1065 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
1066
1067 sample_rate = params_rate(params);
1068 switch (sample_rate) {
1069 case 8000:
1070 tx_fs_rate = 0;
1071 break;
1072 case 16000:
1073 tx_fs_rate = 1;
1074 break;
1075 case 32000:
1076 tx_fs_rate = 3;
1077 break;
1078 case 48000:
1079 tx_fs_rate = 4;
1080 break;
1081 case 96000:
1082 tx_fs_rate = 5;
1083 break;
1084 case 192000:
1085 tx_fs_rate = 6;
1086 break;
1087 case 384000:
1088 tx_fs_rate = 7;
1089 break;
1090 default:
1091 dev_err(component->dev, "%s: Invalid TX sample rate: %d\n",
1092 __func__, params_rate(params));
1093 return -EINVAL;
1094 }
1095
1096 for_each_set_bit(decimator, &tx->active_ch_mask[dai->id], TX_MACRO_DEC_MAX)
1097 snd_soc_component_update_bits(component, CDC_TXn_TX_PATH_CTL(decimator),
1098 CDC_TXn_PCM_RATE_MASK,
1099 tx_fs_rate);
1100 return 0;
1101 }
1102
tx_macro_get_channel_map(struct snd_soc_dai * dai,unsigned int * tx_num,unsigned int * tx_slot,unsigned int * rx_num,unsigned int * rx_slot)1103 static int tx_macro_get_channel_map(struct snd_soc_dai *dai,
1104 unsigned int *tx_num, unsigned int *tx_slot,
1105 unsigned int *rx_num, unsigned int *rx_slot)
1106 {
1107 struct snd_soc_component *component = dai->component;
1108 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
1109
1110 switch (dai->id) {
1111 case TX_MACRO_AIF1_CAP:
1112 case TX_MACRO_AIF2_CAP:
1113 case TX_MACRO_AIF3_CAP:
1114 *tx_slot = tx->active_ch_mask[dai->id];
1115 *tx_num = tx->active_ch_cnt[dai->id];
1116 break;
1117 default:
1118 break;
1119 }
1120 return 0;
1121 }
1122
tx_macro_digital_mute(struct snd_soc_dai * dai,int mute,int stream)1123 static int tx_macro_digital_mute(struct snd_soc_dai *dai, int mute, int stream)
1124 {
1125 struct snd_soc_component *component = dai->component;
1126 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
1127 u16 decimator;
1128
1129 /* active decimator not set yet */
1130 if (tx->active_decimator[dai->id] == -1)
1131 return 0;
1132
1133 decimator = tx->active_decimator[dai->id];
1134
1135 if (mute)
1136 snd_soc_component_write_field(component,
1137 CDC_TXn_TX_PATH_CTL(decimator),
1138 CDC_TXn_PGA_MUTE_MASK, 0x1);
1139 else
1140 snd_soc_component_update_bits(component,
1141 CDC_TXn_TX_PATH_CTL(decimator),
1142 CDC_TXn_PGA_MUTE_MASK, 0x0);
1143
1144 return 0;
1145 }
1146
1147 static const struct snd_soc_dai_ops tx_macro_dai_ops = {
1148 .hw_params = tx_macro_hw_params,
1149 .get_channel_map = tx_macro_get_channel_map,
1150 .mute_stream = tx_macro_digital_mute,
1151 };
1152
1153 static struct snd_soc_dai_driver tx_macro_dai[] = {
1154 {
1155 .name = "tx_macro_tx1",
1156 .id = TX_MACRO_AIF1_CAP,
1157 .capture = {
1158 .stream_name = "TX_AIF1 Capture",
1159 .rates = TX_MACRO_RATES,
1160 .formats = TX_MACRO_FORMATS,
1161 .rate_max = 192000,
1162 .rate_min = 8000,
1163 .channels_min = 1,
1164 .channels_max = 8,
1165 },
1166 .ops = &tx_macro_dai_ops,
1167 },
1168 {
1169 .name = "tx_macro_tx2",
1170 .id = TX_MACRO_AIF2_CAP,
1171 .capture = {
1172 .stream_name = "TX_AIF2 Capture",
1173 .rates = TX_MACRO_RATES,
1174 .formats = TX_MACRO_FORMATS,
1175 .rate_max = 192000,
1176 .rate_min = 8000,
1177 .channels_min = 1,
1178 .channels_max = 8,
1179 },
1180 .ops = &tx_macro_dai_ops,
1181 },
1182 {
1183 .name = "tx_macro_tx3",
1184 .id = TX_MACRO_AIF3_CAP,
1185 .capture = {
1186 .stream_name = "TX_AIF3 Capture",
1187 .rates = TX_MACRO_RATES,
1188 .formats = TX_MACRO_FORMATS,
1189 .rate_max = 192000,
1190 .rate_min = 8000,
1191 .channels_min = 1,
1192 .channels_max = 8,
1193 },
1194 .ops = &tx_macro_dai_ops,
1195 },
1196 };
1197
1198 static const char * const adc_mux_text[] = {
1199 "MSM_DMIC", "SWR_MIC", "ANC_FB_TUNE1"
1200 };
1201
1202 static SOC_ENUM_SINGLE_DECL(tx_dec0_enum, CDC_TX_INP_MUX_ADC_MUX0_CFG1,
1203 0, adc_mux_text);
1204 static SOC_ENUM_SINGLE_DECL(tx_dec1_enum, CDC_TX_INP_MUX_ADC_MUX1_CFG1,
1205 0, adc_mux_text);
1206 static SOC_ENUM_SINGLE_DECL(tx_dec2_enum, CDC_TX_INP_MUX_ADC_MUX2_CFG1,
1207 0, adc_mux_text);
1208 static SOC_ENUM_SINGLE_DECL(tx_dec3_enum, CDC_TX_INP_MUX_ADC_MUX3_CFG1,
1209 0, adc_mux_text);
1210 static SOC_ENUM_SINGLE_DECL(tx_dec4_enum, CDC_TX_INP_MUX_ADC_MUX4_CFG1,
1211 0, adc_mux_text);
1212 static SOC_ENUM_SINGLE_DECL(tx_dec5_enum, CDC_TX_INP_MUX_ADC_MUX5_CFG1,
1213 0, adc_mux_text);
1214 static SOC_ENUM_SINGLE_DECL(tx_dec6_enum, CDC_TX_INP_MUX_ADC_MUX6_CFG1,
1215 0, adc_mux_text);
1216 static SOC_ENUM_SINGLE_DECL(tx_dec7_enum, CDC_TX_INP_MUX_ADC_MUX7_CFG1,
1217 0, adc_mux_text);
1218
1219 static const struct snd_kcontrol_new tx_dec0_mux = SOC_DAPM_ENUM("tx_dec0", tx_dec0_enum);
1220 static const struct snd_kcontrol_new tx_dec1_mux = SOC_DAPM_ENUM("tx_dec1", tx_dec1_enum);
1221 static const struct snd_kcontrol_new tx_dec2_mux = SOC_DAPM_ENUM("tx_dec2", tx_dec2_enum);
1222 static const struct snd_kcontrol_new tx_dec3_mux = SOC_DAPM_ENUM("tx_dec3", tx_dec3_enum);
1223 static const struct snd_kcontrol_new tx_dec4_mux = SOC_DAPM_ENUM("tx_dec4", tx_dec4_enum);
1224 static const struct snd_kcontrol_new tx_dec5_mux = SOC_DAPM_ENUM("tx_dec5", tx_dec5_enum);
1225 static const struct snd_kcontrol_new tx_dec6_mux = SOC_DAPM_ENUM("tx_dec6", tx_dec6_enum);
1226 static const struct snd_kcontrol_new tx_dec7_mux = SOC_DAPM_ENUM("tx_dec7", tx_dec7_enum);
1227
1228 static const char * const smic_mux_text[] = {
1229 "ZERO", "ADC0", "ADC1", "ADC2", "ADC3", "SWR_DMIC0",
1230 "SWR_DMIC1", "SWR_DMIC2", "SWR_DMIC3", "SWR_DMIC4",
1231 "SWR_DMIC5", "SWR_DMIC6", "SWR_DMIC7"
1232 };
1233
1234 static SOC_ENUM_SINGLE_DECL(tx_smic0_enum, CDC_TX_INP_MUX_ADC_MUX0_CFG0,
1235 0, smic_mux_text);
1236
1237 static SOC_ENUM_SINGLE_DECL(tx_smic1_enum, CDC_TX_INP_MUX_ADC_MUX1_CFG0,
1238 0, smic_mux_text);
1239
1240 static SOC_ENUM_SINGLE_DECL(tx_smic2_enum, CDC_TX_INP_MUX_ADC_MUX2_CFG0,
1241 0, smic_mux_text);
1242
1243 static SOC_ENUM_SINGLE_DECL(tx_smic3_enum, CDC_TX_INP_MUX_ADC_MUX3_CFG0,
1244 0, smic_mux_text);
1245
1246 static SOC_ENUM_SINGLE_DECL(tx_smic4_enum, CDC_TX_INP_MUX_ADC_MUX4_CFG0,
1247 0, smic_mux_text);
1248
1249 static SOC_ENUM_SINGLE_DECL(tx_smic5_enum, CDC_TX_INP_MUX_ADC_MUX5_CFG0,
1250 0, smic_mux_text);
1251
1252 static SOC_ENUM_SINGLE_DECL(tx_smic6_enum, CDC_TX_INP_MUX_ADC_MUX6_CFG0,
1253 0, smic_mux_text);
1254
1255 static SOC_ENUM_SINGLE_DECL(tx_smic7_enum, CDC_TX_INP_MUX_ADC_MUX7_CFG0,
1256 0, smic_mux_text);
1257
1258 static const struct snd_kcontrol_new tx_smic0_mux = SOC_DAPM_ENUM_EXT("tx_smic0", tx_smic0_enum,
1259 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1260 static const struct snd_kcontrol_new tx_smic1_mux = SOC_DAPM_ENUM_EXT("tx_smic1", tx_smic1_enum,
1261 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1262 static const struct snd_kcontrol_new tx_smic2_mux = SOC_DAPM_ENUM_EXT("tx_smic2", tx_smic2_enum,
1263 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1264 static const struct snd_kcontrol_new tx_smic3_mux = SOC_DAPM_ENUM_EXT("tx_smic3", tx_smic3_enum,
1265 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1266 static const struct snd_kcontrol_new tx_smic4_mux = SOC_DAPM_ENUM_EXT("tx_smic4", tx_smic4_enum,
1267 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1268 static const struct snd_kcontrol_new tx_smic5_mux = SOC_DAPM_ENUM_EXT("tx_smic5", tx_smic5_enum,
1269 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1270 static const struct snd_kcontrol_new tx_smic6_mux = SOC_DAPM_ENUM_EXT("tx_smic6", tx_smic6_enum,
1271 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1272 static const struct snd_kcontrol_new tx_smic7_mux = SOC_DAPM_ENUM_EXT("tx_smic7", tx_smic7_enum,
1273 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1274
1275 static const char * const dec_mode_mux_text[] = {
1276 "ADC_DEFAULT", "ADC_LOW_PWR", "ADC_HIGH_PERF",
1277 };
1278
1279 static const struct soc_enum dec_mode_mux_enum[] = {
1280 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(dec_mode_mux_text),
1281 dec_mode_mux_text),
1282 SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(dec_mode_mux_text),
1283 dec_mode_mux_text),
1284 SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(dec_mode_mux_text),
1285 dec_mode_mux_text),
1286 SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(dec_mode_mux_text),
1287 dec_mode_mux_text),
1288 SOC_ENUM_SINGLE(SND_SOC_NOPM, 4, ARRAY_SIZE(dec_mode_mux_text),
1289 dec_mode_mux_text),
1290 SOC_ENUM_SINGLE(SND_SOC_NOPM, 5, ARRAY_SIZE(dec_mode_mux_text),
1291 dec_mode_mux_text),
1292 SOC_ENUM_SINGLE(SND_SOC_NOPM, 6, ARRAY_SIZE(dec_mode_mux_text),
1293 dec_mode_mux_text),
1294 SOC_ENUM_SINGLE(SND_SOC_NOPM, 7, ARRAY_SIZE(dec_mode_mux_text),
1295 dec_mode_mux_text),
1296 };
1297
1298 static const struct snd_kcontrol_new tx_aif1_cap_mixer[] = {
1299 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, TX_MACRO_DEC0, 1, 0,
1300 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1301 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, TX_MACRO_DEC1, 1, 0,
1302 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1303 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, TX_MACRO_DEC2, 1, 0,
1304 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1305 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, TX_MACRO_DEC3, 1, 0,
1306 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1307 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, TX_MACRO_DEC4, 1, 0,
1308 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1309 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, TX_MACRO_DEC5, 1, 0,
1310 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1311 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, TX_MACRO_DEC6, 1, 0,
1312 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1313 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, TX_MACRO_DEC7, 1, 0,
1314 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1315 };
1316
1317 static const struct snd_kcontrol_new tx_aif2_cap_mixer[] = {
1318 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, TX_MACRO_DEC0, 1, 0,
1319 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1320 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, TX_MACRO_DEC1, 1, 0,
1321 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1322 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, TX_MACRO_DEC2, 1, 0,
1323 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1324 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, TX_MACRO_DEC3, 1, 0,
1325 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1326 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, TX_MACRO_DEC4, 1, 0,
1327 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1328 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, TX_MACRO_DEC5, 1, 0,
1329 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1330 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, TX_MACRO_DEC6, 1, 0,
1331 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1332 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, TX_MACRO_DEC7, 1, 0,
1333 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1334 };
1335
1336 static const struct snd_kcontrol_new tx_aif3_cap_mixer[] = {
1337 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, TX_MACRO_DEC0, 1, 0,
1338 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1339 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, TX_MACRO_DEC1, 1, 0,
1340 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1341 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, TX_MACRO_DEC2, 1, 0,
1342 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1343 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, TX_MACRO_DEC3, 1, 0,
1344 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1345 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, TX_MACRO_DEC4, 1, 0,
1346 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1347 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, TX_MACRO_DEC5, 1, 0,
1348 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1349 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, TX_MACRO_DEC6, 1, 0,
1350 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1351 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, TX_MACRO_DEC7, 1, 0,
1352 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1353 };
1354
1355 static const struct snd_soc_dapm_widget tx_macro_dapm_widgets[] = {
1356 SND_SOC_DAPM_AIF_OUT("TX_AIF1 CAP", "TX_AIF1 Capture", 0,
1357 SND_SOC_NOPM, TX_MACRO_AIF1_CAP, 0),
1358
1359 SND_SOC_DAPM_AIF_OUT("TX_AIF2 CAP", "TX_AIF2 Capture", 0,
1360 SND_SOC_NOPM, TX_MACRO_AIF2_CAP, 0),
1361
1362 SND_SOC_DAPM_AIF_OUT("TX_AIF3 CAP", "TX_AIF3 Capture", 0,
1363 SND_SOC_NOPM, TX_MACRO_AIF3_CAP, 0),
1364
1365 SND_SOC_DAPM_MIXER("TX_AIF1_CAP Mixer", SND_SOC_NOPM, TX_MACRO_AIF1_CAP, 0,
1366 tx_aif1_cap_mixer, ARRAY_SIZE(tx_aif1_cap_mixer)),
1367
1368 SND_SOC_DAPM_MIXER("TX_AIF2_CAP Mixer", SND_SOC_NOPM, TX_MACRO_AIF2_CAP, 0,
1369 tx_aif2_cap_mixer, ARRAY_SIZE(tx_aif2_cap_mixer)),
1370
1371 SND_SOC_DAPM_MIXER("TX_AIF3_CAP Mixer", SND_SOC_NOPM, TX_MACRO_AIF3_CAP, 0,
1372 tx_aif3_cap_mixer, ARRAY_SIZE(tx_aif3_cap_mixer)),
1373
1374 SND_SOC_DAPM_MUX("TX SMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_smic0_mux),
1375 SND_SOC_DAPM_MUX("TX SMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_smic1_mux),
1376 SND_SOC_DAPM_MUX("TX SMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_smic2_mux),
1377 SND_SOC_DAPM_MUX("TX SMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_smic3_mux),
1378 SND_SOC_DAPM_MUX("TX SMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_smic4_mux),
1379 SND_SOC_DAPM_MUX("TX SMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_smic5_mux),
1380 SND_SOC_DAPM_MUX("TX SMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_smic6_mux),
1381 SND_SOC_DAPM_MUX("TX SMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_smic7_mux),
1382
1383 SND_SOC_DAPM_INPUT("TX SWR_ADC0"),
1384 SND_SOC_DAPM_INPUT("TX SWR_ADC1"),
1385 SND_SOC_DAPM_INPUT("TX SWR_ADC2"),
1386 SND_SOC_DAPM_INPUT("TX SWR_ADC3"),
1387 SND_SOC_DAPM_INPUT("TX SWR_DMIC0"),
1388 SND_SOC_DAPM_INPUT("TX SWR_DMIC1"),
1389 SND_SOC_DAPM_INPUT("TX SWR_DMIC2"),
1390 SND_SOC_DAPM_INPUT("TX SWR_DMIC3"),
1391 SND_SOC_DAPM_INPUT("TX SWR_DMIC4"),
1392 SND_SOC_DAPM_INPUT("TX SWR_DMIC5"),
1393 SND_SOC_DAPM_INPUT("TX SWR_DMIC6"),
1394 SND_SOC_DAPM_INPUT("TX SWR_DMIC7"),
1395
1396 SND_SOC_DAPM_MUX_E("TX DEC0 MUX", SND_SOC_NOPM,
1397 TX_MACRO_DEC0, 0,
1398 &tx_dec0_mux, tx_macro_enable_dec,
1399 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1400 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1401
1402 SND_SOC_DAPM_MUX_E("TX DEC1 MUX", SND_SOC_NOPM,
1403 TX_MACRO_DEC1, 0,
1404 &tx_dec1_mux, tx_macro_enable_dec,
1405 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1406 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1407
1408 SND_SOC_DAPM_MUX_E("TX DEC2 MUX", SND_SOC_NOPM,
1409 TX_MACRO_DEC2, 0,
1410 &tx_dec2_mux, tx_macro_enable_dec,
1411 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1412 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1413
1414 SND_SOC_DAPM_MUX_E("TX DEC3 MUX", SND_SOC_NOPM,
1415 TX_MACRO_DEC3, 0,
1416 &tx_dec3_mux, tx_macro_enable_dec,
1417 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1418 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1419
1420 SND_SOC_DAPM_MUX_E("TX DEC4 MUX", SND_SOC_NOPM,
1421 TX_MACRO_DEC4, 0,
1422 &tx_dec4_mux, tx_macro_enable_dec,
1423 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1424 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1425
1426 SND_SOC_DAPM_MUX_E("TX DEC5 MUX", SND_SOC_NOPM,
1427 TX_MACRO_DEC5, 0,
1428 &tx_dec5_mux, tx_macro_enable_dec,
1429 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1430 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1431
1432 SND_SOC_DAPM_MUX_E("TX DEC6 MUX", SND_SOC_NOPM,
1433 TX_MACRO_DEC6, 0,
1434 &tx_dec6_mux, tx_macro_enable_dec,
1435 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1436 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1437
1438 SND_SOC_DAPM_MUX_E("TX DEC7 MUX", SND_SOC_NOPM,
1439 TX_MACRO_DEC7, 0,
1440 &tx_dec7_mux, tx_macro_enable_dec,
1441 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1442 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1443
1444 SND_SOC_DAPM_SUPPLY_S("TX_MCLK", 0, SND_SOC_NOPM, 0, 0,
1445 tx_macro_mclk_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1446
1447 SND_SOC_DAPM_SUPPLY_S("TX_SWR_CLK", 0, SND_SOC_NOPM, 0, 0, NULL, 0),
1448
1449 SND_SOC_DAPM_SUPPLY_S("VA_SWR_CLK", 0, SND_SOC_NOPM, 0, 0,
1450 NULL, 0),
1451 };
1452
1453 static const struct snd_soc_dapm_route tx_audio_map[] = {
1454 {"TX_AIF1 CAP", NULL, "TX_MCLK"},
1455 {"TX_AIF2 CAP", NULL, "TX_MCLK"},
1456 {"TX_AIF3 CAP", NULL, "TX_MCLK"},
1457
1458 {"TX_AIF1 CAP", NULL, "TX_AIF1_CAP Mixer"},
1459 {"TX_AIF2 CAP", NULL, "TX_AIF2_CAP Mixer"},
1460 {"TX_AIF3 CAP", NULL, "TX_AIF3_CAP Mixer"},
1461
1462 {"TX_AIF1_CAP Mixer", "DEC0", "TX DEC0 MUX"},
1463 {"TX_AIF1_CAP Mixer", "DEC1", "TX DEC1 MUX"},
1464 {"TX_AIF1_CAP Mixer", "DEC2", "TX DEC2 MUX"},
1465 {"TX_AIF1_CAP Mixer", "DEC3", "TX DEC3 MUX"},
1466 {"TX_AIF1_CAP Mixer", "DEC4", "TX DEC4 MUX"},
1467 {"TX_AIF1_CAP Mixer", "DEC5", "TX DEC5 MUX"},
1468 {"TX_AIF1_CAP Mixer", "DEC6", "TX DEC6 MUX"},
1469 {"TX_AIF1_CAP Mixer", "DEC7", "TX DEC7 MUX"},
1470
1471 {"TX_AIF2_CAP Mixer", "DEC0", "TX DEC0 MUX"},
1472 {"TX_AIF2_CAP Mixer", "DEC1", "TX DEC1 MUX"},
1473 {"TX_AIF2_CAP Mixer", "DEC2", "TX DEC2 MUX"},
1474 {"TX_AIF2_CAP Mixer", "DEC3", "TX DEC3 MUX"},
1475 {"TX_AIF2_CAP Mixer", "DEC4", "TX DEC4 MUX"},
1476 {"TX_AIF2_CAP Mixer", "DEC5", "TX DEC5 MUX"},
1477 {"TX_AIF2_CAP Mixer", "DEC6", "TX DEC6 MUX"},
1478 {"TX_AIF2_CAP Mixer", "DEC7", "TX DEC7 MUX"},
1479
1480 {"TX_AIF3_CAP Mixer", "DEC0", "TX DEC0 MUX"},
1481 {"TX_AIF3_CAP Mixer", "DEC1", "TX DEC1 MUX"},
1482 {"TX_AIF3_CAP Mixer", "DEC2", "TX DEC2 MUX"},
1483 {"TX_AIF3_CAP Mixer", "DEC3", "TX DEC3 MUX"},
1484 {"TX_AIF3_CAP Mixer", "DEC4", "TX DEC4 MUX"},
1485 {"TX_AIF3_CAP Mixer", "DEC5", "TX DEC5 MUX"},
1486 {"TX_AIF3_CAP Mixer", "DEC6", "TX DEC6 MUX"},
1487 {"TX_AIF3_CAP Mixer", "DEC7", "TX DEC7 MUX"},
1488
1489 {"TX DEC0 MUX", NULL, "TX_MCLK"},
1490 {"TX DEC1 MUX", NULL, "TX_MCLK"},
1491 {"TX DEC2 MUX", NULL, "TX_MCLK"},
1492 {"TX DEC3 MUX", NULL, "TX_MCLK"},
1493 {"TX DEC4 MUX", NULL, "TX_MCLK"},
1494 {"TX DEC5 MUX", NULL, "TX_MCLK"},
1495 {"TX DEC6 MUX", NULL, "TX_MCLK"},
1496 {"TX DEC7 MUX", NULL, "TX_MCLK"},
1497
1498 {"TX DEC0 MUX", "SWR_MIC", "TX SMIC MUX0"},
1499 {"TX SMIC MUX0", NULL, "TX_SWR_CLK"},
1500 {"TX SMIC MUX0", "ADC0", "TX SWR_ADC0"},
1501 {"TX SMIC MUX0", "ADC1", "TX SWR_ADC1"},
1502 {"TX SMIC MUX0", "ADC2", "TX SWR_ADC2"},
1503 {"TX SMIC MUX0", "ADC3", "TX SWR_ADC3"},
1504 {"TX SMIC MUX0", "SWR_DMIC0", "TX SWR_DMIC0"},
1505 {"TX SMIC MUX0", "SWR_DMIC1", "TX SWR_DMIC1"},
1506 {"TX SMIC MUX0", "SWR_DMIC2", "TX SWR_DMIC2"},
1507 {"TX SMIC MUX0", "SWR_DMIC3", "TX SWR_DMIC3"},
1508 {"TX SMIC MUX0", "SWR_DMIC4", "TX SWR_DMIC4"},
1509 {"TX SMIC MUX0", "SWR_DMIC5", "TX SWR_DMIC5"},
1510 {"TX SMIC MUX0", "SWR_DMIC6", "TX SWR_DMIC6"},
1511 {"TX SMIC MUX0", "SWR_DMIC7", "TX SWR_DMIC7"},
1512
1513 {"TX DEC1 MUX", "SWR_MIC", "TX SMIC MUX1"},
1514 {"TX SMIC MUX1", NULL, "TX_SWR_CLK"},
1515 {"TX SMIC MUX1", "ADC0", "TX SWR_ADC0"},
1516 {"TX SMIC MUX1", "ADC1", "TX SWR_ADC1"},
1517 {"TX SMIC MUX1", "ADC2", "TX SWR_ADC2"},
1518 {"TX SMIC MUX1", "ADC3", "TX SWR_ADC3"},
1519 {"TX SMIC MUX1", "SWR_DMIC0", "TX SWR_DMIC0"},
1520 {"TX SMIC MUX1", "SWR_DMIC1", "TX SWR_DMIC1"},
1521 {"TX SMIC MUX1", "SWR_DMIC2", "TX SWR_DMIC2"},
1522 {"TX SMIC MUX1", "SWR_DMIC3", "TX SWR_DMIC3"},
1523 {"TX SMIC MUX1", "SWR_DMIC4", "TX SWR_DMIC4"},
1524 {"TX SMIC MUX1", "SWR_DMIC5", "TX SWR_DMIC5"},
1525 {"TX SMIC MUX1", "SWR_DMIC6", "TX SWR_DMIC6"},
1526 {"TX SMIC MUX1", "SWR_DMIC7", "TX SWR_DMIC7"},
1527
1528 {"TX DEC2 MUX", "SWR_MIC", "TX SMIC MUX2"},
1529 {"TX SMIC MUX2", NULL, "TX_SWR_CLK"},
1530 {"TX SMIC MUX2", "ADC0", "TX SWR_ADC0"},
1531 {"TX SMIC MUX2", "ADC1", "TX SWR_ADC1"},
1532 {"TX SMIC MUX2", "ADC2", "TX SWR_ADC2"},
1533 {"TX SMIC MUX2", "ADC3", "TX SWR_ADC3"},
1534 {"TX SMIC MUX2", "SWR_DMIC0", "TX SWR_DMIC0"},
1535 {"TX SMIC MUX2", "SWR_DMIC1", "TX SWR_DMIC1"},
1536 {"TX SMIC MUX2", "SWR_DMIC2", "TX SWR_DMIC2"},
1537 {"TX SMIC MUX2", "SWR_DMIC3", "TX SWR_DMIC3"},
1538 {"TX SMIC MUX2", "SWR_DMIC4", "TX SWR_DMIC4"},
1539 {"TX SMIC MUX2", "SWR_DMIC5", "TX SWR_DMIC5"},
1540 {"TX SMIC MUX2", "SWR_DMIC6", "TX SWR_DMIC6"},
1541 {"TX SMIC MUX2", "SWR_DMIC7", "TX SWR_DMIC7"},
1542
1543 {"TX DEC3 MUX", "SWR_MIC", "TX SMIC MUX3"},
1544 {"TX SMIC MUX3", NULL, "TX_SWR_CLK"},
1545 {"TX SMIC MUX3", "ADC0", "TX SWR_ADC0"},
1546 {"TX SMIC MUX3", "ADC1", "TX SWR_ADC1"},
1547 {"TX SMIC MUX3", "ADC2", "TX SWR_ADC2"},
1548 {"TX SMIC MUX3", "ADC3", "TX SWR_ADC3"},
1549 {"TX SMIC MUX3", "SWR_DMIC0", "TX SWR_DMIC0"},
1550 {"TX SMIC MUX3", "SWR_DMIC1", "TX SWR_DMIC1"},
1551 {"TX SMIC MUX3", "SWR_DMIC2", "TX SWR_DMIC2"},
1552 {"TX SMIC MUX3", "SWR_DMIC3", "TX SWR_DMIC3"},
1553 {"TX SMIC MUX3", "SWR_DMIC4", "TX SWR_DMIC4"},
1554 {"TX SMIC MUX3", "SWR_DMIC5", "TX SWR_DMIC5"},
1555 {"TX SMIC MUX3", "SWR_DMIC6", "TX SWR_DMIC6"},
1556 {"TX SMIC MUX3", "SWR_DMIC7", "TX SWR_DMIC7"},
1557
1558 {"TX DEC4 MUX", "SWR_MIC", "TX SMIC MUX4"},
1559 {"TX SMIC MUX4", NULL, "TX_SWR_CLK"},
1560 {"TX SMIC MUX4", "ADC0", "TX SWR_ADC0"},
1561 {"TX SMIC MUX4", "ADC1", "TX SWR_ADC1"},
1562 {"TX SMIC MUX4", "ADC2", "TX SWR_ADC2"},
1563 {"TX SMIC MUX4", "ADC3", "TX SWR_ADC3"},
1564 {"TX SMIC MUX4", "SWR_DMIC0", "TX SWR_DMIC0"},
1565 {"TX SMIC MUX4", "SWR_DMIC1", "TX SWR_DMIC1"},
1566 {"TX SMIC MUX4", "SWR_DMIC2", "TX SWR_DMIC2"},
1567 {"TX SMIC MUX4", "SWR_DMIC3", "TX SWR_DMIC3"},
1568 {"TX SMIC MUX4", "SWR_DMIC4", "TX SWR_DMIC4"},
1569 {"TX SMIC MUX4", "SWR_DMIC5", "TX SWR_DMIC5"},
1570 {"TX SMIC MUX4", "SWR_DMIC6", "TX SWR_DMIC6"},
1571 {"TX SMIC MUX4", "SWR_DMIC7", "TX SWR_DMIC7"},
1572
1573 {"TX DEC5 MUX", "SWR_MIC", "TX SMIC MUX5"},
1574 {"TX SMIC MUX5", NULL, "TX_SWR_CLK"},
1575 {"TX SMIC MUX5", "ADC0", "TX SWR_ADC0"},
1576 {"TX SMIC MUX5", "ADC1", "TX SWR_ADC1"},
1577 {"TX SMIC MUX5", "ADC2", "TX SWR_ADC2"},
1578 {"TX SMIC MUX5", "ADC3", "TX SWR_ADC3"},
1579 {"TX SMIC MUX5", "SWR_DMIC0", "TX SWR_DMIC0"},
1580 {"TX SMIC MUX5", "SWR_DMIC1", "TX SWR_DMIC1"},
1581 {"TX SMIC MUX5", "SWR_DMIC2", "TX SWR_DMIC2"},
1582 {"TX SMIC MUX5", "SWR_DMIC3", "TX SWR_DMIC3"},
1583 {"TX SMIC MUX5", "SWR_DMIC4", "TX SWR_DMIC4"},
1584 {"TX SMIC MUX5", "SWR_DMIC5", "TX SWR_DMIC5"},
1585 {"TX SMIC MUX5", "SWR_DMIC6", "TX SWR_DMIC6"},
1586 {"TX SMIC MUX5", "SWR_DMIC7", "TX SWR_DMIC7"},
1587
1588 {"TX DEC6 MUX", "SWR_MIC", "TX SMIC MUX6"},
1589 {"TX SMIC MUX6", NULL, "TX_SWR_CLK"},
1590 {"TX SMIC MUX6", "ADC0", "TX SWR_ADC0"},
1591 {"TX SMIC MUX6", "ADC1", "TX SWR_ADC1"},
1592 {"TX SMIC MUX6", "ADC2", "TX SWR_ADC2"},
1593 {"TX SMIC MUX6", "ADC3", "TX SWR_ADC3"},
1594 {"TX SMIC MUX6", "SWR_DMIC0", "TX SWR_DMIC0"},
1595 {"TX SMIC MUX6", "SWR_DMIC1", "TX SWR_DMIC1"},
1596 {"TX SMIC MUX6", "SWR_DMIC2", "TX SWR_DMIC2"},
1597 {"TX SMIC MUX6", "SWR_DMIC3", "TX SWR_DMIC3"},
1598 {"TX SMIC MUX6", "SWR_DMIC4", "TX SWR_DMIC4"},
1599 {"TX SMIC MUX6", "SWR_DMIC5", "TX SWR_DMIC5"},
1600 {"TX SMIC MUX6", "SWR_DMIC6", "TX SWR_DMIC6"},
1601 {"TX SMIC MUX6", "SWR_DMIC7", "TX SWR_DMIC7"},
1602
1603 {"TX DEC7 MUX", "SWR_MIC", "TX SMIC MUX7"},
1604 {"TX SMIC MUX7", NULL, "TX_SWR_CLK"},
1605 {"TX SMIC MUX7", "ADC0", "TX SWR_ADC0"},
1606 {"TX SMIC MUX7", "ADC1", "TX SWR_ADC1"},
1607 {"TX SMIC MUX7", "ADC2", "TX SWR_ADC2"},
1608 {"TX SMIC MUX7", "ADC3", "TX SWR_ADC3"},
1609 {"TX SMIC MUX7", "SWR_DMIC0", "TX SWR_DMIC0"},
1610 {"TX SMIC MUX7", "SWR_DMIC1", "TX SWR_DMIC1"},
1611 {"TX SMIC MUX7", "SWR_DMIC2", "TX SWR_DMIC2"},
1612 {"TX SMIC MUX7", "SWR_DMIC3", "TX SWR_DMIC3"},
1613 {"TX SMIC MUX7", "SWR_DMIC4", "TX SWR_DMIC4"},
1614 {"TX SMIC MUX7", "SWR_DMIC5", "TX SWR_DMIC5"},
1615 {"TX SMIC MUX7", "SWR_DMIC6", "TX SWR_DMIC6"},
1616 {"TX SMIC MUX7", "SWR_DMIC7", "TX SWR_DMIC7"},
1617 };
1618
1619 static const struct snd_kcontrol_new tx_macro_snd_controls[] = {
1620 SOC_SINGLE_S8_TLV("TX_DEC0 Volume",
1621 CDC_TX0_TX_VOL_CTL,
1622 -84, 40, digital_gain),
1623 SOC_SINGLE_S8_TLV("TX_DEC1 Volume",
1624 CDC_TX1_TX_VOL_CTL,
1625 -84, 40, digital_gain),
1626 SOC_SINGLE_S8_TLV("TX_DEC2 Volume",
1627 CDC_TX2_TX_VOL_CTL,
1628 -84, 40, digital_gain),
1629 SOC_SINGLE_S8_TLV("TX_DEC3 Volume",
1630 CDC_TX3_TX_VOL_CTL,
1631 -84, 40, digital_gain),
1632 SOC_SINGLE_S8_TLV("TX_DEC4 Volume",
1633 CDC_TX4_TX_VOL_CTL,
1634 -84, 40, digital_gain),
1635 SOC_SINGLE_S8_TLV("TX_DEC5 Volume",
1636 CDC_TX5_TX_VOL_CTL,
1637 -84, 40, digital_gain),
1638 SOC_SINGLE_S8_TLV("TX_DEC6 Volume",
1639 CDC_TX6_TX_VOL_CTL,
1640 -84, 40, digital_gain),
1641 SOC_SINGLE_S8_TLV("TX_DEC7 Volume",
1642 CDC_TX7_TX_VOL_CTL,
1643 -84, 40, digital_gain),
1644
1645 SOC_ENUM_EXT("DEC0 MODE", dec_mode_mux_enum[0],
1646 tx_macro_dec_mode_get, tx_macro_dec_mode_put),
1647
1648 SOC_ENUM_EXT("DEC1 MODE", dec_mode_mux_enum[1],
1649 tx_macro_dec_mode_get, tx_macro_dec_mode_put),
1650
1651 SOC_ENUM_EXT("DEC2 MODE", dec_mode_mux_enum[2],
1652 tx_macro_dec_mode_get, tx_macro_dec_mode_put),
1653
1654 SOC_ENUM_EXT("DEC3 MODE", dec_mode_mux_enum[3],
1655 tx_macro_dec_mode_get, tx_macro_dec_mode_put),
1656
1657 SOC_ENUM_EXT("DEC4 MODE", dec_mode_mux_enum[4],
1658 tx_macro_dec_mode_get, tx_macro_dec_mode_put),
1659
1660 SOC_ENUM_EXT("DEC5 MODE", dec_mode_mux_enum[5],
1661 tx_macro_dec_mode_get, tx_macro_dec_mode_put),
1662
1663 SOC_ENUM_EXT("DEC6 MODE", dec_mode_mux_enum[6],
1664 tx_macro_dec_mode_get, tx_macro_dec_mode_put),
1665
1666 SOC_ENUM_EXT("DEC7 MODE", dec_mode_mux_enum[7],
1667 tx_macro_dec_mode_get, tx_macro_dec_mode_put),
1668
1669 SOC_SINGLE_EXT("DEC0_BCS Switch", SND_SOC_NOPM, 0, 1, 0,
1670 tx_macro_get_bcs, tx_macro_set_bcs),
1671 };
1672
tx_macro_component_probe(struct snd_soc_component * comp)1673 static int tx_macro_component_probe(struct snd_soc_component *comp)
1674 {
1675 struct tx_macro *tx = snd_soc_component_get_drvdata(comp);
1676 int i;
1677
1678 snd_soc_component_init_regmap(comp, tx->regmap);
1679
1680 for (i = 0; i < NUM_DECIMATORS; i++) {
1681 tx->tx_hpf_work[i].tx = tx;
1682 tx->tx_hpf_work[i].decimator = i;
1683 INIT_DELAYED_WORK(&tx->tx_hpf_work[i].dwork,
1684 tx_macro_tx_hpf_corner_freq_callback);
1685 }
1686
1687 for (i = 0; i < NUM_DECIMATORS; i++) {
1688 tx->tx_mute_dwork[i].tx = tx;
1689 tx->tx_mute_dwork[i].decimator = i;
1690 INIT_DELAYED_WORK(&tx->tx_mute_dwork[i].dwork,
1691 tx_macro_mute_update_callback);
1692 }
1693 tx->component = comp;
1694
1695 snd_soc_component_update_bits(comp, CDC_TX0_TX_PATH_SEC7, 0x3F,
1696 0x0A);
1697 /* Enable swr mic0 and mic1 clock */
1698 snd_soc_component_update_bits(comp, CDC_TX_TOP_CSR_SWR_AMIC0_CTL, 0xFF, 0x00);
1699 snd_soc_component_update_bits(comp, CDC_TX_TOP_CSR_SWR_AMIC1_CTL, 0xFF, 0x00);
1700
1701 return 0;
1702 }
1703
swclk_gate_enable(struct clk_hw * hw)1704 static int swclk_gate_enable(struct clk_hw *hw)
1705 {
1706 struct tx_macro *tx = to_tx_macro(hw);
1707 struct regmap *regmap = tx->regmap;
1708 int ret;
1709
1710 ret = clk_prepare_enable(tx->mclk);
1711 if (ret) {
1712 dev_err(tx->dev, "failed to enable mclk\n");
1713 return ret;
1714 }
1715
1716 tx_macro_mclk_enable(tx, true);
1717 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
1718 CDC_TX_SWR_RESET_MASK, CDC_TX_SWR_RESET_ENABLE);
1719
1720 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
1721 CDC_TX_SWR_CLK_EN_MASK,
1722 CDC_TX_SWR_CLK_ENABLE);
1723 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
1724 CDC_TX_SWR_RESET_MASK, 0x0);
1725
1726 return 0;
1727 }
1728
swclk_gate_disable(struct clk_hw * hw)1729 static void swclk_gate_disable(struct clk_hw *hw)
1730 {
1731 struct tx_macro *tx = to_tx_macro(hw);
1732 struct regmap *regmap = tx->regmap;
1733
1734 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
1735 CDC_TX_SWR_CLK_EN_MASK, 0x0);
1736
1737 tx_macro_mclk_enable(tx, false);
1738 clk_disable_unprepare(tx->mclk);
1739 }
1740
swclk_gate_is_enabled(struct clk_hw * hw)1741 static int swclk_gate_is_enabled(struct clk_hw *hw)
1742 {
1743 struct tx_macro *tx = to_tx_macro(hw);
1744 int ret, val;
1745
1746 regmap_read(tx->regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL, &val);
1747 ret = val & BIT(0);
1748
1749 return ret;
1750 }
1751
swclk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)1752 static unsigned long swclk_recalc_rate(struct clk_hw *hw,
1753 unsigned long parent_rate)
1754 {
1755 return parent_rate / 2;
1756 }
1757
1758 static const struct clk_ops swclk_gate_ops = {
1759 .prepare = swclk_gate_enable,
1760 .unprepare = swclk_gate_disable,
1761 .is_enabled = swclk_gate_is_enabled,
1762 .recalc_rate = swclk_recalc_rate,
1763
1764 };
1765
tx_macro_register_mclk_output(struct tx_macro * tx)1766 static int tx_macro_register_mclk_output(struct tx_macro *tx)
1767 {
1768 struct device *dev = tx->dev;
1769 const char *parent_clk_name = NULL;
1770 const char *clk_name = "lpass-tx-mclk";
1771 struct clk_hw *hw;
1772 struct clk_init_data init;
1773 int ret;
1774
1775 parent_clk_name = __clk_get_name(tx->npl);
1776
1777 init.name = clk_name;
1778 init.ops = &swclk_gate_ops;
1779 init.flags = 0;
1780 init.parent_names = &parent_clk_name;
1781 init.num_parents = 1;
1782 tx->hw.init = &init;
1783 hw = &tx->hw;
1784 ret = devm_clk_hw_register(dev, hw);
1785 if (ret)
1786 return ret;
1787
1788 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
1789 }
1790
1791 static const struct snd_soc_component_driver tx_macro_component_drv = {
1792 .name = "RX-MACRO",
1793 .probe = tx_macro_component_probe,
1794 .controls = tx_macro_snd_controls,
1795 .num_controls = ARRAY_SIZE(tx_macro_snd_controls),
1796 .dapm_widgets = tx_macro_dapm_widgets,
1797 .num_dapm_widgets = ARRAY_SIZE(tx_macro_dapm_widgets),
1798 .dapm_routes = tx_audio_map,
1799 .num_dapm_routes = ARRAY_SIZE(tx_audio_map),
1800 };
1801
tx_macro_probe(struct platform_device * pdev)1802 static int tx_macro_probe(struct platform_device *pdev)
1803 {
1804 struct device *dev = &pdev->dev;
1805 struct device_node *np = dev->of_node;
1806 struct tx_macro *tx;
1807 void __iomem *base;
1808 int ret, reg;
1809
1810 tx = devm_kzalloc(dev, sizeof(*tx), GFP_KERNEL);
1811 if (!tx)
1812 return -ENOMEM;
1813
1814 tx->macro = devm_clk_get_optional(dev, "macro");
1815 if (IS_ERR(tx->macro))
1816 return PTR_ERR(tx->macro);
1817
1818 tx->dcodec = devm_clk_get_optional(dev, "dcodec");
1819 if (IS_ERR(tx->dcodec))
1820 return PTR_ERR(tx->dcodec);
1821
1822 tx->mclk = devm_clk_get(dev, "mclk");
1823 if (IS_ERR(tx->mclk))
1824 return PTR_ERR(tx->mclk);
1825
1826 tx->npl = devm_clk_get(dev, "npl");
1827 if (IS_ERR(tx->npl))
1828 return PTR_ERR(tx->npl);
1829
1830 tx->fsgen = devm_clk_get(dev, "fsgen");
1831 if (IS_ERR(tx->fsgen))
1832 return PTR_ERR(tx->fsgen);
1833
1834 tx->pds = lpass_macro_pds_init(dev);
1835 if (IS_ERR(tx->pds))
1836 return PTR_ERR(tx->pds);
1837
1838 base = devm_platform_ioremap_resource(pdev, 0);
1839 if (IS_ERR(base)) {
1840 ret = PTR_ERR(base);
1841 goto err;
1842 }
1843
1844 /* Update defaults for lpass sc7280 */
1845 if (of_device_is_compatible(np, "qcom,sc7280-lpass-tx-macro")) {
1846 for (reg = 0; reg < ARRAY_SIZE(tx_defaults); reg++) {
1847 switch (tx_defaults[reg].reg) {
1848 case CDC_TX_TOP_CSR_SWR_AMIC0_CTL:
1849 case CDC_TX_TOP_CSR_SWR_AMIC1_CTL:
1850 tx_defaults[reg].def = 0x0E;
1851 break;
1852 default:
1853 break;
1854 }
1855 }
1856 }
1857
1858 tx->regmap = devm_regmap_init_mmio(dev, base, &tx_regmap_config);
1859 if (IS_ERR(tx->regmap)) {
1860 ret = PTR_ERR(tx->regmap);
1861 goto err;
1862 }
1863
1864 dev_set_drvdata(dev, tx);
1865
1866 tx->dev = dev;
1867
1868 /* set MCLK and NPL rates */
1869 clk_set_rate(tx->mclk, MCLK_FREQ);
1870 clk_set_rate(tx->npl, 2 * MCLK_FREQ);
1871
1872 ret = clk_prepare_enable(tx->macro);
1873 if (ret)
1874 goto err;
1875
1876 ret = clk_prepare_enable(tx->dcodec);
1877 if (ret)
1878 goto err_dcodec;
1879
1880 ret = clk_prepare_enable(tx->mclk);
1881 if (ret)
1882 goto err_mclk;
1883
1884 ret = clk_prepare_enable(tx->npl);
1885 if (ret)
1886 goto err_npl;
1887
1888 ret = clk_prepare_enable(tx->fsgen);
1889 if (ret)
1890 goto err_fsgen;
1891
1892 ret = tx_macro_register_mclk_output(tx);
1893 if (ret)
1894 goto err_clkout;
1895
1896 ret = devm_snd_soc_register_component(dev, &tx_macro_component_drv,
1897 tx_macro_dai,
1898 ARRAY_SIZE(tx_macro_dai));
1899 if (ret)
1900 goto err_clkout;
1901
1902 pm_runtime_set_autosuspend_delay(dev, 3000);
1903 pm_runtime_use_autosuspend(dev);
1904 pm_runtime_mark_last_busy(dev);
1905 pm_runtime_set_active(dev);
1906 pm_runtime_enable(dev);
1907
1908 return 0;
1909
1910 err_clkout:
1911 clk_disable_unprepare(tx->fsgen);
1912 err_fsgen:
1913 clk_disable_unprepare(tx->npl);
1914 err_npl:
1915 clk_disable_unprepare(tx->mclk);
1916 err_mclk:
1917 clk_disable_unprepare(tx->dcodec);
1918 err_dcodec:
1919 clk_disable_unprepare(tx->macro);
1920 err:
1921 lpass_macro_pds_exit(tx->pds);
1922
1923 return ret;
1924 }
1925
tx_macro_remove(struct platform_device * pdev)1926 static int tx_macro_remove(struct platform_device *pdev)
1927 {
1928 struct tx_macro *tx = dev_get_drvdata(&pdev->dev);
1929
1930 clk_disable_unprepare(tx->macro);
1931 clk_disable_unprepare(tx->dcodec);
1932 clk_disable_unprepare(tx->mclk);
1933 clk_disable_unprepare(tx->npl);
1934 clk_disable_unprepare(tx->fsgen);
1935
1936 lpass_macro_pds_exit(tx->pds);
1937
1938 return 0;
1939 }
1940
tx_macro_runtime_suspend(struct device * dev)1941 static int __maybe_unused tx_macro_runtime_suspend(struct device *dev)
1942 {
1943 struct tx_macro *tx = dev_get_drvdata(dev);
1944
1945 regcache_cache_only(tx->regmap, true);
1946 regcache_mark_dirty(tx->regmap);
1947
1948 clk_disable_unprepare(tx->mclk);
1949 clk_disable_unprepare(tx->npl);
1950 clk_disable_unprepare(tx->fsgen);
1951
1952 return 0;
1953 }
1954
tx_macro_runtime_resume(struct device * dev)1955 static int __maybe_unused tx_macro_runtime_resume(struct device *dev)
1956 {
1957 struct tx_macro *tx = dev_get_drvdata(dev);
1958 int ret;
1959
1960 ret = clk_prepare_enable(tx->mclk);
1961 if (ret) {
1962 dev_err(dev, "unable to prepare mclk\n");
1963 return ret;
1964 }
1965
1966 ret = clk_prepare_enable(tx->npl);
1967 if (ret) {
1968 dev_err(dev, "unable to prepare npl\n");
1969 goto err_npl;
1970 }
1971
1972 ret = clk_prepare_enable(tx->fsgen);
1973 if (ret) {
1974 dev_err(dev, "unable to prepare fsgen\n");
1975 goto err_fsgen;
1976 }
1977
1978 regcache_cache_only(tx->regmap, false);
1979 regcache_sync(tx->regmap);
1980
1981 return 0;
1982 err_fsgen:
1983 clk_disable_unprepare(tx->npl);
1984 err_npl:
1985 clk_disable_unprepare(tx->mclk);
1986
1987 return ret;
1988 }
1989
1990 static const struct dev_pm_ops tx_macro_pm_ops = {
1991 SET_RUNTIME_PM_OPS(tx_macro_runtime_suspend, tx_macro_runtime_resume, NULL)
1992 };
1993
1994 static const struct of_device_id tx_macro_dt_match[] = {
1995 { .compatible = "qcom,sc7280-lpass-tx-macro" },
1996 { .compatible = "qcom,sm8250-lpass-tx-macro" },
1997 { .compatible = "qcom,sm8450-lpass-tx-macro" },
1998 { .compatible = "qcom,sc8280xp-lpass-tx-macro" },
1999 { }
2000 };
2001 MODULE_DEVICE_TABLE(of, tx_macro_dt_match);
2002 static struct platform_driver tx_macro_driver = {
2003 .driver = {
2004 .name = "tx_macro",
2005 .of_match_table = tx_macro_dt_match,
2006 .suppress_bind_attrs = true,
2007 .pm = &tx_macro_pm_ops,
2008 },
2009 .probe = tx_macro_probe,
2010 .remove = tx_macro_remove,
2011 };
2012
2013 module_platform_driver(tx_macro_driver);
2014
2015 MODULE_DESCRIPTION("TX macro driver");
2016 MODULE_LICENSE("GPL");
2017
