1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2012 Altera <www.altera.com> 4 */ 5 6#include <dt-bindings/reset/altr,rst-mgr.h> 7 8/ { 9 #address-cells = <1>; 10 #size-cells = <1>; 11 12 aliases { 13 serial0 = &uart0; 14 serial1 = &uart1; 15 timer0 = &timer0; 16 timer1 = &timer1; 17 timer2 = &timer2; 18 timer3 = &timer3; 19 }; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 enable-method = "altr,socfpga-smp"; 25 26 cpu0: cpu@0 { 27 compatible = "arm,cortex-a9"; 28 device_type = "cpu"; 29 reg = <0>; 30 next-level-cache = <&L2>; 31 }; 32 cpu1: cpu@1 { 33 compatible = "arm,cortex-a9"; 34 device_type = "cpu"; 35 reg = <1>; 36 next-level-cache = <&L2>; 37 }; 38 }; 39 40 pmu: pmu@ff111000 { 41 compatible = "arm,cortex-a9-pmu"; 42 interrupt-parent = <&intc>; 43 interrupts = <0 176 4>, <0 177 4>; 44 interrupt-affinity = <&cpu0>, <&cpu1>; 45 reg = <0xff111000 0x1000>, 46 <0xff113000 0x1000>; 47 }; 48 49 intc: interrupt-controller@fffed000 { 50 compatible = "arm,cortex-a9-gic"; 51 #interrupt-cells = <3>; 52 interrupt-controller; 53 reg = <0xfffed000 0x1000>, 54 <0xfffec100 0x100>; 55 }; 56 57 soc { 58 #address-cells = <1>; 59 #size-cells = <1>; 60 compatible = "simple-bus"; 61 device_type = "soc"; 62 interrupt-parent = <&intc>; 63 ranges; 64 65 amba { 66 compatible = "simple-bus"; 67 #address-cells = <1>; 68 #size-cells = <1>; 69 ranges; 70 71 pdma: pdma@ffe01000 { 72 compatible = "arm,pl330", "arm,primecell"; 73 reg = <0xffe01000 0x1000>; 74 interrupts = <0 104 4>, 75 <0 105 4>, 76 <0 106 4>, 77 <0 107 4>, 78 <0 108 4>, 79 <0 109 4>, 80 <0 110 4>, 81 <0 111 4>; 82 #dma-cells = <1>; 83 clocks = <&l4_main_clk>; 84 clock-names = "apb_pclk"; 85 resets = <&rst DMA_RESET>; 86 reset-names = "dma"; 87 }; 88 }; 89 90 base_fpga_region { 91 compatible = "fpga-region"; 92 fpga-mgr = <&fpgamgr0>; 93 94 #address-cells = <0x1>; 95 #size-cells = <0x1>; 96 }; 97 98 can0: can@ffc00000 { 99 compatible = "bosch,d_can"; 100 reg = <0xffc00000 0x1000>; 101 interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>; 102 clocks = <&can0_clk>; 103 resets = <&rst CAN0_RESET>; 104 status = "disabled"; 105 }; 106 107 can1: can@ffc01000 { 108 compatible = "bosch,d_can"; 109 reg = <0xffc01000 0x1000>; 110 interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>; 111 clocks = <&can1_clk>; 112 resets = <&rst CAN1_RESET>; 113 status = "disabled"; 114 }; 115 116 clkmgr@ffd04000 { 117 compatible = "altr,clk-mgr"; 118 reg = <0xffd04000 0x1000>; 119 120 clocks { 121 #address-cells = <1>; 122 #size-cells = <0>; 123 124 osc1: osc1 { 125 #clock-cells = <0>; 126 compatible = "fixed-clock"; 127 }; 128 129 osc2: osc2 { 130 #clock-cells = <0>; 131 compatible = "fixed-clock"; 132 }; 133 134 f2s_periph_ref_clk: f2s_periph_ref_clk { 135 #clock-cells = <0>; 136 compatible = "fixed-clock"; 137 }; 138 139 f2s_sdram_ref_clk: f2s_sdram_ref_clk { 140 #clock-cells = <0>; 141 compatible = "fixed-clock"; 142 }; 143 144 main_pll: main_pll@40 { 145 #address-cells = <1>; 146 #size-cells = <0>; 147 #clock-cells = <0>; 148 compatible = "altr,socfpga-pll-clock"; 149 clocks = <&osc1>; 150 reg = <0x40>; 151 152 mpuclk: mpuclk@48 { 153 #clock-cells = <0>; 154 compatible = "altr,socfpga-perip-clk"; 155 clocks = <&main_pll>; 156 div-reg = <0xe0 0 9>; 157 reg = <0x48>; 158 }; 159 160 mainclk: mainclk@4c { 161 #clock-cells = <0>; 162 compatible = "altr,socfpga-perip-clk"; 163 clocks = <&main_pll>; 164 div-reg = <0xe4 0 9>; 165 reg = <0x4C>; 166 }; 167 168 dbg_base_clk: dbg_base_clk@50 { 169 #clock-cells = <0>; 170 compatible = "altr,socfpga-perip-clk"; 171 clocks = <&main_pll>, <&osc1>; 172 div-reg = <0xe8 0 9>; 173 reg = <0x50>; 174 }; 175 176 main_qspi_clk: main_qspi_clk@54 { 177 #clock-cells = <0>; 178 compatible = "altr,socfpga-perip-clk"; 179 clocks = <&main_pll>; 180 reg = <0x54>; 181 }; 182 183 main_nand_sdmmc_clk: main_nand_sdmmc_clk@58 { 184 #clock-cells = <0>; 185 compatible = "altr,socfpga-perip-clk"; 186 clocks = <&main_pll>; 187 reg = <0x58>; 188 }; 189 190 cfg_h2f_usr0_clk: cfg_h2f_usr0_clk@5c { 191 #clock-cells = <0>; 192 compatible = "altr,socfpga-perip-clk"; 193 clocks = <&main_pll>; 194 reg = <0x5C>; 195 }; 196 }; 197 198 periph_pll: periph_pll@80 { 199 #address-cells = <1>; 200 #size-cells = <0>; 201 #clock-cells = <0>; 202 compatible = "altr,socfpga-pll-clock"; 203 clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>; 204 reg = <0x80>; 205 206 emac0_clk: emac0_clk@88 { 207 #clock-cells = <0>; 208 compatible = "altr,socfpga-perip-clk"; 209 clocks = <&periph_pll>; 210 reg = <0x88>; 211 }; 212 213 emac1_clk: emac1_clk@8c { 214 #clock-cells = <0>; 215 compatible = "altr,socfpga-perip-clk"; 216 clocks = <&periph_pll>; 217 reg = <0x8C>; 218 }; 219 220 per_qspi_clk: per_qsi_clk@90 { 221 #clock-cells = <0>; 222 compatible = "altr,socfpga-perip-clk"; 223 clocks = <&periph_pll>; 224 reg = <0x90>; 225 }; 226 227 per_nand_mmc_clk: per_nand_mmc_clk@94 { 228 #clock-cells = <0>; 229 compatible = "altr,socfpga-perip-clk"; 230 clocks = <&periph_pll>; 231 reg = <0x94>; 232 }; 233 234 per_base_clk: per_base_clk@98 { 235 #clock-cells = <0>; 236 compatible = "altr,socfpga-perip-clk"; 237 clocks = <&periph_pll>; 238 reg = <0x98>; 239 }; 240 241 h2f_usr1_clk: h2f_usr1_clk@9c { 242 #clock-cells = <0>; 243 compatible = "altr,socfpga-perip-clk"; 244 clocks = <&periph_pll>; 245 reg = <0x9C>; 246 }; 247 }; 248 249 sdram_pll: sdram_pll@c0 { 250 #address-cells = <1>; 251 #size-cells = <0>; 252 #clock-cells = <0>; 253 compatible = "altr,socfpga-pll-clock"; 254 clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>; 255 reg = <0xC0>; 256 257 ddr_dqs_clk: ddr_dqs_clk@c8 { 258 #clock-cells = <0>; 259 compatible = "altr,socfpga-perip-clk"; 260 clocks = <&sdram_pll>; 261 reg = <0xC8>; 262 }; 263 264 ddr_2x_dqs_clk: ddr_2x_dqs_clk@cc { 265 #clock-cells = <0>; 266 compatible = "altr,socfpga-perip-clk"; 267 clocks = <&sdram_pll>; 268 reg = <0xCC>; 269 }; 270 271 ddr_dq_clk: ddr_dq_clk@d0 { 272 #clock-cells = <0>; 273 compatible = "altr,socfpga-perip-clk"; 274 clocks = <&sdram_pll>; 275 reg = <0xD0>; 276 }; 277 278 h2f_usr2_clk: h2f_usr2_clk@d4 { 279 #clock-cells = <0>; 280 compatible = "altr,socfpga-perip-clk"; 281 clocks = <&sdram_pll>; 282 reg = <0xD4>; 283 }; 284 }; 285 286 mpu_periph_clk: mpu_periph_clk { 287 #clock-cells = <0>; 288 compatible = "altr,socfpga-perip-clk"; 289 clocks = <&mpuclk>; 290 fixed-divider = <4>; 291 }; 292 293 mpu_l2_ram_clk: mpu_l2_ram_clk { 294 #clock-cells = <0>; 295 compatible = "altr,socfpga-perip-clk"; 296 clocks = <&mpuclk>; 297 fixed-divider = <2>; 298 }; 299 300 l4_main_clk: l4_main_clk { 301 #clock-cells = <0>; 302 compatible = "altr,socfpga-gate-clk"; 303 clocks = <&mainclk>; 304 clk-gate = <0x60 0>; 305 }; 306 307 l3_main_clk: l3_main_clk { 308 #clock-cells = <0>; 309 compatible = "altr,socfpga-perip-clk"; 310 clocks = <&mainclk>; 311 fixed-divider = <1>; 312 }; 313 314 l3_mp_clk: l3_mp_clk { 315 #clock-cells = <0>; 316 compatible = "altr,socfpga-gate-clk"; 317 clocks = <&mainclk>; 318 div-reg = <0x64 0 2>; 319 clk-gate = <0x60 1>; 320 }; 321 322 l3_sp_clk: l3_sp_clk { 323 #clock-cells = <0>; 324 compatible = "altr,socfpga-gate-clk"; 325 clocks = <&l3_mp_clk>; 326 div-reg = <0x64 2 2>; 327 }; 328 329 l4_mp_clk: l4_mp_clk { 330 #clock-cells = <0>; 331 compatible = "altr,socfpga-gate-clk"; 332 clocks = <&mainclk>, <&per_base_clk>; 333 div-reg = <0x64 4 3>; 334 clk-gate = <0x60 2>; 335 }; 336 337 l4_sp_clk: l4_sp_clk { 338 #clock-cells = <0>; 339 compatible = "altr,socfpga-gate-clk"; 340 clocks = <&mainclk>, <&per_base_clk>; 341 div-reg = <0x64 7 3>; 342 clk-gate = <0x60 3>; 343 }; 344 345 dbg_at_clk: dbg_at_clk { 346 #clock-cells = <0>; 347 compatible = "altr,socfpga-gate-clk"; 348 clocks = <&dbg_base_clk>; 349 div-reg = <0x68 0 2>; 350 clk-gate = <0x60 4>; 351 }; 352 353 dbg_clk: dbg_clk { 354 #clock-cells = <0>; 355 compatible = "altr,socfpga-gate-clk"; 356 clocks = <&dbg_at_clk>; 357 div-reg = <0x68 2 2>; 358 clk-gate = <0x60 5>; 359 }; 360 361 dbg_trace_clk: dbg_trace_clk { 362 #clock-cells = <0>; 363 compatible = "altr,socfpga-gate-clk"; 364 clocks = <&dbg_base_clk>; 365 div-reg = <0x6C 0 3>; 366 clk-gate = <0x60 6>; 367 }; 368 369 dbg_timer_clk: dbg_timer_clk { 370 #clock-cells = <0>; 371 compatible = "altr,socfpga-gate-clk"; 372 clocks = <&dbg_base_clk>; 373 clk-gate = <0x60 7>; 374 }; 375 376 cfg_clk: cfg_clk { 377 #clock-cells = <0>; 378 compatible = "altr,socfpga-gate-clk"; 379 clocks = <&cfg_h2f_usr0_clk>; 380 clk-gate = <0x60 8>; 381 }; 382 383 h2f_user0_clk: h2f_user0_clk { 384 #clock-cells = <0>; 385 compatible = "altr,socfpga-gate-clk"; 386 clocks = <&cfg_h2f_usr0_clk>; 387 clk-gate = <0x60 9>; 388 }; 389 390 emac_0_clk: emac_0_clk { 391 #clock-cells = <0>; 392 compatible = "altr,socfpga-gate-clk"; 393 clocks = <&emac0_clk>; 394 clk-gate = <0xa0 0>; 395 }; 396 397 emac_1_clk: emac_1_clk { 398 #clock-cells = <0>; 399 compatible = "altr,socfpga-gate-clk"; 400 clocks = <&emac1_clk>; 401 clk-gate = <0xa0 1>; 402 }; 403 404 usb_mp_clk: usb_mp_clk { 405 #clock-cells = <0>; 406 compatible = "altr,socfpga-gate-clk"; 407 clocks = <&per_base_clk>; 408 clk-gate = <0xa0 2>; 409 div-reg = <0xa4 0 3>; 410 }; 411 412 spi_m_clk: spi_m_clk { 413 #clock-cells = <0>; 414 compatible = "altr,socfpga-gate-clk"; 415 clocks = <&per_base_clk>; 416 clk-gate = <0xa0 3>; 417 div-reg = <0xa4 3 3>; 418 }; 419 420 can0_clk: can0_clk { 421 #clock-cells = <0>; 422 compatible = "altr,socfpga-gate-clk"; 423 clocks = <&per_base_clk>; 424 clk-gate = <0xa0 4>; 425 div-reg = <0xa4 6 3>; 426 }; 427 428 can1_clk: can1_clk { 429 #clock-cells = <0>; 430 compatible = "altr,socfpga-gate-clk"; 431 clocks = <&per_base_clk>; 432 clk-gate = <0xa0 5>; 433 div-reg = <0xa4 9 3>; 434 }; 435 436 gpio_db_clk: gpio_db_clk { 437 #clock-cells = <0>; 438 compatible = "altr,socfpga-gate-clk"; 439 clocks = <&per_base_clk>; 440 clk-gate = <0xa0 6>; 441 div-reg = <0xa8 0 24>; 442 }; 443 444 h2f_user1_clk: h2f_user1_clk { 445 #clock-cells = <0>; 446 compatible = "altr,socfpga-gate-clk"; 447 clocks = <&h2f_usr1_clk>; 448 clk-gate = <0xa0 7>; 449 }; 450 451 sdmmc_clk: sdmmc_clk { 452 #clock-cells = <0>; 453 compatible = "altr,socfpga-gate-clk"; 454 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; 455 clk-gate = <0xa0 8>; 456 clk-phase = <0 135>; 457 }; 458 459 sdmmc_clk_divided: sdmmc_clk_divided { 460 #clock-cells = <0>; 461 compatible = "altr,socfpga-gate-clk"; 462 clocks = <&sdmmc_clk>; 463 clk-gate = <0xa0 8>; 464 fixed-divider = <4>; 465 }; 466 467 nand_x_clk: nand_x_clk { 468 #clock-cells = <0>; 469 compatible = "altr,socfpga-gate-clk"; 470 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; 471 clk-gate = <0xa0 9>; 472 }; 473 474 nand_ecc_clk: nand_ecc_clk { 475 #clock-cells = <0>; 476 compatible = "altr,socfpga-gate-clk"; 477 clocks = <&nand_x_clk>; 478 clk-gate = <0xa0 9>; 479 }; 480 481 nand_clk: nand_clk { 482 #clock-cells = <0>; 483 compatible = "altr,socfpga-gate-clk"; 484 clocks = <&nand_x_clk>; 485 clk-gate = <0xa0 10>; 486 fixed-divider = <4>; 487 }; 488 489 qspi_clk: qspi_clk { 490 #clock-cells = <0>; 491 compatible = "altr,socfpga-gate-clk"; 492 clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>; 493 clk-gate = <0xa0 11>; 494 }; 495 496 ddr_dqs_clk_gate: ddr_dqs_clk_gate { 497 #clock-cells = <0>; 498 compatible = "altr,socfpga-gate-clk"; 499 clocks = <&ddr_dqs_clk>; 500 clk-gate = <0xd8 0>; 501 }; 502 503 ddr_2x_dqs_clk_gate: ddr_2x_dqs_clk_gate { 504 #clock-cells = <0>; 505 compatible = "altr,socfpga-gate-clk"; 506 clocks = <&ddr_2x_dqs_clk>; 507 clk-gate = <0xd8 1>; 508 }; 509 510 ddr_dq_clk_gate: ddr_dq_clk_gate { 511 #clock-cells = <0>; 512 compatible = "altr,socfpga-gate-clk"; 513 clocks = <&ddr_dq_clk>; 514 clk-gate = <0xd8 2>; 515 }; 516 517 h2f_user2_clk: h2f_user2_clk { 518 #clock-cells = <0>; 519 compatible = "altr,socfpga-gate-clk"; 520 clocks = <&h2f_usr2_clk>; 521 clk-gate = <0xd8 3>; 522 }; 523 524 }; 525 }; 526 527 fpga_bridge0: fpga_bridge@ff400000 { 528 compatible = "altr,socfpga-lwhps2fpga-bridge"; 529 reg = <0xff400000 0x100000>; 530 resets = <&rst LWHPS2FPGA_RESET>; 531 clocks = <&l4_main_clk>; 532 status = "disabled"; 533 }; 534 535 fpga_bridge1: fpga_bridge@ff500000 { 536 compatible = "altr,socfpga-hps2fpga-bridge"; 537 reg = <0xff500000 0x10000>; 538 resets = <&rst HPS2FPGA_RESET>; 539 clocks = <&l4_main_clk>; 540 status = "disabled"; 541 }; 542 543 fpga_bridge2: fpga-bridge@ff600000 { 544 compatible = "altr,socfpga-fpga2hps-bridge"; 545 reg = <0xff600000 0x100000>; 546 resets = <&rst FPGA2HPS_RESET>; 547 clocks = <&l4_main_clk>; 548 status = "disabled"; 549 }; 550 551 fpga_bridge3: fpga-bridge@ffc25080 { 552 compatible = "altr,socfpga-fpga2sdram-bridge"; 553 reg = <0xffc25080 0x4>; 554 status = "disabled"; 555 }; 556 557 fpgamgr0: fpgamgr@ff706000 { 558 compatible = "altr,socfpga-fpga-mgr"; 559 reg = <0xff706000 0x1000 560 0xffb90000 0x4>; 561 interrupts = <0 175 4>; 562 }; 563 564 socfpga_axi_setup: stmmac-axi-config { 565 snps,wr_osr_lmt = <0xf>; 566 snps,rd_osr_lmt = <0xf>; 567 snps,blen = <0 0 0 0 16 0 0>; 568 }; 569 570 gmac0: ethernet@ff700000 { 571 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; 572 altr,sysmgr-syscon = <&sysmgr 0x60 0>; 573 reg = <0xff700000 0x2000>; 574 interrupts = <0 115 4>; 575 interrupt-names = "macirq"; 576 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ 577 clocks = <&emac_0_clk>; 578 clock-names = "stmmaceth"; 579 resets = <&rst EMAC0_RESET>; 580 reset-names = "stmmaceth"; 581 snps,multicast-filter-bins = <256>; 582 snps,perfect-filter-entries = <128>; 583 tx-fifo-depth = <4096>; 584 rx-fifo-depth = <4096>; 585 snps,axi-config = <&socfpga_axi_setup>; 586 status = "disabled"; 587 }; 588 589 gmac1: ethernet@ff702000 { 590 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; 591 altr,sysmgr-syscon = <&sysmgr 0x60 2>; 592 reg = <0xff702000 0x2000>; 593 interrupts = <0 120 4>; 594 interrupt-names = "macirq"; 595 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ 596 clocks = <&emac_1_clk>; 597 clock-names = "stmmaceth"; 598 resets = <&rst EMAC1_RESET>; 599 reset-names = "stmmaceth"; 600 snps,multicast-filter-bins = <256>; 601 snps,perfect-filter-entries = <128>; 602 tx-fifo-depth = <4096>; 603 rx-fifo-depth = <4096>; 604 snps,axi-config = <&socfpga_axi_setup>; 605 status = "disabled"; 606 }; 607 608 gpio0: gpio@ff708000 { 609 #address-cells = <1>; 610 #size-cells = <0>; 611 compatible = "snps,dw-apb-gpio"; 612 reg = <0xff708000 0x1000>; 613 clocks = <&l4_mp_clk>; 614 resets = <&rst GPIO0_RESET>; 615 status = "disabled"; 616 617 porta: gpio-controller@0 { 618 compatible = "snps,dw-apb-gpio-port"; 619 gpio-controller; 620 #gpio-cells = <2>; 621 snps,nr-gpios = <29>; 622 reg = <0>; 623 interrupt-controller; 624 #interrupt-cells = <2>; 625 interrupts = <0 164 4>; 626 }; 627 }; 628 629 gpio1: gpio@ff709000 { 630 #address-cells = <1>; 631 #size-cells = <0>; 632 compatible = "snps,dw-apb-gpio"; 633 reg = <0xff709000 0x1000>; 634 clocks = <&l4_mp_clk>; 635 resets = <&rst GPIO1_RESET>; 636 status = "disabled"; 637 638 portb: gpio-controller@0 { 639 compatible = "snps,dw-apb-gpio-port"; 640 gpio-controller; 641 #gpio-cells = <2>; 642 snps,nr-gpios = <29>; 643 reg = <0>; 644 interrupt-controller; 645 #interrupt-cells = <2>; 646 interrupts = <0 165 4>; 647 }; 648 }; 649 650 gpio2: gpio@ff70a000 { 651 #address-cells = <1>; 652 #size-cells = <0>; 653 compatible = "snps,dw-apb-gpio"; 654 reg = <0xff70a000 0x1000>; 655 clocks = <&l4_mp_clk>; 656 resets = <&rst GPIO2_RESET>; 657 status = "disabled"; 658 659 portc: gpio-controller@0 { 660 compatible = "snps,dw-apb-gpio-port"; 661 gpio-controller; 662 #gpio-cells = <2>; 663 snps,nr-gpios = <27>; 664 reg = <0>; 665 interrupt-controller; 666 #interrupt-cells = <2>; 667 interrupts = <0 166 4>; 668 }; 669 }; 670 671 i2c0: i2c@ffc04000 { 672 #address-cells = <1>; 673 #size-cells = <0>; 674 compatible = "snps,designware-i2c"; 675 reg = <0xffc04000 0x1000>; 676 resets = <&rst I2C0_RESET>; 677 clocks = <&l4_sp_clk>; 678 interrupts = <0 158 0x4>; 679 status = "disabled"; 680 }; 681 682 i2c1: i2c@ffc05000 { 683 #address-cells = <1>; 684 #size-cells = <0>; 685 compatible = "snps,designware-i2c"; 686 reg = <0xffc05000 0x1000>; 687 resets = <&rst I2C1_RESET>; 688 clocks = <&l4_sp_clk>; 689 interrupts = <0 159 0x4>; 690 status = "disabled"; 691 }; 692 693 i2c2: i2c@ffc06000 { 694 #address-cells = <1>; 695 #size-cells = <0>; 696 compatible = "snps,designware-i2c"; 697 reg = <0xffc06000 0x1000>; 698 resets = <&rst I2C2_RESET>; 699 clocks = <&l4_sp_clk>; 700 interrupts = <0 160 0x4>; 701 status = "disabled"; 702 }; 703 704 i2c3: i2c@ffc07000 { 705 #address-cells = <1>; 706 #size-cells = <0>; 707 compatible = "snps,designware-i2c"; 708 reg = <0xffc07000 0x1000>; 709 resets = <&rst I2C3_RESET>; 710 clocks = <&l4_sp_clk>; 711 interrupts = <0 161 0x4>; 712 status = "disabled"; 713 }; 714 715 eccmgr: eccmgr { 716 compatible = "altr,socfpga-ecc-manager"; 717 #address-cells = <1>; 718 #size-cells = <1>; 719 ranges; 720 721 l2-ecc@ffd08140 { 722 compatible = "altr,socfpga-l2-ecc"; 723 reg = <0xffd08140 0x4>; 724 interrupts = <0 36 1>, <0 37 1>; 725 }; 726 727 ocram-ecc@ffd08144 { 728 compatible = "altr,socfpga-ocram-ecc"; 729 reg = <0xffd08144 0x4>; 730 iram = <&ocram>; 731 interrupts = <0 178 1>, <0 179 1>; 732 }; 733 }; 734 735 L2: cache-controller@fffef000 { 736 compatible = "arm,pl310-cache"; 737 reg = <0xfffef000 0x1000>; 738 interrupts = <0 38 0x04>; 739 cache-unified; 740 cache-level = <2>; 741 arm,tag-latency = <1 1 1>; 742 arm,data-latency = <2 1 1>; 743 prefetch-data = <1>; 744 prefetch-instr = <1>; 745 arm,shared-override; 746 arm,double-linefill = <1>; 747 arm,double-linefill-incr = <0>; 748 arm,double-linefill-wrap = <1>; 749 arm,prefetch-drop = <0>; 750 arm,prefetch-offset = <7>; 751 }; 752 753 l3regs@0xff800000 { 754 compatible = "altr,l3regs", "syscon"; 755 reg = <0xff800000 0x1000>; 756 }; 757 758 mmc: dwmmc0@ff704000 { 759 compatible = "altr,socfpga-dw-mshc"; 760 reg = <0xff704000 0x1000>; 761 interrupts = <0 139 4>; 762 fifo-depth = <0x400>; 763 #address-cells = <1>; 764 #size-cells = <0>; 765 clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>; 766 clock-names = "biu", "ciu"; 767 resets = <&rst SDMMC_RESET>; 768 status = "disabled"; 769 }; 770 771 nand0: nand@ff900000 { 772 #address-cells = <0x1>; 773 #size-cells = <0x0>; 774 compatible = "altr,socfpga-denali-nand"; 775 reg = <0xff900000 0x100000>, 776 <0xffb80000 0x10000>; 777 reg-names = "nand_data", "denali_reg"; 778 interrupts = <0x0 0x90 0x4>; 779 clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>; 780 clock-names = "nand", "nand_x", "ecc"; 781 resets = <&rst NAND_RESET>; 782 status = "disabled"; 783 }; 784 785 ocram: sram@ffff0000 { 786 compatible = "mmio-sram"; 787 reg = <0xffff0000 0x10000>; 788 }; 789 790 qspi: spi@ff705000 { 791 compatible = "intel,socfpga-qspi", "cdns,qspi-nor"; 792 #address-cells = <1>; 793 #size-cells = <0>; 794 reg = <0xff705000 0x1000>, 795 <0xffa00000 0x1000>; 796 interrupts = <0 151 4>; 797 cdns,fifo-depth = <128>; 798 cdns,fifo-width = <4>; 799 cdns,trigger-address = <0x00000000>; 800 clocks = <&qspi_clk>; 801 resets = <&rst QSPI_RESET>; 802 status = "disabled"; 803 }; 804 805 rst: rstmgr@ffd05000 { 806 #reset-cells = <1>; 807 compatible = "altr,rst-mgr"; 808 reg = <0xffd05000 0x1000>; 809 altr,modrst-offset = <0x10>; 810 }; 811 812 scu: snoop-control-unit@fffec000 { 813 compatible = "arm,cortex-a9-scu"; 814 reg = <0xfffec000 0x100>; 815 }; 816 817 sdr: sdr@ffc25000 { 818 compatible = "altr,sdr-ctl", "syscon"; 819 reg = <0xffc25000 0x1000>; 820 resets = <&rst SDR_RESET>; 821 }; 822 823 sdramedac { 824 compatible = "altr,sdram-edac"; 825 altr,sdr-syscon = <&sdr>; 826 interrupts = <0 39 4>; 827 }; 828 829 spi0: spi@fff00000 { 830 compatible = "snps,dw-apb-ssi"; 831 #address-cells = <1>; 832 #size-cells = <0>; 833 reg = <0xfff00000 0x1000>; 834 interrupts = <0 154 4>; 835 num-cs = <4>; 836 clocks = <&spi_m_clk>; 837 resets = <&rst SPIM0_RESET>; 838 reset-names = "spi"; 839 status = "disabled"; 840 }; 841 842 spi1: spi@fff01000 { 843 compatible = "snps,dw-apb-ssi"; 844 #address-cells = <1>; 845 #size-cells = <0>; 846 reg = <0xfff01000 0x1000>; 847 interrupts = <0 155 4>; 848 num-cs = <4>; 849 clocks = <&spi_m_clk>; 850 resets = <&rst SPIM1_RESET>; 851 reset-names = "spi"; 852 status = "disabled"; 853 }; 854 855 sysmgr: sysmgr@ffd08000 { 856 compatible = "altr,sys-mgr", "syscon"; 857 reg = <0xffd08000 0x4000>; 858 }; 859 860 /* Local timer */ 861 timer@fffec600 { 862 compatible = "arm,cortex-a9-twd-timer"; 863 reg = <0xfffec600 0x100>; 864 interrupts = <1 13 0xf01>; 865 clocks = <&mpu_periph_clk>; 866 }; 867 868 timer0: timer0@ffc08000 { 869 compatible = "snps,dw-apb-timer"; 870 interrupts = <0 167 4>; 871 reg = <0xffc08000 0x1000>; 872 clocks = <&l4_sp_clk>; 873 clock-names = "timer"; 874 resets = <&rst SPTIMER0_RESET>; 875 reset-names = "timer"; 876 }; 877 878 timer1: timer1@ffc09000 { 879 compatible = "snps,dw-apb-timer"; 880 interrupts = <0 168 4>; 881 reg = <0xffc09000 0x1000>; 882 clocks = <&l4_sp_clk>; 883 clock-names = "timer"; 884 resets = <&rst SPTIMER1_RESET>; 885 reset-names = "timer"; 886 }; 887 888 timer2: timer2@ffd00000 { 889 compatible = "snps,dw-apb-timer"; 890 interrupts = <0 169 4>; 891 reg = <0xffd00000 0x1000>; 892 clocks = <&osc1>; 893 clock-names = "timer"; 894 resets = <&rst OSC1TIMER0_RESET>; 895 reset-names = "timer"; 896 }; 897 898 timer3: timer3@ffd01000 { 899 compatible = "snps,dw-apb-timer"; 900 interrupts = <0 170 4>; 901 reg = <0xffd01000 0x1000>; 902 clocks = <&osc1>; 903 clock-names = "timer"; 904 resets = <&rst OSC1TIMER1_RESET>; 905 reset-names = "timer"; 906 }; 907 908 uart0: serial0@ffc02000 { 909 compatible = "snps,dw-apb-uart"; 910 reg = <0xffc02000 0x1000>; 911 interrupts = <0 162 4>; 912 reg-shift = <2>; 913 reg-io-width = <4>; 914 clocks = <&l4_sp_clk>; 915 dmas = <&pdma 28>, 916 <&pdma 29>; 917 dma-names = "tx", "rx"; 918 resets = <&rst UART0_RESET>; 919 }; 920 921 uart1: serial1@ffc03000 { 922 compatible = "snps,dw-apb-uart"; 923 reg = <0xffc03000 0x1000>; 924 interrupts = <0 163 4>; 925 reg-shift = <2>; 926 reg-io-width = <4>; 927 clocks = <&l4_sp_clk>; 928 dmas = <&pdma 30>, 929 <&pdma 31>; 930 dma-names = "tx", "rx"; 931 resets = <&rst UART1_RESET>; 932 }; 933 934 usbphy0: usbphy { 935 #phy-cells = <0>; 936 compatible = "usb-nop-xceiv"; 937 status = "okay"; 938 }; 939 940 usb0: usb@ffb00000 { 941 compatible = "snps,dwc2"; 942 reg = <0xffb00000 0xffff>; 943 interrupts = <0 125 4>; 944 clocks = <&usb_mp_clk>; 945 clock-names = "otg"; 946 resets = <&rst USB0_RESET>; 947 reset-names = "dwc2"; 948 phys = <&usbphy0>; 949 phy-names = "usb2-phy"; 950 status = "disabled"; 951 }; 952 953 usb1: usb@ffb40000 { 954 compatible = "snps,dwc2"; 955 reg = <0xffb40000 0xffff>; 956 interrupts = <0 128 4>; 957 clocks = <&usb_mp_clk>; 958 clock-names = "otg"; 959 resets = <&rst USB1_RESET>; 960 reset-names = "dwc2"; 961 phys = <&usbphy0>; 962 phy-names = "usb2-phy"; 963 status = "disabled"; 964 }; 965 966 watchdog0: watchdog@ffd02000 { 967 compatible = "snps,dw-wdt"; 968 reg = <0xffd02000 0x1000>; 969 interrupts = <0 171 4>; 970 clocks = <&osc1>; 971 resets = <&rst L4WD0_RESET>; 972 status = "disabled"; 973 }; 974 975 watchdog1: watchdog@ffd03000 { 976 compatible = "snps,dw-wdt"; 977 reg = <0xffd03000 0x1000>; 978 interrupts = <0 172 4>; 979 clocks = <&osc1>; 980 resets = <&rst L4WD1_RESET>; 981 status = "disabled"; 982 }; 983 }; 984}; 985
