1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2012 Altera <www.altera.com> 4 */ 5 6#include <dt-bindings/reset/altr,rst-mgr.h> 7 8/ { 9 #address-cells = <1>; 10 #size-cells = <1>; 11 12 aliases { 13 serial0 = &uart0; 14 serial1 = &uart1; 15 timer0 = &timer0; 16 timer1 = &timer1; 17 timer2 = &timer2; 18 timer3 = &timer3; 19 }; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 enable-method = "altr,socfpga-smp"; 25 26 cpu0: cpu@0 { 27 compatible = "arm,cortex-a9"; 28 device_type = "cpu"; 29 reg = <0>; 30 next-level-cache = <&L2>; 31 }; 32 cpu1: cpu@1 { 33 compatible = "arm,cortex-a9"; 34 device_type = "cpu"; 35 reg = <1>; 36 next-level-cache = <&L2>; 37 }; 38 }; 39 40 pmu: pmu@ff111000 { 41 compatible = "arm,cortex-a9-pmu"; 42 interrupt-parent = <&intc>; 43 interrupts = <0 176 4>, <0 177 4>; 44 interrupt-affinity = <&cpu0>, <&cpu1>; 45 reg = <0xff111000 0x1000>, 46 <0xff113000 0x1000>; 47 }; 48 49 intc: intc@fffed000 { 50 compatible = "arm,cortex-a9-gic"; 51 #interrupt-cells = <3>; 52 interrupt-controller; 53 reg = <0xfffed000 0x1000>, 54 <0xfffec100 0x100>; 55 }; 56 57 soc { 58 #address-cells = <1>; 59 #size-cells = <1>; 60 compatible = "simple-bus"; 61 device_type = "soc"; 62 interrupt-parent = <&intc>; 63 ranges; 64 65 amba { 66 compatible = "simple-bus"; 67 #address-cells = <1>; 68 #size-cells = <1>; 69 ranges; 70 71 pdma: pdma@ffe01000 { 72 compatible = "arm,pl330", "arm,primecell"; 73 reg = <0xffe01000 0x1000>; 74 interrupts = <0 104 4>, 75 <0 105 4>, 76 <0 106 4>, 77 <0 107 4>, 78 <0 108 4>, 79 <0 109 4>, 80 <0 110 4>, 81 <0 111 4>; 82 #dma-cells = <1>; 83 #dma-channels = <8>; 84 #dma-requests = <32>; 85 clocks = <&l4_main_clk>; 86 clock-names = "apb_pclk"; 87 resets = <&rst DMA_RESET>; 88 reset-names = "dma"; 89 }; 90 }; 91 92 base_fpga_region { 93 compatible = "fpga-region"; 94 fpga-mgr = <&fpgamgr0>; 95 96 #address-cells = <0x1>; 97 #size-cells = <0x1>; 98 }; 99 100 can0: can@ffc00000 { 101 compatible = "bosch,d_can"; 102 reg = <0xffc00000 0x1000>; 103 interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>; 104 clocks = <&can0_clk>; 105 resets = <&rst CAN0_RESET>; 106 status = "disabled"; 107 }; 108 109 can1: can@ffc01000 { 110 compatible = "bosch,d_can"; 111 reg = <0xffc01000 0x1000>; 112 interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>; 113 clocks = <&can1_clk>; 114 resets = <&rst CAN1_RESET>; 115 status = "disabled"; 116 }; 117 118 clkmgr@ffd04000 { 119 compatible = "altr,clk-mgr"; 120 reg = <0xffd04000 0x1000>; 121 122 clocks { 123 #address-cells = <1>; 124 #size-cells = <0>; 125 126 osc1: osc1 { 127 #clock-cells = <0>; 128 compatible = "fixed-clock"; 129 }; 130 131 osc2: osc2 { 132 #clock-cells = <0>; 133 compatible = "fixed-clock"; 134 }; 135 136 f2s_periph_ref_clk: f2s_periph_ref_clk { 137 #clock-cells = <0>; 138 compatible = "fixed-clock"; 139 }; 140 141 f2s_sdram_ref_clk: f2s_sdram_ref_clk { 142 #clock-cells = <0>; 143 compatible = "fixed-clock"; 144 }; 145 146 main_pll: main_pll@40 { 147 #address-cells = <1>; 148 #size-cells = <0>; 149 #clock-cells = <0>; 150 compatible = "altr,socfpga-pll-clock"; 151 clocks = <&osc1>; 152 reg = <0x40>; 153 154 mpuclk: mpuclk@48 { 155 #clock-cells = <0>; 156 compatible = "altr,socfpga-perip-clk"; 157 clocks = <&main_pll>; 158 div-reg = <0xe0 0 9>; 159 reg = <0x48>; 160 }; 161 162 mainclk: mainclk@4c { 163 #clock-cells = <0>; 164 compatible = "altr,socfpga-perip-clk"; 165 clocks = <&main_pll>; 166 div-reg = <0xe4 0 9>; 167 reg = <0x4C>; 168 }; 169 170 dbg_base_clk: dbg_base_clk@50 { 171 #clock-cells = <0>; 172 compatible = "altr,socfpga-perip-clk"; 173 clocks = <&main_pll>, <&osc1>; 174 div-reg = <0xe8 0 9>; 175 reg = <0x50>; 176 }; 177 178 main_qspi_clk: main_qspi_clk@54 { 179 #clock-cells = <0>; 180 compatible = "altr,socfpga-perip-clk"; 181 clocks = <&main_pll>; 182 reg = <0x54>; 183 }; 184 185 main_nand_sdmmc_clk: main_nand_sdmmc_clk@58 { 186 #clock-cells = <0>; 187 compatible = "altr,socfpga-perip-clk"; 188 clocks = <&main_pll>; 189 reg = <0x58>; 190 }; 191 192 cfg_h2f_usr0_clk: cfg_h2f_usr0_clk@5c { 193 #clock-cells = <0>; 194 compatible = "altr,socfpga-perip-clk"; 195 clocks = <&main_pll>; 196 reg = <0x5C>; 197 }; 198 }; 199 200 periph_pll: periph_pll@80 { 201 #address-cells = <1>; 202 #size-cells = <0>; 203 #clock-cells = <0>; 204 compatible = "altr,socfpga-pll-clock"; 205 clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>; 206 reg = <0x80>; 207 208 emac0_clk: emac0_clk@88 { 209 #clock-cells = <0>; 210 compatible = "altr,socfpga-perip-clk"; 211 clocks = <&periph_pll>; 212 reg = <0x88>; 213 }; 214 215 emac1_clk: emac1_clk@8c { 216 #clock-cells = <0>; 217 compatible = "altr,socfpga-perip-clk"; 218 clocks = <&periph_pll>; 219 reg = <0x8C>; 220 }; 221 222 per_qspi_clk: per_qsi_clk@90 { 223 #clock-cells = <0>; 224 compatible = "altr,socfpga-perip-clk"; 225 clocks = <&periph_pll>; 226 reg = <0x90>; 227 }; 228 229 per_nand_mmc_clk: per_nand_mmc_clk@94 { 230 #clock-cells = <0>; 231 compatible = "altr,socfpga-perip-clk"; 232 clocks = <&periph_pll>; 233 reg = <0x94>; 234 }; 235 236 per_base_clk: per_base_clk@98 { 237 #clock-cells = <0>; 238 compatible = "altr,socfpga-perip-clk"; 239 clocks = <&periph_pll>; 240 reg = <0x98>; 241 }; 242 243 h2f_usr1_clk: h2f_usr1_clk@9c { 244 #clock-cells = <0>; 245 compatible = "altr,socfpga-perip-clk"; 246 clocks = <&periph_pll>; 247 reg = <0x9C>; 248 }; 249 }; 250 251 sdram_pll: sdram_pll@c0 { 252 #address-cells = <1>; 253 #size-cells = <0>; 254 #clock-cells = <0>; 255 compatible = "altr,socfpga-pll-clock"; 256 clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>; 257 reg = <0xC0>; 258 259 ddr_dqs_clk: ddr_dqs_clk@c8 { 260 #clock-cells = <0>; 261 compatible = "altr,socfpga-perip-clk"; 262 clocks = <&sdram_pll>; 263 reg = <0xC8>; 264 }; 265 266 ddr_2x_dqs_clk: ddr_2x_dqs_clk@cc { 267 #clock-cells = <0>; 268 compatible = "altr,socfpga-perip-clk"; 269 clocks = <&sdram_pll>; 270 reg = <0xCC>; 271 }; 272 273 ddr_dq_clk: ddr_dq_clk@d0 { 274 #clock-cells = <0>; 275 compatible = "altr,socfpga-perip-clk"; 276 clocks = <&sdram_pll>; 277 reg = <0xD0>; 278 }; 279 280 h2f_usr2_clk: h2f_usr2_clk@d4 { 281 #clock-cells = <0>; 282 compatible = "altr,socfpga-perip-clk"; 283 clocks = <&sdram_pll>; 284 reg = <0xD4>; 285 }; 286 }; 287 288 mpu_periph_clk: mpu_periph_clk { 289 #clock-cells = <0>; 290 compatible = "altr,socfpga-perip-clk"; 291 clocks = <&mpuclk>; 292 fixed-divider = <4>; 293 }; 294 295 mpu_l2_ram_clk: mpu_l2_ram_clk { 296 #clock-cells = <0>; 297 compatible = "altr,socfpga-perip-clk"; 298 clocks = <&mpuclk>; 299 fixed-divider = <2>; 300 }; 301 302 l4_main_clk: l4_main_clk { 303 #clock-cells = <0>; 304 compatible = "altr,socfpga-gate-clk"; 305 clocks = <&mainclk>; 306 clk-gate = <0x60 0>; 307 }; 308 309 l3_main_clk: l3_main_clk { 310 #clock-cells = <0>; 311 compatible = "altr,socfpga-perip-clk"; 312 clocks = <&mainclk>; 313 fixed-divider = <1>; 314 }; 315 316 l3_mp_clk: l3_mp_clk { 317 #clock-cells = <0>; 318 compatible = "altr,socfpga-gate-clk"; 319 clocks = <&mainclk>; 320 div-reg = <0x64 0 2>; 321 clk-gate = <0x60 1>; 322 }; 323 324 l3_sp_clk: l3_sp_clk { 325 #clock-cells = <0>; 326 compatible = "altr,socfpga-gate-clk"; 327 clocks = <&l3_mp_clk>; 328 div-reg = <0x64 2 2>; 329 }; 330 331 l4_mp_clk: l4_mp_clk { 332 #clock-cells = <0>; 333 compatible = "altr,socfpga-gate-clk"; 334 clocks = <&mainclk>, <&per_base_clk>; 335 div-reg = <0x64 4 3>; 336 clk-gate = <0x60 2>; 337 }; 338 339 l4_sp_clk: l4_sp_clk { 340 #clock-cells = <0>; 341 compatible = "altr,socfpga-gate-clk"; 342 clocks = <&mainclk>, <&per_base_clk>; 343 div-reg = <0x64 7 3>; 344 clk-gate = <0x60 3>; 345 }; 346 347 dbg_at_clk: dbg_at_clk { 348 #clock-cells = <0>; 349 compatible = "altr,socfpga-gate-clk"; 350 clocks = <&dbg_base_clk>; 351 div-reg = <0x68 0 2>; 352 clk-gate = <0x60 4>; 353 }; 354 355 dbg_clk: dbg_clk { 356 #clock-cells = <0>; 357 compatible = "altr,socfpga-gate-clk"; 358 clocks = <&dbg_at_clk>; 359 div-reg = <0x68 2 2>; 360 clk-gate = <0x60 5>; 361 }; 362 363 dbg_trace_clk: dbg_trace_clk { 364 #clock-cells = <0>; 365 compatible = "altr,socfpga-gate-clk"; 366 clocks = <&dbg_base_clk>; 367 div-reg = <0x6C 0 3>; 368 clk-gate = <0x60 6>; 369 }; 370 371 dbg_timer_clk: dbg_timer_clk { 372 #clock-cells = <0>; 373 compatible = "altr,socfpga-gate-clk"; 374 clocks = <&dbg_base_clk>; 375 clk-gate = <0x60 7>; 376 }; 377 378 cfg_clk: cfg_clk { 379 #clock-cells = <0>; 380 compatible = "altr,socfpga-gate-clk"; 381 clocks = <&cfg_h2f_usr0_clk>; 382 clk-gate = <0x60 8>; 383 }; 384 385 h2f_user0_clk: h2f_user0_clk { 386 #clock-cells = <0>; 387 compatible = "altr,socfpga-gate-clk"; 388 clocks = <&cfg_h2f_usr0_clk>; 389 clk-gate = <0x60 9>; 390 }; 391 392 emac_0_clk: emac_0_clk { 393 #clock-cells = <0>; 394 compatible = "altr,socfpga-gate-clk"; 395 clocks = <&emac0_clk>; 396 clk-gate = <0xa0 0>; 397 }; 398 399 emac_1_clk: emac_1_clk { 400 #clock-cells = <0>; 401 compatible = "altr,socfpga-gate-clk"; 402 clocks = <&emac1_clk>; 403 clk-gate = <0xa0 1>; 404 }; 405 406 usb_mp_clk: usb_mp_clk { 407 #clock-cells = <0>; 408 compatible = "altr,socfpga-gate-clk"; 409 clocks = <&per_base_clk>; 410 clk-gate = <0xa0 2>; 411 div-reg = <0xa4 0 3>; 412 }; 413 414 spi_m_clk: spi_m_clk { 415 #clock-cells = <0>; 416 compatible = "altr,socfpga-gate-clk"; 417 clocks = <&per_base_clk>; 418 clk-gate = <0xa0 3>; 419 div-reg = <0xa4 3 3>; 420 }; 421 422 can0_clk: can0_clk { 423 #clock-cells = <0>; 424 compatible = "altr,socfpga-gate-clk"; 425 clocks = <&per_base_clk>; 426 clk-gate = <0xa0 4>; 427 div-reg = <0xa4 6 3>; 428 }; 429 430 can1_clk: can1_clk { 431 #clock-cells = <0>; 432 compatible = "altr,socfpga-gate-clk"; 433 clocks = <&per_base_clk>; 434 clk-gate = <0xa0 5>; 435 div-reg = <0xa4 9 3>; 436 }; 437 438 gpio_db_clk: gpio_db_clk { 439 #clock-cells = <0>; 440 compatible = "altr,socfpga-gate-clk"; 441 clocks = <&per_base_clk>; 442 clk-gate = <0xa0 6>; 443 div-reg = <0xa8 0 24>; 444 }; 445 446 h2f_user1_clk: h2f_user1_clk { 447 #clock-cells = <0>; 448 compatible = "altr,socfpga-gate-clk"; 449 clocks = <&h2f_usr1_clk>; 450 clk-gate = <0xa0 7>; 451 }; 452 453 sdmmc_clk: sdmmc_clk { 454 #clock-cells = <0>; 455 compatible = "altr,socfpga-gate-clk"; 456 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; 457 clk-gate = <0xa0 8>; 458 clk-phase = <0 135>; 459 }; 460 461 sdmmc_clk_divided: sdmmc_clk_divided { 462 #clock-cells = <0>; 463 compatible = "altr,socfpga-gate-clk"; 464 clocks = <&sdmmc_clk>; 465 clk-gate = <0xa0 8>; 466 fixed-divider = <4>; 467 }; 468 469 nand_x_clk: nand_x_clk { 470 #clock-cells = <0>; 471 compatible = "altr,socfpga-gate-clk"; 472 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; 473 clk-gate = <0xa0 9>; 474 }; 475 476 nand_ecc_clk: nand_ecc_clk { 477 #clock-cells = <0>; 478 compatible = "altr,socfpga-gate-clk"; 479 clocks = <&nand_x_clk>; 480 clk-gate = <0xa0 9>; 481 }; 482 483 nand_clk: nand_clk { 484 #clock-cells = <0>; 485 compatible = "altr,socfpga-gate-clk"; 486 clocks = <&nand_x_clk>; 487 clk-gate = <0xa0 10>; 488 fixed-divider = <4>; 489 }; 490 491 qspi_clk: qspi_clk { 492 #clock-cells = <0>; 493 compatible = "altr,socfpga-gate-clk"; 494 clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>; 495 clk-gate = <0xa0 11>; 496 }; 497 498 ddr_dqs_clk_gate: ddr_dqs_clk_gate { 499 #clock-cells = <0>; 500 compatible = "altr,socfpga-gate-clk"; 501 clocks = <&ddr_dqs_clk>; 502 clk-gate = <0xd8 0>; 503 }; 504 505 ddr_2x_dqs_clk_gate: ddr_2x_dqs_clk_gate { 506 #clock-cells = <0>; 507 compatible = "altr,socfpga-gate-clk"; 508 clocks = <&ddr_2x_dqs_clk>; 509 clk-gate = <0xd8 1>; 510 }; 511 512 ddr_dq_clk_gate: ddr_dq_clk_gate { 513 #clock-cells = <0>; 514 compatible = "altr,socfpga-gate-clk"; 515 clocks = <&ddr_dq_clk>; 516 clk-gate = <0xd8 2>; 517 }; 518 519 h2f_user2_clk: h2f_user2_clk { 520 #clock-cells = <0>; 521 compatible = "altr,socfpga-gate-clk"; 522 clocks = <&h2f_usr2_clk>; 523 clk-gate = <0xd8 3>; 524 }; 525 526 }; 527 }; 528 529 fpga_bridge0: fpga_bridge@ff400000 { 530 compatible = "altr,socfpga-lwhps2fpga-bridge"; 531 reg = <0xff400000 0x100000>; 532 resets = <&rst LWHPS2FPGA_RESET>; 533 clocks = <&l4_main_clk>; 534 status = "disabled"; 535 }; 536 537 fpga_bridge1: fpga_bridge@ff500000 { 538 compatible = "altr,socfpga-hps2fpga-bridge"; 539 reg = <0xff500000 0x10000>; 540 resets = <&rst HPS2FPGA_RESET>; 541 clocks = <&l4_main_clk>; 542 status = "disabled"; 543 }; 544 545 fpga_bridge2: fpga-bridge@ff600000 { 546 compatible = "altr,socfpga-fpga2hps-bridge"; 547 reg = <0xff600000 0x100000>; 548 resets = <&rst FPGA2HPS_RESET>; 549 clocks = <&l4_main_clk>; 550 status = "disabled"; 551 }; 552 553 fpga_bridge3: fpga-bridge@ffc25080 { 554 compatible = "altr,socfpga-fpga2sdram-bridge"; 555 reg = <0xffc25080 0x4>; 556 status = "disabled"; 557 }; 558 559 fpgamgr0: fpgamgr@ff706000 { 560 compatible = "altr,socfpga-fpga-mgr"; 561 reg = <0xff706000 0x1000 562 0xffb90000 0x4>; 563 interrupts = <0 175 4>; 564 }; 565 566 gmac0: ethernet@ff700000 { 567 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; 568 altr,sysmgr-syscon = <&sysmgr 0x60 0>; 569 reg = <0xff700000 0x2000>; 570 interrupts = <0 115 4>; 571 interrupt-names = "macirq"; 572 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ 573 clocks = <&emac_0_clk>; 574 clock-names = "stmmaceth"; 575 resets = <&rst EMAC0_RESET>; 576 reset-names = "stmmaceth"; 577 snps,multicast-filter-bins = <256>; 578 snps,perfect-filter-entries = <128>; 579 tx-fifo-depth = <4096>; 580 rx-fifo-depth = <4096>; 581 status = "disabled"; 582 }; 583 584 gmac1: ethernet@ff702000 { 585 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; 586 altr,sysmgr-syscon = <&sysmgr 0x60 2>; 587 reg = <0xff702000 0x2000>; 588 interrupts = <0 120 4>; 589 interrupt-names = "macirq"; 590 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ 591 clocks = <&emac_1_clk>; 592 clock-names = "stmmaceth"; 593 resets = <&rst EMAC1_RESET>; 594 reset-names = "stmmaceth"; 595 snps,multicast-filter-bins = <256>; 596 snps,perfect-filter-entries = <128>; 597 tx-fifo-depth = <4096>; 598 rx-fifo-depth = <4096>; 599 status = "disabled"; 600 }; 601 602 gpio0: gpio@ff708000 { 603 #address-cells = <1>; 604 #size-cells = <0>; 605 compatible = "snps,dw-apb-gpio"; 606 reg = <0xff708000 0x1000>; 607 clocks = <&l4_mp_clk>; 608 resets = <&rst GPIO0_RESET>; 609 status = "disabled"; 610 611 porta: gpio-controller@0 { 612 compatible = "snps,dw-apb-gpio-port"; 613 gpio-controller; 614 #gpio-cells = <2>; 615 snps,nr-gpios = <29>; 616 reg = <0>; 617 interrupt-controller; 618 #interrupt-cells = <2>; 619 interrupts = <0 164 4>; 620 }; 621 }; 622 623 gpio1: gpio@ff709000 { 624 #address-cells = <1>; 625 #size-cells = <0>; 626 compatible = "snps,dw-apb-gpio"; 627 reg = <0xff709000 0x1000>; 628 clocks = <&l4_mp_clk>; 629 resets = <&rst GPIO1_RESET>; 630 status = "disabled"; 631 632 portb: gpio-controller@0 { 633 compatible = "snps,dw-apb-gpio-port"; 634 gpio-controller; 635 #gpio-cells = <2>; 636 snps,nr-gpios = <29>; 637 reg = <0>; 638 interrupt-controller; 639 #interrupt-cells = <2>; 640 interrupts = <0 165 4>; 641 }; 642 }; 643 644 gpio2: gpio@ff70a000 { 645 #address-cells = <1>; 646 #size-cells = <0>; 647 compatible = "snps,dw-apb-gpio"; 648 reg = <0xff70a000 0x1000>; 649 clocks = <&l4_mp_clk>; 650 resets = <&rst GPIO2_RESET>; 651 status = "disabled"; 652 653 portc: gpio-controller@0 { 654 compatible = "snps,dw-apb-gpio-port"; 655 gpio-controller; 656 #gpio-cells = <2>; 657 snps,nr-gpios = <27>; 658 reg = <0>; 659 interrupt-controller; 660 #interrupt-cells = <2>; 661 interrupts = <0 166 4>; 662 }; 663 }; 664 665 i2c0: i2c@ffc04000 { 666 #address-cells = <1>; 667 #size-cells = <0>; 668 compatible = "snps,designware-i2c"; 669 reg = <0xffc04000 0x1000>; 670 resets = <&rst I2C0_RESET>; 671 clocks = <&l4_sp_clk>; 672 interrupts = <0 158 0x4>; 673 status = "disabled"; 674 }; 675 676 i2c1: i2c@ffc05000 { 677 #address-cells = <1>; 678 #size-cells = <0>; 679 compatible = "snps,designware-i2c"; 680 reg = <0xffc05000 0x1000>; 681 resets = <&rst I2C1_RESET>; 682 clocks = <&l4_sp_clk>; 683 interrupts = <0 159 0x4>; 684 status = "disabled"; 685 }; 686 687 i2c2: i2c@ffc06000 { 688 #address-cells = <1>; 689 #size-cells = <0>; 690 compatible = "snps,designware-i2c"; 691 reg = <0xffc06000 0x1000>; 692 resets = <&rst I2C2_RESET>; 693 clocks = <&l4_sp_clk>; 694 interrupts = <0 160 0x4>; 695 status = "disabled"; 696 }; 697 698 i2c3: i2c@ffc07000 { 699 #address-cells = <1>; 700 #size-cells = <0>; 701 compatible = "snps,designware-i2c"; 702 reg = <0xffc07000 0x1000>; 703 resets = <&rst I2C3_RESET>; 704 clocks = <&l4_sp_clk>; 705 interrupts = <0 161 0x4>; 706 status = "disabled"; 707 }; 708 709 eccmgr: eccmgr { 710 compatible = "altr,socfpga-ecc-manager"; 711 #address-cells = <1>; 712 #size-cells = <1>; 713 ranges; 714 715 l2-ecc@ffd08140 { 716 compatible = "altr,socfpga-l2-ecc"; 717 reg = <0xffd08140 0x4>; 718 interrupts = <0 36 1>, <0 37 1>; 719 }; 720 721 ocram-ecc@ffd08144 { 722 compatible = "altr,socfpga-ocram-ecc"; 723 reg = <0xffd08144 0x4>; 724 iram = <&ocram>; 725 interrupts = <0 178 1>, <0 179 1>; 726 }; 727 }; 728 729 L2: cache-controller@fffef000 { 730 compatible = "arm,pl310-cache"; 731 reg = <0xfffef000 0x1000>; 732 interrupts = <0 38 0x04>; 733 cache-unified; 734 cache-level = <2>; 735 arm,tag-latency = <1 1 1>; 736 arm,data-latency = <2 1 1>; 737 prefetch-data = <1>; 738 prefetch-instr = <1>; 739 arm,shared-override; 740 arm,double-linefill = <1>; 741 arm,double-linefill-incr = <0>; 742 arm,double-linefill-wrap = <1>; 743 arm,prefetch-drop = <0>; 744 arm,prefetch-offset = <7>; 745 }; 746 747 l3regs@0xff800000 { 748 compatible = "altr,l3regs", "syscon"; 749 reg = <0xff800000 0x1000>; 750 }; 751 752 mmc: dwmmc0@ff704000 { 753 compatible = "altr,socfpga-dw-mshc"; 754 reg = <0xff704000 0x1000>; 755 interrupts = <0 139 4>; 756 fifo-depth = <0x400>; 757 #address-cells = <1>; 758 #size-cells = <0>; 759 clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>; 760 clock-names = "biu", "ciu"; 761 resets = <&rst SDMMC_RESET>; 762 status = "disabled"; 763 }; 764 765 nand0: nand@ff900000 { 766 #address-cells = <0x1>; 767 #size-cells = <0x0>; 768 compatible = "altr,socfpga-denali-nand"; 769 reg = <0xff900000 0x100000>, 770 <0xffb80000 0x10000>; 771 reg-names = "nand_data", "denali_reg"; 772 interrupts = <0x0 0x90 0x4>; 773 clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>; 774 clock-names = "nand", "nand_x", "ecc"; 775 resets = <&rst NAND_RESET>; 776 status = "disabled"; 777 }; 778 779 ocram: sram@ffff0000 { 780 compatible = "mmio-sram"; 781 reg = <0xffff0000 0x10000>; 782 }; 783 784 qspi: spi@ff705000 { 785 compatible = "cdns,qspi-nor"; 786 #address-cells = <1>; 787 #size-cells = <0>; 788 reg = <0xff705000 0x1000>, 789 <0xffa00000 0x1000>; 790 interrupts = <0 151 4>; 791 cdns,fifo-depth = <128>; 792 cdns,fifo-width = <4>; 793 cdns,trigger-address = <0x00000000>; 794 clocks = <&qspi_clk>; 795 resets = <&rst QSPI_RESET>; 796 status = "disabled"; 797 }; 798 799 rst: rstmgr@ffd05000 { 800 #reset-cells = <1>; 801 compatible = "altr,rst-mgr"; 802 reg = <0xffd05000 0x1000>; 803 altr,modrst-offset = <0x10>; 804 }; 805 806 scu: snoop-control-unit@fffec000 { 807 compatible = "arm,cortex-a9-scu"; 808 reg = <0xfffec000 0x100>; 809 }; 810 811 sdr: sdr@ffc25000 { 812 compatible = "altr,sdr-ctl", "syscon"; 813 reg = <0xffc25000 0x1000>; 814 resets = <&rst SDR_RESET>; 815 }; 816 817 sdramedac { 818 compatible = "altr,sdram-edac"; 819 altr,sdr-syscon = <&sdr>; 820 interrupts = <0 39 4>; 821 }; 822 823 spi0: spi@fff00000 { 824 compatible = "snps,dw-apb-ssi"; 825 #address-cells = <1>; 826 #size-cells = <0>; 827 reg = <0xfff00000 0x1000>; 828 interrupts = <0 154 4>; 829 num-cs = <4>; 830 clocks = <&spi_m_clk>; 831 resets = <&rst SPIM0_RESET>; 832 reset-names = "spi"; 833 status = "disabled"; 834 }; 835 836 spi1: spi@fff01000 { 837 compatible = "snps,dw-apb-ssi"; 838 #address-cells = <1>; 839 #size-cells = <0>; 840 reg = <0xfff01000 0x1000>; 841 interrupts = <0 155 4>; 842 num-cs = <4>; 843 clocks = <&spi_m_clk>; 844 resets = <&rst SPIM1_RESET>; 845 reset-names = "spi"; 846 status = "disabled"; 847 }; 848 849 sysmgr: sysmgr@ffd08000 { 850 compatible = "altr,sys-mgr", "syscon"; 851 reg = <0xffd08000 0x4000>; 852 }; 853 854 /* Local timer */ 855 timer@fffec600 { 856 compatible = "arm,cortex-a9-twd-timer"; 857 reg = <0xfffec600 0x100>; 858 interrupts = <1 13 0xf01>; 859 clocks = <&mpu_periph_clk>; 860 }; 861 862 timer0: timer0@ffc08000 { 863 compatible = "snps,dw-apb-timer"; 864 interrupts = <0 167 4>; 865 reg = <0xffc08000 0x1000>; 866 clocks = <&l4_sp_clk>; 867 clock-names = "timer"; 868 resets = <&rst SPTIMER0_RESET>; 869 reset-names = "timer"; 870 }; 871 872 timer1: timer1@ffc09000 { 873 compatible = "snps,dw-apb-timer"; 874 interrupts = <0 168 4>; 875 reg = <0xffc09000 0x1000>; 876 clocks = <&l4_sp_clk>; 877 clock-names = "timer"; 878 resets = <&rst SPTIMER1_RESET>; 879 reset-names = "timer"; 880 }; 881 882 timer2: timer2@ffd00000 { 883 compatible = "snps,dw-apb-timer"; 884 interrupts = <0 169 4>; 885 reg = <0xffd00000 0x1000>; 886 clocks = <&osc1>; 887 clock-names = "timer"; 888 resets = <&rst OSC1TIMER0_RESET>; 889 reset-names = "timer"; 890 }; 891 892 timer3: timer3@ffd01000 { 893 compatible = "snps,dw-apb-timer"; 894 interrupts = <0 170 4>; 895 reg = <0xffd01000 0x1000>; 896 clocks = <&osc1>; 897 clock-names = "timer"; 898 resets = <&rst OSC1TIMER1_RESET>; 899 reset-names = "timer"; 900 }; 901 902 uart0: serial0@ffc02000 { 903 compatible = "snps,dw-apb-uart"; 904 reg = <0xffc02000 0x1000>; 905 interrupts = <0 162 4>; 906 reg-shift = <2>; 907 reg-io-width = <4>; 908 clocks = <&l4_sp_clk>; 909 dmas = <&pdma 28>, 910 <&pdma 29>; 911 dma-names = "tx", "rx"; 912 resets = <&rst UART0_RESET>; 913 }; 914 915 uart1: serial1@ffc03000 { 916 compatible = "snps,dw-apb-uart"; 917 reg = <0xffc03000 0x1000>; 918 interrupts = <0 163 4>; 919 reg-shift = <2>; 920 reg-io-width = <4>; 921 clocks = <&l4_sp_clk>; 922 dmas = <&pdma 30>, 923 <&pdma 31>; 924 dma-names = "tx", "rx"; 925 resets = <&rst UART1_RESET>; 926 }; 927 928 usbphy0: usbphy { 929 #phy-cells = <0>; 930 compatible = "usb-nop-xceiv"; 931 status = "okay"; 932 }; 933 934 usb0: usb@ffb00000 { 935 compatible = "snps,dwc2"; 936 reg = <0xffb00000 0xffff>; 937 interrupts = <0 125 4>; 938 clocks = <&usb_mp_clk>; 939 clock-names = "otg"; 940 resets = <&rst USB0_RESET>; 941 reset-names = "dwc2"; 942 phys = <&usbphy0>; 943 phy-names = "usb2-phy"; 944 status = "disabled"; 945 }; 946 947 usb1: usb@ffb40000 { 948 compatible = "snps,dwc2"; 949 reg = <0xffb40000 0xffff>; 950 interrupts = <0 128 4>; 951 clocks = <&usb_mp_clk>; 952 clock-names = "otg"; 953 resets = <&rst USB1_RESET>; 954 reset-names = "dwc2"; 955 phys = <&usbphy0>; 956 phy-names = "usb2-phy"; 957 status = "disabled"; 958 }; 959 960 watchdog0: watchdog@ffd02000 { 961 compatible = "snps,dw-wdt"; 962 reg = <0xffd02000 0x1000>; 963 interrupts = <0 171 4>; 964 clocks = <&osc1>; 965 resets = <&rst L4WD0_RESET>; 966 status = "disabled"; 967 }; 968 969 watchdog1: watchdog@ffd03000 { 970 compatible = "snps,dw-wdt"; 971 reg = <0xffd03000 0x1000>; 972 interrupts = <0 172 4>; 973 clocks = <&osc1>; 974 resets = <&rst L4WD1_RESET>; 975 status = "disabled"; 976 }; 977 }; 978}; 979
