1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
4 * Ethernet adapters. Based on earlier sk98lin, e100 and
5 * FreeBSD if_sk drivers.
6 *
7 * This driver intentionally does not support all the features
8 * of the original driver such as link fail-over and link management because
9 * those should be done at higher levels.
10 *
11 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
12 */
13
14 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15
16 #include <linux/in.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/netdevice.h>
21 #include <linux/etherdevice.h>
22 #include <linux/ethtool.h>
23 #include <linux/pci.h>
24 #include <linux/if_vlan.h>
25 #include <linux/ip.h>
26 #include <linux/delay.h>
27 #include <linux/crc32.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/debugfs.h>
30 #include <linux/sched.h>
31 #include <linux/seq_file.h>
32 #include <linux/mii.h>
33 #include <linux/slab.h>
34 #include <linux/dmi.h>
35 #include <linux/prefetch.h>
36 #include <asm/irq.h>
37
38 #include "skge.h"
39
40 #define DRV_NAME "skge"
41 #define DRV_VERSION "1.14"
42
43 #define DEFAULT_TX_RING_SIZE 128
44 #define DEFAULT_RX_RING_SIZE 512
45 #define MAX_TX_RING_SIZE 1024
46 #define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
47 #define MAX_RX_RING_SIZE 4096
48 #define RX_COPY_THRESHOLD 128
49 #define RX_BUF_SIZE 1536
50 #define PHY_RETRIES 1000
51 #define ETH_JUMBO_MTU 9000
52 #define TX_WATCHDOG (5 * HZ)
53 #define NAPI_WEIGHT 64
54 #define BLINK_MS 250
55 #define LINK_HZ HZ
56
57 #define SKGE_EEPROM_MAGIC 0x9933aabb
58
59
60 MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
61 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
62 MODULE_LICENSE("GPL");
63 MODULE_VERSION(DRV_VERSION);
64
65 static const u32 default_msg = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
66 NETIF_MSG_LINK | NETIF_MSG_IFUP |
67 NETIF_MSG_IFDOWN);
68
69 static int debug = -1; /* defaults above */
70 module_param(debug, int, 0);
71 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
72
73 static const struct pci_device_id skge_id_table[] = {
74 { PCI_DEVICE(PCI_VENDOR_ID_3COM, 0x1700) }, /* 3Com 3C940 */
75 { PCI_DEVICE(PCI_VENDOR_ID_3COM, 0x80EB) }, /* 3Com 3C940B */
76 #ifdef CONFIG_SKGE_GENESIS
77 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x4300) }, /* SK-9xx */
78 #endif
79 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x4320) }, /* SK-98xx V2.0 */
80 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* D-Link DGE-530T (rev.B) */
81 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4c00) }, /* D-Link DGE-530T */
82 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302) }, /* D-Link DGE-530T Rev C1 */
83 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) }, /* Marvell Yukon 88E8001/8003/8010 */
84 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
85 { PCI_DEVICE(PCI_VENDOR_ID_CNET, 0x434E) }, /* CNet PowerG-2000 */
86 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, 0x1064) }, /* Linksys EG1064 v2 */
87 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015 }, /* Linksys EG1032 v2 */
88 { 0 }
89 };
90 MODULE_DEVICE_TABLE(pci, skge_id_table);
91
92 static int skge_up(struct net_device *dev);
93 static int skge_down(struct net_device *dev);
94 static void skge_phy_reset(struct skge_port *skge);
95 static void skge_tx_clean(struct net_device *dev);
96 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
97 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
98 static void genesis_get_stats(struct skge_port *skge, u64 *data);
99 static void yukon_get_stats(struct skge_port *skge, u64 *data);
100 static void yukon_init(struct skge_hw *hw, int port);
101 static void genesis_mac_init(struct skge_hw *hw, int port);
102 static void genesis_link_up(struct skge_port *skge);
103 static void skge_set_multicast(struct net_device *dev);
104 static irqreturn_t skge_intr(int irq, void *dev_id);
105
106 /* Avoid conditionals by using array */
107 static const int txqaddr[] = { Q_XA1, Q_XA2 };
108 static const int rxqaddr[] = { Q_R1, Q_R2 };
109 static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
110 static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
111 static const u32 napimask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F };
112 static const u32 portmask[] = { IS_PORT_1, IS_PORT_2 };
113
is_genesis(const struct skge_hw * hw)114 static inline bool is_genesis(const struct skge_hw *hw)
115 {
116 #ifdef CONFIG_SKGE_GENESIS
117 return hw->chip_id == CHIP_ID_GENESIS;
118 #else
119 return false;
120 #endif
121 }
122
skge_get_regs_len(struct net_device * dev)123 static int skge_get_regs_len(struct net_device *dev)
124 {
125 return 0x4000;
126 }
127
128 /*
129 * Returns copy of whole control register region
130 * Note: skip RAM address register because accessing it will
131 * cause bus hangs!
132 */
skge_get_regs(struct net_device * dev,struct ethtool_regs * regs,void * p)133 static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
134 void *p)
135 {
136 const struct skge_port *skge = netdev_priv(dev);
137 const void __iomem *io = skge->hw->regs;
138
139 regs->version = 1;
140 memset(p, 0, regs->len);
141 memcpy_fromio(p, io, B3_RAM_ADDR);
142
143 if (regs->len > B3_RI_WTO_R1) {
144 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
145 regs->len - B3_RI_WTO_R1);
146 }
147 }
148
149 /* Wake on Lan only supported on Yukon chips with rev 1 or above */
wol_supported(const struct skge_hw * hw)150 static u32 wol_supported(const struct skge_hw *hw)
151 {
152 if (is_genesis(hw))
153 return 0;
154
155 if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
156 return 0;
157
158 return WAKE_MAGIC | WAKE_PHY;
159 }
160
skge_wol_init(struct skge_port * skge)161 static void skge_wol_init(struct skge_port *skge)
162 {
163 struct skge_hw *hw = skge->hw;
164 int port = skge->port;
165 u16 ctrl;
166
167 skge_write16(hw, B0_CTST, CS_RST_CLR);
168 skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
169
170 /* Turn on Vaux */
171 skge_write8(hw, B0_POWER_CTRL,
172 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
173
174 /* WA code for COMA mode -- clear PHY reset */
175 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
176 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
177 u32 reg = skge_read32(hw, B2_GP_IO);
178 reg |= GP_DIR_9;
179 reg &= ~GP_IO_9;
180 skge_write32(hw, B2_GP_IO, reg);
181 }
182
183 skge_write32(hw, SK_REG(port, GPHY_CTRL),
184 GPC_DIS_SLEEP |
185 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
186 GPC_ANEG_1 | GPC_RST_SET);
187
188 skge_write32(hw, SK_REG(port, GPHY_CTRL),
189 GPC_DIS_SLEEP |
190 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
191 GPC_ANEG_1 | GPC_RST_CLR);
192
193 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
194
195 /* Force to 10/100 skge_reset will re-enable on resume */
196 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
197 (PHY_AN_100FULL | PHY_AN_100HALF |
198 PHY_AN_10FULL | PHY_AN_10HALF | PHY_AN_CSMA));
199 /* no 1000 HD/FD */
200 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, 0);
201 gm_phy_write(hw, port, PHY_MARV_CTRL,
202 PHY_CT_RESET | PHY_CT_SPS_LSB | PHY_CT_ANE |
203 PHY_CT_RE_CFG | PHY_CT_DUP_MD);
204
205
206 /* Set GMAC to no flow control and auto update for speed/duplex */
207 gma_write16(hw, port, GM_GP_CTRL,
208 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
209 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
210
211 /* Set WOL address */
212 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
213 skge->netdev->dev_addr, ETH_ALEN);
214
215 /* Turn on appropriate WOL control bits */
216 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
217 ctrl = 0;
218 if (skge->wol & WAKE_PHY)
219 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
220 else
221 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
222
223 if (skge->wol & WAKE_MAGIC)
224 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
225 else
226 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
227
228 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
229 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
230
231 /* block receiver */
232 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
233 }
234
skge_get_wol(struct net_device * dev,struct ethtool_wolinfo * wol)235 static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
236 {
237 struct skge_port *skge = netdev_priv(dev);
238
239 wol->supported = wol_supported(skge->hw);
240 wol->wolopts = skge->wol;
241 }
242
skge_set_wol(struct net_device * dev,struct ethtool_wolinfo * wol)243 static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
244 {
245 struct skge_port *skge = netdev_priv(dev);
246 struct skge_hw *hw = skge->hw;
247
248 if ((wol->wolopts & ~wol_supported(hw)) ||
249 !device_can_wakeup(&hw->pdev->dev))
250 return -EOPNOTSUPP;
251
252 skge->wol = wol->wolopts;
253
254 device_set_wakeup_enable(&hw->pdev->dev, skge->wol);
255
256 return 0;
257 }
258
259 /* Determine supported/advertised modes based on hardware.
260 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
261 */
skge_supported_modes(const struct skge_hw * hw)262 static u32 skge_supported_modes(const struct skge_hw *hw)
263 {
264 u32 supported;
265
266 if (hw->copper) {
267 supported = (SUPPORTED_10baseT_Half |
268 SUPPORTED_10baseT_Full |
269 SUPPORTED_100baseT_Half |
270 SUPPORTED_100baseT_Full |
271 SUPPORTED_1000baseT_Half |
272 SUPPORTED_1000baseT_Full |
273 SUPPORTED_Autoneg |
274 SUPPORTED_TP);
275
276 if (is_genesis(hw))
277 supported &= ~(SUPPORTED_10baseT_Half |
278 SUPPORTED_10baseT_Full |
279 SUPPORTED_100baseT_Half |
280 SUPPORTED_100baseT_Full);
281
282 else if (hw->chip_id == CHIP_ID_YUKON)
283 supported &= ~SUPPORTED_1000baseT_Half;
284 } else
285 supported = (SUPPORTED_1000baseT_Full |
286 SUPPORTED_1000baseT_Half |
287 SUPPORTED_FIBRE |
288 SUPPORTED_Autoneg);
289
290 return supported;
291 }
292
skge_get_link_ksettings(struct net_device * dev,struct ethtool_link_ksettings * cmd)293 static int skge_get_link_ksettings(struct net_device *dev,
294 struct ethtool_link_ksettings *cmd)
295 {
296 struct skge_port *skge = netdev_priv(dev);
297 struct skge_hw *hw = skge->hw;
298 u32 supported, advertising;
299
300 supported = skge_supported_modes(hw);
301
302 if (hw->copper) {
303 cmd->base.port = PORT_TP;
304 cmd->base.phy_address = hw->phy_addr;
305 } else
306 cmd->base.port = PORT_FIBRE;
307
308 advertising = skge->advertising;
309 cmd->base.autoneg = skge->autoneg;
310 cmd->base.speed = skge->speed;
311 cmd->base.duplex = skge->duplex;
312
313 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
314 supported);
315 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
316 advertising);
317
318 return 0;
319 }
320
skge_set_link_ksettings(struct net_device * dev,const struct ethtool_link_ksettings * cmd)321 static int skge_set_link_ksettings(struct net_device *dev,
322 const struct ethtool_link_ksettings *cmd)
323 {
324 struct skge_port *skge = netdev_priv(dev);
325 const struct skge_hw *hw = skge->hw;
326 u32 supported = skge_supported_modes(hw);
327 int err = 0;
328 u32 advertising;
329
330 ethtool_convert_link_mode_to_legacy_u32(&advertising,
331 cmd->link_modes.advertising);
332
333 if (cmd->base.autoneg == AUTONEG_ENABLE) {
334 advertising = supported;
335 skge->duplex = -1;
336 skge->speed = -1;
337 } else {
338 u32 setting;
339 u32 speed = cmd->base.speed;
340
341 switch (speed) {
342 case SPEED_1000:
343 if (cmd->base.duplex == DUPLEX_FULL)
344 setting = SUPPORTED_1000baseT_Full;
345 else if (cmd->base.duplex == DUPLEX_HALF)
346 setting = SUPPORTED_1000baseT_Half;
347 else
348 return -EINVAL;
349 break;
350 case SPEED_100:
351 if (cmd->base.duplex == DUPLEX_FULL)
352 setting = SUPPORTED_100baseT_Full;
353 else if (cmd->base.duplex == DUPLEX_HALF)
354 setting = SUPPORTED_100baseT_Half;
355 else
356 return -EINVAL;
357 break;
358
359 case SPEED_10:
360 if (cmd->base.duplex == DUPLEX_FULL)
361 setting = SUPPORTED_10baseT_Full;
362 else if (cmd->base.duplex == DUPLEX_HALF)
363 setting = SUPPORTED_10baseT_Half;
364 else
365 return -EINVAL;
366 break;
367 default:
368 return -EINVAL;
369 }
370
371 if ((setting & supported) == 0)
372 return -EINVAL;
373
374 skge->speed = speed;
375 skge->duplex = cmd->base.duplex;
376 }
377
378 skge->autoneg = cmd->base.autoneg;
379 skge->advertising = advertising;
380
381 if (netif_running(dev)) {
382 skge_down(dev);
383 err = skge_up(dev);
384 if (err) {
385 dev_close(dev);
386 return err;
387 }
388 }
389
390 return 0;
391 }
392
skge_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * info)393 static void skge_get_drvinfo(struct net_device *dev,
394 struct ethtool_drvinfo *info)
395 {
396 struct skge_port *skge = netdev_priv(dev);
397
398 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
399 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
400 strlcpy(info->bus_info, pci_name(skge->hw->pdev),
401 sizeof(info->bus_info));
402 }
403
404 static const struct skge_stat {
405 char name[ETH_GSTRING_LEN];
406 u16 xmac_offset;
407 u16 gma_offset;
408 } skge_stats[] = {
409 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
410 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
411
412 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
413 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
414 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
415 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
416 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
417 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
418 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
419 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
420
421 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
422 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
423 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
424 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
425 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
426 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
427
428 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
429 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
430 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
431 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
432 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
433 };
434
skge_get_sset_count(struct net_device * dev,int sset)435 static int skge_get_sset_count(struct net_device *dev, int sset)
436 {
437 switch (sset) {
438 case ETH_SS_STATS:
439 return ARRAY_SIZE(skge_stats);
440 default:
441 return -EOPNOTSUPP;
442 }
443 }
444
skge_get_ethtool_stats(struct net_device * dev,struct ethtool_stats * stats,u64 * data)445 static void skge_get_ethtool_stats(struct net_device *dev,
446 struct ethtool_stats *stats, u64 *data)
447 {
448 struct skge_port *skge = netdev_priv(dev);
449
450 if (is_genesis(skge->hw))
451 genesis_get_stats(skge, data);
452 else
453 yukon_get_stats(skge, data);
454 }
455
456 /* Use hardware MIB variables for critical path statistics and
457 * transmit feedback not reported at interrupt.
458 * Other errors are accounted for in interrupt handler.
459 */
skge_get_stats(struct net_device * dev)460 static struct net_device_stats *skge_get_stats(struct net_device *dev)
461 {
462 struct skge_port *skge = netdev_priv(dev);
463 u64 data[ARRAY_SIZE(skge_stats)];
464
465 if (is_genesis(skge->hw))
466 genesis_get_stats(skge, data);
467 else
468 yukon_get_stats(skge, data);
469
470 dev->stats.tx_bytes = data[0];
471 dev->stats.rx_bytes = data[1];
472 dev->stats.tx_packets = data[2] + data[4] + data[6];
473 dev->stats.rx_packets = data[3] + data[5] + data[7];
474 dev->stats.multicast = data[3] + data[5];
475 dev->stats.collisions = data[10];
476 dev->stats.tx_aborted_errors = data[12];
477
478 return &dev->stats;
479 }
480
skge_get_strings(struct net_device * dev,u32 stringset,u8 * data)481 static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
482 {
483 int i;
484
485 switch (stringset) {
486 case ETH_SS_STATS:
487 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
488 memcpy(data + i * ETH_GSTRING_LEN,
489 skge_stats[i].name, ETH_GSTRING_LEN);
490 break;
491 }
492 }
493
skge_get_ring_param(struct net_device * dev,struct ethtool_ringparam * p)494 static void skge_get_ring_param(struct net_device *dev,
495 struct ethtool_ringparam *p)
496 {
497 struct skge_port *skge = netdev_priv(dev);
498
499 p->rx_max_pending = MAX_RX_RING_SIZE;
500 p->tx_max_pending = MAX_TX_RING_SIZE;
501
502 p->rx_pending = skge->rx_ring.count;
503 p->tx_pending = skge->tx_ring.count;
504 }
505
skge_set_ring_param(struct net_device * dev,struct ethtool_ringparam * p)506 static int skge_set_ring_param(struct net_device *dev,
507 struct ethtool_ringparam *p)
508 {
509 struct skge_port *skge = netdev_priv(dev);
510 int err = 0;
511
512 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
513 p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE)
514 return -EINVAL;
515
516 skge->rx_ring.count = p->rx_pending;
517 skge->tx_ring.count = p->tx_pending;
518
519 if (netif_running(dev)) {
520 skge_down(dev);
521 err = skge_up(dev);
522 if (err)
523 dev_close(dev);
524 }
525
526 return err;
527 }
528
skge_get_msglevel(struct net_device * netdev)529 static u32 skge_get_msglevel(struct net_device *netdev)
530 {
531 struct skge_port *skge = netdev_priv(netdev);
532 return skge->msg_enable;
533 }
534
skge_set_msglevel(struct net_device * netdev,u32 value)535 static void skge_set_msglevel(struct net_device *netdev, u32 value)
536 {
537 struct skge_port *skge = netdev_priv(netdev);
538 skge->msg_enable = value;
539 }
540
skge_nway_reset(struct net_device * dev)541 static int skge_nway_reset(struct net_device *dev)
542 {
543 struct skge_port *skge = netdev_priv(dev);
544
545 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
546 return -EINVAL;
547
548 skge_phy_reset(skge);
549 return 0;
550 }
551
skge_get_pauseparam(struct net_device * dev,struct ethtool_pauseparam * ecmd)552 static void skge_get_pauseparam(struct net_device *dev,
553 struct ethtool_pauseparam *ecmd)
554 {
555 struct skge_port *skge = netdev_priv(dev);
556
557 ecmd->rx_pause = ((skge->flow_control == FLOW_MODE_SYMMETRIC) ||
558 (skge->flow_control == FLOW_MODE_SYM_OR_REM));
559 ecmd->tx_pause = (ecmd->rx_pause ||
560 (skge->flow_control == FLOW_MODE_LOC_SEND));
561
562 ecmd->autoneg = ecmd->rx_pause || ecmd->tx_pause;
563 }
564
skge_set_pauseparam(struct net_device * dev,struct ethtool_pauseparam * ecmd)565 static int skge_set_pauseparam(struct net_device *dev,
566 struct ethtool_pauseparam *ecmd)
567 {
568 struct skge_port *skge = netdev_priv(dev);
569 struct ethtool_pauseparam old;
570 int err = 0;
571
572 skge_get_pauseparam(dev, &old);
573
574 if (ecmd->autoneg != old.autoneg)
575 skge->flow_control = ecmd->autoneg ? FLOW_MODE_NONE : FLOW_MODE_SYMMETRIC;
576 else {
577 if (ecmd->rx_pause && ecmd->tx_pause)
578 skge->flow_control = FLOW_MODE_SYMMETRIC;
579 else if (ecmd->rx_pause && !ecmd->tx_pause)
580 skge->flow_control = FLOW_MODE_SYM_OR_REM;
581 else if (!ecmd->rx_pause && ecmd->tx_pause)
582 skge->flow_control = FLOW_MODE_LOC_SEND;
583 else
584 skge->flow_control = FLOW_MODE_NONE;
585 }
586
587 if (netif_running(dev)) {
588 skge_down(dev);
589 err = skge_up(dev);
590 if (err) {
591 dev_close(dev);
592 return err;
593 }
594 }
595
596 return 0;
597 }
598
599 /* Chip internal frequency for clock calculations */
hwkhz(const struct skge_hw * hw)600 static inline u32 hwkhz(const struct skge_hw *hw)
601 {
602 return is_genesis(hw) ? 53125 : 78125;
603 }
604
605 /* Chip HZ to microseconds */
skge_clk2usec(const struct skge_hw * hw,u32 ticks)606 static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
607 {
608 return (ticks * 1000) / hwkhz(hw);
609 }
610
611 /* Microseconds to chip HZ */
skge_usecs2clk(const struct skge_hw * hw,u32 usec)612 static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
613 {
614 return hwkhz(hw) * usec / 1000;
615 }
616
skge_get_coalesce(struct net_device * dev,struct ethtool_coalesce * ecmd,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)617 static int skge_get_coalesce(struct net_device *dev,
618 struct ethtool_coalesce *ecmd,
619 struct kernel_ethtool_coalesce *kernel_coal,
620 struct netlink_ext_ack *extack)
621 {
622 struct skge_port *skge = netdev_priv(dev);
623 struct skge_hw *hw = skge->hw;
624 int port = skge->port;
625
626 ecmd->rx_coalesce_usecs = 0;
627 ecmd->tx_coalesce_usecs = 0;
628
629 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
630 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
631 u32 msk = skge_read32(hw, B2_IRQM_MSK);
632
633 if (msk & rxirqmask[port])
634 ecmd->rx_coalesce_usecs = delay;
635 if (msk & txirqmask[port])
636 ecmd->tx_coalesce_usecs = delay;
637 }
638
639 return 0;
640 }
641
642 /* Note: interrupt timer is per board, but can turn on/off per port */
skge_set_coalesce(struct net_device * dev,struct ethtool_coalesce * ecmd,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)643 static int skge_set_coalesce(struct net_device *dev,
644 struct ethtool_coalesce *ecmd,
645 struct kernel_ethtool_coalesce *kernel_coal,
646 struct netlink_ext_ack *extack)
647 {
648 struct skge_port *skge = netdev_priv(dev);
649 struct skge_hw *hw = skge->hw;
650 int port = skge->port;
651 u32 msk = skge_read32(hw, B2_IRQM_MSK);
652 u32 delay = 25;
653
654 if (ecmd->rx_coalesce_usecs == 0)
655 msk &= ~rxirqmask[port];
656 else if (ecmd->rx_coalesce_usecs < 25 ||
657 ecmd->rx_coalesce_usecs > 33333)
658 return -EINVAL;
659 else {
660 msk |= rxirqmask[port];
661 delay = ecmd->rx_coalesce_usecs;
662 }
663
664 if (ecmd->tx_coalesce_usecs == 0)
665 msk &= ~txirqmask[port];
666 else if (ecmd->tx_coalesce_usecs < 25 ||
667 ecmd->tx_coalesce_usecs > 33333)
668 return -EINVAL;
669 else {
670 msk |= txirqmask[port];
671 delay = min(delay, ecmd->rx_coalesce_usecs);
672 }
673
674 skge_write32(hw, B2_IRQM_MSK, msk);
675 if (msk == 0)
676 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
677 else {
678 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
679 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
680 }
681 return 0;
682 }
683
684 enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
skge_led(struct skge_port * skge,enum led_mode mode)685 static void skge_led(struct skge_port *skge, enum led_mode mode)
686 {
687 struct skge_hw *hw = skge->hw;
688 int port = skge->port;
689
690 spin_lock_bh(&hw->phy_lock);
691 if (is_genesis(hw)) {
692 switch (mode) {
693 case LED_MODE_OFF:
694 if (hw->phy_type == SK_PHY_BCOM)
695 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
696 else {
697 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
698 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
699 }
700 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
701 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
702 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
703 break;
704
705 case LED_MODE_ON:
706 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
707 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
708
709 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
710 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
711
712 break;
713
714 case LED_MODE_TST:
715 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
716 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
717 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
718
719 if (hw->phy_type == SK_PHY_BCOM)
720 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
721 else {
722 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
723 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
724 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
725 }
726
727 }
728 } else {
729 switch (mode) {
730 case LED_MODE_OFF:
731 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
732 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
733 PHY_M_LED_MO_DUP(MO_LED_OFF) |
734 PHY_M_LED_MO_10(MO_LED_OFF) |
735 PHY_M_LED_MO_100(MO_LED_OFF) |
736 PHY_M_LED_MO_1000(MO_LED_OFF) |
737 PHY_M_LED_MO_RX(MO_LED_OFF));
738 break;
739 case LED_MODE_ON:
740 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
741 PHY_M_LED_PULS_DUR(PULS_170MS) |
742 PHY_M_LED_BLINK_RT(BLINK_84MS) |
743 PHY_M_LEDC_TX_CTRL |
744 PHY_M_LEDC_DP_CTRL);
745
746 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
747 PHY_M_LED_MO_RX(MO_LED_OFF) |
748 (skge->speed == SPEED_100 ?
749 PHY_M_LED_MO_100(MO_LED_ON) : 0));
750 break;
751 case LED_MODE_TST:
752 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
753 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
754 PHY_M_LED_MO_DUP(MO_LED_ON) |
755 PHY_M_LED_MO_10(MO_LED_ON) |
756 PHY_M_LED_MO_100(MO_LED_ON) |
757 PHY_M_LED_MO_1000(MO_LED_ON) |
758 PHY_M_LED_MO_RX(MO_LED_ON));
759 }
760 }
761 spin_unlock_bh(&hw->phy_lock);
762 }
763
764 /* blink LED's for finding board */
skge_set_phys_id(struct net_device * dev,enum ethtool_phys_id_state state)765 static int skge_set_phys_id(struct net_device *dev,
766 enum ethtool_phys_id_state state)
767 {
768 struct skge_port *skge = netdev_priv(dev);
769
770 switch (state) {
771 case ETHTOOL_ID_ACTIVE:
772 return 2; /* cycle on/off twice per second */
773
774 case ETHTOOL_ID_ON:
775 skge_led(skge, LED_MODE_TST);
776 break;
777
778 case ETHTOOL_ID_OFF:
779 skge_led(skge, LED_MODE_OFF);
780 break;
781
782 case ETHTOOL_ID_INACTIVE:
783 /* back to regular LED state */
784 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
785 }
786
787 return 0;
788 }
789
skge_get_eeprom_len(struct net_device * dev)790 static int skge_get_eeprom_len(struct net_device *dev)
791 {
792 struct skge_port *skge = netdev_priv(dev);
793 u32 reg2;
794
795 pci_read_config_dword(skge->hw->pdev, PCI_DEV_REG2, ®2);
796 return 1 << (((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
797 }
798
skge_vpd_read(struct pci_dev * pdev,int cap,u16 offset)799 static u32 skge_vpd_read(struct pci_dev *pdev, int cap, u16 offset)
800 {
801 u32 val;
802
803 pci_write_config_word(pdev, cap + PCI_VPD_ADDR, offset);
804
805 do {
806 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
807 } while (!(offset & PCI_VPD_ADDR_F));
808
809 pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &val);
810 return val;
811 }
812
skge_vpd_write(struct pci_dev * pdev,int cap,u16 offset,u32 val)813 static void skge_vpd_write(struct pci_dev *pdev, int cap, u16 offset, u32 val)
814 {
815 pci_write_config_dword(pdev, cap + PCI_VPD_DATA, val);
816 pci_write_config_word(pdev, cap + PCI_VPD_ADDR,
817 offset | PCI_VPD_ADDR_F);
818
819 do {
820 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
821 } while (offset & PCI_VPD_ADDR_F);
822 }
823
skge_get_eeprom(struct net_device * dev,struct ethtool_eeprom * eeprom,u8 * data)824 static int skge_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
825 u8 *data)
826 {
827 struct skge_port *skge = netdev_priv(dev);
828 struct pci_dev *pdev = skge->hw->pdev;
829 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
830 int length = eeprom->len;
831 u16 offset = eeprom->offset;
832
833 if (!cap)
834 return -EINVAL;
835
836 eeprom->magic = SKGE_EEPROM_MAGIC;
837
838 while (length > 0) {
839 u32 val = skge_vpd_read(pdev, cap, offset);
840 int n = min_t(int, length, sizeof(val));
841
842 memcpy(data, &val, n);
843 length -= n;
844 data += n;
845 offset += n;
846 }
847 return 0;
848 }
849
skge_set_eeprom(struct net_device * dev,struct ethtool_eeprom * eeprom,u8 * data)850 static int skge_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
851 u8 *data)
852 {
853 struct skge_port *skge = netdev_priv(dev);
854 struct pci_dev *pdev = skge->hw->pdev;
855 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
856 int length = eeprom->len;
857 u16 offset = eeprom->offset;
858
859 if (!cap)
860 return -EINVAL;
861
862 if (eeprom->magic != SKGE_EEPROM_MAGIC)
863 return -EINVAL;
864
865 while (length > 0) {
866 u32 val;
867 int n = min_t(int, length, sizeof(val));
868
869 if (n < sizeof(val))
870 val = skge_vpd_read(pdev, cap, offset);
871 memcpy(&val, data, n);
872
873 skge_vpd_write(pdev, cap, offset, val);
874
875 length -= n;
876 data += n;
877 offset += n;
878 }
879 return 0;
880 }
881
882 static const struct ethtool_ops skge_ethtool_ops = {
883 .supported_coalesce_params = ETHTOOL_COALESCE_USECS,
884 .get_drvinfo = skge_get_drvinfo,
885 .get_regs_len = skge_get_regs_len,
886 .get_regs = skge_get_regs,
887 .get_wol = skge_get_wol,
888 .set_wol = skge_set_wol,
889 .get_msglevel = skge_get_msglevel,
890 .set_msglevel = skge_set_msglevel,
891 .nway_reset = skge_nway_reset,
892 .get_link = ethtool_op_get_link,
893 .get_eeprom_len = skge_get_eeprom_len,
894 .get_eeprom = skge_get_eeprom,
895 .set_eeprom = skge_set_eeprom,
896 .get_ringparam = skge_get_ring_param,
897 .set_ringparam = skge_set_ring_param,
898 .get_pauseparam = skge_get_pauseparam,
899 .set_pauseparam = skge_set_pauseparam,
900 .get_coalesce = skge_get_coalesce,
901 .set_coalesce = skge_set_coalesce,
902 .get_strings = skge_get_strings,
903 .set_phys_id = skge_set_phys_id,
904 .get_sset_count = skge_get_sset_count,
905 .get_ethtool_stats = skge_get_ethtool_stats,
906 .get_link_ksettings = skge_get_link_ksettings,
907 .set_link_ksettings = skge_set_link_ksettings,
908 };
909
910 /*
911 * Allocate ring elements and chain them together
912 * One-to-one association of board descriptors with ring elements
913 */
skge_ring_alloc(struct skge_ring * ring,void * vaddr,u32 base)914 static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
915 {
916 struct skge_tx_desc *d;
917 struct skge_element *e;
918 int i;
919
920 ring->start = kcalloc(ring->count, sizeof(*e), GFP_KERNEL);
921 if (!ring->start)
922 return -ENOMEM;
923
924 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
925 e->desc = d;
926 if (i == ring->count - 1) {
927 e->next = ring->start;
928 d->next_offset = base;
929 } else {
930 e->next = e + 1;
931 d->next_offset = base + (i+1) * sizeof(*d);
932 }
933 }
934 ring->to_use = ring->to_clean = ring->start;
935
936 return 0;
937 }
938
939 /* Allocate and setup a new buffer for receiving */
skge_rx_setup(struct skge_port * skge,struct skge_element * e,struct sk_buff * skb,unsigned int bufsize)940 static int skge_rx_setup(struct skge_port *skge, struct skge_element *e,
941 struct sk_buff *skb, unsigned int bufsize)
942 {
943 struct skge_rx_desc *rd = e->desc;
944 dma_addr_t map;
945
946 map = dma_map_single(&skge->hw->pdev->dev, skb->data, bufsize,
947 DMA_FROM_DEVICE);
948
949 if (dma_mapping_error(&skge->hw->pdev->dev, map))
950 return -1;
951
952 rd->dma_lo = lower_32_bits(map);
953 rd->dma_hi = upper_32_bits(map);
954 e->skb = skb;
955 rd->csum1_start = ETH_HLEN;
956 rd->csum2_start = ETH_HLEN;
957 rd->csum1 = 0;
958 rd->csum2 = 0;
959
960 wmb();
961
962 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
963 dma_unmap_addr_set(e, mapaddr, map);
964 dma_unmap_len_set(e, maplen, bufsize);
965 return 0;
966 }
967
968 /* Resume receiving using existing skb,
969 * Note: DMA address is not changed by chip.
970 * MTU not changed while receiver active.
971 */
skge_rx_reuse(struct skge_element * e,unsigned int size)972 static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
973 {
974 struct skge_rx_desc *rd = e->desc;
975
976 rd->csum2 = 0;
977 rd->csum2_start = ETH_HLEN;
978
979 wmb();
980
981 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
982 }
983
984
985 /* Free all buffers in receive ring, assumes receiver stopped */
skge_rx_clean(struct skge_port * skge)986 static void skge_rx_clean(struct skge_port *skge)
987 {
988 struct skge_hw *hw = skge->hw;
989 struct skge_ring *ring = &skge->rx_ring;
990 struct skge_element *e;
991
992 e = ring->start;
993 do {
994 struct skge_rx_desc *rd = e->desc;
995 rd->control = 0;
996 if (e->skb) {
997 dma_unmap_single(&hw->pdev->dev,
998 dma_unmap_addr(e, mapaddr),
999 dma_unmap_len(e, maplen),
1000 DMA_FROM_DEVICE);
1001 dev_kfree_skb(e->skb);
1002 e->skb = NULL;
1003 }
1004 } while ((e = e->next) != ring->start);
1005 }
1006
1007
1008 /* Allocate buffers for receive ring
1009 * For receive: to_clean is next received frame.
1010 */
skge_rx_fill(struct net_device * dev)1011 static int skge_rx_fill(struct net_device *dev)
1012 {
1013 struct skge_port *skge = netdev_priv(dev);
1014 struct skge_ring *ring = &skge->rx_ring;
1015 struct skge_element *e;
1016
1017 e = ring->start;
1018 do {
1019 struct sk_buff *skb;
1020
1021 skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN,
1022 GFP_KERNEL);
1023 if (!skb)
1024 return -ENOMEM;
1025
1026 skb_reserve(skb, NET_IP_ALIGN);
1027 if (skge_rx_setup(skge, e, skb, skge->rx_buf_size) < 0) {
1028 dev_kfree_skb(skb);
1029 return -EIO;
1030 }
1031 } while ((e = e->next) != ring->start);
1032
1033 ring->to_clean = ring->start;
1034 return 0;
1035 }
1036
skge_pause(enum pause_status status)1037 static const char *skge_pause(enum pause_status status)
1038 {
1039 switch (status) {
1040 case FLOW_STAT_NONE:
1041 return "none";
1042 case FLOW_STAT_REM_SEND:
1043 return "rx only";
1044 case FLOW_STAT_LOC_SEND:
1045 return "tx_only";
1046 case FLOW_STAT_SYMMETRIC: /* Both station may send PAUSE */
1047 return "both";
1048 default:
1049 return "indeterminated";
1050 }
1051 }
1052
1053
skge_link_up(struct skge_port * skge)1054 static void skge_link_up(struct skge_port *skge)
1055 {
1056 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
1057 LED_BLK_OFF|LED_SYNC_OFF|LED_REG_ON);
1058
1059 netif_carrier_on(skge->netdev);
1060 netif_wake_queue(skge->netdev);
1061
1062 netif_info(skge, link, skge->netdev,
1063 "Link is up at %d Mbps, %s duplex, flow control %s\n",
1064 skge->speed,
1065 skge->duplex == DUPLEX_FULL ? "full" : "half",
1066 skge_pause(skge->flow_status));
1067 }
1068
skge_link_down(struct skge_port * skge)1069 static void skge_link_down(struct skge_port *skge)
1070 {
1071 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_REG_OFF);
1072 netif_carrier_off(skge->netdev);
1073 netif_stop_queue(skge->netdev);
1074
1075 netif_info(skge, link, skge->netdev, "Link is down\n");
1076 }
1077
xm_link_down(struct skge_hw * hw,int port)1078 static void xm_link_down(struct skge_hw *hw, int port)
1079 {
1080 struct net_device *dev = hw->dev[port];
1081 struct skge_port *skge = netdev_priv(dev);
1082
1083 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
1084
1085 if (netif_carrier_ok(dev))
1086 skge_link_down(skge);
1087 }
1088
__xm_phy_read(struct skge_hw * hw,int port,u16 reg,u16 * val)1089 static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1090 {
1091 int i;
1092
1093 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
1094 *val = xm_read16(hw, port, XM_PHY_DATA);
1095
1096 if (hw->phy_type == SK_PHY_XMAC)
1097 goto ready;
1098
1099 for (i = 0; i < PHY_RETRIES; i++) {
1100 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
1101 goto ready;
1102 udelay(1);
1103 }
1104
1105 return -ETIMEDOUT;
1106 ready:
1107 *val = xm_read16(hw, port, XM_PHY_DATA);
1108
1109 return 0;
1110 }
1111
xm_phy_read(struct skge_hw * hw,int port,u16 reg)1112 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
1113 {
1114 u16 v = 0;
1115 if (__xm_phy_read(hw, port, reg, &v))
1116 pr_warn("%s: phy read timed out\n", hw->dev[port]->name);
1117 return v;
1118 }
1119
xm_phy_write(struct skge_hw * hw,int port,u16 reg,u16 val)1120 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1121 {
1122 int i;
1123
1124 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
1125 for (i = 0; i < PHY_RETRIES; i++) {
1126 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1127 goto ready;
1128 udelay(1);
1129 }
1130 return -EIO;
1131
1132 ready:
1133 xm_write16(hw, port, XM_PHY_DATA, val);
1134 for (i = 0; i < PHY_RETRIES; i++) {
1135 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1136 return 0;
1137 udelay(1);
1138 }
1139 return -ETIMEDOUT;
1140 }
1141
genesis_init(struct skge_hw * hw)1142 static void genesis_init(struct skge_hw *hw)
1143 {
1144 /* set blink source counter */
1145 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
1146 skge_write8(hw, B2_BSC_CTRL, BSC_START);
1147
1148 /* configure mac arbiter */
1149 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1150
1151 /* configure mac arbiter timeout values */
1152 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
1153 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
1154 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
1155 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
1156
1157 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1158 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1159 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1160 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1161
1162 /* configure packet arbiter timeout */
1163 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
1164 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
1165 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
1166 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
1167 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
1168 }
1169
genesis_reset(struct skge_hw * hw,int port)1170 static void genesis_reset(struct skge_hw *hw, int port)
1171 {
1172 static const u8 zero[8] = { 0 };
1173 u32 reg;
1174
1175 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1176
1177 /* reset the statistics module */
1178 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
1179 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
1180 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
1181 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
1182 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
1183
1184 /* disable Broadcom PHY IRQ */
1185 if (hw->phy_type == SK_PHY_BCOM)
1186 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
1187
1188 xm_outhash(hw, port, XM_HSM, zero);
1189
1190 /* Flush TX and RX fifo */
1191 reg = xm_read32(hw, port, XM_MODE);
1192 xm_write32(hw, port, XM_MODE, reg | XM_MD_FTF);
1193 xm_write32(hw, port, XM_MODE, reg | XM_MD_FRF);
1194 }
1195
1196 /* Convert mode to MII values */
1197 static const u16 phy_pause_map[] = {
1198 [FLOW_MODE_NONE] = 0,
1199 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
1200 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
1201 [FLOW_MODE_SYM_OR_REM] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
1202 };
1203
1204 /* special defines for FIBER (88E1011S only) */
1205 static const u16 fiber_pause_map[] = {
1206 [FLOW_MODE_NONE] = PHY_X_P_NO_PAUSE,
1207 [FLOW_MODE_LOC_SEND] = PHY_X_P_ASYM_MD,
1208 [FLOW_MODE_SYMMETRIC] = PHY_X_P_SYM_MD,
1209 [FLOW_MODE_SYM_OR_REM] = PHY_X_P_BOTH_MD,
1210 };
1211
1212
1213 /* Check status of Broadcom phy link */
bcom_check_link(struct skge_hw * hw,int port)1214 static void bcom_check_link(struct skge_hw *hw, int port)
1215 {
1216 struct net_device *dev = hw->dev[port];
1217 struct skge_port *skge = netdev_priv(dev);
1218 u16 status;
1219
1220 /* read twice because of latch */
1221 xm_phy_read(hw, port, PHY_BCOM_STAT);
1222 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1223
1224 if ((status & PHY_ST_LSYNC) == 0) {
1225 xm_link_down(hw, port);
1226 return;
1227 }
1228
1229 if (skge->autoneg == AUTONEG_ENABLE) {
1230 u16 lpa, aux;
1231
1232 if (!(status & PHY_ST_AN_OVER))
1233 return;
1234
1235 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1236 if (lpa & PHY_B_AN_RF) {
1237 netdev_notice(dev, "remote fault\n");
1238 return;
1239 }
1240
1241 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1242
1243 /* Check Duplex mismatch */
1244 switch (aux & PHY_B_AS_AN_RES_MSK) {
1245 case PHY_B_RES_1000FD:
1246 skge->duplex = DUPLEX_FULL;
1247 break;
1248 case PHY_B_RES_1000HD:
1249 skge->duplex = DUPLEX_HALF;
1250 break;
1251 default:
1252 netdev_notice(dev, "duplex mismatch\n");
1253 return;
1254 }
1255
1256 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1257 switch (aux & PHY_B_AS_PAUSE_MSK) {
1258 case PHY_B_AS_PAUSE_MSK:
1259 skge->flow_status = FLOW_STAT_SYMMETRIC;
1260 break;
1261 case PHY_B_AS_PRR:
1262 skge->flow_status = FLOW_STAT_REM_SEND;
1263 break;
1264 case PHY_B_AS_PRT:
1265 skge->flow_status = FLOW_STAT_LOC_SEND;
1266 break;
1267 default:
1268 skge->flow_status = FLOW_STAT_NONE;
1269 }
1270 skge->speed = SPEED_1000;
1271 }
1272
1273 if (!netif_carrier_ok(dev))
1274 genesis_link_up(skge);
1275 }
1276
1277 /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1278 * Phy on for 100 or 10Mbit operation
1279 */
bcom_phy_init(struct skge_port * skge)1280 static void bcom_phy_init(struct skge_port *skge)
1281 {
1282 struct skge_hw *hw = skge->hw;
1283 int port = skge->port;
1284 int i;
1285 u16 id1, r, ext, ctl;
1286
1287 /* magic workaround patterns for Broadcom */
1288 static const struct {
1289 u16 reg;
1290 u16 val;
1291 } A1hack[] = {
1292 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1293 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1294 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1295 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1296 }, C0hack[] = {
1297 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1298 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1299 };
1300
1301 /* read Id from external PHY (all have the same address) */
1302 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1303
1304 /* Optimize MDIO transfer by suppressing preamble. */
1305 r = xm_read16(hw, port, XM_MMU_CMD);
1306 r |= XM_MMU_NO_PRE;
1307 xm_write16(hw, port, XM_MMU_CMD, r);
1308
1309 switch (id1) {
1310 case PHY_BCOM_ID1_C0:
1311 /*
1312 * Workaround BCOM Errata for the C0 type.
1313 * Write magic patterns to reserved registers.
1314 */
1315 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1316 xm_phy_write(hw, port,
1317 C0hack[i].reg, C0hack[i].val);
1318
1319 break;
1320 case PHY_BCOM_ID1_A1:
1321 /*
1322 * Workaround BCOM Errata for the A1 type.
1323 * Write magic patterns to reserved registers.
1324 */
1325 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1326 xm_phy_write(hw, port,
1327 A1hack[i].reg, A1hack[i].val);
1328 break;
1329 }
1330
1331 /*
1332 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1333 * Disable Power Management after reset.
1334 */
1335 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1336 r |= PHY_B_AC_DIS_PM;
1337 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1338
1339 /* Dummy read */
1340 xm_read16(hw, port, XM_ISRC);
1341
1342 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1343 ctl = PHY_CT_SP1000; /* always 1000mbit */
1344
1345 if (skge->autoneg == AUTONEG_ENABLE) {
1346 /*
1347 * Workaround BCOM Errata #1 for the C5 type.
1348 * 1000Base-T Link Acquisition Failure in Slave Mode
1349 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1350 */
1351 u16 adv = PHY_B_1000C_RD;
1352 if (skge->advertising & ADVERTISED_1000baseT_Half)
1353 adv |= PHY_B_1000C_AHD;
1354 if (skge->advertising & ADVERTISED_1000baseT_Full)
1355 adv |= PHY_B_1000C_AFD;
1356 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1357
1358 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1359 } else {
1360 if (skge->duplex == DUPLEX_FULL)
1361 ctl |= PHY_CT_DUP_MD;
1362 /* Force to slave */
1363 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1364 }
1365
1366 /* Set autonegotiation pause parameters */
1367 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1368 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1369
1370 /* Handle Jumbo frames */
1371 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
1372 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1373 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1374
1375 ext |= PHY_B_PEC_HIGH_LA;
1376
1377 }
1378
1379 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1380 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1381
1382 /* Use link status change interrupt */
1383 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1384 }
1385
xm_phy_init(struct skge_port * skge)1386 static void xm_phy_init(struct skge_port *skge)
1387 {
1388 struct skge_hw *hw = skge->hw;
1389 int port = skge->port;
1390 u16 ctrl = 0;
1391
1392 if (skge->autoneg == AUTONEG_ENABLE) {
1393 if (skge->advertising & ADVERTISED_1000baseT_Half)
1394 ctrl |= PHY_X_AN_HD;
1395 if (skge->advertising & ADVERTISED_1000baseT_Full)
1396 ctrl |= PHY_X_AN_FD;
1397
1398 ctrl |= fiber_pause_map[skge->flow_control];
1399
1400 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
1401
1402 /* Restart Auto-negotiation */
1403 ctrl = PHY_CT_ANE | PHY_CT_RE_CFG;
1404 } else {
1405 /* Set DuplexMode in Config register */
1406 if (skge->duplex == DUPLEX_FULL)
1407 ctrl |= PHY_CT_DUP_MD;
1408 /*
1409 * Do NOT enable Auto-negotiation here. This would hold
1410 * the link down because no IDLEs are transmitted
1411 */
1412 }
1413
1414 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
1415
1416 /* Poll PHY for status changes */
1417 mod_timer(&skge->link_timer, jiffies + LINK_HZ);
1418 }
1419
xm_check_link(struct net_device * dev)1420 static int xm_check_link(struct net_device *dev)
1421 {
1422 struct skge_port *skge = netdev_priv(dev);
1423 struct skge_hw *hw = skge->hw;
1424 int port = skge->port;
1425 u16 status;
1426
1427 /* read twice because of latch */
1428 xm_phy_read(hw, port, PHY_XMAC_STAT);
1429 status = xm_phy_read(hw, port, PHY_XMAC_STAT);
1430
1431 if ((status & PHY_ST_LSYNC) == 0) {
1432 xm_link_down(hw, port);
1433 return 0;
1434 }
1435
1436 if (skge->autoneg == AUTONEG_ENABLE) {
1437 u16 lpa, res;
1438
1439 if (!(status & PHY_ST_AN_OVER))
1440 return 0;
1441
1442 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1443 if (lpa & PHY_B_AN_RF) {
1444 netdev_notice(dev, "remote fault\n");
1445 return 0;
1446 }
1447
1448 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
1449
1450 /* Check Duplex mismatch */
1451 switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) {
1452 case PHY_X_RS_FD:
1453 skge->duplex = DUPLEX_FULL;
1454 break;
1455 case PHY_X_RS_HD:
1456 skge->duplex = DUPLEX_HALF;
1457 break;
1458 default:
1459 netdev_notice(dev, "duplex mismatch\n");
1460 return 0;
1461 }
1462
1463 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1464 if ((skge->flow_control == FLOW_MODE_SYMMETRIC ||
1465 skge->flow_control == FLOW_MODE_SYM_OR_REM) &&
1466 (lpa & PHY_X_P_SYM_MD))
1467 skge->flow_status = FLOW_STAT_SYMMETRIC;
1468 else if (skge->flow_control == FLOW_MODE_SYM_OR_REM &&
1469 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD)
1470 /* Enable PAUSE receive, disable PAUSE transmit */
1471 skge->flow_status = FLOW_STAT_REM_SEND;
1472 else if (skge->flow_control == FLOW_MODE_LOC_SEND &&
1473 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD)
1474 /* Disable PAUSE receive, enable PAUSE transmit */
1475 skge->flow_status = FLOW_STAT_LOC_SEND;
1476 else
1477 skge->flow_status = FLOW_STAT_NONE;
1478
1479 skge->speed = SPEED_1000;
1480 }
1481
1482 if (!netif_carrier_ok(dev))
1483 genesis_link_up(skge);
1484 return 1;
1485 }
1486
1487 /* Poll to check for link coming up.
1488 *
1489 * Since internal PHY is wired to a level triggered pin, can't
1490 * get an interrupt when carrier is detected, need to poll for
1491 * link coming up.
1492 */
xm_link_timer(struct timer_list * t)1493 static void xm_link_timer(struct timer_list *t)
1494 {
1495 struct skge_port *skge = from_timer(skge, t, link_timer);
1496 struct net_device *dev = skge->netdev;
1497 struct skge_hw *hw = skge->hw;
1498 int port = skge->port;
1499 int i;
1500 unsigned long flags;
1501
1502 if (!netif_running(dev))
1503 return;
1504
1505 spin_lock_irqsave(&hw->phy_lock, flags);
1506
1507 /*
1508 * Verify that the link by checking GPIO register three times.
1509 * This pin has the signal from the link_sync pin connected to it.
1510 */
1511 for (i = 0; i < 3; i++) {
1512 if (xm_read16(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
1513 goto link_down;
1514 }
1515
1516 /* Re-enable interrupt to detect link down */
1517 if (xm_check_link(dev)) {
1518 u16 msk = xm_read16(hw, port, XM_IMSK);
1519 msk &= ~XM_IS_INP_ASS;
1520 xm_write16(hw, port, XM_IMSK, msk);
1521 xm_read16(hw, port, XM_ISRC);
1522 } else {
1523 link_down:
1524 mod_timer(&skge->link_timer,
1525 round_jiffies(jiffies + LINK_HZ));
1526 }
1527 spin_unlock_irqrestore(&hw->phy_lock, flags);
1528 }
1529
genesis_mac_init(struct skge_hw * hw,int port)1530 static void genesis_mac_init(struct skge_hw *hw, int port)
1531 {
1532 struct net_device *dev = hw->dev[port];
1533 struct skge_port *skge = netdev_priv(dev);
1534 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1535 int i;
1536 u32 r;
1537 static const u8 zero[6] = { 0 };
1538
1539 for (i = 0; i < 10; i++) {
1540 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1541 MFF_SET_MAC_RST);
1542 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1543 goto reset_ok;
1544 udelay(1);
1545 }
1546
1547 netdev_warn(dev, "genesis reset failed\n");
1548
1549 reset_ok:
1550 /* Unreset the XMAC. */
1551 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1552
1553 /*
1554 * Perform additional initialization for external PHYs,
1555 * namely for the 1000baseTX cards that use the XMAC's
1556 * GMII mode.
1557 */
1558 if (hw->phy_type != SK_PHY_XMAC) {
1559 /* Take external Phy out of reset */
1560 r = skge_read32(hw, B2_GP_IO);
1561 if (port == 0)
1562 r |= GP_DIR_0|GP_IO_0;
1563 else
1564 r |= GP_DIR_2|GP_IO_2;
1565
1566 skge_write32(hw, B2_GP_IO, r);
1567
1568 /* Enable GMII interface */
1569 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1570 }
1571
1572
1573 switch (hw->phy_type) {
1574 case SK_PHY_XMAC:
1575 xm_phy_init(skge);
1576 break;
1577 case SK_PHY_BCOM:
1578 bcom_phy_init(skge);
1579 bcom_check_link(hw, port);
1580 }
1581
1582 /* Set Station Address */
1583 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
1584
1585 /* We don't use match addresses so clear */
1586 for (i = 1; i < 16; i++)
1587 xm_outaddr(hw, port, XM_EXM(i), zero);
1588
1589 /* Clear MIB counters */
1590 xm_write16(hw, port, XM_STAT_CMD,
1591 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1592 /* Clear two times according to Errata #3 */
1593 xm_write16(hw, port, XM_STAT_CMD,
1594 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1595
1596 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1597 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1598
1599 /* We don't need the FCS appended to the packet. */
1600 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1601 if (jumbo)
1602 r |= XM_RX_BIG_PK_OK;
1603
1604 if (skge->duplex == DUPLEX_HALF) {
1605 /*
1606 * If in manual half duplex mode the other side might be in
1607 * full duplex mode, so ignore if a carrier extension is not seen
1608 * on frames received
1609 */
1610 r |= XM_RX_DIS_CEXT;
1611 }
1612 xm_write16(hw, port, XM_RX_CMD, r);
1613
1614 /* We want short frames padded to 60 bytes. */
1615 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1616
1617 /* Increase threshold for jumbo frames on dual port */
1618 if (hw->ports > 1 && jumbo)
1619 xm_write16(hw, port, XM_TX_THR, 1020);
1620 else
1621 xm_write16(hw, port, XM_TX_THR, 512);
1622
1623 /*
1624 * Enable the reception of all error frames. This is
1625 * a necessary evil due to the design of the XMAC. The
1626 * XMAC's receive FIFO is only 8K in size, however jumbo
1627 * frames can be up to 9000 bytes in length. When bad
1628 * frame filtering is enabled, the XMAC's RX FIFO operates
1629 * in 'store and forward' mode. For this to work, the
1630 * entire frame has to fit into the FIFO, but that means
1631 * that jumbo frames larger than 8192 bytes will be
1632 * truncated. Disabling all bad frame filtering causes
1633 * the RX FIFO to operate in streaming mode, in which
1634 * case the XMAC will start transferring frames out of the
1635 * RX FIFO as soon as the FIFO threshold is reached.
1636 */
1637 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
1638
1639
1640 /*
1641 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1642 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1643 * and 'Octets Rx OK Hi Cnt Ov'.
1644 */
1645 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1646
1647 /*
1648 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1649 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1650 * and 'Octets Tx OK Hi Cnt Ov'.
1651 */
1652 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
1653
1654 /* Configure MAC arbiter */
1655 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1656
1657 /* configure timeout values */
1658 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1659 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1660 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1661 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1662
1663 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1664 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1665 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1666 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1667
1668 /* Configure Rx MAC FIFO */
1669 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1670 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1671 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
1672
1673 /* Configure Tx MAC FIFO */
1674 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1675 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1676 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
1677
1678 if (jumbo) {
1679 /* Enable frame flushing if jumbo frames used */
1680 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_FLUSH);
1681 } else {
1682 /* enable timeout timers if normal frames */
1683 skge_write16(hw, B3_PA_CTRL,
1684 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
1685 }
1686 }
1687
genesis_stop(struct skge_port * skge)1688 static void genesis_stop(struct skge_port *skge)
1689 {
1690 struct skge_hw *hw = skge->hw;
1691 int port = skge->port;
1692 unsigned retries = 1000;
1693 u16 cmd;
1694
1695 /* Disable Tx and Rx */
1696 cmd = xm_read16(hw, port, XM_MMU_CMD);
1697 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1698 xm_write16(hw, port, XM_MMU_CMD, cmd);
1699
1700 genesis_reset(hw, port);
1701
1702 /* Clear Tx packet arbiter timeout IRQ */
1703 skge_write16(hw, B3_PA_CTRL,
1704 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1705
1706 /* Reset the MAC */
1707 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1708 do {
1709 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1710 if (!(skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST))
1711 break;
1712 } while (--retries > 0);
1713
1714 /* For external PHYs there must be special handling */
1715 if (hw->phy_type != SK_PHY_XMAC) {
1716 u32 reg = skge_read32(hw, B2_GP_IO);
1717 if (port == 0) {
1718 reg |= GP_DIR_0;
1719 reg &= ~GP_IO_0;
1720 } else {
1721 reg |= GP_DIR_2;
1722 reg &= ~GP_IO_2;
1723 }
1724 skge_write32(hw, B2_GP_IO, reg);
1725 skge_read32(hw, B2_GP_IO);
1726 }
1727
1728 xm_write16(hw, port, XM_MMU_CMD,
1729 xm_read16(hw, port, XM_MMU_CMD)
1730 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1731
1732 xm_read16(hw, port, XM_MMU_CMD);
1733 }
1734
1735
genesis_get_stats(struct skge_port * skge,u64 * data)1736 static void genesis_get_stats(struct skge_port *skge, u64 *data)
1737 {
1738 struct skge_hw *hw = skge->hw;
1739 int port = skge->port;
1740 int i;
1741 unsigned long timeout = jiffies + HZ;
1742
1743 xm_write16(hw, port,
1744 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1745
1746 /* wait for update to complete */
1747 while (xm_read16(hw, port, XM_STAT_CMD)
1748 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1749 if (time_after(jiffies, timeout))
1750 break;
1751 udelay(10);
1752 }
1753
1754 /* special case for 64 bit octet counter */
1755 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1756 | xm_read32(hw, port, XM_TXO_OK_LO);
1757 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1758 | xm_read32(hw, port, XM_RXO_OK_LO);
1759
1760 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1761 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
1762 }
1763
genesis_mac_intr(struct skge_hw * hw,int port)1764 static void genesis_mac_intr(struct skge_hw *hw, int port)
1765 {
1766 struct net_device *dev = hw->dev[port];
1767 struct skge_port *skge = netdev_priv(dev);
1768 u16 status = xm_read16(hw, port, XM_ISRC);
1769
1770 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
1771 "mac interrupt status 0x%x\n", status);
1772
1773 if (hw->phy_type == SK_PHY_XMAC && (status & XM_IS_INP_ASS)) {
1774 xm_link_down(hw, port);
1775 mod_timer(&skge->link_timer, jiffies + 1);
1776 }
1777
1778 if (status & XM_IS_TXF_UR) {
1779 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
1780 ++dev->stats.tx_fifo_errors;
1781 }
1782 }
1783
genesis_link_up(struct skge_port * skge)1784 static void genesis_link_up(struct skge_port *skge)
1785 {
1786 struct skge_hw *hw = skge->hw;
1787 int port = skge->port;
1788 u16 cmd, msk;
1789 u32 mode;
1790
1791 cmd = xm_read16(hw, port, XM_MMU_CMD);
1792
1793 /*
1794 * enabling pause frame reception is required for 1000BT
1795 * because the XMAC is not reset if the link is going down
1796 */
1797 if (skge->flow_status == FLOW_STAT_NONE ||
1798 skge->flow_status == FLOW_STAT_LOC_SEND)
1799 /* Disable Pause Frame Reception */
1800 cmd |= XM_MMU_IGN_PF;
1801 else
1802 /* Enable Pause Frame Reception */
1803 cmd &= ~XM_MMU_IGN_PF;
1804
1805 xm_write16(hw, port, XM_MMU_CMD, cmd);
1806
1807 mode = xm_read32(hw, port, XM_MODE);
1808 if (skge->flow_status == FLOW_STAT_SYMMETRIC ||
1809 skge->flow_status == FLOW_STAT_LOC_SEND) {
1810 /*
1811 * Configure Pause Frame Generation
1812 * Use internal and external Pause Frame Generation.
1813 * Sending pause frames is edge triggered.
1814 * Send a Pause frame with the maximum pause time if
1815 * internal oder external FIFO full condition occurs.
1816 * Send a zero pause time frame to re-start transmission.
1817 */
1818 /* XM_PAUSE_DA = '010000C28001' (default) */
1819 /* XM_MAC_PTIME = 0xffff (maximum) */
1820 /* remember this value is defined in big endian (!) */
1821 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1822
1823 mode |= XM_PAUSE_MODE;
1824 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1825 } else {
1826 /*
1827 * disable pause frame generation is required for 1000BT
1828 * because the XMAC is not reset if the link is going down
1829 */
1830 /* Disable Pause Mode in Mode Register */
1831 mode &= ~XM_PAUSE_MODE;
1832
1833 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1834 }
1835
1836 xm_write32(hw, port, XM_MODE, mode);
1837
1838 /* Turn on detection of Tx underrun */
1839 msk = xm_read16(hw, port, XM_IMSK);
1840 msk &= ~XM_IS_TXF_UR;
1841 xm_write16(hw, port, XM_IMSK, msk);
1842
1843 xm_read16(hw, port, XM_ISRC);
1844
1845 /* get MMU Command Reg. */
1846 cmd = xm_read16(hw, port, XM_MMU_CMD);
1847 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
1848 cmd |= XM_MMU_GMII_FD;
1849
1850 /*
1851 * Workaround BCOM Errata (#10523) for all BCom Phys
1852 * Enable Power Management after link up
1853 */
1854 if (hw->phy_type == SK_PHY_BCOM) {
1855 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1856 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1857 & ~PHY_B_AC_DIS_PM);
1858 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1859 }
1860
1861 /* enable Rx/Tx */
1862 xm_write16(hw, port, XM_MMU_CMD,
1863 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1864 skge_link_up(skge);
1865 }
1866
1867
bcom_phy_intr(struct skge_port * skge)1868 static inline void bcom_phy_intr(struct skge_port *skge)
1869 {
1870 struct skge_hw *hw = skge->hw;
1871 int port = skge->port;
1872 u16 isrc;
1873
1874 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1875 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
1876 "phy interrupt status 0x%x\n", isrc);
1877
1878 if (isrc & PHY_B_IS_PSE)
1879 pr_err("%s: uncorrectable pair swap error\n",
1880 hw->dev[port]->name);
1881
1882 /* Workaround BCom Errata:
1883 * enable and disable loopback mode if "NO HCD" occurs.
1884 */
1885 if (isrc & PHY_B_IS_NO_HDCL) {
1886 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1887 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1888 ctrl | PHY_CT_LOOP);
1889 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1890 ctrl & ~PHY_CT_LOOP);
1891 }
1892
1893 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1894 bcom_check_link(hw, port);
1895
1896 }
1897
gm_phy_write(struct skge_hw * hw,int port,u16 reg,u16 val)1898 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1899 {
1900 int i;
1901
1902 gma_write16(hw, port, GM_SMI_DATA, val);
1903 gma_write16(hw, port, GM_SMI_CTRL,
1904 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1905 for (i = 0; i < PHY_RETRIES; i++) {
1906 udelay(1);
1907
1908 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1909 return 0;
1910 }
1911
1912 pr_warn("%s: phy write timeout\n", hw->dev[port]->name);
1913 return -EIO;
1914 }
1915
__gm_phy_read(struct skge_hw * hw,int port,u16 reg,u16 * val)1916 static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1917 {
1918 int i;
1919
1920 gma_write16(hw, port, GM_SMI_CTRL,
1921 GM_SMI_CT_PHY_AD(hw->phy_addr)
1922 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1923
1924 for (i = 0; i < PHY_RETRIES; i++) {
1925 udelay(1);
1926 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1927 goto ready;
1928 }
1929
1930 return -ETIMEDOUT;
1931 ready:
1932 *val = gma_read16(hw, port, GM_SMI_DATA);
1933 return 0;
1934 }
1935
gm_phy_read(struct skge_hw * hw,int port,u16 reg)1936 static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1937 {
1938 u16 v = 0;
1939 if (__gm_phy_read(hw, port, reg, &v))
1940 pr_warn("%s: phy read timeout\n", hw->dev[port]->name);
1941 return v;
1942 }
1943
1944 /* Marvell Phy Initialization */
yukon_init(struct skge_hw * hw,int port)1945 static void yukon_init(struct skge_hw *hw, int port)
1946 {
1947 struct skge_port *skge = netdev_priv(hw->dev[port]);
1948 u16 ctrl, ct1000, adv;
1949
1950 if (skge->autoneg == AUTONEG_ENABLE) {
1951 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1952
1953 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1954 PHY_M_EC_MAC_S_MSK);
1955 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1956
1957 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1958
1959 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1960 }
1961
1962 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1963 if (skge->autoneg == AUTONEG_DISABLE)
1964 ctrl &= ~PHY_CT_ANE;
1965
1966 ctrl |= PHY_CT_RESET;
1967 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1968
1969 ctrl = 0;
1970 ct1000 = 0;
1971 adv = PHY_AN_CSMA;
1972
1973 if (skge->autoneg == AUTONEG_ENABLE) {
1974 if (hw->copper) {
1975 if (skge->advertising & ADVERTISED_1000baseT_Full)
1976 ct1000 |= PHY_M_1000C_AFD;
1977 if (skge->advertising & ADVERTISED_1000baseT_Half)
1978 ct1000 |= PHY_M_1000C_AHD;
1979 if (skge->advertising & ADVERTISED_100baseT_Full)
1980 adv |= PHY_M_AN_100_FD;
1981 if (skge->advertising & ADVERTISED_100baseT_Half)
1982 adv |= PHY_M_AN_100_HD;
1983 if (skge->advertising & ADVERTISED_10baseT_Full)
1984 adv |= PHY_M_AN_10_FD;
1985 if (skge->advertising & ADVERTISED_10baseT_Half)
1986 adv |= PHY_M_AN_10_HD;
1987
1988 /* Set Flow-control capabilities */
1989 adv |= phy_pause_map[skge->flow_control];
1990 } else {
1991 if (skge->advertising & ADVERTISED_1000baseT_Full)
1992 adv |= PHY_M_AN_1000X_AFD;
1993 if (skge->advertising & ADVERTISED_1000baseT_Half)
1994 adv |= PHY_M_AN_1000X_AHD;
1995
1996 adv |= fiber_pause_map[skge->flow_control];
1997 }
1998
1999 /* Restart Auto-negotiation */
2000 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
2001 } else {
2002 /* forced speed/duplex settings */
2003 ct1000 = PHY_M_1000C_MSE;
2004
2005 if (skge->duplex == DUPLEX_FULL)
2006 ctrl |= PHY_CT_DUP_MD;
2007
2008 switch (skge->speed) {
2009 case SPEED_1000:
2010 ctrl |= PHY_CT_SP1000;
2011 break;
2012 case SPEED_100:
2013 ctrl |= PHY_CT_SP100;
2014 break;
2015 }
2016
2017 ctrl |= PHY_CT_RESET;
2018 }
2019
2020 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
2021
2022 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
2023 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2024
2025 /* Enable phy interrupt on autonegotiation complete (or link up) */
2026 if (skge->autoneg == AUTONEG_ENABLE)
2027 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
2028 else
2029 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
2030 }
2031
yukon_reset(struct skge_hw * hw,int port)2032 static void yukon_reset(struct skge_hw *hw, int port)
2033 {
2034 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
2035 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
2036 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
2037 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
2038 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
2039
2040 gma_write16(hw, port, GM_RX_CTRL,
2041 gma_read16(hw, port, GM_RX_CTRL)
2042 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2043 }
2044
2045 /* Apparently, early versions of Yukon-Lite had wrong chip_id? */
is_yukon_lite_a0(struct skge_hw * hw)2046 static int is_yukon_lite_a0(struct skge_hw *hw)
2047 {
2048 u32 reg;
2049 int ret;
2050
2051 if (hw->chip_id != CHIP_ID_YUKON)
2052 return 0;
2053
2054 reg = skge_read32(hw, B2_FAR);
2055 skge_write8(hw, B2_FAR + 3, 0xff);
2056 ret = (skge_read8(hw, B2_FAR + 3) != 0);
2057 skge_write32(hw, B2_FAR, reg);
2058 return ret;
2059 }
2060
yukon_mac_init(struct skge_hw * hw,int port)2061 static void yukon_mac_init(struct skge_hw *hw, int port)
2062 {
2063 struct skge_port *skge = netdev_priv(hw->dev[port]);
2064 int i;
2065 u32 reg;
2066 const u8 *addr = hw->dev[port]->dev_addr;
2067
2068 /* WA code for COMA mode -- set PHY reset */
2069 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
2070 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2071 reg = skge_read32(hw, B2_GP_IO);
2072 reg |= GP_DIR_9 | GP_IO_9;
2073 skge_write32(hw, B2_GP_IO, reg);
2074 }
2075
2076 /* hard reset */
2077 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2078 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2079
2080 /* WA code for COMA mode -- clear PHY reset */
2081 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
2082 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2083 reg = skge_read32(hw, B2_GP_IO);
2084 reg |= GP_DIR_9;
2085 reg &= ~GP_IO_9;
2086 skge_write32(hw, B2_GP_IO, reg);
2087 }
2088
2089 /* Set hardware config mode */
2090 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
2091 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
2092 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
2093
2094 /* Clear GMC reset */
2095 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
2096 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
2097 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
2098
2099 if (skge->autoneg == AUTONEG_DISABLE) {
2100 reg = GM_GPCR_AU_ALL_DIS;
2101 gma_write16(hw, port, GM_GP_CTRL,
2102 gma_read16(hw, port, GM_GP_CTRL) | reg);
2103
2104 switch (skge->speed) {
2105 case SPEED_1000:
2106 reg &= ~GM_GPCR_SPEED_100;
2107 reg |= GM_GPCR_SPEED_1000;
2108 break;
2109 case SPEED_100:
2110 reg &= ~GM_GPCR_SPEED_1000;
2111 reg |= GM_GPCR_SPEED_100;
2112 break;
2113 case SPEED_10:
2114 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
2115 break;
2116 }
2117
2118 if (skge->duplex == DUPLEX_FULL)
2119 reg |= GM_GPCR_DUP_FULL;
2120 } else
2121 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
2122
2123 switch (skge->flow_control) {
2124 case FLOW_MODE_NONE:
2125 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2126 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2127 break;
2128 case FLOW_MODE_LOC_SEND:
2129 /* disable Rx flow-control */
2130 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2131 break;
2132 case FLOW_MODE_SYMMETRIC:
2133 case FLOW_MODE_SYM_OR_REM:
2134 /* enable Tx & Rx flow-control */
2135 break;
2136 }
2137
2138 gma_write16(hw, port, GM_GP_CTRL, reg);
2139 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
2140
2141 yukon_init(hw, port);
2142
2143 /* MIB clear */
2144 reg = gma_read16(hw, port, GM_PHY_ADDR);
2145 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
2146
2147 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
2148 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
2149 gma_write16(hw, port, GM_PHY_ADDR, reg);
2150
2151 /* transmit control */
2152 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
2153
2154 /* receive control reg: unicast + multicast + no FCS */
2155 gma_write16(hw, port, GM_RX_CTRL,
2156 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
2157
2158 /* transmit flow control */
2159 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
2160
2161 /* transmit parameter */
2162 gma_write16(hw, port, GM_TX_PARAM,
2163 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
2164 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
2165 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
2166
2167 /* configure the Serial Mode Register */
2168 reg = DATA_BLIND_VAL(DATA_BLIND_DEF)
2169 | GM_SMOD_VLAN_ENA
2170 | IPG_DATA_VAL(IPG_DATA_DEF);
2171
2172 if (hw->dev[port]->mtu > ETH_DATA_LEN)
2173 reg |= GM_SMOD_JUMBO_ENA;
2174
2175 gma_write16(hw, port, GM_SERIAL_MODE, reg);
2176
2177 /* physical address: used for pause frames */
2178 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
2179 /* virtual address for data */
2180 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
2181
2182 /* enable interrupt mask for counter overflows */
2183 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
2184 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
2185 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
2186
2187 /* Initialize Mac Fifo */
2188
2189 /* Configure Rx MAC FIFO */
2190 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
2191 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
2192
2193 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
2194 if (is_yukon_lite_a0(hw))
2195 reg &= ~GMF_RX_F_FL_ON;
2196
2197 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
2198 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
2199 /*
2200 * because Pause Packet Truncation in GMAC is not working
2201 * we have to increase the Flush Threshold to 64 bytes
2202 * in order to flush pause packets in Rx FIFO on Yukon-1
2203 */
2204 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
2205
2206 /* Configure Tx MAC FIFO */
2207 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
2208 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
2209 }
2210
2211 /* Go into power down mode */
yukon_suspend(struct skge_hw * hw,int port)2212 static void yukon_suspend(struct skge_hw *hw, int port)
2213 {
2214 u16 ctrl;
2215
2216 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2217 ctrl |= PHY_M_PC_POL_R_DIS;
2218 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
2219
2220 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2221 ctrl |= PHY_CT_RESET;
2222 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2223
2224 /* switch IEEE compatible power down mode on */
2225 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2226 ctrl |= PHY_CT_PDOWN;
2227 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2228 }
2229
yukon_stop(struct skge_port * skge)2230 static void yukon_stop(struct skge_port *skge)
2231 {
2232 struct skge_hw *hw = skge->hw;
2233 int port = skge->port;
2234
2235 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
2236 yukon_reset(hw, port);
2237
2238 gma_write16(hw, port, GM_GP_CTRL,
2239 gma_read16(hw, port, GM_GP_CTRL)
2240 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
2241 gma_read16(hw, port, GM_GP_CTRL);
2242
2243 yukon_suspend(hw, port);
2244
2245 /* set GPHY Control reset */
2246 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2247 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2248 }
2249
yukon_get_stats(struct skge_port * skge,u64 * data)2250 static void yukon_get_stats(struct skge_port *skge, u64 *data)
2251 {
2252 struct skge_hw *hw = skge->hw;
2253 int port = skge->port;
2254 int i;
2255
2256 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2257 | gma_read32(hw, port, GM_TXO_OK_LO);
2258 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2259 | gma_read32(hw, port, GM_RXO_OK_LO);
2260
2261 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
2262 data[i] = gma_read32(hw, port,
2263 skge_stats[i].gma_offset);
2264 }
2265
yukon_mac_intr(struct skge_hw * hw,int port)2266 static void yukon_mac_intr(struct skge_hw *hw, int port)
2267 {
2268 struct net_device *dev = hw->dev[port];
2269 struct skge_port *skge = netdev_priv(dev);
2270 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2271
2272 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
2273 "mac interrupt status 0x%x\n", status);
2274
2275 if (status & GM_IS_RX_FF_OR) {
2276 ++dev->stats.rx_fifo_errors;
2277 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2278 }
2279
2280 if (status & GM_IS_TX_FF_UR) {
2281 ++dev->stats.tx_fifo_errors;
2282 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2283 }
2284
2285 }
2286
yukon_speed(const struct skge_hw * hw,u16 aux)2287 static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
2288 {
2289 switch (aux & PHY_M_PS_SPEED_MSK) {
2290 case PHY_M_PS_SPEED_1000:
2291 return SPEED_1000;
2292 case PHY_M_PS_SPEED_100:
2293 return SPEED_100;
2294 default:
2295 return SPEED_10;
2296 }
2297 }
2298
yukon_link_up(struct skge_port * skge)2299 static void yukon_link_up(struct skge_port *skge)
2300 {
2301 struct skge_hw *hw = skge->hw;
2302 int port = skge->port;
2303 u16 reg;
2304
2305 /* Enable Transmit FIFO Underrun */
2306 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
2307
2308 reg = gma_read16(hw, port, GM_GP_CTRL);
2309 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
2310 reg |= GM_GPCR_DUP_FULL;
2311
2312 /* enable Rx/Tx */
2313 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
2314 gma_write16(hw, port, GM_GP_CTRL, reg);
2315
2316 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
2317 skge_link_up(skge);
2318 }
2319
yukon_link_down(struct skge_port * skge)2320 static void yukon_link_down(struct skge_port *skge)
2321 {
2322 struct skge_hw *hw = skge->hw;
2323 int port = skge->port;
2324 u16 ctrl;
2325
2326 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2327 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2328 gma_write16(hw, port, GM_GP_CTRL, ctrl);
2329
2330 if (skge->flow_status == FLOW_STAT_REM_SEND) {
2331 ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2332 ctrl |= PHY_M_AN_ASP;
2333 /* restore Asymmetric Pause bit */
2334 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl);
2335 }
2336
2337 skge_link_down(skge);
2338
2339 yukon_init(hw, port);
2340 }
2341
yukon_phy_intr(struct skge_port * skge)2342 static void yukon_phy_intr(struct skge_port *skge)
2343 {
2344 struct skge_hw *hw = skge->hw;
2345 int port = skge->port;
2346 const char *reason = NULL;
2347 u16 istatus, phystat;
2348
2349 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2350 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2351
2352 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
2353 "phy interrupt status 0x%x 0x%x\n", istatus, phystat);
2354
2355 if (istatus & PHY_M_IS_AN_COMPL) {
2356 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
2357 & PHY_M_AN_RF) {
2358 reason = "remote fault";
2359 goto failed;
2360 }
2361
2362 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
2363 reason = "master/slave fault";
2364 goto failed;
2365 }
2366
2367 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
2368 reason = "speed/duplex";
2369 goto failed;
2370 }
2371
2372 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
2373 ? DUPLEX_FULL : DUPLEX_HALF;
2374 skge->speed = yukon_speed(hw, phystat);
2375
2376 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
2377 switch (phystat & PHY_M_PS_PAUSE_MSK) {
2378 case PHY_M_PS_PAUSE_MSK:
2379 skge->flow_status = FLOW_STAT_SYMMETRIC;
2380 break;
2381 case PHY_M_PS_RX_P_EN:
2382 skge->flow_status = FLOW_STAT_REM_SEND;
2383 break;
2384 case PHY_M_PS_TX_P_EN:
2385 skge->flow_status = FLOW_STAT_LOC_SEND;
2386 break;
2387 default:
2388 skge->flow_status = FLOW_STAT_NONE;
2389 }
2390
2391 if (skge->flow_status == FLOW_STAT_NONE ||
2392 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
2393 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2394 else
2395 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2396 yukon_link_up(skge);
2397 return;
2398 }
2399
2400 if (istatus & PHY_M_IS_LSP_CHANGE)
2401 skge->speed = yukon_speed(hw, phystat);
2402
2403 if (istatus & PHY_M_IS_DUP_CHANGE)
2404 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2405 if (istatus & PHY_M_IS_LST_CHANGE) {
2406 if (phystat & PHY_M_PS_LINK_UP)
2407 yukon_link_up(skge);
2408 else
2409 yukon_link_down(skge);
2410 }
2411 return;
2412 failed:
2413 pr_err("%s: autonegotiation failed (%s)\n", skge->netdev->name, reason);
2414
2415 /* XXX restart autonegotiation? */
2416 }
2417
skge_phy_reset(struct skge_port * skge)2418 static void skge_phy_reset(struct skge_port *skge)
2419 {
2420 struct skge_hw *hw = skge->hw;
2421 int port = skge->port;
2422 struct net_device *dev = hw->dev[port];
2423
2424 netif_stop_queue(skge->netdev);
2425 netif_carrier_off(skge->netdev);
2426
2427 spin_lock_bh(&hw->phy_lock);
2428 if (is_genesis(hw)) {
2429 genesis_reset(hw, port);
2430 genesis_mac_init(hw, port);
2431 } else {
2432 yukon_reset(hw, port);
2433 yukon_init(hw, port);
2434 }
2435 spin_unlock_bh(&hw->phy_lock);
2436
2437 skge_set_multicast(dev);
2438 }
2439
2440 /* Basic MII support */
skge_ioctl(struct net_device * dev,struct ifreq * ifr,int cmd)2441 static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2442 {
2443 struct mii_ioctl_data *data = if_mii(ifr);
2444 struct skge_port *skge = netdev_priv(dev);
2445 struct skge_hw *hw = skge->hw;
2446 int err = -EOPNOTSUPP;
2447
2448 if (!netif_running(dev))
2449 return -ENODEV; /* Phy still in reset */
2450
2451 switch (cmd) {
2452 case SIOCGMIIPHY:
2453 data->phy_id = hw->phy_addr;
2454
2455 fallthrough;
2456 case SIOCGMIIREG: {
2457 u16 val = 0;
2458 spin_lock_bh(&hw->phy_lock);
2459
2460 if (is_genesis(hw))
2461 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2462 else
2463 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2464 spin_unlock_bh(&hw->phy_lock);
2465 data->val_out = val;
2466 break;
2467 }
2468
2469 case SIOCSMIIREG:
2470 spin_lock_bh(&hw->phy_lock);
2471 if (is_genesis(hw))
2472 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2473 data->val_in);
2474 else
2475 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2476 data->val_in);
2477 spin_unlock_bh(&hw->phy_lock);
2478 break;
2479 }
2480 return err;
2481 }
2482
skge_ramset(struct skge_hw * hw,u16 q,u32 start,size_t len)2483 static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2484 {
2485 u32 end;
2486
2487 start /= 8;
2488 len /= 8;
2489 end = start + len - 1;
2490
2491 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2492 skge_write32(hw, RB_ADDR(q, RB_START), start);
2493 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2494 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2495 skge_write32(hw, RB_ADDR(q, RB_END), end);
2496
2497 if (q == Q_R1 || q == Q_R2) {
2498 /* Set thresholds on receive queue's */
2499 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2500 start + (2*len)/3);
2501 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2502 start + (len/3));
2503 } else {
2504 /* Enable store & forward on Tx queue's because
2505 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2506 */
2507 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2508 }
2509
2510 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2511 }
2512
2513 /* Setup Bus Memory Interface */
skge_qset(struct skge_port * skge,u16 q,const struct skge_element * e)2514 static void skge_qset(struct skge_port *skge, u16 q,
2515 const struct skge_element *e)
2516 {
2517 struct skge_hw *hw = skge->hw;
2518 u32 watermark = 0x600;
2519 u64 base = skge->dma + (e->desc - skge->mem);
2520
2521 /* optimization to reduce window on 32bit/33mhz */
2522 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2523 watermark /= 2;
2524
2525 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2526 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2527 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2528 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2529 }
2530
skge_up(struct net_device * dev)2531 static int skge_up(struct net_device *dev)
2532 {
2533 struct skge_port *skge = netdev_priv(dev);
2534 struct skge_hw *hw = skge->hw;
2535 int port = skge->port;
2536 u32 chunk, ram_addr;
2537 size_t rx_size, tx_size;
2538 int err;
2539
2540 if (!is_valid_ether_addr(dev->dev_addr))
2541 return -EINVAL;
2542
2543 netif_info(skge, ifup, skge->netdev, "enabling interface\n");
2544
2545 if (dev->mtu > RX_BUF_SIZE)
2546 skge->rx_buf_size = dev->mtu + ETH_HLEN;
2547 else
2548 skge->rx_buf_size = RX_BUF_SIZE;
2549
2550
2551 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2552 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2553 skge->mem_size = tx_size + rx_size;
2554 skge->mem = dma_alloc_coherent(&hw->pdev->dev, skge->mem_size,
2555 &skge->dma, GFP_KERNEL);
2556 if (!skge->mem)
2557 return -ENOMEM;
2558
2559 BUG_ON(skge->dma & 7);
2560
2561 if (upper_32_bits(skge->dma) != upper_32_bits(skge->dma + skge->mem_size)) {
2562 dev_err(&hw->pdev->dev, "dma_alloc_coherent region crosses 4G boundary\n");
2563 err = -EINVAL;
2564 goto free_pci_mem;
2565 }
2566
2567 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
2568 if (err)
2569 goto free_pci_mem;
2570
2571 err = skge_rx_fill(dev);
2572 if (err)
2573 goto free_rx_ring;
2574
2575 err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2576 skge->dma + rx_size);
2577 if (err)
2578 goto free_rx_ring;
2579
2580 if (hw->ports == 1) {
2581 err = request_irq(hw->pdev->irq, skge_intr, IRQF_SHARED,
2582 dev->name, hw);
2583 if (err) {
2584 netdev_err(dev, "Unable to allocate interrupt %d error: %d\n",
2585 hw->pdev->irq, err);
2586 goto free_tx_ring;
2587 }
2588 }
2589
2590 /* Initialize MAC */
2591 netif_carrier_off(dev);
2592 spin_lock_bh(&hw->phy_lock);
2593 if (is_genesis(hw))
2594 genesis_mac_init(hw, port);
2595 else
2596 yukon_mac_init(hw, port);
2597 spin_unlock_bh(&hw->phy_lock);
2598
2599 /* Configure RAMbuffers - equally between ports and tx/rx */
2600 chunk = (hw->ram_size - hw->ram_offset) / (hw->ports * 2);
2601 ram_addr = hw->ram_offset + 2 * chunk * port;
2602
2603 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2604 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2605
2606 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2607 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2608 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2609
2610 /* Start receiver BMU */
2611 wmb();
2612 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2613 skge_led(skge, LED_MODE_ON);
2614
2615 spin_lock_irq(&hw->hw_lock);
2616 hw->intr_mask |= portmask[port];
2617 skge_write32(hw, B0_IMSK, hw->intr_mask);
2618 skge_read32(hw, B0_IMSK);
2619 spin_unlock_irq(&hw->hw_lock);
2620
2621 napi_enable(&skge->napi);
2622
2623 skge_set_multicast(dev);
2624
2625 return 0;
2626
2627 free_tx_ring:
2628 kfree(skge->tx_ring.start);
2629 free_rx_ring:
2630 skge_rx_clean(skge);
2631 kfree(skge->rx_ring.start);
2632 free_pci_mem:
2633 dma_free_coherent(&hw->pdev->dev, skge->mem_size, skge->mem,
2634 skge->dma);
2635 skge->mem = NULL;
2636
2637 return err;
2638 }
2639
2640 /* stop receiver */
skge_rx_stop(struct skge_hw * hw,int port)2641 static void skge_rx_stop(struct skge_hw *hw, int port)
2642 {
2643 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2644 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2645 RB_RST_SET|RB_DIS_OP_MD);
2646 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2647 }
2648
skge_down(struct net_device * dev)2649 static int skge_down(struct net_device *dev)
2650 {
2651 struct skge_port *skge = netdev_priv(dev);
2652 struct skge_hw *hw = skge->hw;
2653 int port = skge->port;
2654
2655 if (!skge->mem)
2656 return 0;
2657
2658 netif_info(skge, ifdown, skge->netdev, "disabling interface\n");
2659
2660 netif_tx_disable(dev);
2661
2662 if (is_genesis(hw) && hw->phy_type == SK_PHY_XMAC)
2663 del_timer_sync(&skge->link_timer);
2664
2665 napi_disable(&skge->napi);
2666 netif_carrier_off(dev);
2667
2668 spin_lock_irq(&hw->hw_lock);
2669 hw->intr_mask &= ~portmask[port];
2670 skge_write32(hw, B0_IMSK, (hw->ports == 1) ? 0 : hw->intr_mask);
2671 skge_read32(hw, B0_IMSK);
2672 spin_unlock_irq(&hw->hw_lock);
2673
2674 if (hw->ports == 1)
2675 free_irq(hw->pdev->irq, hw);
2676
2677 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_REG_OFF);
2678 if (is_genesis(hw))
2679 genesis_stop(skge);
2680 else
2681 yukon_stop(skge);
2682
2683 /* Stop transmitter */
2684 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2685 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2686 RB_RST_SET|RB_DIS_OP_MD);
2687
2688
2689 /* Disable Force Sync bit and Enable Alloc bit */
2690 skge_write8(hw, SK_REG(port, TXA_CTRL),
2691 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2692
2693 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2694 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2695 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2696
2697 /* Reset PCI FIFO */
2698 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2699 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2700
2701 /* Reset the RAM Buffer async Tx queue */
2702 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2703
2704 skge_rx_stop(hw, port);
2705
2706 if (is_genesis(hw)) {
2707 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2708 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2709 } else {
2710 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2711 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2712 }
2713
2714 skge_led(skge, LED_MODE_OFF);
2715
2716 netif_tx_lock_bh(dev);
2717 skge_tx_clean(dev);
2718 netif_tx_unlock_bh(dev);
2719
2720 skge_rx_clean(skge);
2721
2722 kfree(skge->rx_ring.start);
2723 kfree(skge->tx_ring.start);
2724 dma_free_coherent(&hw->pdev->dev, skge->mem_size, skge->mem,
2725 skge->dma);
2726 skge->mem = NULL;
2727 return 0;
2728 }
2729
skge_avail(const struct skge_ring * ring)2730 static inline int skge_avail(const struct skge_ring *ring)
2731 {
2732 smp_mb();
2733 return ((ring->to_clean > ring->to_use) ? 0 : ring->count)
2734 + (ring->to_clean - ring->to_use) - 1;
2735 }
2736
skge_xmit_frame(struct sk_buff * skb,struct net_device * dev)2737 static netdev_tx_t skge_xmit_frame(struct sk_buff *skb,
2738 struct net_device *dev)
2739 {
2740 struct skge_port *skge = netdev_priv(dev);
2741 struct skge_hw *hw = skge->hw;
2742 struct skge_element *e;
2743 struct skge_tx_desc *td;
2744 int i;
2745 u32 control, len;
2746 dma_addr_t map;
2747
2748 if (skb_padto(skb, ETH_ZLEN))
2749 return NETDEV_TX_OK;
2750
2751 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1))
2752 return NETDEV_TX_BUSY;
2753
2754 e = skge->tx_ring.to_use;
2755 td = e->desc;
2756 BUG_ON(td->control & BMU_OWN);
2757 e->skb = skb;
2758 len = skb_headlen(skb);
2759 map = dma_map_single(&hw->pdev->dev, skb->data, len, DMA_TO_DEVICE);
2760 if (dma_mapping_error(&hw->pdev->dev, map))
2761 goto mapping_error;
2762
2763 dma_unmap_addr_set(e, mapaddr, map);
2764 dma_unmap_len_set(e, maplen, len);
2765
2766 td->dma_lo = lower_32_bits(map);
2767 td->dma_hi = upper_32_bits(map);
2768
2769 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2770 const int offset = skb_checksum_start_offset(skb);
2771
2772 /* This seems backwards, but it is what the sk98lin
2773 * does. Looks like hardware is wrong?
2774 */
2775 if (ipip_hdr(skb)->protocol == IPPROTO_UDP &&
2776 hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
2777 control = BMU_TCP_CHECK;
2778 else
2779 control = BMU_UDP_CHECK;
2780
2781 td->csum_offs = 0;
2782 td->csum_start = offset;
2783 td->csum_write = offset + skb->csum_offset;
2784 } else
2785 control = BMU_CHECK;
2786
2787 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2788 control |= BMU_EOF | BMU_IRQ_EOF;
2789 else {
2790 struct skge_tx_desc *tf = td;
2791
2792 control |= BMU_STFWD;
2793 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2794 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2795
2796 map = skb_frag_dma_map(&hw->pdev->dev, frag, 0,
2797 skb_frag_size(frag), DMA_TO_DEVICE);
2798 if (dma_mapping_error(&hw->pdev->dev, map))
2799 goto mapping_unwind;
2800
2801 e = e->next;
2802 e->skb = skb;
2803 tf = e->desc;
2804 BUG_ON(tf->control & BMU_OWN);
2805
2806 tf->dma_lo = lower_32_bits(map);
2807 tf->dma_hi = upper_32_bits(map);
2808 dma_unmap_addr_set(e, mapaddr, map);
2809 dma_unmap_len_set(e, maplen, skb_frag_size(frag));
2810
2811 tf->control = BMU_OWN | BMU_SW | control | skb_frag_size(frag);
2812 }
2813 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2814 }
2815 /* Make sure all the descriptors written */
2816 wmb();
2817 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2818 wmb();
2819
2820 netdev_sent_queue(dev, skb->len);
2821
2822 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2823
2824 netif_printk(skge, tx_queued, KERN_DEBUG, skge->netdev,
2825 "tx queued, slot %td, len %d\n",
2826 e - skge->tx_ring.start, skb->len);
2827
2828 skge->tx_ring.to_use = e->next;
2829 smp_wmb();
2830
2831 if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) {
2832 netdev_dbg(dev, "transmit queue full\n");
2833 netif_stop_queue(dev);
2834 }
2835
2836 return NETDEV_TX_OK;
2837
2838 mapping_unwind:
2839 e = skge->tx_ring.to_use;
2840 dma_unmap_single(&hw->pdev->dev, dma_unmap_addr(e, mapaddr),
2841 dma_unmap_len(e, maplen), DMA_TO_DEVICE);
2842 while (i-- > 0) {
2843 e = e->next;
2844 dma_unmap_page(&hw->pdev->dev, dma_unmap_addr(e, mapaddr),
2845 dma_unmap_len(e, maplen), DMA_TO_DEVICE);
2846 }
2847
2848 mapping_error:
2849 if (net_ratelimit())
2850 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
2851 dev_kfree_skb_any(skb);
2852 return NETDEV_TX_OK;
2853 }
2854
2855
2856 /* Free resources associated with this reing element */
skge_tx_unmap(struct pci_dev * pdev,struct skge_element * e,u32 control)2857 static inline void skge_tx_unmap(struct pci_dev *pdev, struct skge_element *e,
2858 u32 control)
2859 {
2860 /* skb header vs. fragment */
2861 if (control & BMU_STF)
2862 dma_unmap_single(&pdev->dev, dma_unmap_addr(e, mapaddr),
2863 dma_unmap_len(e, maplen), DMA_TO_DEVICE);
2864 else
2865 dma_unmap_page(&pdev->dev, dma_unmap_addr(e, mapaddr),
2866 dma_unmap_len(e, maplen), DMA_TO_DEVICE);
2867 }
2868
2869 /* Free all buffers in transmit ring */
skge_tx_clean(struct net_device * dev)2870 static void skge_tx_clean(struct net_device *dev)
2871 {
2872 struct skge_port *skge = netdev_priv(dev);
2873 struct skge_element *e;
2874
2875 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
2876 struct skge_tx_desc *td = e->desc;
2877
2878 skge_tx_unmap(skge->hw->pdev, e, td->control);
2879
2880 if (td->control & BMU_EOF)
2881 dev_kfree_skb(e->skb);
2882 td->control = 0;
2883 }
2884
2885 netdev_reset_queue(dev);
2886 skge->tx_ring.to_clean = e;
2887 }
2888
skge_tx_timeout(struct net_device * dev,unsigned int txqueue)2889 static void skge_tx_timeout(struct net_device *dev, unsigned int txqueue)
2890 {
2891 struct skge_port *skge = netdev_priv(dev);
2892
2893 netif_printk(skge, timer, KERN_DEBUG, skge->netdev, "tx timeout\n");
2894
2895 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2896 skge_tx_clean(dev);
2897 netif_wake_queue(dev);
2898 }
2899
skge_change_mtu(struct net_device * dev,int new_mtu)2900 static int skge_change_mtu(struct net_device *dev, int new_mtu)
2901 {
2902 int err;
2903
2904 if (!netif_running(dev)) {
2905 dev->mtu = new_mtu;
2906 return 0;
2907 }
2908
2909 skge_down(dev);
2910
2911 dev->mtu = new_mtu;
2912
2913 err = skge_up(dev);
2914 if (err)
2915 dev_close(dev);
2916
2917 return err;
2918 }
2919
2920 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
2921
genesis_add_filter(u8 filter[8],const u8 * addr)2922 static void genesis_add_filter(u8 filter[8], const u8 *addr)
2923 {
2924 u32 crc, bit;
2925
2926 crc = ether_crc_le(ETH_ALEN, addr);
2927 bit = ~crc & 0x3f;
2928 filter[bit/8] |= 1 << (bit%8);
2929 }
2930
genesis_set_multicast(struct net_device * dev)2931 static void genesis_set_multicast(struct net_device *dev)
2932 {
2933 struct skge_port *skge = netdev_priv(dev);
2934 struct skge_hw *hw = skge->hw;
2935 int port = skge->port;
2936 struct netdev_hw_addr *ha;
2937 u32 mode;
2938 u8 filter[8];
2939
2940 mode = xm_read32(hw, port, XM_MODE);
2941 mode |= XM_MD_ENA_HASH;
2942 if (dev->flags & IFF_PROMISC)
2943 mode |= XM_MD_ENA_PROM;
2944 else
2945 mode &= ~XM_MD_ENA_PROM;
2946
2947 if (dev->flags & IFF_ALLMULTI)
2948 memset(filter, 0xff, sizeof(filter));
2949 else {
2950 memset(filter, 0, sizeof(filter));
2951
2952 if (skge->flow_status == FLOW_STAT_REM_SEND ||
2953 skge->flow_status == FLOW_STAT_SYMMETRIC)
2954 genesis_add_filter(filter, pause_mc_addr);
2955
2956 netdev_for_each_mc_addr(ha, dev)
2957 genesis_add_filter(filter, ha->addr);
2958 }
2959
2960 xm_write32(hw, port, XM_MODE, mode);
2961 xm_outhash(hw, port, XM_HSM, filter);
2962 }
2963
yukon_add_filter(u8 filter[8],const u8 * addr)2964 static void yukon_add_filter(u8 filter[8], const u8 *addr)
2965 {
2966 u32 bit = ether_crc(ETH_ALEN, addr) & 0x3f;
2967
2968 filter[bit / 8] |= 1 << (bit % 8);
2969 }
2970
yukon_set_multicast(struct net_device * dev)2971 static void yukon_set_multicast(struct net_device *dev)
2972 {
2973 struct skge_port *skge = netdev_priv(dev);
2974 struct skge_hw *hw = skge->hw;
2975 int port = skge->port;
2976 struct netdev_hw_addr *ha;
2977 int rx_pause = (skge->flow_status == FLOW_STAT_REM_SEND ||
2978 skge->flow_status == FLOW_STAT_SYMMETRIC);
2979 u16 reg;
2980 u8 filter[8];
2981
2982 memset(filter, 0, sizeof(filter));
2983
2984 reg = gma_read16(hw, port, GM_RX_CTRL);
2985 reg |= GM_RXCR_UCF_ENA;
2986
2987 if (dev->flags & IFF_PROMISC) /* promiscuous */
2988 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2989 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2990 memset(filter, 0xff, sizeof(filter));
2991 else if (netdev_mc_empty(dev) && !rx_pause)/* no multicast */
2992 reg &= ~GM_RXCR_MCF_ENA;
2993 else {
2994 reg |= GM_RXCR_MCF_ENA;
2995
2996 if (rx_pause)
2997 yukon_add_filter(filter, pause_mc_addr);
2998
2999 netdev_for_each_mc_addr(ha, dev)
3000 yukon_add_filter(filter, ha->addr);
3001 }
3002
3003
3004 gma_write16(hw, port, GM_MC_ADDR_H1,
3005 (u16)filter[0] | ((u16)filter[1] << 8));
3006 gma_write16(hw, port, GM_MC_ADDR_H2,
3007 (u16)filter[2] | ((u16)filter[3] << 8));
3008 gma_write16(hw, port, GM_MC_ADDR_H3,
3009 (u16)filter[4] | ((u16)filter[5] << 8));
3010 gma_write16(hw, port, GM_MC_ADDR_H4,
3011 (u16)filter[6] | ((u16)filter[7] << 8));
3012
3013 gma_write16(hw, port, GM_RX_CTRL, reg);
3014 }
3015
phy_length(const struct skge_hw * hw,u32 status)3016 static inline u16 phy_length(const struct skge_hw *hw, u32 status)
3017 {
3018 if (is_genesis(hw))
3019 return status >> XMR_FS_LEN_SHIFT;
3020 else
3021 return status >> GMR_FS_LEN_SHIFT;
3022 }
3023
bad_phy_status(const struct skge_hw * hw,u32 status)3024 static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
3025 {
3026 if (is_genesis(hw))
3027 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
3028 else
3029 return (status & GMR_FS_ANY_ERR) ||
3030 (status & GMR_FS_RX_OK) == 0;
3031 }
3032
skge_set_multicast(struct net_device * dev)3033 static void skge_set_multicast(struct net_device *dev)
3034 {
3035 struct skge_port *skge = netdev_priv(dev);
3036
3037 if (is_genesis(skge->hw))
3038 genesis_set_multicast(dev);
3039 else
3040 yukon_set_multicast(dev);
3041
3042 }
3043
3044
3045 /* Get receive buffer from descriptor.
3046 * Handles copy of small buffers and reallocation failures
3047 */
skge_rx_get(struct net_device * dev,struct skge_element * e,u32 control,u32 status,u16 csum)3048 static struct sk_buff *skge_rx_get(struct net_device *dev,
3049 struct skge_element *e,
3050 u32 control, u32 status, u16 csum)
3051 {
3052 struct skge_port *skge = netdev_priv(dev);
3053 struct sk_buff *skb;
3054 u16 len = control & BMU_BBC;
3055
3056 netif_printk(skge, rx_status, KERN_DEBUG, skge->netdev,
3057 "rx slot %td status 0x%x len %d\n",
3058 e - skge->rx_ring.start, status, len);
3059
3060 if (len > skge->rx_buf_size)
3061 goto error;
3062
3063 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
3064 goto error;
3065
3066 if (bad_phy_status(skge->hw, status))
3067 goto error;
3068
3069 if (phy_length(skge->hw, status) != len)
3070 goto error;
3071
3072 if (len < RX_COPY_THRESHOLD) {
3073 skb = netdev_alloc_skb_ip_align(dev, len);
3074 if (!skb)
3075 goto resubmit;
3076
3077 dma_sync_single_for_cpu(&skge->hw->pdev->dev,
3078 dma_unmap_addr(e, mapaddr),
3079 dma_unmap_len(e, maplen),
3080 DMA_FROM_DEVICE);
3081 skb_copy_from_linear_data(e->skb, skb->data, len);
3082 dma_sync_single_for_device(&skge->hw->pdev->dev,
3083 dma_unmap_addr(e, mapaddr),
3084 dma_unmap_len(e, maplen),
3085 DMA_FROM_DEVICE);
3086 skge_rx_reuse(e, skge->rx_buf_size);
3087 } else {
3088 struct skge_element ee;
3089 struct sk_buff *nskb;
3090
3091 nskb = netdev_alloc_skb_ip_align(dev, skge->rx_buf_size);
3092 if (!nskb)
3093 goto resubmit;
3094
3095 ee = *e;
3096
3097 skb = ee.skb;
3098 prefetch(skb->data);
3099
3100 if (skge_rx_setup(skge, e, nskb, skge->rx_buf_size) < 0) {
3101 dev_kfree_skb(nskb);
3102 goto resubmit;
3103 }
3104
3105 dma_unmap_single(&skge->hw->pdev->dev,
3106 dma_unmap_addr(&ee, mapaddr),
3107 dma_unmap_len(&ee, maplen), DMA_FROM_DEVICE);
3108 }
3109
3110 skb_put(skb, len);
3111
3112 if (dev->features & NETIF_F_RXCSUM) {
3113 skb->csum = le16_to_cpu(csum);
3114 skb->ip_summed = CHECKSUM_COMPLETE;
3115 }
3116
3117 skb->protocol = eth_type_trans(skb, dev);
3118
3119 return skb;
3120 error:
3121
3122 netif_printk(skge, rx_err, KERN_DEBUG, skge->netdev,
3123 "rx err, slot %td control 0x%x status 0x%x\n",
3124 e - skge->rx_ring.start, control, status);
3125
3126 if (is_genesis(skge->hw)) {
3127 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
3128 dev->stats.rx_length_errors++;
3129 if (status & XMR_FS_FRA_ERR)
3130 dev->stats.rx_frame_errors++;
3131 if (status & XMR_FS_FCS_ERR)
3132 dev->stats.rx_crc_errors++;
3133 } else {
3134 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
3135 dev->stats.rx_length_errors++;
3136 if (status & GMR_FS_FRAGMENT)
3137 dev->stats.rx_frame_errors++;
3138 if (status & GMR_FS_CRC_ERR)
3139 dev->stats.rx_crc_errors++;
3140 }
3141
3142 resubmit:
3143 skge_rx_reuse(e, skge->rx_buf_size);
3144 return NULL;
3145 }
3146
3147 /* Free all buffers in Tx ring which are no longer owned by device */
skge_tx_done(struct net_device * dev)3148 static void skge_tx_done(struct net_device *dev)
3149 {
3150 struct skge_port *skge = netdev_priv(dev);
3151 struct skge_ring *ring = &skge->tx_ring;
3152 struct skge_element *e;
3153 unsigned int bytes_compl = 0, pkts_compl = 0;
3154
3155 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3156
3157 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
3158 u32 control = ((const struct skge_tx_desc *) e->desc)->control;
3159
3160 if (control & BMU_OWN)
3161 break;
3162
3163 skge_tx_unmap(skge->hw->pdev, e, control);
3164
3165 if (control & BMU_EOF) {
3166 netif_printk(skge, tx_done, KERN_DEBUG, skge->netdev,
3167 "tx done slot %td\n",
3168 e - skge->tx_ring.start);
3169
3170 pkts_compl++;
3171 bytes_compl += e->skb->len;
3172
3173 dev_consume_skb_any(e->skb);
3174 }
3175 }
3176 netdev_completed_queue(dev, pkts_compl, bytes_compl);
3177 skge->tx_ring.to_clean = e;
3178
3179 /* Can run lockless until we need to synchronize to restart queue. */
3180 smp_mb();
3181
3182 if (unlikely(netif_queue_stopped(dev) &&
3183 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3184 netif_tx_lock(dev);
3185 if (unlikely(netif_queue_stopped(dev) &&
3186 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3187 netif_wake_queue(dev);
3188
3189 }
3190 netif_tx_unlock(dev);
3191 }
3192 }
3193
skge_poll(struct napi_struct * napi,int budget)3194 static int skge_poll(struct napi_struct *napi, int budget)
3195 {
3196 struct skge_port *skge = container_of(napi, struct skge_port, napi);
3197 struct net_device *dev = skge->netdev;
3198 struct skge_hw *hw = skge->hw;
3199 struct skge_ring *ring = &skge->rx_ring;
3200 struct skge_element *e;
3201 int work_done = 0;
3202
3203 skge_tx_done(dev);
3204
3205 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3206
3207 for (e = ring->to_clean; prefetch(e->next), work_done < budget; e = e->next) {
3208 struct skge_rx_desc *rd = e->desc;
3209 struct sk_buff *skb;
3210 u32 control;
3211
3212 rmb();
3213 control = rd->control;
3214 if (control & BMU_OWN)
3215 break;
3216
3217 skb = skge_rx_get(dev, e, control, rd->status, rd->csum2);
3218 if (likely(skb)) {
3219 napi_gro_receive(napi, skb);
3220 ++work_done;
3221 }
3222 }
3223 ring->to_clean = e;
3224
3225 /* restart receiver */
3226 wmb();
3227 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
3228
3229 if (work_done < budget && napi_complete_done(napi, work_done)) {
3230 unsigned long flags;
3231
3232 spin_lock_irqsave(&hw->hw_lock, flags);
3233 hw->intr_mask |= napimask[skge->port];
3234 skge_write32(hw, B0_IMSK, hw->intr_mask);
3235 skge_read32(hw, B0_IMSK);
3236 spin_unlock_irqrestore(&hw->hw_lock, flags);
3237 }
3238
3239 return work_done;
3240 }
3241
3242 /* Parity errors seem to happen when Genesis is connected to a switch
3243 * with no other ports present. Heartbeat error??
3244 */
skge_mac_parity(struct skge_hw * hw,int port)3245 static void skge_mac_parity(struct skge_hw *hw, int port)
3246 {
3247 struct net_device *dev = hw->dev[port];
3248
3249 ++dev->stats.tx_heartbeat_errors;
3250
3251 if (is_genesis(hw))
3252 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
3253 MFF_CLR_PERR);
3254 else
3255 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
3256 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
3257 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
3258 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
3259 }
3260
skge_mac_intr(struct skge_hw * hw,int port)3261 static void skge_mac_intr(struct skge_hw *hw, int port)
3262 {
3263 if (is_genesis(hw))
3264 genesis_mac_intr(hw, port);
3265 else
3266 yukon_mac_intr(hw, port);
3267 }
3268
3269 /* Handle device specific framing and timeout interrupts */
skge_error_irq(struct skge_hw * hw)3270 static void skge_error_irq(struct skge_hw *hw)
3271 {
3272 struct pci_dev *pdev = hw->pdev;
3273 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3274
3275 if (is_genesis(hw)) {
3276 /* clear xmac errors */
3277 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
3278 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
3279 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
3280 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
3281 } else {
3282 /* Timestamp (unused) overflow */
3283 if (hwstatus & IS_IRQ_TIST_OV)
3284 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3285 }
3286
3287 if (hwstatus & IS_RAM_RD_PAR) {
3288 dev_err(&pdev->dev, "Ram read data parity error\n");
3289 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
3290 }
3291
3292 if (hwstatus & IS_RAM_WR_PAR) {
3293 dev_err(&pdev->dev, "Ram write data parity error\n");
3294 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
3295 }
3296
3297 if (hwstatus & IS_M1_PAR_ERR)
3298 skge_mac_parity(hw, 0);
3299
3300 if (hwstatus & IS_M2_PAR_ERR)
3301 skge_mac_parity(hw, 1);
3302
3303 if (hwstatus & IS_R1_PAR_ERR) {
3304 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3305 hw->dev[0]->name);
3306 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
3307 }
3308
3309 if (hwstatus & IS_R2_PAR_ERR) {
3310 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3311 hw->dev[1]->name);
3312 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
3313 }
3314
3315 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
3316 u16 pci_status, pci_cmd;
3317
3318 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3319 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
3320
3321 dev_err(&pdev->dev, "PCI error cmd=%#x status=%#x\n",
3322 pci_cmd, pci_status);
3323
3324 /* Write the error bits back to clear them. */
3325 pci_status &= PCI_STATUS_ERROR_BITS;
3326 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3327 pci_write_config_word(pdev, PCI_COMMAND,
3328 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
3329 pci_write_config_word(pdev, PCI_STATUS, pci_status);
3330 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3331
3332 /* if error still set then just ignore it */
3333 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3334 if (hwstatus & IS_IRQ_STAT) {
3335 dev_warn(&hw->pdev->dev, "unable to clear error (so ignoring them)\n");
3336 hw->intr_mask &= ~IS_HW_ERR;
3337 }
3338 }
3339 }
3340
3341 /*
3342 * Interrupt from PHY are handled in tasklet (softirq)
3343 * because accessing phy registers requires spin wait which might
3344 * cause excess interrupt latency.
3345 */
skge_extirq(struct tasklet_struct * t)3346 static void skge_extirq(struct tasklet_struct *t)
3347 {
3348 struct skge_hw *hw = from_tasklet(hw, t, phy_task);
3349 int port;
3350
3351 for (port = 0; port < hw->ports; port++) {
3352 struct net_device *dev = hw->dev[port];
3353
3354 if (netif_running(dev)) {
3355 struct skge_port *skge = netdev_priv(dev);
3356
3357 spin_lock(&hw->phy_lock);
3358 if (!is_genesis(hw))
3359 yukon_phy_intr(skge);
3360 else if (hw->phy_type == SK_PHY_BCOM)
3361 bcom_phy_intr(skge);
3362 spin_unlock(&hw->phy_lock);
3363 }
3364 }
3365
3366 spin_lock_irq(&hw->hw_lock);
3367 hw->intr_mask |= IS_EXT_REG;
3368 skge_write32(hw, B0_IMSK, hw->intr_mask);
3369 skge_read32(hw, B0_IMSK);
3370 spin_unlock_irq(&hw->hw_lock);
3371 }
3372
skge_intr(int irq,void * dev_id)3373 static irqreturn_t skge_intr(int irq, void *dev_id)
3374 {
3375 struct skge_hw *hw = dev_id;
3376 u32 status;
3377 int handled = 0;
3378
3379 spin_lock(&hw->hw_lock);
3380 /* Reading this register masks IRQ */
3381 status = skge_read32(hw, B0_SP_ISRC);
3382 if (status == 0 || status == ~0)
3383 goto out;
3384
3385 handled = 1;
3386 status &= hw->intr_mask;
3387 if (status & IS_EXT_REG) {
3388 hw->intr_mask &= ~IS_EXT_REG;
3389 tasklet_schedule(&hw->phy_task);
3390 }
3391
3392 if (status & (IS_XA1_F|IS_R1_F)) {
3393 struct skge_port *skge = netdev_priv(hw->dev[0]);
3394 hw->intr_mask &= ~(IS_XA1_F|IS_R1_F);
3395 napi_schedule(&skge->napi);
3396 }
3397
3398 if (status & IS_PA_TO_TX1)
3399 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
3400
3401 if (status & IS_PA_TO_RX1) {
3402 ++hw->dev[0]->stats.rx_over_errors;
3403 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
3404 }
3405
3406
3407 if (status & IS_MAC1)
3408 skge_mac_intr(hw, 0);
3409
3410 if (hw->dev[1]) {
3411 struct skge_port *skge = netdev_priv(hw->dev[1]);
3412
3413 if (status & (IS_XA2_F|IS_R2_F)) {
3414 hw->intr_mask &= ~(IS_XA2_F|IS_R2_F);
3415 napi_schedule(&skge->napi);
3416 }
3417
3418 if (status & IS_PA_TO_RX2) {
3419 ++hw->dev[1]->stats.rx_over_errors;
3420 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
3421 }
3422
3423 if (status & IS_PA_TO_TX2)
3424 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
3425
3426 if (status & IS_MAC2)
3427 skge_mac_intr(hw, 1);
3428 }
3429
3430 if (status & IS_HW_ERR)
3431 skge_error_irq(hw);
3432 out:
3433 skge_write32(hw, B0_IMSK, hw->intr_mask);
3434 skge_read32(hw, B0_IMSK);
3435 spin_unlock(&hw->hw_lock);
3436
3437 return IRQ_RETVAL(handled);
3438 }
3439
3440 #ifdef CONFIG_NET_POLL_CONTROLLER
skge_netpoll(struct net_device * dev)3441 static void skge_netpoll(struct net_device *dev)
3442 {
3443 struct skge_port *skge = netdev_priv(dev);
3444
3445 disable_irq(dev->irq);
3446 skge_intr(dev->irq, skge->hw);
3447 enable_irq(dev->irq);
3448 }
3449 #endif
3450
skge_set_mac_address(struct net_device * dev,void * p)3451 static int skge_set_mac_address(struct net_device *dev, void *p)
3452 {
3453 struct skge_port *skge = netdev_priv(dev);
3454 struct skge_hw *hw = skge->hw;
3455 unsigned port = skge->port;
3456 const struct sockaddr *addr = p;
3457 u16 ctrl;
3458
3459 if (!is_valid_ether_addr(addr->sa_data))
3460 return -EADDRNOTAVAIL;
3461
3462 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3463
3464 if (!netif_running(dev)) {
3465 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3466 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3467 } else {
3468 /* disable Rx */
3469 spin_lock_bh(&hw->phy_lock);
3470 ctrl = gma_read16(hw, port, GM_GP_CTRL);
3471 gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA);
3472
3473 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3474 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3475
3476 if (is_genesis(hw))
3477 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
3478 else {
3479 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3480 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3481 }
3482
3483 gma_write16(hw, port, GM_GP_CTRL, ctrl);
3484 spin_unlock_bh(&hw->phy_lock);
3485 }
3486
3487 return 0;
3488 }
3489
3490 static const struct {
3491 u8 id;
3492 const char *name;
3493 } skge_chips[] = {
3494 { CHIP_ID_GENESIS, "Genesis" },
3495 { CHIP_ID_YUKON, "Yukon" },
3496 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
3497 { CHIP_ID_YUKON_LP, "Yukon-LP"},
3498 };
3499
skge_board_name(const struct skge_hw * hw)3500 static const char *skge_board_name(const struct skge_hw *hw)
3501 {
3502 int i;
3503 static char buf[16];
3504
3505 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
3506 if (skge_chips[i].id == hw->chip_id)
3507 return skge_chips[i].name;
3508
3509 snprintf(buf, sizeof(buf), "chipid 0x%x", hw->chip_id);
3510 return buf;
3511 }
3512
3513
3514 /*
3515 * Setup the board data structure, but don't bring up
3516 * the port(s)
3517 */
skge_reset(struct skge_hw * hw)3518 static int skge_reset(struct skge_hw *hw)
3519 {
3520 u32 reg;
3521 u16 ctst, pci_status;
3522 u8 t8, mac_cfg, pmd_type;
3523 int i;
3524
3525 ctst = skge_read16(hw, B0_CTST);
3526
3527 /* do a SW reset */
3528 skge_write8(hw, B0_CTST, CS_RST_SET);
3529 skge_write8(hw, B0_CTST, CS_RST_CLR);
3530
3531 /* clear PCI errors, if any */
3532 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3533 skge_write8(hw, B2_TST_CTRL2, 0);
3534
3535 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
3536 pci_write_config_word(hw->pdev, PCI_STATUS,
3537 pci_status | PCI_STATUS_ERROR_BITS);
3538 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3539 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3540
3541 /* restore CLK_RUN bits (for Yukon-Lite) */
3542 skge_write16(hw, B0_CTST,
3543 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3544
3545 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
3546 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
3547 pmd_type = skge_read8(hw, B2_PMD_TYP);
3548 hw->copper = (pmd_type == 'T' || pmd_type == '1');
3549
3550 switch (hw->chip_id) {
3551 case CHIP_ID_GENESIS:
3552 #ifdef CONFIG_SKGE_GENESIS
3553 switch (hw->phy_type) {
3554 case SK_PHY_XMAC:
3555 hw->phy_addr = PHY_ADDR_XMAC;
3556 break;
3557 case SK_PHY_BCOM:
3558 hw->phy_addr = PHY_ADDR_BCOM;
3559 break;
3560 default:
3561 dev_err(&hw->pdev->dev, "unsupported phy type 0x%x\n",
3562 hw->phy_type);
3563 return -EOPNOTSUPP;
3564 }
3565 break;
3566 #else
3567 dev_err(&hw->pdev->dev, "Genesis chip detected but not configured\n");
3568 return -EOPNOTSUPP;
3569 #endif
3570
3571 case CHIP_ID_YUKON:
3572 case CHIP_ID_YUKON_LITE:
3573 case CHIP_ID_YUKON_LP:
3574 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
3575 hw->copper = 1;
3576
3577 hw->phy_addr = PHY_ADDR_MARV;
3578 break;
3579
3580 default:
3581 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3582 hw->chip_id);
3583 return -EOPNOTSUPP;
3584 }
3585
3586 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3587 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3588 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
3589
3590 /* read the adapters RAM size */
3591 t8 = skge_read8(hw, B2_E_0);
3592 if (is_genesis(hw)) {
3593 if (t8 == 3) {
3594 /* special case: 4 x 64k x 36, offset = 0x80000 */
3595 hw->ram_size = 0x100000;
3596 hw->ram_offset = 0x80000;
3597 } else
3598 hw->ram_size = t8 * 512;
3599 } else if (t8 == 0)
3600 hw->ram_size = 0x20000;
3601 else
3602 hw->ram_size = t8 * 4096;
3603
3604 hw->intr_mask = IS_HW_ERR;
3605
3606 /* Use PHY IRQ for all but fiber based Genesis board */
3607 if (!(is_genesis(hw) && hw->phy_type == SK_PHY_XMAC))
3608 hw->intr_mask |= IS_EXT_REG;
3609
3610 if (is_genesis(hw))
3611 genesis_init(hw);
3612 else {
3613 /* switch power to VCC (WA for VAUX problem) */
3614 skge_write8(hw, B0_POWER_CTRL,
3615 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
3616
3617 /* avoid boards with stuck Hardware error bits */
3618 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3619 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
3620 dev_warn(&hw->pdev->dev, "stuck hardware sensor bit\n");
3621 hw->intr_mask &= ~IS_HW_ERR;
3622 }
3623
3624 /* Clear PHY COMA */
3625 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3626 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®);
3627 reg &= ~PCI_PHY_COMA;
3628 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3629 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3630
3631
3632 for (i = 0; i < hw->ports; i++) {
3633 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3634 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3635 }
3636 }
3637
3638 /* turn off hardware timer (unused) */
3639 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3640 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3641 skge_write8(hw, B0_LED, LED_STAT_ON);
3642
3643 /* enable the Tx Arbiters */
3644 for (i = 0; i < hw->ports; i++)
3645 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3646
3647 /* Initialize ram interface */
3648 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3649
3650 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3651 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3652 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3653 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3654 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3655 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3656 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3657 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3658 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3659 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3660 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3661 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3662
3663 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3664
3665 /* Set interrupt moderation for Transmit only
3666 * Receive interrupts avoided by NAPI
3667 */
3668 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3669 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3670 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3671
3672 /* Leave irq disabled until first port is brought up. */
3673 skge_write32(hw, B0_IMSK, 0);
3674
3675 for (i = 0; i < hw->ports; i++) {
3676 if (is_genesis(hw))
3677 genesis_reset(hw, i);
3678 else
3679 yukon_reset(hw, i);
3680 }
3681
3682 return 0;
3683 }
3684
3685
3686 #ifdef CONFIG_SKGE_DEBUG
3687
3688 static struct dentry *skge_debug;
3689
skge_debug_show(struct seq_file * seq,void * v)3690 static int skge_debug_show(struct seq_file *seq, void *v)
3691 {
3692 struct net_device *dev = seq->private;
3693 const struct skge_port *skge = netdev_priv(dev);
3694 const struct skge_hw *hw = skge->hw;
3695 const struct skge_element *e;
3696
3697 if (!netif_running(dev))
3698 return -ENETDOWN;
3699
3700 seq_printf(seq, "IRQ src=%x mask=%x\n", skge_read32(hw, B0_ISRC),
3701 skge_read32(hw, B0_IMSK));
3702
3703 seq_printf(seq, "Tx Ring: (%d)\n", skge_avail(&skge->tx_ring));
3704 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
3705 const struct skge_tx_desc *t = e->desc;
3706 seq_printf(seq, "%#x dma=%#x%08x %#x csum=%#x/%x/%x\n",
3707 t->control, t->dma_hi, t->dma_lo, t->status,
3708 t->csum_offs, t->csum_write, t->csum_start);
3709 }
3710
3711 seq_puts(seq, "\nRx Ring:\n");
3712 for (e = skge->rx_ring.to_clean; ; e = e->next) {
3713 const struct skge_rx_desc *r = e->desc;
3714
3715 if (r->control & BMU_OWN)
3716 break;
3717
3718 seq_printf(seq, "%#x dma=%#x%08x %#x %#x csum=%#x/%x\n",
3719 r->control, r->dma_hi, r->dma_lo, r->status,
3720 r->timestamp, r->csum1, r->csum1_start);
3721 }
3722
3723 return 0;
3724 }
3725 DEFINE_SHOW_ATTRIBUTE(skge_debug);
3726
3727 /*
3728 * Use network device events to create/remove/rename
3729 * debugfs file entries
3730 */
skge_device_event(struct notifier_block * unused,unsigned long event,void * ptr)3731 static int skge_device_event(struct notifier_block *unused,
3732 unsigned long event, void *ptr)
3733 {
3734 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
3735 struct skge_port *skge;
3736
3737 if (dev->netdev_ops->ndo_open != &skge_up || !skge_debug)
3738 goto done;
3739
3740 skge = netdev_priv(dev);
3741 switch (event) {
3742 case NETDEV_CHANGENAME:
3743 if (skge->debugfs)
3744 skge->debugfs = debugfs_rename(skge_debug,
3745 skge->debugfs,
3746 skge_debug, dev->name);
3747 break;
3748
3749 case NETDEV_GOING_DOWN:
3750 debugfs_remove(skge->debugfs);
3751 skge->debugfs = NULL;
3752 break;
3753
3754 case NETDEV_UP:
3755 skge->debugfs = debugfs_create_file(dev->name, 0444, skge_debug,
3756 dev, &skge_debug_fops);
3757 break;
3758 }
3759
3760 done:
3761 return NOTIFY_DONE;
3762 }
3763
3764 static struct notifier_block skge_notifier = {
3765 .notifier_call = skge_device_event,
3766 };
3767
3768
skge_debug_init(void)3769 static __init void skge_debug_init(void)
3770 {
3771 skge_debug = debugfs_create_dir("skge", NULL);
3772
3773 register_netdevice_notifier(&skge_notifier);
3774 }
3775
skge_debug_cleanup(void)3776 static __exit void skge_debug_cleanup(void)
3777 {
3778 if (skge_debug) {
3779 unregister_netdevice_notifier(&skge_notifier);
3780 debugfs_remove(skge_debug);
3781 skge_debug = NULL;
3782 }
3783 }
3784
3785 #else
3786 #define skge_debug_init()
3787 #define skge_debug_cleanup()
3788 #endif
3789
3790 static const struct net_device_ops skge_netdev_ops = {
3791 .ndo_open = skge_up,
3792 .ndo_stop = skge_down,
3793 .ndo_start_xmit = skge_xmit_frame,
3794 .ndo_eth_ioctl = skge_ioctl,
3795 .ndo_get_stats = skge_get_stats,
3796 .ndo_tx_timeout = skge_tx_timeout,
3797 .ndo_change_mtu = skge_change_mtu,
3798 .ndo_validate_addr = eth_validate_addr,
3799 .ndo_set_rx_mode = skge_set_multicast,
3800 .ndo_set_mac_address = skge_set_mac_address,
3801 #ifdef CONFIG_NET_POLL_CONTROLLER
3802 .ndo_poll_controller = skge_netpoll,
3803 #endif
3804 };
3805
3806
3807 /* Initialize network device */
skge_devinit(struct skge_hw * hw,int port,int highmem)3808 static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3809 int highmem)
3810 {
3811 struct skge_port *skge;
3812 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3813
3814 if (!dev)
3815 return NULL;
3816
3817 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3818 dev->netdev_ops = &skge_netdev_ops;
3819 dev->ethtool_ops = &skge_ethtool_ops;
3820 dev->watchdog_timeo = TX_WATCHDOG;
3821 dev->irq = hw->pdev->irq;
3822
3823 /* MTU range: 60 - 9000 */
3824 dev->min_mtu = ETH_ZLEN;
3825 dev->max_mtu = ETH_JUMBO_MTU;
3826
3827 if (highmem)
3828 dev->features |= NETIF_F_HIGHDMA;
3829
3830 skge = netdev_priv(dev);
3831 netif_napi_add(dev, &skge->napi, skge_poll, NAPI_WEIGHT);
3832 skge->netdev = dev;
3833 skge->hw = hw;
3834 skge->msg_enable = netif_msg_init(debug, default_msg);
3835
3836 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3837 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3838
3839 /* Auto speed and flow control */
3840 skge->autoneg = AUTONEG_ENABLE;
3841 skge->flow_control = FLOW_MODE_SYM_OR_REM;
3842 skge->duplex = -1;
3843 skge->speed = -1;
3844 skge->advertising = skge_supported_modes(hw);
3845
3846 if (device_can_wakeup(&hw->pdev->dev)) {
3847 skge->wol = wol_supported(hw) & WAKE_MAGIC;
3848 device_set_wakeup_enable(&hw->pdev->dev, skge->wol);
3849 }
3850
3851 hw->dev[port] = dev;
3852
3853 skge->port = port;
3854
3855 /* Only used for Genesis XMAC */
3856 if (is_genesis(hw))
3857 timer_setup(&skge->link_timer, xm_link_timer, 0);
3858 else {
3859 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
3860 NETIF_F_RXCSUM;
3861 dev->features |= dev->hw_features;
3862 }
3863
3864 /* read the mac address */
3865 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3866
3867 return dev;
3868 }
3869
skge_show_addr(struct net_device * dev)3870 static void skge_show_addr(struct net_device *dev)
3871 {
3872 const struct skge_port *skge = netdev_priv(dev);
3873
3874 netif_info(skge, probe, skge->netdev, "addr %pM\n", dev->dev_addr);
3875 }
3876
3877 static int only_32bit_dma;
3878
skge_probe(struct pci_dev * pdev,const struct pci_device_id * ent)3879 static int skge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3880 {
3881 struct net_device *dev, *dev1;
3882 struct skge_hw *hw;
3883 int err, using_dac = 0;
3884
3885 err = pci_enable_device(pdev);
3886 if (err) {
3887 dev_err(&pdev->dev, "cannot enable PCI device\n");
3888 goto err_out;
3889 }
3890
3891 err = pci_request_regions(pdev, DRV_NAME);
3892 if (err) {
3893 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
3894 goto err_out_disable_pdev;
3895 }
3896
3897 pci_set_master(pdev);
3898
3899 if (!only_32bit_dma && !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
3900 using_dac = 1;
3901 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
3902 } else if (!(err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)))) {
3903 using_dac = 0;
3904 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
3905 }
3906
3907 if (err) {
3908 dev_err(&pdev->dev, "no usable DMA configuration\n");
3909 goto err_out_free_regions;
3910 }
3911
3912 #ifdef __BIG_ENDIAN
3913 /* byte swap descriptors in hardware */
3914 {
3915 u32 reg;
3916
3917 pci_read_config_dword(pdev, PCI_DEV_REG2, ®);
3918 reg |= PCI_REV_DESC;
3919 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3920 }
3921 #endif
3922
3923 err = -ENOMEM;
3924 /* space for skge@pci:0000:04:00.0 */
3925 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
3926 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
3927 if (!hw)
3928 goto err_out_free_regions;
3929
3930 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
3931
3932 hw->pdev = pdev;
3933 spin_lock_init(&hw->hw_lock);
3934 spin_lock_init(&hw->phy_lock);
3935 tasklet_setup(&hw->phy_task, skge_extirq);
3936
3937 hw->regs = ioremap(pci_resource_start(pdev, 0), 0x4000);
3938 if (!hw->regs) {
3939 dev_err(&pdev->dev, "cannot map device registers\n");
3940 goto err_out_free_hw;
3941 }
3942
3943 err = skge_reset(hw);
3944 if (err)
3945 goto err_out_iounmap;
3946
3947 pr_info("%s addr 0x%llx irq %d chip %s rev %d\n",
3948 DRV_VERSION,
3949 (unsigned long long)pci_resource_start(pdev, 0), pdev->irq,
3950 skge_board_name(hw), hw->chip_rev);
3951
3952 dev = skge_devinit(hw, 0, using_dac);
3953 if (!dev) {
3954 err = -ENOMEM;
3955 goto err_out_led_off;
3956 }
3957
3958 /* Some motherboards are broken and has zero in ROM. */
3959 if (!is_valid_ether_addr(dev->dev_addr))
3960 dev_warn(&pdev->dev, "bad (zero?) ethernet address in rom\n");
3961
3962 err = register_netdev(dev);
3963 if (err) {
3964 dev_err(&pdev->dev, "cannot register net device\n");
3965 goto err_out_free_netdev;
3966 }
3967
3968 skge_show_addr(dev);
3969
3970 if (hw->ports > 1) {
3971 dev1 = skge_devinit(hw, 1, using_dac);
3972 if (!dev1) {
3973 err = -ENOMEM;
3974 goto err_out_unregister;
3975 }
3976
3977 err = register_netdev(dev1);
3978 if (err) {
3979 dev_err(&pdev->dev, "cannot register second net device\n");
3980 goto err_out_free_dev1;
3981 }
3982
3983 err = request_irq(pdev->irq, skge_intr, IRQF_SHARED,
3984 hw->irq_name, hw);
3985 if (err) {
3986 dev_err(&pdev->dev, "cannot assign irq %d\n",
3987 pdev->irq);
3988 goto err_out_unregister_dev1;
3989 }
3990
3991 skge_show_addr(dev1);
3992 }
3993 pci_set_drvdata(pdev, hw);
3994
3995 return 0;
3996
3997 err_out_unregister_dev1:
3998 unregister_netdev(dev1);
3999 err_out_free_dev1:
4000 free_netdev(dev1);
4001 err_out_unregister:
4002 unregister_netdev(dev);
4003 err_out_free_netdev:
4004 free_netdev(dev);
4005 err_out_led_off:
4006 skge_write16(hw, B0_LED, LED_STAT_OFF);
4007 err_out_iounmap:
4008 iounmap(hw->regs);
4009 err_out_free_hw:
4010 kfree(hw);
4011 err_out_free_regions:
4012 pci_release_regions(pdev);
4013 err_out_disable_pdev:
4014 pci_disable_device(pdev);
4015 err_out:
4016 return err;
4017 }
4018
skge_remove(struct pci_dev * pdev)4019 static void skge_remove(struct pci_dev *pdev)
4020 {
4021 struct skge_hw *hw = pci_get_drvdata(pdev);
4022 struct net_device *dev0, *dev1;
4023
4024 if (!hw)
4025 return;
4026
4027 dev1 = hw->dev[1];
4028 if (dev1)
4029 unregister_netdev(dev1);
4030 dev0 = hw->dev[0];
4031 unregister_netdev(dev0);
4032
4033 tasklet_kill(&hw->phy_task);
4034
4035 spin_lock_irq(&hw->hw_lock);
4036 hw->intr_mask = 0;
4037
4038 if (hw->ports > 1) {
4039 skge_write32(hw, B0_IMSK, 0);
4040 skge_read32(hw, B0_IMSK);
4041 }
4042 spin_unlock_irq(&hw->hw_lock);
4043
4044 skge_write16(hw, B0_LED, LED_STAT_OFF);
4045 skge_write8(hw, B0_CTST, CS_RST_SET);
4046
4047 if (hw->ports > 1)
4048 free_irq(pdev->irq, hw);
4049 pci_release_regions(pdev);
4050 pci_disable_device(pdev);
4051 if (dev1)
4052 free_netdev(dev1);
4053 free_netdev(dev0);
4054
4055 iounmap(hw->regs);
4056 kfree(hw);
4057 }
4058
4059 #ifdef CONFIG_PM_SLEEP
skge_suspend(struct device * dev)4060 static int skge_suspend(struct device *dev)
4061 {
4062 struct skge_hw *hw = dev_get_drvdata(dev);
4063 int i;
4064
4065 if (!hw)
4066 return 0;
4067
4068 for (i = 0; i < hw->ports; i++) {
4069 struct net_device *dev = hw->dev[i];
4070 struct skge_port *skge = netdev_priv(dev);
4071
4072 if (netif_running(dev))
4073 skge_down(dev);
4074
4075 if (skge->wol)
4076 skge_wol_init(skge);
4077 }
4078
4079 skge_write32(hw, B0_IMSK, 0);
4080
4081 return 0;
4082 }
4083
skge_resume(struct device * dev)4084 static int skge_resume(struct device *dev)
4085 {
4086 struct skge_hw *hw = dev_get_drvdata(dev);
4087 int i, err;
4088
4089 if (!hw)
4090 return 0;
4091
4092 err = skge_reset(hw);
4093 if (err)
4094 goto out;
4095
4096 for (i = 0; i < hw->ports; i++) {
4097 struct net_device *dev = hw->dev[i];
4098
4099 if (netif_running(dev)) {
4100 err = skge_up(dev);
4101
4102 if (err) {
4103 netdev_err(dev, "could not up: %d\n", err);
4104 dev_close(dev);
4105 goto out;
4106 }
4107 }
4108 }
4109 out:
4110 return err;
4111 }
4112
4113 static SIMPLE_DEV_PM_OPS(skge_pm_ops, skge_suspend, skge_resume);
4114 #define SKGE_PM_OPS (&skge_pm_ops)
4115
4116 #else
4117
4118 #define SKGE_PM_OPS NULL
4119 #endif /* CONFIG_PM_SLEEP */
4120
skge_shutdown(struct pci_dev * pdev)4121 static void skge_shutdown(struct pci_dev *pdev)
4122 {
4123 struct skge_hw *hw = pci_get_drvdata(pdev);
4124 int i;
4125
4126 if (!hw)
4127 return;
4128
4129 for (i = 0; i < hw->ports; i++) {
4130 struct net_device *dev = hw->dev[i];
4131 struct skge_port *skge = netdev_priv(dev);
4132
4133 if (skge->wol)
4134 skge_wol_init(skge);
4135 }
4136
4137 pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev));
4138 pci_set_power_state(pdev, PCI_D3hot);
4139 }
4140
4141 static struct pci_driver skge_driver = {
4142 .name = DRV_NAME,
4143 .id_table = skge_id_table,
4144 .probe = skge_probe,
4145 .remove = skge_remove,
4146 .shutdown = skge_shutdown,
4147 .driver.pm = SKGE_PM_OPS,
4148 };
4149
4150 static const struct dmi_system_id skge_32bit_dma_boards[] = {
4151 {
4152 .ident = "Gigabyte nForce boards",
4153 .matches = {
4154 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co"),
4155 DMI_MATCH(DMI_BOARD_NAME, "nForce"),
4156 },
4157 },
4158 {
4159 .ident = "ASUS P5NSLI",
4160 .matches = {
4161 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
4162 DMI_MATCH(DMI_BOARD_NAME, "P5NSLI")
4163 },
4164 },
4165 {
4166 .ident = "FUJITSU SIEMENS A8NE-FM",
4167 .matches = {
4168 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTek Computer INC."),
4169 DMI_MATCH(DMI_BOARD_NAME, "A8NE-FM")
4170 },
4171 },
4172 {}
4173 };
4174
skge_init_module(void)4175 static int __init skge_init_module(void)
4176 {
4177 if (dmi_check_system(skge_32bit_dma_boards))
4178 only_32bit_dma = 1;
4179 skge_debug_init();
4180 return pci_register_driver(&skge_driver);
4181 }
4182
skge_cleanup_module(void)4183 static void __exit skge_cleanup_module(void)
4184 {
4185 pci_unregister_driver(&skge_driver);
4186 skge_debug_cleanup();
4187 }
4188
4189 module_init(skge_init_module);
4190 module_exit(skge_cleanup_module);
4191
