1 /* 2 * Copyright (C) 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21 #ifndef _sdma0_4_0_SH_MASK_HEADER 22 #define _sdma0_4_0_SH_MASK_HEADER 23 24 25 // addressBlock: sdma0_sdma0dec 26 //SDMA0_UCODE_ADDR 27 #define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0 28 #define SDMA0_UCODE_ADDR__VALUE_MASK 0x00001FFFL 29 //SDMA0_UCODE_DATA 30 #define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0 31 #define SDMA0_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL 32 //SDMA0_VM_CNTL 33 #define SDMA0_VM_CNTL__CMD__SHIFT 0x0 34 #define SDMA0_VM_CNTL__CMD_MASK 0x0000000FL 35 //SDMA0_VM_CTX_LO 36 #define SDMA0_VM_CTX_LO__ADDR__SHIFT 0x2 37 #define SDMA0_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL 38 //SDMA0_VM_CTX_HI 39 #define SDMA0_VM_CTX_HI__ADDR__SHIFT 0x0 40 #define SDMA0_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL 41 //SDMA0_ACTIVE_FCN_ID 42 #define SDMA0_ACTIVE_FCN_ID__VFID__SHIFT 0x0 43 #define SDMA0_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 44 #define SDMA0_ACTIVE_FCN_ID__VF__SHIFT 0x1f 45 #define SDMA0_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL 46 #define SDMA0_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L 47 #define SDMA0_ACTIVE_FCN_ID__VF_MASK 0x80000000L 48 //SDMA0_VM_CTX_CNTL 49 #define SDMA0_VM_CTX_CNTL__PRIV__SHIFT 0x0 50 #define SDMA0_VM_CTX_CNTL__VMID__SHIFT 0x4 51 #define SDMA0_VM_CTX_CNTL__PRIV_MASK 0x00000001L 52 #define SDMA0_VM_CTX_CNTL__VMID_MASK 0x000000F0L 53 //SDMA0_VIRT_RESET_REQ 54 #define SDMA0_VIRT_RESET_REQ__VF__SHIFT 0x0 55 #define SDMA0_VIRT_RESET_REQ__PF__SHIFT 0x1f 56 #define SDMA0_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL 57 #define SDMA0_VIRT_RESET_REQ__PF_MASK 0x80000000L 58 //SDMA0_VF_ENABLE 59 #define SDMA0_VF_ENABLE__VF_ENABLE__SHIFT 0x0 60 #define SDMA0_VF_ENABLE__VF_ENABLE_MASK 0x00000001L 61 //SDMA0_CONTEXT_REG_TYPE0 62 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL__SHIFT 0x0 63 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE__SHIFT 0x1 64 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI__SHIFT 0x2 65 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR__SHIFT 0x3 66 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI__SHIFT 0x4 67 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR__SHIFT 0x5 68 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI__SHIFT 0x6 69 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 70 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 71 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 72 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT 0xa 73 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR__SHIFT 0xb 74 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET__SHIFT 0xc 75 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO__SHIFT 0xd 76 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI__SHIFT 0xe 77 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE__SHIFT 0xf 78 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL__SHIFT 0x10 79 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS__SHIFT 0x11 80 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL__SHIFT 0x12 81 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL__SHIFT 0x13 82 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL_MASK 0x00000001L 83 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_MASK 0x00000002L 84 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI_MASK 0x00000004L 85 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_MASK 0x00000008L 86 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI_MASK 0x00000010L 87 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_MASK 0x00000020L 88 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI_MASK 0x00000040L 89 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L 90 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L 91 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L 92 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL_MASK 0x00000400L 93 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR_MASK 0x00000800L 94 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET_MASK 0x00001000L 95 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO_MASK 0x00002000L 96 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI_MASK 0x00004000L 97 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE_MASK 0x00008000L 98 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL_MASK 0x00010000L 99 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS_MASK 0x00020000L 100 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL_MASK 0x00040000L 101 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL_MASK 0x00080000L 102 //SDMA0_CONTEXT_REG_TYPE1 103 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS__SHIFT 0x8 104 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG__SHIFT 0x9 105 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT 0xa 106 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET__SHIFT 0xb 107 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO__SHIFT 0xc 108 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI__SHIFT 0xd 109 #define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe 110 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN__SHIFT 0xf 111 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT__SHIFT 0x10 112 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG__SHIFT 0x11 113 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 114 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 115 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL__SHIFT 0x14 116 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 117 #define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16 118 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS_MASK 0x00000100L 119 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG_MASK 0x00000200L 120 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK_MASK 0x00000400L 121 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET_MASK 0x00000800L 122 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO_MASK 0x00001000L 123 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI_MASK 0x00002000L 124 #define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L 125 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN_MASK 0x00008000L 126 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT_MASK 0x00010000L 127 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG_MASK 0x00020000L 128 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L 129 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L 130 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL_MASK 0x00100000L 131 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L 132 #define SDMA0_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L 133 //SDMA0_CONTEXT_REG_TYPE2 134 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0__SHIFT 0x0 135 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1__SHIFT 0x1 136 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2__SHIFT 0x2 137 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3__SHIFT 0x3 138 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4__SHIFT 0x4 139 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5__SHIFT 0x5 140 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6__SHIFT 0x6 141 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7__SHIFT 0x7 142 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8__SHIFT 0x8 143 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL__SHIFT 0x9 144 #define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa 145 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0_MASK 0x00000001L 146 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1_MASK 0x00000002L 147 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2_MASK 0x00000004L 148 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3_MASK 0x00000008L 149 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4_MASK 0x00000010L 150 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5_MASK 0x00000020L 151 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6_MASK 0x00000040L 152 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7_MASK 0x00000080L 153 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8_MASK 0x00000100L 154 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL_MASK 0x00000200L 155 #define SDMA0_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L 156 //SDMA0_CONTEXT_REG_TYPE3 157 #define SDMA0_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 158 #define SDMA0_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL 159 //SDMA0_PUB_REG_TYPE0 160 #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT 0x0 161 #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT 0x1 162 #define SDMA0_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3 163 #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL__SHIFT 0x4 164 #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO__SHIFT 0x5 165 #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI__SHIFT 0x6 166 #define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID__SHIFT 0x7 167 #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL__SHIFT 0x8 168 #define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ__SHIFT 0x9 169 #define SDMA0_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa 170 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0__SHIFT 0xb 171 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1__SHIFT 0xc 172 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2__SHIFT 0xd 173 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3__SHIFT 0xe 174 #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0__SHIFT 0xf 175 #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1__SHIFT 0x10 176 #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2__SHIFT 0x11 177 #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3__SHIFT 0x12 178 #define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL__SHIFT 0x13 179 #define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x14 180 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19 181 #define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT 0x1a 182 #define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL__SHIFT 0x1b 183 #define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL__SHIFT 0x1c 184 #define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT 0x1d 185 #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG__SHIFT 0x1e 186 #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ__SHIFT 0x1f 187 #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR_MASK 0x00000001L 188 #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA_MASK 0x00000002L 189 #define SDMA0_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L 190 #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL_MASK 0x00000010L 191 #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO_MASK 0x00000020L 192 #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI_MASK 0x00000040L 193 #define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID_MASK 0x00000080L 194 #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL_MASK 0x00000100L 195 #define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ_MASK 0x00000200L 196 #define SDMA0_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L 197 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0_MASK 0x00000800L 198 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1_MASK 0x00001000L 199 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2_MASK 0x00002000L 200 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3_MASK 0x00004000L 201 #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0_MASK 0x00008000L 202 #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1_MASK 0x00010000L 203 #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2_MASK 0x00020000L 204 #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3_MASK 0x00040000L 205 #define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL_MASK 0x00080000L 206 #define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01F00000L 207 #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L 208 #define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL_MASK 0x04000000L 209 #define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL_MASK 0x08000000L 210 #define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL_MASK 0x10000000L 211 #define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS_MASK 0x20000000L 212 #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_MASK 0x40000000L 213 #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ_MASK 0x80000000L 214 //SDMA0_PUB_REG_TYPE1 215 #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI__SHIFT 0x0 216 #define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 217 #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH__SHIFT 0x2 218 #define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH__SHIFT 0x3 219 #define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM__SHIFT 0x4 220 #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG__SHIFT 0x5 221 #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG__SHIFT 0x6 222 #define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL__SHIFT 0x7 223 #define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG__SHIFT 0x8 224 #define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM__SHIFT 0x9 225 #define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL__SHIFT 0xa 226 #define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE__SHIFT 0xb 227 #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM__SHIFT 0xc 228 #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM__SHIFT 0xd 229 #define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe 230 #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf 231 #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10 232 #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11 233 #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG__SHIFT 0x12 234 #define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD__SHIFT 0x13 235 #define SDMA0_PUB_REG_TYPE1__SDMA0_ID__SHIFT 0x14 236 #define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION__SHIFT 0x15 237 #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER__SHIFT 0x16 238 #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR__SHIFT 0x17 239 #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT 0x18 240 #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT 0x19 241 #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO__SHIFT 0x1a 242 #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI__SHIFT 0x1b 243 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL__SHIFT 0x1c 244 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK__SHIFT 0x1d 245 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS__SHIFT 0x1e 246 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS__SHIFT 0x1f 247 #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI_MASK 0x00000001L 248 #define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L 249 #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_MASK 0x00000004L 250 #define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH_MASK 0x00000008L 251 #define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM_MASK 0x00000010L 252 #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG_MASK 0x00000020L 253 #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG_MASK 0x00000040L 254 #define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL_MASK 0x00000080L 255 #define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG_MASK 0x00000100L 256 #define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM_MASK 0x00000200L 257 #define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL_MASK 0x00000400L 258 #define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE_MASK 0x00000800L 259 #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM_MASK 0x00001000L 260 #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM_MASK 0x00002000L 261 #define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L 262 #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L 263 #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L 264 #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L 265 #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG_MASK 0x00040000L 266 #define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD_MASK 0x00080000L 267 #define SDMA0_PUB_REG_TYPE1__SDMA0_ID_MASK 0x00100000L 268 #define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION_MASK 0x00200000L 269 #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_MASK 0x00400000L 270 #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR_MASK 0x00800000L 271 #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG_MASK 0x01000000L 272 #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL_MASK 0x02000000L 273 #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO_MASK 0x04000000L 274 #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI_MASK 0x08000000L 275 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL_MASK 0x10000000L 276 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK_MASK 0x20000000L 277 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS_MASK 0x40000000L 278 #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS_MASK 0x80000000L 279 //SDMA0_PUB_REG_TYPE2 280 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0__SHIFT 0x0 281 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1__SHIFT 0x1 282 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2__SHIFT 0x2 283 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0__SHIFT 0x3 284 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1__SHIFT 0x4 285 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0__SHIFT 0x5 286 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1__SHIFT 0x6 287 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT__SHIFT 0x7 288 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE__SHIFT 0x8 289 #define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE__SHIFT 0x9 290 #define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT__SHIFT 0xa 291 #define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2__SHIFT 0xb 292 #define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG__SHIFT 0xc 293 #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO__SHIFT 0xd 294 #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI__SHIFT 0xe 295 #define SDMA0_PUB_REG_TYPE2__SDMA0_PHASE2_QUANTUM__SHIFT 0xf 296 #define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG__SHIFT 0x10 297 #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0__SHIFT 0x11 298 #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1__SHIFT 0x12 299 #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2__SHIFT 0x13 300 #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3__SHIFT 0x14 301 #define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER__SHIFT 0x15 302 #define SDMA0_PUB_REG_TYPE2__SDMA0_UNBREAKABLE__SHIFT 0x16 303 #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL__SHIFT 0x17 304 #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT__SHIFT 0x18 305 #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT__SHIFT 0x19 306 #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a 307 #define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL__SHIFT 0x1b 308 #define SDMA0_PUB_REG_TYPE2__SDMA0_MMHUB_TRUSTLVL__SHIFT 0x1c 309 #define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d 310 #define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL__SHIFT 0x1e 311 #define SDMA0_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f 312 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0_MASK 0x00000001L 313 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1_MASK 0x00000002L 314 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2_MASK 0x00000004L 315 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0_MASK 0x00000008L 316 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1_MASK 0x00000010L 317 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0_MASK 0x00000020L 318 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1_MASK 0x00000040L 319 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT_MASK 0x00000080L 320 #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE_MASK 0x00000100L 321 #define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE_MASK 0x00000200L 322 #define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT_MASK 0x00000400L 323 #define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2_MASK 0x00000800L 324 #define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG_MASK 0x00001000L 325 #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO_MASK 0x00002000L 326 #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI_MASK 0x00004000L 327 #define SDMA0_PUB_REG_TYPE2__SDMA0_PHASE2_QUANTUM_MASK 0x00008000L 328 #define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG_MASK 0x00010000L 329 #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0_MASK 0x00020000L 330 #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1_MASK 0x00040000L 331 #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2_MASK 0x00080000L 332 #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3_MASK 0x00100000L 333 #define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER_MASK 0x00200000L 334 #define SDMA0_PUB_REG_TYPE2__SDMA0_UNBREAKABLE_MASK 0x00400000L 335 #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL_MASK 0x00800000L 336 #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT_MASK 0x01000000L 337 #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT_MASK 0x02000000L 338 #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L 339 #define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL_MASK 0x08000000L 340 #define SDMA0_PUB_REG_TYPE2__SDMA0_MMHUB_TRUSTLVL_MASK 0x10000000L 341 #define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L 342 #define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL_MASK 0x40000000L 343 #define SDMA0_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L 344 //SDMA0_PUB_REG_TYPE3 345 #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA__SHIFT 0x0 346 #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX__SHIFT 0x1 347 #define SDMA0_PUB_REG_TYPE3__RESERVED__SHIFT 0x2 348 #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA_MASK 0x00000001L 349 #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX_MASK 0x00000002L 350 #define SDMA0_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFFCL 351 //SDMA0_MMHUB_CNTL 352 #define SDMA0_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 353 #define SDMA0_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL 354 //SDMA0_CONTEXT_GROUP_BOUNDARY 355 #define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 356 #define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL 357 //SDMA0_POWER_CNTL 358 #define SDMA0_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0 359 #define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1 360 #define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2 361 #define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 362 #define SDMA0_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 363 #define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa 364 #define SDMA0_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb 365 #define SDMA0_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc 366 #define SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L 367 #define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L 368 #define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L 369 #define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L 370 #define SDMA0_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L 371 #define SDMA0_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L 372 #define SDMA0_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L 373 #define SDMA0_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L 374 //SDMA0_CLK_CTRL 375 #define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0 376 #define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 377 #define SDMA0_CLK_CTRL__RESERVED__SHIFT 0xc 378 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 379 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 380 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 381 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 382 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 383 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 384 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 385 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 386 #define SDMA0_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 387 #define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 388 #define SDMA0_CLK_CTRL__RESERVED_MASK 0x00FFF000L 389 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 390 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 391 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L 392 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 393 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 394 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 395 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L 396 #define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L 397 //SDMA0_CNTL 398 #define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0 399 #define SDMA0_CNTL__UTC_L1_ENABLE__SHIFT 0x1 400 #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 401 #define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 402 #define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 403 #define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 404 #define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 405 #define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 406 #define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c 407 #define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d 408 #define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e 409 #define SDMA0_CNTL__TRAP_ENABLE_MASK 0x00000001L 410 #define SDMA0_CNTL__UTC_L1_ENABLE_MASK 0x00000002L 411 #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L 412 #define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L 413 #define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L 414 #define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L 415 #define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L 416 #define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L 417 #define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L 418 #define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L 419 #define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L 420 //SDMA0_CHICKEN_BITS 421 #define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 422 #define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 423 #define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 424 #define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 425 #define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa 426 #define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 427 #define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 428 #define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 429 #define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 430 #define SDMA0_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 431 #define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a 432 #define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c 433 #define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e 434 #define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L 435 #define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L 436 #define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L 437 #define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L 438 #define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L 439 #define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L 440 #define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L 441 #define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L 442 #define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L 443 #define SDMA0_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L 444 #define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L 445 #define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L 446 #define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L 447 //SDMA0_GB_ADDR_CONFIG 448 #define SDMA0_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 449 #define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 450 #define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 451 #define SDMA0_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 452 #define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 453 #define SDMA0_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 454 #define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 455 #define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 456 #define SDMA0_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 457 #define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 458 //SDMA0_GB_ADDR_CONFIG_READ 459 #define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 460 #define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 461 #define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 462 #define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc 463 #define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 464 #define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L 465 #define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 466 #define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 467 #define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L 468 #define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L 469 //SDMA0_RB_RPTR_FETCH_HI 470 #define SDMA0_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 471 #define SDMA0_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL 472 //SDMA0_SEM_WAIT_FAIL_TIMER_CNTL 473 #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 474 #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL 475 //SDMA0_RB_RPTR_FETCH 476 #define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 477 #define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL 478 //SDMA0_IB_OFFSET_FETCH 479 #define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 480 #define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL 481 //SDMA0_PROGRAM 482 #define SDMA0_PROGRAM__STREAM__SHIFT 0x0 483 #define SDMA0_PROGRAM__STREAM_MASK 0xFFFFFFFFL 484 //SDMA0_STATUS_REG 485 #define SDMA0_STATUS_REG__IDLE__SHIFT 0x0 486 #define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1 487 #define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2 488 #define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3 489 #define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 490 #define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 491 #define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 492 #define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 493 #define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 494 #define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9 495 #define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa 496 #define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb 497 #define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc 498 #define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd 499 #define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe 500 #define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf 501 #define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 502 #define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 503 #define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 504 #define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 505 #define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 506 #define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 507 #define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 508 #define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 509 #define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a 510 #define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b 511 #define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c 512 #define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e 513 #define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f 514 #define SDMA0_STATUS_REG__IDLE_MASK 0x00000001L 515 #define SDMA0_STATUS_REG__REG_IDLE_MASK 0x00000002L 516 #define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x00000004L 517 #define SDMA0_STATUS_REG__RB_FULL_MASK 0x00000008L 518 #define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L 519 #define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L 520 #define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L 521 #define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L 522 #define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L 523 #define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x00000200L 524 #define SDMA0_STATUS_REG__EX_IDLE_MASK 0x00000400L 525 #define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L 526 #define SDMA0_STATUS_REG__PACKET_READY_MASK 0x00001000L 527 #define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L 528 #define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x00004000L 529 #define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L 530 #define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L 531 #define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L 532 #define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L 533 #define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L 534 #define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L 535 #define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L 536 #define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L 537 #define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L 538 #define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x04000000L 539 #define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L 540 #define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L 541 #define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000L 542 #define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L 543 //SDMA0_STATUS1_REG 544 #define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 545 #define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 546 #define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 547 #define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 548 #define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 549 #define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 550 #define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 551 #define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 552 #define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa 553 #define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd 554 #define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe 555 #define SDMA0_STATUS1_REG__EX_START__SHIFT 0xf 556 #define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 557 #define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 558 #define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L 559 #define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L 560 #define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L 561 #define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L 562 #define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L 563 #define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L 564 #define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L 565 #define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L 566 #define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L 567 #define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L 568 #define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L 569 #define SDMA0_STATUS1_REG__EX_START_MASK 0x00008000L 570 #define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L 571 #define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L 572 //SDMA0_RD_BURST_CNTL 573 #define SDMA0_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 574 #define SDMA0_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L 575 //SDMA0_HBM_PAGE_CONFIG 576 #define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 577 #define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L 578 //SDMA0_UCODE_CHECKSUM 579 #define SDMA0_UCODE_CHECKSUM__DATA__SHIFT 0x0 580 #define SDMA0_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL 581 //SDMA0_F32_CNTL 582 #define SDMA0_F32_CNTL__HALT__SHIFT 0x0 583 #define SDMA0_F32_CNTL__STEP__SHIFT 0x1 584 #define SDMA0_F32_CNTL__HALT_MASK 0x00000001L 585 #define SDMA0_F32_CNTL__STEP_MASK 0x00000002L 586 //SDMA0_FREEZE 587 #define SDMA0_FREEZE__PREEMPT__SHIFT 0x0 588 #define SDMA0_FREEZE__FREEZE__SHIFT 0x4 589 #define SDMA0_FREEZE__FROZEN__SHIFT 0x5 590 #define SDMA0_FREEZE__F32_FREEZE__SHIFT 0x6 591 #define SDMA0_FREEZE__PREEMPT_MASK 0x00000001L 592 #define SDMA0_FREEZE__FREEZE_MASK 0x00000010L 593 #define SDMA0_FREEZE__FROZEN_MASK 0x00000020L 594 #define SDMA0_FREEZE__F32_FREEZE_MASK 0x00000040L 595 //SDMA0_PHASE0_QUANTUM 596 #define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0 597 #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8 598 #define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e 599 #define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL 600 #define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L 601 #define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000L 602 //SDMA0_PHASE1_QUANTUM 603 #define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0 604 #define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8 605 #define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e 606 #define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL 607 #define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L 608 #define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000L 609 //SDMA_POWER_GATING 610 #define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION__SHIFT 0x0 611 #define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION__SHIFT 0x1 612 #define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ__SHIFT 0x2 613 #define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ__SHIFT 0x3 614 #define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4 615 #define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION_MASK 0x00000001L 616 #define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION_MASK 0x00000002L 617 #define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ_MASK 0x00000004L 618 #define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ_MASK 0x00000008L 619 #define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x00000030L 620 //SDMA_PGFSM_CONFIG 621 #define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0 622 #define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8 623 #define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9 624 #define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa 625 #define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb 626 #define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc 627 #define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd 628 #define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b 629 #define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c 630 #define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0x000000FFL 631 #define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x00000100L 632 #define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x00000200L 633 #define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x00000400L 634 #define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x00000800L 635 #define SDMA_PGFSM_CONFIG__WRITE_MASK 0x00001000L 636 #define SDMA_PGFSM_CONFIG__READ_MASK 0x00002000L 637 #define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x08000000L 638 #define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xF0000000L 639 //SDMA_PGFSM_WRITE 640 #define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0 641 #define SDMA_PGFSM_WRITE__VALUE_MASK 0xFFFFFFFFL 642 //SDMA_PGFSM_READ 643 #define SDMA_PGFSM_READ__VALUE__SHIFT 0x0 644 #define SDMA_PGFSM_READ__VALUE_MASK 0x00FFFFFFL 645 //SDMA0_EDC_CONFIG 646 #define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1 647 #define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 648 #define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x00000002L 649 #define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L 650 //SDMA0_BA_THRESHOLD 651 #define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT 0x0 652 #define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 653 #define SDMA0_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL 654 #define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L 655 //SDMA0_ID 656 #define SDMA0_ID__DEVICE_ID__SHIFT 0x0 657 #define SDMA0_ID__DEVICE_ID_MASK 0x000000FFL 658 //SDMA0_VERSION 659 #define SDMA0_VERSION__MINVER__SHIFT 0x0 660 #define SDMA0_VERSION__MAJVER__SHIFT 0x8 661 #define SDMA0_VERSION__REV__SHIFT 0x10 662 #define SDMA0_VERSION__MINVER_MASK 0x0000007FL 663 #define SDMA0_VERSION__MAJVER_MASK 0x00007F00L 664 #define SDMA0_VERSION__REV_MASK 0x003F0000L 665 //SDMA0_EDC_COUNTER 666 #define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT 0x0 667 #define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT 0x1 668 #define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 669 #define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 670 #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 671 #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 672 #define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 673 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 674 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 675 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 676 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa 677 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb 678 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc 679 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd 680 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe 681 #define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0xf 682 #define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10 683 #define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK 0x00000001L 684 #define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK 0x00000002L 685 #define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L 686 #define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L 687 #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L 688 #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L 689 #define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L 690 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L 691 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L 692 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L 693 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L 694 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L 695 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L 696 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L 697 #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L 698 #define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00008000L 699 #define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00010000L 700 //SDMA0_EDC_COUNTER_CLEAR 701 #define SDMA0_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 702 #define SDMA0_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L 703 //SDMA0_STATUS2_REG 704 #define SDMA0_STATUS2_REG__ID__SHIFT 0x0 705 #define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2 706 #define SDMA0_STATUS2_REG__CMD_OP__SHIFT 0x10 707 #define SDMA0_STATUS2_REG__ID_MASK 0x00000003L 708 #define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK 0x00000FFCL 709 #define SDMA0_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L 710 //SDMA0_ATOMIC_CNTL 711 #define SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 712 #define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f 713 #define SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL 714 #define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L 715 //SDMA0_ATOMIC_PREOP_LO 716 #define SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 717 #define SDMA0_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL 718 //SDMA0_ATOMIC_PREOP_HI 719 #define SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 720 #define SDMA0_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL 721 //SDMA0_UTCL1_CNTL 722 #define SDMA0_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 723 #define SDMA0_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 724 #define SDMA0_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb 725 #define SDMA0_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe 726 #define SDMA0_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 727 #define SDMA0_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d 728 #define SDMA0_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L 729 #define SDMA0_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL 730 #define SDMA0_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L 731 #define SDMA0_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L 732 #define SDMA0_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L 733 #define SDMA0_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L 734 //SDMA0_UTCL1_WATERMK 735 #define SDMA0_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 736 #define SDMA0_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa 737 #define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x12 738 #define SDMA0_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x1a 739 #define SDMA0_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000003FFL 740 #define SDMA0_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0003FC00L 741 #define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x03FC0000L 742 #define SDMA0_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFC000000L 743 //SDMA0_UTCL1_RD_STATUS 744 #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 745 #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 746 #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 747 #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 748 #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 749 #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 750 #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 751 #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 752 #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 753 #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 754 #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 755 #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 756 #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 757 #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 758 #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 759 #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 760 #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 761 #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 762 #define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 763 #define SDMA0_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 764 #define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 765 #define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 766 #define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 767 #define SDMA0_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a 768 #define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d 769 #define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e 770 #define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f 771 #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 772 #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 773 #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 774 #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 775 #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 776 #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 777 #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 778 #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 779 #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 780 #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 781 #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 782 #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 783 #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 784 #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 785 #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 786 #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 787 #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 788 #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 789 #define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L 790 #define SDMA0_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L 791 #define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L 792 #define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L 793 #define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L 794 #define SDMA0_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L 795 #define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L 796 #define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L 797 #define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L 798 //SDMA0_UTCL1_WR_STATUS 799 #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 800 #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 801 #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 802 #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 803 #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 804 #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 805 #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 806 #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 807 #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 808 #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 809 #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 810 #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 811 #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 812 #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 813 #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 814 #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 815 #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 816 #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 817 #define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 818 #define SDMA0_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 819 #define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 820 #define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 821 #define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 822 #define SDMA0_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 823 #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c 824 #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d 825 #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e 826 #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f 827 #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 828 #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 829 #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 830 #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 831 #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 832 #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 833 #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 834 #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 835 #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 836 #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 837 #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 838 #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 839 #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 840 #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 841 #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 842 #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 843 #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 844 #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 845 #define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L 846 #define SDMA0_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L 847 #define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L 848 #define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L 849 #define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L 850 #define SDMA0_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L 851 #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L 852 #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L 853 #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L 854 #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L 855 //SDMA0_UTCL1_INV0 856 #define SDMA0_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 857 #define SDMA0_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 858 #define SDMA0_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 859 #define SDMA0_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 860 #define SDMA0_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 861 #define SDMA0_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 862 #define SDMA0_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 863 #define SDMA0_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 864 #define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 865 #define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 866 #define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa 867 #define SDMA0_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb 868 #define SDMA0_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc 869 #define SDMA0_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c 870 #define SDMA0_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L 871 #define SDMA0_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L 872 #define SDMA0_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L 873 #define SDMA0_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L 874 #define SDMA0_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L 875 #define SDMA0_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L 876 #define SDMA0_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L 877 #define SDMA0_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L 878 #define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L 879 #define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L 880 #define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L 881 #define SDMA0_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L 882 #define SDMA0_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L 883 #define SDMA0_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L 884 //SDMA0_UTCL1_INV1 885 #define SDMA0_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 886 #define SDMA0_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL 887 //SDMA0_UTCL1_INV2 888 #define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 889 #define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL 890 //SDMA0_UTCL1_RD_XNACK0 891 #define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 892 #define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 893 //SDMA0_UTCL1_RD_XNACK1 894 #define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 895 #define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 896 #define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 897 #define SDMA0_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a 898 #define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 899 #define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L 900 #define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 901 #define SDMA0_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L 902 //SDMA0_UTCL1_WR_XNACK0 903 #define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 904 #define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 905 //SDMA0_UTCL1_WR_XNACK1 906 #define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 907 #define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 908 #define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 909 #define SDMA0_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a 910 #define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 911 #define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L 912 #define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 913 #define SDMA0_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L 914 //SDMA0_UTCL1_TIMEOUT 915 #define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 916 #define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 917 #define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL 918 #define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L 919 //SDMA0_UTCL1_PAGE 920 #define SDMA0_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 921 #define SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 922 #define SDMA0_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 923 #define SDMA0_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 924 #define SDMA0_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L 925 #define SDMA0_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL 926 #define SDMA0_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L 927 #define SDMA0_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L 928 //SDMA0_POWER_CNTL_IDLE 929 #define SDMA0_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 930 #define SDMA0_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 931 #define SDMA0_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 932 #define SDMA0_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL 933 #define SDMA0_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L 934 #define SDMA0_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L 935 //SDMA0_RELAX_ORDERING_LUT 936 #define SDMA0_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 937 #define SDMA0_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 938 #define SDMA0_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 939 #define SDMA0_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 940 #define SDMA0_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 941 #define SDMA0_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 942 #define SDMA0_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 943 #define SDMA0_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 944 #define SDMA0_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 945 #define SDMA0_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa 946 #define SDMA0_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb 947 #define SDMA0_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc 948 #define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd 949 #define SDMA0_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe 950 #define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b 951 #define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c 952 #define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d 953 #define SDMA0_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e 954 #define SDMA0_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f 955 #define SDMA0_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L 956 #define SDMA0_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L 957 #define SDMA0_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L 958 #define SDMA0_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L 959 #define SDMA0_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L 960 #define SDMA0_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L 961 #define SDMA0_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L 962 #define SDMA0_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L 963 #define SDMA0_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L 964 #define SDMA0_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L 965 #define SDMA0_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L 966 #define SDMA0_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L 967 #define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L 968 #define SDMA0_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L 969 #define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L 970 #define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L 971 #define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L 972 #define SDMA0_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L 973 #define SDMA0_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L 974 //SDMA0_CHICKEN_BITS_2 975 #define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 976 #define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL 977 //SDMA0_STATUS3_REG 978 #define SDMA0_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 979 #define SDMA0_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 980 #define SDMA0_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 981 #define SDMA0_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL 982 #define SDMA0_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L 983 #define SDMA0_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L 984 //SDMA0_PHYSICAL_ADDR_LO 985 #define SDMA0_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 986 #define SDMA0_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 987 #define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 988 #define SDMA0_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc 989 #define SDMA0_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L 990 #define SDMA0_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L 991 #define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L 992 #define SDMA0_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L 993 //SDMA0_PHYSICAL_ADDR_HI 994 #define SDMA0_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 995 #define SDMA0_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL 996 //SDMA0_PHASE2_QUANTUM 997 #define SDMA0_PHASE2_QUANTUM__UNIT__SHIFT 0x0 998 #define SDMA0_PHASE2_QUANTUM__VALUE__SHIFT 0x8 999 #define SDMA0_PHASE2_QUANTUM__PREFER__SHIFT 0x1e 1000 #define SDMA0_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL 1001 #define SDMA0_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L 1002 #define SDMA0_PHASE2_QUANTUM__PREFER_MASK 0x40000000L 1003 //SDMA0_ERROR_LOG 1004 #define SDMA0_ERROR_LOG__OVERRIDE__SHIFT 0x0 1005 #define SDMA0_ERROR_LOG__STATUS__SHIFT 0x10 1006 #define SDMA0_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL 1007 #define SDMA0_ERROR_LOG__STATUS_MASK 0xFFFF0000L 1008 //SDMA0_PUB_DUMMY_REG0 1009 #define SDMA0_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 1010 #define SDMA0_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL 1011 //SDMA0_PUB_DUMMY_REG1 1012 #define SDMA0_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 1013 #define SDMA0_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL 1014 //SDMA0_PUB_DUMMY_REG2 1015 #define SDMA0_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 1016 #define SDMA0_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL 1017 //SDMA0_PUB_DUMMY_REG3 1018 #define SDMA0_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 1019 #define SDMA0_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL 1020 //SDMA0_F32_COUNTER 1021 #define SDMA0_F32_COUNTER__VALUE__SHIFT 0x0 1022 #define SDMA0_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL 1023 //SDMA0_UNBREAKABLE 1024 #define SDMA0_UNBREAKABLE__VALUE__SHIFT 0x0 1025 #define SDMA0_UNBREAKABLE__VALUE_MASK 0x00000001L 1026 //SDMA0_PERFMON_CNTL 1027 #define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 1028 #define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 1029 #define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 1030 #define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa 1031 #define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb 1032 #define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc 1033 #define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L 1034 #define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L 1035 #define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL 1036 #define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L 1037 #define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L 1038 #define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L 1039 //SDMA0_PERFCOUNTER0_RESULT 1040 #define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 1041 #define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 1042 //SDMA0_PERFCOUNTER1_RESULT 1043 #define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 1044 #define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 1045 //SDMA0_PERFCOUNTER_TAG_DELAY_RANGE 1046 #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0 1047 #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe 1048 #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c 1049 #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL 1050 #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L 1051 #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L 1052 //SDMA0_CRD_CNTL 1053 #define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 1054 #define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd 1055 #define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L 1056 #define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L 1057 //SDMA0_MMHUB_TRUSTLVL 1058 #define SDMA0_MMHUB_TRUSTLVL__SECFLAG0__SHIFT 0x0 1059 #define SDMA0_MMHUB_TRUSTLVL__SECFLAG1__SHIFT 0x3 1060 #define SDMA0_MMHUB_TRUSTLVL__SECFLAG2__SHIFT 0x6 1061 #define SDMA0_MMHUB_TRUSTLVL__SECFLAG3__SHIFT 0x9 1062 #define SDMA0_MMHUB_TRUSTLVL__SECFLAG4__SHIFT 0xc 1063 #define SDMA0_MMHUB_TRUSTLVL__SECFLAG5__SHIFT 0xf 1064 #define SDMA0_MMHUB_TRUSTLVL__SECFLAG6__SHIFT 0x12 1065 #define SDMA0_MMHUB_TRUSTLVL__SECFLAG7__SHIFT 0x15 1066 #define SDMA0_MMHUB_TRUSTLVL__SECFLAG0_MASK 0x00000007L 1067 #define SDMA0_MMHUB_TRUSTLVL__SECFLAG1_MASK 0x00000038L 1068 #define SDMA0_MMHUB_TRUSTLVL__SECFLAG2_MASK 0x000001C0L 1069 #define SDMA0_MMHUB_TRUSTLVL__SECFLAG3_MASK 0x00000E00L 1070 #define SDMA0_MMHUB_TRUSTLVL__SECFLAG4_MASK 0x00007000L 1071 #define SDMA0_MMHUB_TRUSTLVL__SECFLAG5_MASK 0x00038000L 1072 #define SDMA0_MMHUB_TRUSTLVL__SECFLAG6_MASK 0x001C0000L 1073 #define SDMA0_MMHUB_TRUSTLVL__SECFLAG7_MASK 0x00E00000L 1074 //SDMA0_GPU_IOV_VIOLATION_LOG 1075 #define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 1076 #define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 1077 #define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 1078 #define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x12 1079 #define SDMA0_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13 1080 #define SDMA0_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14 1081 #define SDMA0_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18 1082 #define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L 1083 #define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L 1084 #define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL 1085 #define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00040000L 1086 #define SDMA0_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L 1087 #define SDMA0_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x00F00000L 1088 #define SDMA0_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L 1089 //SDMA0_ULV_CNTL 1090 #define SDMA0_ULV_CNTL__HYSTERESIS__SHIFT 0x0 1091 #define SDMA0_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d 1092 #define SDMA0_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e 1093 #define SDMA0_ULV_CNTL__ULV_STATUS__SHIFT 0x1f 1094 #define SDMA0_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL 1095 #define SDMA0_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L 1096 #define SDMA0_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L 1097 #define SDMA0_ULV_CNTL__ULV_STATUS_MASK 0x80000000L 1098 //SDMA0_EA_DBIT_ADDR_DATA 1099 #define SDMA0_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 1100 #define SDMA0_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL 1101 //SDMA0_EA_DBIT_ADDR_INDEX 1102 #define SDMA0_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 1103 #define SDMA0_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L 1104 //SDMA0_GFX_RB_CNTL 1105 #define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 1106 #define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 1107 #define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1108 #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1109 #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1110 #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1111 #define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 1112 #define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 1113 #define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1114 #define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x0000007EL 1115 #define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1116 #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1117 #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1118 #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1119 #define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L 1120 #define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L 1121 //SDMA0_GFX_RB_BASE 1122 #define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0 1123 #define SDMA0_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1124 //SDMA0_GFX_RB_BASE_HI 1125 #define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 1126 #define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1127 //SDMA0_GFX_RB_RPTR 1128 #define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x0 1129 #define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1130 //SDMA0_GFX_RB_RPTR_HI 1131 #define SDMA0_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 1132 #define SDMA0_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1133 //SDMA0_GFX_RB_WPTR 1134 #define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x0 1135 #define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1136 //SDMA0_GFX_RB_WPTR_HI 1137 #define SDMA0_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 1138 #define SDMA0_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1139 //SDMA0_GFX_RB_WPTR_POLL_CNTL 1140 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1141 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1142 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1143 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1144 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1145 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1146 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1147 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1148 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1149 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1150 //SDMA0_GFX_RB_RPTR_ADDR_HI 1151 #define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1152 #define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1153 //SDMA0_GFX_RB_RPTR_ADDR_LO 1154 #define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1155 #define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1156 //SDMA0_GFX_IB_CNTL 1157 #define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 1158 #define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1159 #define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1160 #define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 1161 #define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1162 #define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1163 #define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1164 #define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1165 //SDMA0_GFX_IB_RPTR 1166 #define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2 1167 #define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1168 //SDMA0_GFX_IB_OFFSET 1169 #define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 1170 #define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1171 //SDMA0_GFX_IB_BASE_LO 1172 #define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 1173 #define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1174 //SDMA0_GFX_IB_BASE_HI 1175 #define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 1176 #define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1177 //SDMA0_GFX_IB_SIZE 1178 #define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0 1179 #define SDMA0_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL 1180 //SDMA0_GFX_SKIP_CNTL 1181 #define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1182 #define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL 1183 //SDMA0_GFX_CONTEXT_STATUS 1184 #define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1185 #define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 1186 #define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1187 #define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1188 #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1189 #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1190 #define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1191 #define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1192 #define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1193 #define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1194 #define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1195 #define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1196 #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1197 #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1198 #define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1199 #define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1200 //SDMA0_GFX_DOORBELL 1201 #define SDMA0_GFX_DOORBELL__ENABLE__SHIFT 0x1c 1202 #define SDMA0_GFX_DOORBELL__CAPTURED__SHIFT 0x1e 1203 #define SDMA0_GFX_DOORBELL__ENABLE_MASK 0x10000000L 1204 #define SDMA0_GFX_DOORBELL__CAPTURED_MASK 0x40000000L 1205 //SDMA0_GFX_CONTEXT_CNTL 1206 #define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 1207 #define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L 1208 //SDMA0_GFX_STATUS 1209 #define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1210 #define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1211 #define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1212 #define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1213 //SDMA0_GFX_DOORBELL_LOG 1214 #define SDMA0_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1215 #define SDMA0_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 1216 #define SDMA0_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1217 #define SDMA0_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1218 //SDMA0_GFX_WATERMARK 1219 #define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1220 #define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1221 #define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1222 #define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1223 //SDMA0_GFX_DOORBELL_OFFSET 1224 #define SDMA0_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1225 #define SDMA0_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1226 //SDMA0_GFX_CSA_ADDR_LO 1227 #define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 1228 #define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1229 //SDMA0_GFX_CSA_ADDR_HI 1230 #define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 1231 #define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1232 //SDMA0_GFX_IB_SUB_REMAIN 1233 #define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1234 #define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 1235 //SDMA0_GFX_PREEMPT 1236 #define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 1237 #define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1238 //SDMA0_GFX_DUMMY_REG 1239 #define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 1240 #define SDMA0_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1241 //SDMA0_GFX_RB_WPTR_POLL_ADDR_HI 1242 #define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1243 #define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1244 //SDMA0_GFX_RB_WPTR_POLL_ADDR_LO 1245 #define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1246 #define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1247 //SDMA0_GFX_RB_AQL_CNTL 1248 #define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1249 #define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1250 #define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1251 #define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1252 #define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1253 #define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1254 //SDMA0_GFX_MINOR_PTR_UPDATE 1255 #define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1256 #define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1257 //SDMA0_GFX_MIDCMD_DATA0 1258 #define SDMA0_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 1259 #define SDMA0_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1260 //SDMA0_GFX_MIDCMD_DATA1 1261 #define SDMA0_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 1262 #define SDMA0_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1263 //SDMA0_GFX_MIDCMD_DATA2 1264 #define SDMA0_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 1265 #define SDMA0_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1266 //SDMA0_GFX_MIDCMD_DATA3 1267 #define SDMA0_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 1268 #define SDMA0_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1269 //SDMA0_GFX_MIDCMD_DATA4 1270 #define SDMA0_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 1271 #define SDMA0_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1272 //SDMA0_GFX_MIDCMD_DATA5 1273 #define SDMA0_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 1274 #define SDMA0_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1275 //SDMA0_GFX_MIDCMD_DATA6 1276 #define SDMA0_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 1277 #define SDMA0_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1278 //SDMA0_GFX_MIDCMD_DATA7 1279 #define SDMA0_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 1280 #define SDMA0_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1281 //SDMA0_GFX_MIDCMD_DATA8 1282 #define SDMA0_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 1283 #define SDMA0_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1284 //SDMA0_GFX_MIDCMD_CNTL 1285 #define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1286 #define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1287 #define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1288 #define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1289 #define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1290 #define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1291 #define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1292 #define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1293 //SDMA0_PAGE_RB_CNTL 1294 #define SDMA0_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 1295 #define SDMA0_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 1296 #define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1297 #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1298 #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1299 #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1300 #define SDMA0_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 1301 #define SDMA0_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 1302 #define SDMA0_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1303 #define SDMA0_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000007EL 1304 #define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1305 #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1306 #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1307 #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1308 #define SDMA0_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L 1309 #define SDMA0_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L 1310 //SDMA0_PAGE_RB_BASE 1311 #define SDMA0_PAGE_RB_BASE__ADDR__SHIFT 0x0 1312 #define SDMA0_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1313 //SDMA0_PAGE_RB_BASE_HI 1314 #define SDMA0_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 1315 #define SDMA0_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1316 //SDMA0_PAGE_RB_RPTR 1317 #define SDMA0_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 1318 #define SDMA0_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1319 //SDMA0_PAGE_RB_RPTR_HI 1320 #define SDMA0_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 1321 #define SDMA0_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1322 //SDMA0_PAGE_RB_WPTR 1323 #define SDMA0_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 1324 #define SDMA0_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1325 //SDMA0_PAGE_RB_WPTR_HI 1326 #define SDMA0_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 1327 #define SDMA0_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1328 //SDMA0_PAGE_RB_WPTR_POLL_CNTL 1329 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1330 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1331 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1332 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1333 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1334 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1335 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1336 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1337 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1338 #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1339 //SDMA0_PAGE_RB_RPTR_ADDR_HI 1340 #define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1341 #define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1342 //SDMA0_PAGE_RB_RPTR_ADDR_LO 1343 #define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1344 #define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1345 //SDMA0_PAGE_IB_CNTL 1346 #define SDMA0_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 1347 #define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1348 #define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1349 #define SDMA0_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 1350 #define SDMA0_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1351 #define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1352 #define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1353 #define SDMA0_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1354 //SDMA0_PAGE_IB_RPTR 1355 #define SDMA0_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 1356 #define SDMA0_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1357 //SDMA0_PAGE_IB_OFFSET 1358 #define SDMA0_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 1359 #define SDMA0_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1360 //SDMA0_PAGE_IB_BASE_LO 1361 #define SDMA0_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 1362 #define SDMA0_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1363 //SDMA0_PAGE_IB_BASE_HI 1364 #define SDMA0_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 1365 #define SDMA0_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1366 //SDMA0_PAGE_IB_SIZE 1367 #define SDMA0_PAGE_IB_SIZE__SIZE__SHIFT 0x0 1368 #define SDMA0_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL 1369 //SDMA0_PAGE_SKIP_CNTL 1370 #define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1371 #define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL 1372 //SDMA0_PAGE_CONTEXT_STATUS 1373 #define SDMA0_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1374 #define SDMA0_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 1375 #define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1376 #define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1377 #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1378 #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1379 #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1380 #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1381 #define SDMA0_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1382 #define SDMA0_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1383 #define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1384 #define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1385 #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1386 #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1387 #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1388 #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1389 //SDMA0_PAGE_DOORBELL 1390 #define SDMA0_PAGE_DOORBELL__ENABLE__SHIFT 0x1c 1391 #define SDMA0_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e 1392 #define SDMA0_PAGE_DOORBELL__ENABLE_MASK 0x10000000L 1393 #define SDMA0_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L 1394 //SDMA0_PAGE_STATUS 1395 #define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1396 #define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1397 #define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1398 #define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1399 //SDMA0_PAGE_DOORBELL_LOG 1400 #define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1401 #define SDMA0_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 1402 #define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1403 #define SDMA0_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1404 //SDMA0_PAGE_WATERMARK 1405 #define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1406 #define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1407 #define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1408 #define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1409 //SDMA0_PAGE_DOORBELL_OFFSET 1410 #define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1411 #define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1412 //SDMA0_PAGE_CSA_ADDR_LO 1413 #define SDMA0_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 1414 #define SDMA0_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1415 //SDMA0_PAGE_CSA_ADDR_HI 1416 #define SDMA0_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 1417 #define SDMA0_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1418 //SDMA0_PAGE_IB_SUB_REMAIN 1419 #define SDMA0_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1420 #define SDMA0_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 1421 //SDMA0_PAGE_PREEMPT 1422 #define SDMA0_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 1423 #define SDMA0_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1424 //SDMA0_PAGE_DUMMY_REG 1425 #define SDMA0_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 1426 #define SDMA0_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1427 //SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI 1428 #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1429 #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1430 //SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO 1431 #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1432 #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1433 //SDMA0_PAGE_RB_AQL_CNTL 1434 #define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1435 #define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1436 #define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1437 #define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1438 #define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1439 #define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1440 //SDMA0_PAGE_MINOR_PTR_UPDATE 1441 #define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1442 #define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1443 //SDMA0_PAGE_MIDCMD_DATA0 1444 #define SDMA0_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 1445 #define SDMA0_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1446 //SDMA0_PAGE_MIDCMD_DATA1 1447 #define SDMA0_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 1448 #define SDMA0_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1449 //SDMA0_PAGE_MIDCMD_DATA2 1450 #define SDMA0_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 1451 #define SDMA0_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1452 //SDMA0_PAGE_MIDCMD_DATA3 1453 #define SDMA0_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 1454 #define SDMA0_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1455 //SDMA0_PAGE_MIDCMD_DATA4 1456 #define SDMA0_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 1457 #define SDMA0_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1458 //SDMA0_PAGE_MIDCMD_DATA5 1459 #define SDMA0_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 1460 #define SDMA0_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1461 //SDMA0_PAGE_MIDCMD_DATA6 1462 #define SDMA0_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 1463 #define SDMA0_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1464 //SDMA0_PAGE_MIDCMD_DATA7 1465 #define SDMA0_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 1466 #define SDMA0_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1467 //SDMA0_PAGE_MIDCMD_DATA8 1468 #define SDMA0_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 1469 #define SDMA0_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1470 //SDMA0_PAGE_MIDCMD_CNTL 1471 #define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1472 #define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1473 #define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1474 #define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1475 #define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1476 #define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1477 #define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1478 #define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1479 //SDMA0_RLC0_RB_CNTL 1480 #define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 1481 #define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 1482 #define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1483 #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1484 #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1485 #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1486 #define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 1487 #define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 1488 #define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1489 #define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000007EL 1490 #define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1491 #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1492 #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1493 #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1494 #define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L 1495 #define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L 1496 //SDMA0_RLC0_RB_BASE 1497 #define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0 1498 #define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1499 //SDMA0_RLC0_RB_BASE_HI 1500 #define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 1501 #define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1502 //SDMA0_RLC0_RB_RPTR 1503 #define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 1504 #define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1505 //SDMA0_RLC0_RB_RPTR_HI 1506 #define SDMA0_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 1507 #define SDMA0_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1508 //SDMA0_RLC0_RB_WPTR 1509 #define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 1510 #define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1511 //SDMA0_RLC0_RB_WPTR_HI 1512 #define SDMA0_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 1513 #define SDMA0_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1514 //SDMA0_RLC0_RB_WPTR_POLL_CNTL 1515 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1516 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1517 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1518 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1519 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1520 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1521 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1522 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1523 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1524 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1525 //SDMA0_RLC0_RB_RPTR_ADDR_HI 1526 #define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1527 #define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1528 //SDMA0_RLC0_RB_RPTR_ADDR_LO 1529 #define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1530 #define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1531 //SDMA0_RLC0_IB_CNTL 1532 #define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 1533 #define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1534 #define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1535 #define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 1536 #define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1537 #define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1538 #define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1539 #define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1540 //SDMA0_RLC0_IB_RPTR 1541 #define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 1542 #define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1543 //SDMA0_RLC0_IB_OFFSET 1544 #define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 1545 #define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1546 //SDMA0_RLC0_IB_BASE_LO 1547 #define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 1548 #define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1549 //SDMA0_RLC0_IB_BASE_HI 1550 #define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 1551 #define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1552 //SDMA0_RLC0_IB_SIZE 1553 #define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0 1554 #define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL 1555 //SDMA0_RLC0_SKIP_CNTL 1556 #define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1557 #define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL 1558 //SDMA0_RLC0_CONTEXT_STATUS 1559 #define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1560 #define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 1561 #define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1562 #define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1563 #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1564 #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1565 #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1566 #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1567 #define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1568 #define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1569 #define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1570 #define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1571 #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1572 #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1573 #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1574 #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1575 //SDMA0_RLC0_DOORBELL 1576 #define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c 1577 #define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e 1578 #define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000L 1579 #define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L 1580 //SDMA0_RLC0_STATUS 1581 #define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1582 #define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1583 #define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1584 #define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1585 //SDMA0_RLC0_DOORBELL_LOG 1586 #define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1587 #define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 1588 #define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1589 #define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1590 //SDMA0_RLC0_WATERMARK 1591 #define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1592 #define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1593 #define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1594 #define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1595 //SDMA0_RLC0_DOORBELL_OFFSET 1596 #define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1597 #define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1598 //SDMA0_RLC0_CSA_ADDR_LO 1599 #define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 1600 #define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1601 //SDMA0_RLC0_CSA_ADDR_HI 1602 #define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 1603 #define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1604 //SDMA0_RLC0_IB_SUB_REMAIN 1605 #define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1606 #define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 1607 //SDMA0_RLC0_PREEMPT 1608 #define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 1609 #define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1610 //SDMA0_RLC0_DUMMY_REG 1611 #define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 1612 #define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1613 //SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 1614 #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1615 #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1616 //SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 1617 #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1618 #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1619 //SDMA0_RLC0_RB_AQL_CNTL 1620 #define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1621 #define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1622 #define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1623 #define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1624 #define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1625 #define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1626 //SDMA0_RLC0_MINOR_PTR_UPDATE 1627 #define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1628 #define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1629 //SDMA0_RLC0_MIDCMD_DATA0 1630 #define SDMA0_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 1631 #define SDMA0_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1632 //SDMA0_RLC0_MIDCMD_DATA1 1633 #define SDMA0_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 1634 #define SDMA0_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1635 //SDMA0_RLC0_MIDCMD_DATA2 1636 #define SDMA0_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 1637 #define SDMA0_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1638 //SDMA0_RLC0_MIDCMD_DATA3 1639 #define SDMA0_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 1640 #define SDMA0_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1641 //SDMA0_RLC0_MIDCMD_DATA4 1642 #define SDMA0_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 1643 #define SDMA0_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1644 //SDMA0_RLC0_MIDCMD_DATA5 1645 #define SDMA0_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 1646 #define SDMA0_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1647 //SDMA0_RLC0_MIDCMD_DATA6 1648 #define SDMA0_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 1649 #define SDMA0_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1650 //SDMA0_RLC0_MIDCMD_DATA7 1651 #define SDMA0_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 1652 #define SDMA0_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1653 //SDMA0_RLC0_MIDCMD_DATA8 1654 #define SDMA0_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 1655 #define SDMA0_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1656 //SDMA0_RLC0_MIDCMD_CNTL 1657 #define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1658 #define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1659 #define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1660 #define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1661 #define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1662 #define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1663 #define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1664 #define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1665 //SDMA0_RLC1_RB_CNTL 1666 #define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 1667 #define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 1668 #define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1669 #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1670 #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1671 #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1672 #define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 1673 #define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 1674 #define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1675 #define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000007EL 1676 #define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1677 #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1678 #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1679 #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1680 #define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L 1681 #define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L 1682 //SDMA0_RLC1_RB_BASE 1683 #define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0 1684 #define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1685 //SDMA0_RLC1_RB_BASE_HI 1686 #define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 1687 #define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1688 //SDMA0_RLC1_RB_RPTR 1689 #define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 1690 #define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1691 //SDMA0_RLC1_RB_RPTR_HI 1692 #define SDMA0_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 1693 #define SDMA0_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1694 //SDMA0_RLC1_RB_WPTR 1695 #define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 1696 #define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1697 //SDMA0_RLC1_RB_WPTR_HI 1698 #define SDMA0_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 1699 #define SDMA0_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1700 //SDMA0_RLC1_RB_WPTR_POLL_CNTL 1701 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1702 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1703 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1704 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1705 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1706 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1707 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1708 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1709 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1710 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1711 //SDMA0_RLC1_RB_RPTR_ADDR_HI 1712 #define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1713 #define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1714 //SDMA0_RLC1_RB_RPTR_ADDR_LO 1715 #define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1716 #define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1717 //SDMA0_RLC1_IB_CNTL 1718 #define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 1719 #define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1720 #define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1721 #define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 1722 #define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1723 #define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1724 #define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1725 #define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1726 //SDMA0_RLC1_IB_RPTR 1727 #define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 1728 #define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1729 //SDMA0_RLC1_IB_OFFSET 1730 #define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 1731 #define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1732 //SDMA0_RLC1_IB_BASE_LO 1733 #define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 1734 #define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1735 //SDMA0_RLC1_IB_BASE_HI 1736 #define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 1737 #define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1738 //SDMA0_RLC1_IB_SIZE 1739 #define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0 1740 #define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL 1741 //SDMA0_RLC1_SKIP_CNTL 1742 #define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1743 #define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL 1744 //SDMA0_RLC1_CONTEXT_STATUS 1745 #define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1746 #define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 1747 #define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1748 #define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1749 #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1750 #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1751 #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1752 #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1753 #define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1754 #define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1755 #define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1756 #define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1757 #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1758 #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1759 #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1760 #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1761 //SDMA0_RLC1_DOORBELL 1762 #define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c 1763 #define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e 1764 #define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000L 1765 #define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L 1766 //SDMA0_RLC1_STATUS 1767 #define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1768 #define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1769 #define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1770 #define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1771 //SDMA0_RLC1_DOORBELL_LOG 1772 #define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1773 #define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 1774 #define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1775 #define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1776 //SDMA0_RLC1_WATERMARK 1777 #define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1778 #define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1779 #define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1780 #define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1781 //SDMA0_RLC1_DOORBELL_OFFSET 1782 #define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1783 #define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1784 //SDMA0_RLC1_CSA_ADDR_LO 1785 #define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 1786 #define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1787 //SDMA0_RLC1_CSA_ADDR_HI 1788 #define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 1789 #define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1790 //SDMA0_RLC1_IB_SUB_REMAIN 1791 #define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1792 #define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 1793 //SDMA0_RLC1_PREEMPT 1794 #define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 1795 #define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1796 //SDMA0_RLC1_DUMMY_REG 1797 #define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 1798 #define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1799 //SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 1800 #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1801 #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1802 //SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 1803 #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1804 #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1805 //SDMA0_RLC1_RB_AQL_CNTL 1806 #define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1807 #define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1808 #define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1809 #define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1810 #define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1811 #define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1812 //SDMA0_RLC1_MINOR_PTR_UPDATE 1813 #define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1814 #define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1815 //SDMA0_RLC1_MIDCMD_DATA0 1816 #define SDMA0_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 1817 #define SDMA0_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1818 //SDMA0_RLC1_MIDCMD_DATA1 1819 #define SDMA0_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 1820 #define SDMA0_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1821 //SDMA0_RLC1_MIDCMD_DATA2 1822 #define SDMA0_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 1823 #define SDMA0_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1824 //SDMA0_RLC1_MIDCMD_DATA3 1825 #define SDMA0_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 1826 #define SDMA0_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1827 //SDMA0_RLC1_MIDCMD_DATA4 1828 #define SDMA0_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 1829 #define SDMA0_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1830 //SDMA0_RLC1_MIDCMD_DATA5 1831 #define SDMA0_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 1832 #define SDMA0_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1833 //SDMA0_RLC1_MIDCMD_DATA6 1834 #define SDMA0_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 1835 #define SDMA0_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1836 //SDMA0_RLC1_MIDCMD_DATA7 1837 #define SDMA0_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 1838 #define SDMA0_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1839 //SDMA0_RLC1_MIDCMD_DATA8 1840 #define SDMA0_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 1841 #define SDMA0_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1842 //SDMA0_RLC1_MIDCMD_CNTL 1843 #define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1844 #define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1845 #define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1846 #define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1847 #define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1848 #define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1849 #define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1850 #define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1851 1852 #endif 1853
