1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * sam9x60.dtsi - Device Tree Include file for Microchip SAM9X60 SoC 4 * 5 * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries 6 * 7 * Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com> 8 */ 9 10#include <dt-bindings/dma/at91.h> 11#include <dt-bindings/pinctrl/at91.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/clock/at91.h> 15#include <dt-bindings/mfd/at91-usart.h> 16#include <dt-bindings/mfd/atmel-flexcom.h> 17 18/ { 19 #address-cells = <1>; 20 #size-cells = <1>; 21 model = "Microchip SAM9X60 SoC"; 22 compatible = "microchip,sam9x60"; 23 interrupt-parent = <&aic>; 24 25 aliases { 26 serial0 = &dbgu; 27 gpio0 = &pioA; 28 gpio1 = &pioB; 29 gpio2 = &pioC; 30 gpio3 = &pioD; 31 tcb0 = &tcb0; 32 tcb1 = &tcb1; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 cpu@0 { 40 compatible = "arm,arm926ej-s"; 41 device_type = "cpu"; 42 reg = <0>; 43 }; 44 }; 45 46 memory@20000000 { 47 device_type = "memory"; 48 reg = <0x20000000 0x10000000>; 49 }; 50 51 clocks { 52 slow_xtal: slow_xtal { 53 compatible = "fixed-clock"; 54 #clock-cells = <0>; 55 }; 56 57 main_xtal: main_xtal { 58 compatible = "fixed-clock"; 59 #clock-cells = <0>; 60 }; 61 }; 62 63 sram: sram@300000 { 64 compatible = "mmio-sram"; 65 reg = <0x00300000 0x100000>; 66 #address-cells = <1>; 67 #size-cells = <1>; 68 ranges = <0 0x00300000 0x100000>; 69 }; 70 71 ahb { 72 compatible = "simple-bus"; 73 #address-cells = <1>; 74 #size-cells = <1>; 75 ranges; 76 77 usb0: gadget@500000 { 78 #address-cells = <1>; 79 #size-cells = <0>; 80 compatible = "microchip,sam9x60-udc"; 81 reg = <0x00500000 0x100000 82 0xf803c000 0x400>; 83 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>; 84 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_CORE PMC_UTMI>; 85 clock-names = "pclk", "hclk"; 86 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>; 87 assigned-clock-rates = <480000000>; 88 status = "disabled"; 89 }; 90 91 usb1: ohci@600000 { 92 compatible = "atmel,at91rm9200-ohci", "usb-ohci"; 93 reg = <0x00600000 0x100000>; 94 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; 95 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>; 96 clock-names = "ohci_clk", "hclk", "uhpck"; 97 status = "disabled"; 98 }; 99 100 usb2: ehci@700000 { 101 compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; 102 reg = <0x00700000 0x100000>; 103 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; 104 clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>; 105 clock-names = "usb_clk", "ehci_clk"; 106 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>; 107 assigned-clock-rates = <480000000>; 108 status = "disabled"; 109 }; 110 111 ebi: ebi@10000000 { 112 compatible = "microchip,sam9x60-ebi"; 113 #address-cells = <2>; 114 #size-cells = <1>; 115 atmel,smc = <&smc>; 116 microchip,sfr = <&sfr>; 117 reg = <0x10000000 0x60000000>; 118 ranges = <0x0 0x0 0x10000000 0x10000000 119 0x1 0x0 0x20000000 0x10000000 120 0x2 0x0 0x30000000 0x10000000 121 0x3 0x0 0x40000000 0x10000000 122 0x4 0x0 0x50000000 0x10000000 123 0x5 0x0 0x60000000 0x10000000>; 124 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; 125 status = "disabled"; 126 127 nand_controller: nand-controller { 128 compatible = "microchip,sam9x60-nand-controller"; 129 ecc-engine = <&pmecc>; 130 #address-cells = <2>; 131 #size-cells = <1>; 132 ranges; 133 status = "disabled"; 134 }; 135 }; 136 137 sdmmc0: sdio-host@80000000 { 138 compatible = "microchip,sam9x60-sdhci"; 139 reg = <0x80000000 0x300>; 140 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; 141 clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>; 142 clock-names = "hclock", "multclk"; 143 assigned-clocks = <&pmc PMC_TYPE_GCK 12>; 144 assigned-clock-rates = <100000000>; 145 status = "disabled"; 146 }; 147 148 sdmmc1: sdio-host@90000000 { 149 compatible = "microchip,sam9x60-sdhci"; 150 reg = <0x90000000 0x300>; 151 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; 152 clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_GCK 26>; 153 clock-names = "hclock", "multclk"; 154 assigned-clocks = <&pmc PMC_TYPE_GCK 26>; 155 assigned-clock-rates = <100000000>; 156 status = "disabled"; 157 }; 158 159 apb { 160 compatible = "simple-bus"; 161 #address-cells = <1>; 162 #size-cells = <1>; 163 ranges; 164 165 flx4: flexcom@f0000000 { 166 compatible = "atmel,sama5d2-flexcom"; 167 reg = <0xf0000000 0x200>; 168 clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; 169 #address-cells = <1>; 170 #size-cells = <1>; 171 ranges = <0x0 0xf0000000 0x800>; 172 status = "disabled"; 173 }; 174 175 flx5: flexcom@f0004000 { 176 compatible = "atmel,sama5d2-flexcom"; 177 reg = <0xf0004000 0x200>; 178 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; 179 #address-cells = <1>; 180 #size-cells = <1>; 181 ranges = <0x0 0xf0004000 0x800>; 182 status = "disabled"; 183 }; 184 185 dma0: dma-controller@f0008000 { 186 compatible = "microchip,sam9x60-dma", "atmel,sama5d4-dma"; 187 reg = <0xf0008000 0x1000>; 188 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; 189 #dma-cells = <1>; 190 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 191 clock-names = "dma_clk"; 192 }; 193 194 ssc: ssc@f0010000 { 195 compatible = "atmel,at91sam9g45-ssc"; 196 reg = <0xf0010000 0x4000>; 197 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; 198 dmas = <&dma0 199 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 200 AT91_XDMAC_DT_PERID(38))>, 201 <&dma0 202 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 203 AT91_XDMAC_DT_PERID(39))>; 204 dma-names = "tx", "rx"; 205 clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; 206 clock-names = "pclk"; 207 status = "disabled"; 208 }; 209 210 qspi: spi@f0014000 { 211 compatible = "microchip,sam9x60-qspi"; 212 reg = <0xf0014000 0x100>, <0x70000000 0x10000000>; 213 reg-names = "qspi_base", "qspi_mmap"; 214 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 7>; 215 dmas = <&dma0 216 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 217 AT91_XDMAC_DT_PERID(26))>, 218 <&dma0 219 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 220 AT91_XDMAC_DT_PERID(27))>; 221 dma-names = "tx", "rx"; 222 clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_SYSTEM 19>; 223 clock-names = "pclk", "qspick"; 224 atmel,pmc = <&pmc>; 225 #address-cells = <1>; 226 #size-cells = <0>; 227 status = "disabled"; 228 }; 229 230 i2s: i2s@f001c000 { 231 compatible = "microchip,sam9x60-i2smcc"; 232 reg = <0xf001c000 0x100>; 233 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>; 234 dmas = <&dma0 235 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 236 AT91_XDMAC_DT_PERID(36))>, 237 <&dma0 238 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 239 AT91_XDMAC_DT_PERID(37))>; 240 dma-names = "tx", "rx"; 241 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc PMC_TYPE_GCK 34>; 242 clock-names = "pclk", "gclk"; 243 status = "disabled"; 244 }; 245 246 flx11: flexcom@f0020000 { 247 compatible = "atmel,sama5d2-flexcom"; 248 reg = <0xf0020000 0x200>; 249 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; 250 #address-cells = <1>; 251 #size-cells = <1>; 252 ranges = <0x0 0xf0020000 0x800>; 253 status = "disabled"; 254 }; 255 256 flx12: flexcom@f0024000 { 257 compatible = "atmel,sama5d2-flexcom"; 258 reg = <0xf0024000 0x200>; 259 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; 260 #address-cells = <1>; 261 #size-cells = <1>; 262 ranges = <0x0 0xf0024000 0x800>; 263 status = "disabled"; 264 }; 265 266 pit64b: timer@f0028000 { 267 compatible = "microchip,sam9x60-pit64b"; 268 reg = <0xf0028000 0x100>; 269 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>; 270 clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>; 271 clock-names = "pclk", "gclk"; 272 }; 273 274 sha: crypto@f002c000 { 275 compatible = "atmel,at91sam9g46-sha"; 276 reg = <0xf002c000 0x100>; 277 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>; 278 dmas = <&dma0 279 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 280 AT91_XDMAC_DT_PERID(34))>; 281 dma-names = "tx"; 282 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; 283 clock-names = "sha_clk"; 284 }; 285 286 trng: trng@f0030000 { 287 compatible = "microchip,sam9x60-trng"; 288 reg = <0xf0030000 0x100>; 289 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>; 290 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; 291 }; 292 293 aes: crypto@f0034000 { 294 compatible = "atmel,at91sam9g46-aes"; 295 reg = <0xf0034000 0x100>; 296 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>; 297 dmas = <&dma0 298 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 299 AT91_XDMAC_DT_PERID(32))>, 300 <&dma0 301 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 302 AT91_XDMAC_DT_PERID(33))>; 303 dma-names = "tx", "rx"; 304 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; 305 clock-names = "aes_clk"; 306 }; 307 308 tdes: crypto@f0038000 { 309 compatible = "atmel,at91sam9g46-tdes"; 310 reg = <0xf0038000 0x100>; 311 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>; 312 dmas = <&dma0 313 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 314 AT91_XDMAC_DT_PERID(31))>, 315 <&dma0 316 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 317 AT91_XDMAC_DT_PERID(30))>; 318 dma-names = "tx", "rx"; 319 clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; 320 clock-names = "tdes_clk"; 321 }; 322 323 classd: classd@f003c000 { 324 compatible = "atmel,sama5d2-classd"; 325 reg = <0xf003c000 0x100>; 326 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 7>; 327 dmas = <&dma0 328 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 329 AT91_XDMAC_DT_PERID(35))>; 330 dma-names = "tx"; 331 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_GCK 42>; 332 clock-names = "pclk", "gclk"; 333 status = "disabled"; 334 }; 335 336 can0: can@f8000000 { 337 compatible = "microchip,sam9x60-can", "atmel,at91sam9x5-can"; 338 reg = <0xf8000000 0x300>; 339 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>; 340 clocks = <&pmc PMC_TYPE_PERIPHERAL 29>; 341 clock-names = "can_clk"; 342 status = "disabled"; 343 }; 344 345 can1: can@f8004000 { 346 compatible = "microchip,sam9x60-can", "atmel,at91sam9x5-can"; 347 reg = <0xf8004000 0x300>; 348 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>; 349 clocks = <&pmc PMC_TYPE_PERIPHERAL 30>; 350 clock-names = "can_clk"; 351 status = "disabled"; 352 }; 353 354 tcb0: timer@f8008000 { 355 compatible = "microchip,sam9x60-tcb", "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; 356 #address-cells = <1>; 357 #size-cells = <0>; 358 reg = <0xf8008000 0x100>; 359 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; 360 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k 0>; 361 clock-names = "t0_clk", "slow_clk"; 362 }; 363 364 tcb1: timer@f800c000 { 365 compatible = "microchip,sam9x60-tcb", "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; 366 #address-cells = <1>; 367 #size-cells = <0>; 368 reg = <0xf800c000 0x100>; 369 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>; 370 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&clk32k 0>; 371 clock-names = "t0_clk", "slow_clk"; 372 }; 373 374 flx6: flexcom@f8010000 { 375 compatible = "atmel,sama5d2-flexcom"; 376 reg = <0xf8010000 0x200>; 377 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; 378 #address-cells = <1>; 379 #size-cells = <1>; 380 ranges = <0x0 0xf8010000 0x800>; 381 status = "disabled"; 382 }; 383 384 flx7: flexcom@f8014000 { 385 compatible = "atmel,sama5d2-flexcom"; 386 reg = <0xf8014000 0x200>; 387 clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; 388 #address-cells = <1>; 389 #size-cells = <1>; 390 ranges = <0x0 0xf8014000 0x800>; 391 status = "disabled"; 392 }; 393 394 flx8: flexcom@f8018000 { 395 compatible = "atmel,sama5d2-flexcom"; 396 reg = <0xf8018000 0x200>; 397 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; 398 #address-cells = <1>; 399 #size-cells = <1>; 400 ranges = <0x0 0xf8018000 0x800>; 401 status = "disabled"; 402 }; 403 404 flx0: flexcom@f801c000 { 405 compatible = "atmel,sama5d2-flexcom"; 406 reg = <0xf801c000 0x200>; 407 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; 408 #address-cells = <1>; 409 #size-cells = <1>; 410 ranges = <0x0 0xf801c000 0x800>; 411 status = "disabled"; 412 }; 413 414 flx1: flexcom@f8020000 { 415 compatible = "atmel,sama5d2-flexcom"; 416 reg = <0xf8020000 0x200>; 417 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 418 #address-cells = <1>; 419 #size-cells = <1>; 420 ranges = <0x0 0xf8020000 0x800>; 421 status = "disabled"; 422 }; 423 424 flx2: flexcom@f8024000 { 425 compatible = "atmel,sama5d2-flexcom"; 426 reg = <0xf8024000 0x200>; 427 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; 428 #address-cells = <1>; 429 #size-cells = <1>; 430 ranges = <0x0 0xf8024000 0x800>; 431 status = "disabled"; 432 }; 433 434 flx3: flexcom@f8028000 { 435 compatible = "atmel,sama5d2-flexcom"; 436 reg = <0xf8028000 0x200>; 437 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; 438 #address-cells = <1>; 439 #size-cells = <1>; 440 ranges = <0x0 0xf8028000 0x800>; 441 status = "disabled"; 442 }; 443 444 macb0: ethernet@f802c000 { 445 compatible = "cdns,sam9x60-macb", "cdns,macb"; 446 reg = <0xf802c000 0x1000>; 447 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; 448 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>; 449 clock-names = "hclk", "pclk"; 450 status = "disabled"; 451 }; 452 453 macb1: ethernet@f8030000 { 454 compatible = "cdns,sam9x60-macb", "cdns,macb"; 455 reg = <0xf8030000 0x1000>; 456 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>; 457 clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_PERIPHERAL 27>; 458 clock-names = "hclk", "pclk"; 459 status = "disabled"; 460 }; 461 462 pwm0: pwm@f8034000 { 463 compatible = "microchip,sam9x60-pwm"; 464 reg = <0xf8034000 0x300>; 465 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>; 466 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; 467 #pwm-cells = <3>; 468 status = "disabled"; 469 }; 470 471 hlcdc: hlcdc@f8038000 { 472 compatible = "microchip,sam9x60-hlcdc"; 473 reg = <0xf8038000 0x4000>; 474 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>; 475 clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_GCK 25>, <&clk32k 1>; 476 clock-names = "periph_clk","sys_clk", "slow_clk"; 477 assigned-clocks = <&pmc PMC_TYPE_GCK 25>; 478 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_MCK>; 479 status = "disabled"; 480 481 hlcdc-display-controller { 482 compatible = "atmel,hlcdc-display-controller"; 483 #address-cells = <1>; 484 #size-cells = <0>; 485 486 port@0 { 487 #address-cells = <1>; 488 #size-cells = <0>; 489 reg = <0>; 490 }; 491 }; 492 493 hlcdc_pwm: hlcdc-pwm { 494 compatible = "atmel,hlcdc-pwm"; 495 #pwm-cells = <3>; 496 }; 497 }; 498 499 flx9: flexcom@f8040000 { 500 compatible = "atmel,sama5d2-flexcom"; 501 reg = <0xf8040000 0x200>; 502 clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; 503 #address-cells = <1>; 504 #size-cells = <1>; 505 ranges = <0x0 0xf8040000 0x800>; 506 status = "disabled"; 507 }; 508 509 flx10: flexcom@f8044000 { 510 compatible = "atmel,sama5d2-flexcom"; 511 reg = <0xf8044000 0x200>; 512 clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; 513 #address-cells = <1>; 514 #size-cells = <1>; 515 ranges = <0x0 0xf8044000 0x800>; 516 status = "disabled"; 517 }; 518 519 isi: isi@f8048000 { 520 compatible = "microchip,sam9x60-isi", "atmel,at91sam9g45-isi"; 521 reg = <0xf8048000 0x100>; 522 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 5>; 523 clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; 524 clock-names = "isi_clk"; 525 status = "disabled"; 526 port { 527 #address-cells = <1>; 528 #size-cells = <0>; 529 }; 530 }; 531 532 adc: adc@f804c000 { 533 compatible = "microchip,sam9x60-adc", "atmel,sama5d2-adc"; 534 reg = <0xf804c000 0x100>; 535 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; 536 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 537 clock-names = "adc_clk"; 538 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(40))>; 539 dma-names = "rx"; 540 atmel,min-sample-rate-hz = <200000>; 541 atmel,max-sample-rate-hz = <20000000>; 542 atmel,startup-time-ms = <4>; 543 atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>; 544 #io-channel-cells = <1>; 545 status = "disabled"; 546 }; 547 548 sfr: sfr@f8050000 { 549 compatible = "microchip,sam9x60-sfr", "syscon"; 550 reg = <0xf8050000 0x100>; 551 }; 552 553 matrix: matrix@ffffde00 { 554 compatible = "microchip,sam9x60-matrix", "atmel,at91sam9x5-matrix", "syscon"; 555 reg = <0xffffde00 0x200>; 556 }; 557 558 pmecc: ecc-engine@ffffe000 { 559 compatible = "microchip,sam9x60-pmecc", "atmel,at91sam9g45-pmecc"; 560 reg = <0xffffe000 0x300>, 561 <0xffffe600 0x100>; 562 }; 563 564 mpddrc: mpddrc@ffffe800 { 565 compatible = "microchip,sam9x60-ddramc", "atmel,sama5d3-ddramc"; 566 reg = <0xffffe800 0x200>; 567 clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_CORE PMC_MCK>; 568 clock-names = "ddrck", "mpddr"; 569 }; 570 571 smc: smc@ffffea00 { 572 compatible = "microchip,sam9x60-smc", "atmel,at91sam9260-smc", "syscon"; 573 reg = <0xffffea00 0x100>; 574 }; 575 576 aic: interrupt-controller@fffff100 { 577 compatible = "microchip,sam9x60-aic"; 578 #interrupt-cells = <3>; 579 interrupt-controller; 580 reg = <0xfffff100 0x100>; 581 atmel,external-irqs = <31>; 582 }; 583 584 dbgu: serial@fffff200 { 585 compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; 586 reg = <0xfffff200 0x200>; 587 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 588 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 7>; 589 dmas = <&dma0 590 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 591 AT91_XDMAC_DT_PERID(28))>, 592 <&dma0 593 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 594 AT91_XDMAC_DT_PERID(29))>; 595 dma-names = "tx", "rx"; 596 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; 597 clock-names = "usart"; 598 status = "disabled"; 599 }; 600 601 pinctrl: pinctrl@fffff400 { 602 #address-cells = <1>; 603 #size-cells = <1>; 604 compatible = "microchip,sam9x60-pinctrl", "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; 605 ranges = <0xfffff400 0xfffff400 0x800>; 606 607 /* mux-mask corresponding to sam9x60 SoC in TFBGA228L package */ 608 atmel,mux-mask = < 609 /* A B C */ 610 0xffffffff 0xffe03fff 0xef00019d /* pioA */ 611 0x03ffffff 0x02fc7e7f 0x00780000 /* pioB */ 612 0xffffffff 0xffffffff 0xf83fffff /* pioC */ 613 0x003fffff 0x003f8000 0x00000000 /* pioD */ 614 >; 615 616 pioA: gpio@fffff400 { 617 compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 618 reg = <0xfffff400 0x200>; 619 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; 620 #gpio-cells = <2>; 621 gpio-controller; 622 interrupt-controller; 623 #interrupt-cells = <2>; 624 clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; 625 }; 626 627 pioB: gpio@fffff600 { 628 compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 629 reg = <0xfffff600 0x200>; 630 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; 631 #gpio-cells = <2>; 632 gpio-controller; 633 #gpio-lines = <26>; 634 interrupt-controller; 635 #interrupt-cells = <2>; 636 clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; 637 }; 638 639 pioC: gpio@fffff800 { 640 compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 641 reg = <0xfffff800 0x200>; 642 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; 643 #gpio-cells = <2>; 644 gpio-controller; 645 interrupt-controller; 646 #interrupt-cells = <2>; 647 clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; 648 }; 649 650 pioD: gpio@fffffa00 { 651 compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 652 reg = <0xfffffa00 0x200>; 653 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 1>; 654 #gpio-cells = <2>; 655 gpio-controller; 656 #gpio-lines = <22>; 657 interrupt-controller; 658 #interrupt-cells = <2>; 659 clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; 660 }; 661 }; 662 663 pmc: pmc@fffffc00 { 664 compatible = "microchip,sam9x60-pmc", "syscon"; 665 reg = <0xfffffc00 0x200>; 666 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 667 #clock-cells = <2>; 668 clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>; 669 clock-names = "td_slck", "md_slck", "main_xtal"; 670 }; 671 672 reset_controller: reset-controller@fffffe00 { 673 compatible = "microchip,sam9x60-rstc"; 674 reg = <0xfffffe00 0x10>; 675 clocks = <&clk32k 0>; 676 }; 677 678 shutdown_controller: shdwc@fffffe10 { 679 compatible = "microchip,sam9x60-shdwc"; 680 reg = <0xfffffe10 0x10>; 681 clocks = <&clk32k 0>; 682 #address-cells = <1>; 683 #size-cells = <0>; 684 atmel,wakeup-rtc-timer; 685 atmel,wakeup-rtt-timer; 686 status = "disabled"; 687 }; 688 689 rtt: rtc@fffffe20 { 690 compatible = "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt"; 691 reg = <0xfffffe20 0x20>; 692 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 693 clocks = <&clk32k 0>; 694 }; 695 696 pit: timer@fffffe40 { 697 compatible = "atmel,at91sam9260-pit"; 698 reg = <0xfffffe40 0x10>; 699 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 700 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; 701 }; 702 703 clk32k: sckc@fffffe50 { 704 compatible = "microchip,sam9x60-sckc"; 705 reg = <0xfffffe50 0x4>; 706 clocks = <&slow_xtal>; 707 #clock-cells = <1>; 708 }; 709 710 gpbr: syscon@fffffe60 { 711 compatible = "microchip,sam9x60-gpbr", "atmel,at91sam9260-gpbr", "syscon"; 712 reg = <0xfffffe60 0x10>; 713 }; 714 715 rtc: rtc@fffffea8 { 716 compatible = "microchip,sam9x60-rtc", "atmel,at91sam9x5-rtc"; 717 reg = <0xfffffea8 0x100>; 718 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 719 clocks = <&clk32k 0>; 720 }; 721 722 watchdog: watchdog@ffffff80 { 723 compatible = "microchip,sam9x60-wdt"; 724 reg = <0xffffff80 0x24>; 725 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 726 clocks = <&clk32k 0>; 727 status = "disabled"; 728 }; 729 }; 730 }; 731}; 732
