1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 3#include <dt-bindings/gpio/gpio.h> 4#include <dt-bindings/interrupt-controller/irq.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/clock/rv1108-cru.h> 7#include <dt-bindings/pinctrl/rockchip.h> 8#include <dt-bindings/thermal/thermal.h> 9/ { 10 #address-cells = <1>; 11 #size-cells = <1>; 12 13 compatible = "rockchip,rv1108"; 14 15 interrupt-parent = <&gic>; 16 17 aliases { 18 i2c0 = &i2c0; 19 i2c1 = &i2c1; 20 i2c2 = &i2c2; 21 i2c3 = &i2c3; 22 serial0 = &uart0; 23 serial1 = &uart1; 24 serial2 = &uart2; 25 }; 26 27 cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 31 cpu0: cpu@f00 { 32 device_type = "cpu"; 33 compatible = "arm,cortex-a7"; 34 reg = <0xf00>; 35 clock-latency = <40000>; 36 clocks = <&cru ARMCLK>; 37 #cooling-cells = <2>; /* min followed by max */ 38 dynamic-power-coefficient = <75>; 39 operating-points-v2 = <&cpu_opp_table>; 40 }; 41 }; 42 43 cpu_opp_table: opp_table { 44 compatible = "operating-points-v2"; 45 46 opp-408000000 { 47 opp-hz = /bits/ 64 <408000000>; 48 opp-microvolt = <975000>; 49 clock-latency-ns = <40000>; 50 }; 51 opp-600000000 { 52 opp-hz = /bits/ 64 <600000000>; 53 opp-microvolt = <975000>; 54 clock-latency-ns = <40000>; 55 }; 56 opp-816000000 { 57 opp-hz = /bits/ 64 <816000000>; 58 opp-microvolt = <1025000>; 59 clock-latency-ns = <40000>; 60 }; 61 opp-1008000000 { 62 opp-hz = /bits/ 64 <1008000000>; 63 opp-microvolt = <1150000>; 64 clock-latency-ns = <40000>; 65 }; 66 }; 67 68 arm-pmu { 69 compatible = "arm,cortex-a7-pmu"; 70 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 71 }; 72 73 timer { 74 compatible = "arm,armv7-timer"; 75 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>, 76 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 77 arm,cpu-registers-not-fw-configured; 78 clock-frequency = <24000000>; 79 }; 80 81 xin24m: oscillator { 82 compatible = "fixed-clock"; 83 clock-frequency = <24000000>; 84 clock-output-names = "xin24m"; 85 #clock-cells = <0>; 86 }; 87 88 amba: bus { 89 compatible = "simple-bus"; 90 #address-cells = <1>; 91 #size-cells = <1>; 92 ranges; 93 94 pdma: pdma@102a0000 { 95 compatible = "arm,pl330", "arm,primecell"; 96 reg = <0x102a0000 0x4000>; 97 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 98 #dma-cells = <1>; 99 arm,pl330-broken-no-flushp; 100 arm,pl330-periph-burst; 101 clocks = <&cru ACLK_DMAC>; 102 clock-names = "apb_pclk"; 103 }; 104 }; 105 106 bus_intmem: sram@10080000 { 107 compatible = "mmio-sram"; 108 reg = <0x10080000 0x2000>; 109 #address-cells = <1>; 110 #size-cells = <1>; 111 ranges = <0 0x10080000 0x2000>; 112 }; 113 114 uart2: serial@10210000 { 115 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; 116 reg = <0x10210000 0x100>; 117 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 118 reg-shift = <2>; 119 reg-io-width = <4>; 120 clock-frequency = <24000000>; 121 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 122 clock-names = "baudclk", "apb_pclk"; 123 dmas = <&pdma 6>, <&pdma 7>; 124 pinctrl-names = "default"; 125 pinctrl-0 = <&uart2m0_xfer>; 126 status = "disabled"; 127 }; 128 129 uart1: serial@10220000 { 130 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; 131 reg = <0x10220000 0x100>; 132 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 133 reg-shift = <2>; 134 reg-io-width = <4>; 135 clock-frequency = <24000000>; 136 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 137 clock-names = "baudclk", "apb_pclk"; 138 dmas = <&pdma 4>, <&pdma 5>; 139 pinctrl-names = "default"; 140 pinctrl-0 = <&uart1_xfer>; 141 status = "disabled"; 142 }; 143 144 uart0: serial@10230000 { 145 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; 146 reg = <0x10230000 0x100>; 147 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 148 reg-shift = <2>; 149 reg-io-width = <4>; 150 clock-frequency = <24000000>; 151 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 152 clock-names = "baudclk", "apb_pclk"; 153 dmas = <&pdma 2>, <&pdma 3>; 154 pinctrl-names = "default"; 155 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 156 status = "disabled"; 157 }; 158 159 i2c1: i2c@10240000 { 160 compatible = "rockchip,rv1108-i2c"; 161 reg = <0x10240000 0x1000>; 162 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 163 #address-cells = <1>; 164 #size-cells = <0>; 165 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 166 clock-names = "i2c", "pclk"; 167 pinctrl-names = "default"; 168 pinctrl-0 = <&i2c1_xfer>; 169 rockchip,grf = <&grf>; 170 status = "disabled"; 171 }; 172 173 i2c2: i2c@10250000 { 174 compatible = "rockchip,rv1108-i2c"; 175 reg = <0x10250000 0x1000>; 176 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 177 #address-cells = <1>; 178 #size-cells = <0>; 179 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 180 clock-names = "i2c", "pclk"; 181 pinctrl-names = "default"; 182 pinctrl-0 = <&i2c2m1_xfer>; 183 rockchip,grf = <&grf>; 184 status = "disabled"; 185 }; 186 187 i2c3: i2c@10260000 { 188 compatible = "rockchip,rv1108-i2c"; 189 reg = <0x10260000 0x1000>; 190 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 191 #address-cells = <1>; 192 #size-cells = <0>; 193 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 194 clock-names = "i2c", "pclk"; 195 pinctrl-names = "default"; 196 pinctrl-0 = <&i2c3_xfer>; 197 rockchip,grf = <&grf>; 198 status = "disabled"; 199 }; 200 201 spi: spi@10270000 { 202 compatible = "rockchip,rv1108-spi"; 203 reg = <0x10270000 0x1000>; 204 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 205 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; 206 clock-names = "spiclk", "apb_pclk"; 207 dmas = <&pdma 8>, <&pdma 9>; 208 dma-names = "tx", "rx"; 209 #address-cells = <1>; 210 #size-cells = <0>; 211 status = "disabled"; 212 }; 213 214 pwm4: pwm@10280000 { 215 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; 216 reg = <0x10280000 0x10>; 217 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 218 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 219 clock-names = "pwm", "pclk"; 220 pinctrl-names = "default"; 221 pinctrl-0 = <&pwm4_pin>; 222 #pwm-cells = <3>; 223 status = "disabled"; 224 }; 225 226 pwm5: pwm@10280010 { 227 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; 228 reg = <0x10280010 0x10>; 229 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 230 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 231 clock-names = "pwm", "pclk"; 232 pinctrl-names = "default"; 233 pinctrl-0 = <&pwm5_pin>; 234 #pwm-cells = <3>; 235 status = "disabled"; 236 }; 237 238 pwm6: pwm@10280020 { 239 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; 240 reg = <0x10280020 0x10>; 241 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 242 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 243 clock-names = "pwm", "pclk"; 244 pinctrl-names = "default"; 245 pinctrl-0 = <&pwm6_pin>; 246 #pwm-cells = <3>; 247 status = "disabled"; 248 }; 249 250 pwm7: pwm@10280030 { 251 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; 252 reg = <0x10280030 0x10>; 253 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 254 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 255 clock-names = "pwm", "pclk"; 256 pinctrl-names = "default"; 257 pinctrl-0 = <&pwm7_pin>; 258 #pwm-cells = <3>; 259 status = "disabled"; 260 }; 261 262 grf: syscon@10300000 { 263 compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd"; 264 reg = <0x10300000 0x1000>; 265 #address-cells = <1>; 266 #size-cells = <1>; 267 268 u2phy: usb2-phy@100 { 269 compatible = "rockchip,rv1108-usb2phy"; 270 reg = <0x100 0x0c>; 271 clocks = <&cru SCLK_USBPHY>; 272 clock-names = "phyclk"; 273 #clock-cells = <0>; 274 clock-output-names = "usbphy"; 275 rockchip,usbgrf = <&usbgrf>; 276 status = "disabled"; 277 278 u2phy_otg: otg-port { 279 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 280 interrupt-names = "otg-mux"; 281 #phy-cells = <0>; 282 status = "disabled"; 283 }; 284 285 u2phy_host: host-port { 286 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 287 interrupt-names = "linestate"; 288 #phy-cells = <0>; 289 status = "disabled"; 290 }; 291 }; 292 }; 293 294 timer: timer@10350000 { 295 compatible = "rockchip,rv1108-timer", "rockchip,rk3288-timer"; 296 reg = <0x10350000 0x20>; 297 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 298 clocks = <&xin24m>, <&cru PCLK_TIMER>; 299 clock-names = "timer", "pclk"; 300 }; 301 302 watchdog: wdt@10360000 { 303 compatible = "snps,dw-wdt"; 304 reg = <0x10360000 0x100>; 305 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 306 clocks = <&cru PCLK_WDT>; 307 clock-names = "pclk_wdt"; 308 status = "disabled"; 309 }; 310 311 thermal-zones { 312 soc_thermal: soc-thermal { 313 polling-delay-passive = <20>; 314 polling-delay = <1000>; 315 sustainable-power = <50>; 316 thermal-sensors = <&tsadc 0>; 317 318 trips { 319 threshold: trip-point0 { 320 temperature = <70000>; 321 hysteresis = <2000>; 322 type = "passive"; 323 }; 324 target: trip-point1 { 325 temperature = <85000>; 326 hysteresis = <2000>; 327 type = "passive"; 328 }; 329 soc_crit: soc-crit { 330 temperature = <95000>; 331 hysteresis = <2000>; 332 type = "critical"; 333 }; 334 }; 335 336 cooling-maps { 337 map0 { 338 trip = <&target>; 339 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 340 contribution = <4096>; 341 }; 342 }; 343 }; 344 }; 345 346 tsadc: tsadc@10370000 { 347 compatible = "rockchip,rv1108-tsadc"; 348 reg = <0x10370000 0x100>; 349 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 350 assigned-clocks = <&cru SCLK_TSADC>; 351 assigned-clock-rates = <750000>; 352 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 353 clock-names = "tsadc", "apb_pclk"; 354 pinctrl-names = "init", "default", "sleep"; 355 pinctrl-0 = <&otp_pin>; 356 pinctrl-1 = <&otp_out>; 357 pinctrl-2 = <&otp_pin>; 358 resets = <&cru SRST_TSADC>; 359 reset-names = "tsadc-apb"; 360 rockchip,hw-tshut-temp = <120000>; 361 #thermal-sensor-cells = <1>; 362 status = "disabled"; 363 }; 364 365 adc: adc@1038c000 { 366 compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc"; 367 reg = <0x1038c000 0x100>; 368 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 369 #io-channel-cells = <1>; 370 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 371 clock-names = "saradc", "apb_pclk"; 372 status = "disabled"; 373 }; 374 375 i2c0: i2c@20000000 { 376 compatible = "rockchip,rv1108-i2c"; 377 reg = <0x20000000 0x1000>; 378 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 379 #address-cells = <1>; 380 #size-cells = <0>; 381 clocks = <&cru SCLK_I2C0_PMU>, <&cru PCLK_I2C0_PMU>; 382 clock-names = "i2c", "pclk"; 383 pinctrl-names = "default"; 384 pinctrl-0 = <&i2c0_xfer>; 385 rockchip,grf = <&grf>; 386 status = "disabled"; 387 }; 388 389 pwm0: pwm@20040000 { 390 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; 391 reg = <0x20040000 0x10>; 392 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 393 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>; 394 clock-names = "pwm", "pclk"; 395 pinctrl-names = "default"; 396 pinctrl-0 = <&pwm0_pin>; 397 #pwm-cells = <3>; 398 status = "disabled"; 399 }; 400 401 pwm1: pwm@20040010 { 402 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; 403 reg = <0x20040010 0x10>; 404 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 405 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>; 406 clock-names = "pwm", "pclk"; 407 pinctrl-names = "default"; 408 pinctrl-0 = <&pwm1_pin>; 409 #pwm-cells = <3>; 410 status = "disabled"; 411 }; 412 413 pwm2: pwm@20040020 { 414 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; 415 reg = <0x20040020 0x10>; 416 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 417 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>; 418 clock-names = "pwm", "pclk"; 419 pinctrl-names = "default"; 420 pinctrl-0 = <&pwm2_pin>; 421 #pwm-cells = <3>; 422 status = "disabled"; 423 }; 424 425 pwm3: pwm@20040030 { 426 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; 427 reg = <0x20040030 0x10>; 428 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 429 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>; 430 clock-names = "pwm", "pclk"; 431 pinctrl-names = "default"; 432 pinctrl-0 = <&pwm3_pin>; 433 #pwm-cells = <3>; 434 status = "disabled"; 435 }; 436 437 pmugrf: syscon@20060000 { 438 compatible = "rockchip,rv1108-pmugrf", "syscon"; 439 reg = <0x20060000 0x1000>; 440 }; 441 442 usbgrf: syscon@202a0000 { 443 compatible = "rockchip,rv1108-usbgrf", "syscon"; 444 reg = <0x202a0000 0x1000>; 445 }; 446 447 cru: clock-controller@20200000 { 448 compatible = "rockchip,rv1108-cru"; 449 reg = <0x20200000 0x1000>; 450 rockchip,grf = <&grf>; 451 #clock-cells = <1>; 452 #reset-cells = <1>; 453 }; 454 455 emmc: mmc@30110000 { 456 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; 457 reg = <0x30110000 0x4000>; 458 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 459 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 460 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 461 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 462 fifo-depth = <0x100>; 463 max-frequency = <150000000>; 464 status = "disabled"; 465 }; 466 467 sdio: mmc@30120000 { 468 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; 469 reg = <0x30120000 0x4000>; 470 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 471 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 472 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 473 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 474 fifo-depth = <0x100>; 475 max-frequency = <150000000>; 476 status = "disabled"; 477 }; 478 479 sdmmc: mmc@30130000 { 480 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; 481 reg = <0x30130000 0x4000>; 482 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 483 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 484 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 485 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 486 fifo-depth = <0x100>; 487 max-frequency = <100000000>; 488 pinctrl-names = "default"; 489 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; 490 status = "disabled"; 491 }; 492 493 usb_host_ehci: usb@30140000 { 494 compatible = "generic-ehci"; 495 reg = <0x30140000 0x20000>; 496 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 497 clocks = <&cru HCLK_HOST0>, <&u2phy>; 498 phys = <&u2phy_host>; 499 phy-names = "usb"; 500 status = "disabled"; 501 }; 502 503 usb_host_ohci: usb@30160000 { 504 compatible = "generic-ohci"; 505 reg = <0x30160000 0x20000>; 506 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 507 clocks = <&cru HCLK_HOST0>, <&u2phy>; 508 phys = <&u2phy_host>; 509 phy-names = "usb"; 510 status = "disabled"; 511 }; 512 513 usb_otg: usb@30180000 { 514 compatible = "rockchip,rv1108-usb", "rockchip,rk3066-usb", 515 "snps,dwc2"; 516 reg = <0x30180000 0x40000>; 517 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 518 clocks = <&cru HCLK_OTG>; 519 clock-names = "otg"; 520 dr_mode = "otg"; 521 g-np-tx-fifo-size = <16>; 522 g-rx-fifo-size = <280>; 523 g-tx-fifo-size = <256 128 128 64 32 16>; 524 phys = <&u2phy_otg>; 525 phy-names = "usb2-phy"; 526 status = "disabled"; 527 }; 528 529 gmac: eth@30200000 { 530 compatible = "rockchip,rv1108-gmac"; 531 reg = <0x30200000 0x10000>; 532 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 534 interrupt-names = "macirq", "eth_wake_irq"; 535 clocks = <&cru SCLK_MAC>, 536 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_RX>, 537 <&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>, 538 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; 539 clock-names = "stmmaceth", 540 "mac_clk_rx", "mac_clk_tx", 541 "clk_mac_ref", "clk_mac_refout", 542 "aclk_mac", "pclk_mac"; 543 /* rv1108 only supports an rmii interface */ 544 phy-mode = "rmii"; 545 pinctrl-names = "default"; 546 pinctrl-0 = <&rmii_pins>; 547 rockchip,grf = <&grf>; 548 status = "disabled"; 549 }; 550 551 gic: interrupt-controller@32010000 { 552 compatible = "arm,gic-400"; 553 interrupt-controller; 554 #interrupt-cells = <3>; 555 #address-cells = <0>; 556 557 reg = <0x32011000 0x1000>, 558 <0x32012000 0x2000>, 559 <0x32014000 0x2000>, 560 <0x32016000 0x2000>; 561 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 562 }; 563 564 pinctrl: pinctrl { 565 compatible = "rockchip,rv1108-pinctrl"; 566 rockchip,grf = <&grf>; 567 rockchip,pmu = <&pmugrf>; 568 #address-cells = <1>; 569 #size-cells = <1>; 570 ranges; 571 572 gpio0: gpio0@20030000 { 573 compatible = "rockchip,gpio-bank"; 574 reg = <0x20030000 0x100>; 575 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 576 clocks = <&cru PCLK_GPIO0_PMU>; 577 578 gpio-controller; 579 #gpio-cells = <2>; 580 581 interrupt-controller; 582 #interrupt-cells = <2>; 583 }; 584 585 gpio1: gpio1@10310000 { 586 compatible = "rockchip,gpio-bank"; 587 reg = <0x10310000 0x100>; 588 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 589 clocks = <&cru PCLK_GPIO1>; 590 591 gpio-controller; 592 #gpio-cells = <2>; 593 594 interrupt-controller; 595 #interrupt-cells = <2>; 596 }; 597 598 gpio2: gpio2@10320000 { 599 compatible = "rockchip,gpio-bank"; 600 reg = <0x10320000 0x100>; 601 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 602 clocks = <&cru PCLK_GPIO2>; 603 604 gpio-controller; 605 #gpio-cells = <2>; 606 607 interrupt-controller; 608 #interrupt-cells = <2>; 609 }; 610 611 gpio3: gpio3@10330000 { 612 compatible = "rockchip,gpio-bank"; 613 reg = <0x10330000 0x100>; 614 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 615 clocks = <&cru PCLK_GPIO3>; 616 617 gpio-controller; 618 #gpio-cells = <2>; 619 620 interrupt-controller; 621 #interrupt-cells = <2>; 622 }; 623 624 pcfg_pull_up: pcfg-pull-up { 625 bias-pull-up; 626 }; 627 628 pcfg_pull_down: pcfg-pull-down { 629 bias-pull-down; 630 }; 631 632 pcfg_pull_none: pcfg-pull-none { 633 bias-disable; 634 }; 635 636 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { 637 drive-strength = <8>; 638 }; 639 640 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { 641 drive-strength = <12>; 642 }; 643 644 pcfg_pull_none_smt: pcfg-pull-none-smt { 645 bias-disable; 646 input-schmitt-enable; 647 }; 648 649 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { 650 bias-pull-up; 651 drive-strength = <8>; 652 }; 653 654 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma { 655 drive-strength = <4>; 656 }; 657 658 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma { 659 bias-pull-up; 660 drive-strength = <4>; 661 }; 662 663 pcfg_output_high: pcfg-output-high { 664 output-high; 665 }; 666 667 pcfg_output_low: pcfg-output-low { 668 output-low; 669 }; 670 671 pcfg_input_high: pcfg-input-high { 672 bias-pull-up; 673 input-enable; 674 }; 675 676 emmc { 677 emmc_bus8: emmc-bus8 { 678 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up_drv_8ma>, 679 <2 RK_PA1 2 &pcfg_pull_up_drv_8ma>, 680 <2 RK_PA2 2 &pcfg_pull_up_drv_8ma>, 681 <2 RK_PA3 2 &pcfg_pull_up_drv_8ma>, 682 <2 RK_PA4 2 &pcfg_pull_up_drv_8ma>, 683 <2 RK_PA5 2 &pcfg_pull_up_drv_8ma>, 684 <2 RK_PA6 2 &pcfg_pull_up_drv_8ma>, 685 <2 RK_PA7 2 &pcfg_pull_up_drv_8ma>; 686 }; 687 688 emmc_clk: emmc-clk { 689 rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none_drv_8ma>; 690 }; 691 692 emmc_cmd: emmc-cmd { 693 rockchip,pins = <2 RK_PB4 2 &pcfg_pull_up_drv_8ma>; 694 }; 695 }; 696 697 gmac { 698 rmii_pins: rmii-pins { 699 rockchip,pins = <1 RK_PC5 2 &pcfg_pull_none>, 700 <1 RK_PC3 2 &pcfg_pull_none>, 701 <1 RK_PC4 2 &pcfg_pull_none>, 702 <1 RK_PB2 3 &pcfg_pull_none_drv_12ma>, 703 <1 RK_PB3 3 &pcfg_pull_none_drv_12ma>, 704 <1 RK_PB4 3 &pcfg_pull_none_drv_12ma>, 705 <1 RK_PB5 3 &pcfg_pull_none>, 706 <1 RK_PB6 3 &pcfg_pull_none>, 707 <1 RK_PB7 3 &pcfg_pull_none>, 708 <1 RK_PC2 3 &pcfg_pull_none>; 709 }; 710 }; 711 712 i2c0 { 713 i2c0_xfer: i2c0-xfer { 714 rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none_smt>, 715 <0 RK_PB2 1 &pcfg_pull_none_smt>; 716 }; 717 }; 718 719 i2c1 { 720 i2c1_xfer: i2c1-xfer { 721 rockchip,pins = <2 RK_PD3 1 &pcfg_pull_up>, 722 <2 RK_PD4 1 &pcfg_pull_up>; 723 }; 724 }; 725 726 i2c2m1 { 727 i2c2m1_xfer: i2c2m1-xfer { 728 rockchip,pins = <0 RK_PC2 2 &pcfg_pull_none>, 729 <0 RK_PC6 3 &pcfg_pull_none>; 730 }; 731 732 i2c2m1_pins: i2c2m1-pins { 733 rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>, 734 <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; 735 }; 736 }; 737 738 i2c2m05v { 739 i2c2m05v_xfer: i2c2m05v-xfer { 740 rockchip,pins = <1 RK_PD5 2 &pcfg_pull_none>, 741 <1 RK_PD4 2 &pcfg_pull_none>; 742 }; 743 744 i2c2m05v_pins: i2c2m05v-pins { 745 rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>, 746 <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; 747 }; 748 }; 749 750 i2c3 { 751 i2c3_xfer: i2c3-xfer { 752 rockchip,pins = <0 RK_PB6 1 &pcfg_pull_none>, 753 <0 RK_PC4 2 &pcfg_pull_none>; 754 }; 755 }; 756 757 pwm0 { 758 pwm0_pin: pwm0-pin { 759 rockchip,pins = <0 RK_PC5 1 &pcfg_pull_none>; 760 }; 761 }; 762 763 pwm1 { 764 pwm1_pin: pwm1-pin { 765 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>; 766 }; 767 }; 768 769 pwm2 { 770 pwm2_pin: pwm2-pin { 771 rockchip,pins = <0 RK_PC6 1 &pcfg_pull_none>; 772 }; 773 }; 774 775 pwm3 { 776 pwm3_pin: pwm3-pin { 777 rockchip,pins = <0 RK_PC0 1 &pcfg_pull_none>; 778 }; 779 }; 780 781 pwm4 { 782 pwm4_pin: pwm4-pin { 783 rockchip,pins = <1 RK_PC1 3 &pcfg_pull_none>; 784 }; 785 }; 786 787 pwm5 { 788 pwm5_pin: pwm5-pin { 789 rockchip,pins = <1 RK_PA7 2 &pcfg_pull_none>; 790 }; 791 }; 792 793 pwm6 { 794 pwm6_pin: pwm6-pin { 795 rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>; 796 }; 797 }; 798 799 pwm7 { 800 pwm7_pin: pwm7-pin { 801 rockchip,pins = <1 RK_PB1 2 &pcfg_pull_none>; 802 }; 803 }; 804 805 sdmmc { 806 sdmmc_clk: sdmmc-clk { 807 rockchip,pins = <3 RK_PC4 1 &pcfg_pull_none_drv_4ma>; 808 }; 809 810 sdmmc_cmd: sdmmc-cmd { 811 rockchip,pins = <3 RK_PC5 1 &pcfg_pull_up_drv_4ma>; 812 }; 813 814 sdmmc_cd: sdmmc-cd { 815 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_up_drv_4ma>; 816 }; 817 818 sdmmc_bus1: sdmmc-bus1 { 819 rockchip,pins = <3 RK_PC3 1 &pcfg_pull_up_drv_4ma>; 820 }; 821 822 sdmmc_bus4: sdmmc-bus4 { 823 rockchip,pins = <3 RK_PC3 1 &pcfg_pull_up_drv_4ma>, 824 <3 RK_PC2 1 &pcfg_pull_up_drv_4ma>, 825 <3 RK_PC1 1 &pcfg_pull_up_drv_4ma>, 826 <3 RK_PC0 1 &pcfg_pull_up_drv_4ma>; 827 }; 828 }; 829 830 spim0 { 831 spim0_clk: spim0-clk { 832 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_up>; 833 }; 834 835 spim0_cs0: spim0-cs0 { 836 rockchip,pins = <1 RK_PD1 2 &pcfg_pull_up>; 837 }; 838 839 spim0_tx: spim0-tx { 840 rockchip,pins = <1 RK_PD3 2 &pcfg_pull_up>; 841 }; 842 843 spim0_rx: spim0-rx { 844 rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up>; 845 }; 846 }; 847 848 spim1 { 849 spim1_clk: spim1-clk { 850 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>; 851 }; 852 853 spim1_cs0: spim1-cs0 { 854 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_up>; 855 }; 856 857 spim1_rx: spim1-rx { 858 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_up>; 859 }; 860 861 spim1_tx: spim1-tx { 862 rockchip,pins = <0 RK_PA7 1 &pcfg_pull_up>; 863 }; 864 }; 865 866 tsadc { 867 otp_out: otp-out { 868 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>; 869 }; 870 871 otp_pin: otp-pin { 872 rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; 873 }; 874 }; 875 876 uart0 { 877 uart0_xfer: uart0-xfer { 878 rockchip,pins = <3 RK_PA6 1 &pcfg_pull_up>, 879 <3 RK_PA5 1 &pcfg_pull_none>; 880 }; 881 882 uart0_cts: uart0-cts { 883 rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>; 884 }; 885 886 uart0_rts: uart0-rts { 887 rockchip,pins = <3 RK_PA3 1 &pcfg_pull_none>; 888 }; 889 890 uart0_rts_pin: uart0-rts-pin { 891 rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; 892 }; 893 }; 894 895 uart1 { 896 uart1_xfer: uart1-xfer { 897 rockchip,pins = <1 RK_PD3 1 &pcfg_pull_up>, 898 <1 RK_PD2 1 &pcfg_pull_none>; 899 }; 900 901 uart1_cts: uart1-cts { 902 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>; 903 }; 904 905 uart1_rts: uart1-rts { 906 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>; 907 }; 908 }; 909 910 uart2m0 { 911 uart2m0_xfer: uart2m0-xfer { 912 rockchip,pins = <2 RK_PD2 1 &pcfg_pull_up>, 913 <2 RK_PD1 1 &pcfg_pull_none>; 914 }; 915 }; 916 917 uart2m1 { 918 uart2m1_xfer: uart2m1-xfer { 919 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up>, 920 <3 RK_PC2 2 &pcfg_pull_none>; 921 }; 922 }; 923 924 uart2_5v { 925 uart2_5v_cts: uart2_5v-cts { 926 rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>; 927 }; 928 929 uart2_5v_rts: uart2_5v-rts { 930 rockchip,pins = <1 RK_PD5 1 &pcfg_pull_none>; 931 }; 932 }; 933 }; 934}; 935
