1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the R-Car V2H (R8A77920) SoC 4 * 5 * Copyright (C) 2016 Cogent Embedded Inc. 6 */ 7 8#include <dt-bindings/clock/r8a7792-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/power/r8a7792-sysc.h> 12 13/ { 14 compatible = "renesas,r8a7792"; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 aliases { 19 i2c0 = &i2c0; 20 i2c1 = &i2c1; 21 i2c2 = &i2c2; 22 i2c3 = &i2c3; 23 i2c4 = &i2c4; 24 i2c5 = &i2c5; 25 i2c6 = &iic3; 26 spi0 = &qspi; 27 spi1 = &msiof0; 28 spi2 = &msiof1; 29 vin0 = &vin0; 30 vin1 = &vin1; 31 vin2 = &vin2; 32 vin3 = &vin3; 33 vin4 = &vin4; 34 vin5 = &vin5; 35 }; 36 37 /* External CAN clock */ 38 can_clk: can { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 /* This value must be overridden by the board. */ 42 clock-frequency = <0>; 43 }; 44 45 cpus { 46 #address-cells = <1>; 47 #size-cells = <0>; 48 enable-method = "renesas,apmu"; 49 50 cpu0: cpu@0 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a15"; 53 reg = <0>; 54 clock-frequency = <1000000000>; 55 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>; 56 power-domains = <&sysc R8A7792_PD_CA15_CPU0>; 57 next-level-cache = <&L2_CA15>; 58 }; 59 60 cpu1: cpu@1 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a15"; 63 reg = <1>; 64 clock-frequency = <1000000000>; 65 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>; 66 power-domains = <&sysc R8A7792_PD_CA15_CPU1>; 67 next-level-cache = <&L2_CA15>; 68 }; 69 70 L2_CA15: cache-controller-0 { 71 compatible = "cache"; 72 cache-unified; 73 cache-level = <2>; 74 power-domains = <&sysc R8A7792_PD_CA15_SCU>; 75 }; 76 }; 77 78 /* External root clock */ 79 extal_clk: extal { 80 compatible = "fixed-clock"; 81 #clock-cells = <0>; 82 /* This value must be overridden by the board. */ 83 clock-frequency = <0>; 84 }; 85 86 pmu { 87 compatible = "arm,cortex-a15-pmu"; 88 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 89 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 90 interrupt-affinity = <&cpu0>, <&cpu1>; 91 }; 92 93 /* External SCIF clock */ 94 scif_clk: scif { 95 compatible = "fixed-clock"; 96 #clock-cells = <0>; 97 /* This value must be overridden by the board. */ 98 clock-frequency = <0>; 99 }; 100 101 soc { 102 compatible = "simple-bus"; 103 interrupt-parent = <&gic>; 104 105 #address-cells = <2>; 106 #size-cells = <2>; 107 ranges; 108 109 rwdt: watchdog@e6020000 { 110 compatible = "renesas,r8a7792-wdt", 111 "renesas,rcar-gen2-wdt"; 112 reg = <0 0xe6020000 0 0x0c>; 113 clocks = <&cpg CPG_MOD 402>; 114 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 115 resets = <&cpg 402>; 116 status = "disabled"; 117 }; 118 119 gpio0: gpio@e6050000 { 120 compatible = "renesas,gpio-r8a7792", 121 "renesas,rcar-gen2-gpio"; 122 reg = <0 0xe6050000 0 0x50>; 123 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 124 #gpio-cells = <2>; 125 gpio-controller; 126 gpio-ranges = <&pfc 0 0 29>; 127 #interrupt-cells = <2>; 128 interrupt-controller; 129 clocks = <&cpg CPG_MOD 912>; 130 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 131 resets = <&cpg 912>; 132 }; 133 134 gpio1: gpio@e6051000 { 135 compatible = "renesas,gpio-r8a7792", 136 "renesas,rcar-gen2-gpio"; 137 reg = <0 0xe6051000 0 0x50>; 138 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 139 #gpio-cells = <2>; 140 gpio-controller; 141 gpio-ranges = <&pfc 0 32 23>; 142 #interrupt-cells = <2>; 143 interrupt-controller; 144 clocks = <&cpg CPG_MOD 911>; 145 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 146 resets = <&cpg 911>; 147 }; 148 149 gpio2: gpio@e6052000 { 150 compatible = "renesas,gpio-r8a7792", 151 "renesas,rcar-gen2-gpio"; 152 reg = <0 0xe6052000 0 0x50>; 153 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 154 #gpio-cells = <2>; 155 gpio-controller; 156 gpio-ranges = <&pfc 0 64 32>; 157 #interrupt-cells = <2>; 158 interrupt-controller; 159 clocks = <&cpg CPG_MOD 910>; 160 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 161 resets = <&cpg 910>; 162 }; 163 164 gpio3: gpio@e6053000 { 165 compatible = "renesas,gpio-r8a7792", 166 "renesas,rcar-gen2-gpio"; 167 reg = <0 0xe6053000 0 0x50>; 168 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 169 #gpio-cells = <2>; 170 gpio-controller; 171 gpio-ranges = <&pfc 0 96 28>; 172 #interrupt-cells = <2>; 173 interrupt-controller; 174 clocks = <&cpg CPG_MOD 909>; 175 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 176 resets = <&cpg 909>; 177 }; 178 179 gpio4: gpio@e6054000 { 180 compatible = "renesas,gpio-r8a7792", 181 "renesas,rcar-gen2-gpio"; 182 reg = <0 0xe6054000 0 0x50>; 183 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 184 #gpio-cells = <2>; 185 gpio-controller; 186 gpio-ranges = <&pfc 0 128 17>; 187 #interrupt-cells = <2>; 188 interrupt-controller; 189 clocks = <&cpg CPG_MOD 908>; 190 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 191 resets = <&cpg 908>; 192 }; 193 194 gpio5: gpio@e6055000 { 195 compatible = "renesas,gpio-r8a7792", 196 "renesas,rcar-gen2-gpio"; 197 reg = <0 0xe6055000 0 0x50>; 198 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 199 #gpio-cells = <2>; 200 gpio-controller; 201 gpio-ranges = <&pfc 0 160 17>; 202 #interrupt-cells = <2>; 203 interrupt-controller; 204 clocks = <&cpg CPG_MOD 907>; 205 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 206 resets = <&cpg 907>; 207 }; 208 209 gpio6: gpio@e6055100 { 210 compatible = "renesas,gpio-r8a7792", 211 "renesas,rcar-gen2-gpio"; 212 reg = <0 0xe6055100 0 0x50>; 213 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 214 #gpio-cells = <2>; 215 gpio-controller; 216 gpio-ranges = <&pfc 0 192 17>; 217 #interrupt-cells = <2>; 218 interrupt-controller; 219 clocks = <&cpg CPG_MOD 905>; 220 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 221 resets = <&cpg 905>; 222 }; 223 224 gpio7: gpio@e6055200 { 225 compatible = "renesas,gpio-r8a7792", 226 "renesas,rcar-gen2-gpio"; 227 reg = <0 0xe6055200 0 0x50>; 228 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 229 #gpio-cells = <2>; 230 gpio-controller; 231 gpio-ranges = <&pfc 0 224 17>; 232 #interrupt-cells = <2>; 233 interrupt-controller; 234 clocks = <&cpg CPG_MOD 904>; 235 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 236 resets = <&cpg 904>; 237 }; 238 239 gpio8: gpio@e6055300 { 240 compatible = "renesas,gpio-r8a7792", 241 "renesas,rcar-gen2-gpio"; 242 reg = <0 0xe6055300 0 0x50>; 243 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 244 #gpio-cells = <2>; 245 gpio-controller; 246 gpio-ranges = <&pfc 0 256 17>; 247 #interrupt-cells = <2>; 248 interrupt-controller; 249 clocks = <&cpg CPG_MOD 921>; 250 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 251 resets = <&cpg 921>; 252 }; 253 254 gpio9: gpio@e6055400 { 255 compatible = "renesas,gpio-r8a7792", 256 "renesas,rcar-gen2-gpio"; 257 reg = <0 0xe6055400 0 0x50>; 258 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 259 #gpio-cells = <2>; 260 gpio-controller; 261 gpio-ranges = <&pfc 0 288 17>; 262 #interrupt-cells = <2>; 263 interrupt-controller; 264 clocks = <&cpg CPG_MOD 919>; 265 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 266 resets = <&cpg 919>; 267 }; 268 269 gpio10: gpio@e6055500 { 270 compatible = "renesas,gpio-r8a7792", 271 "renesas,rcar-gen2-gpio"; 272 reg = <0 0xe6055500 0 0x50>; 273 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 274 #gpio-cells = <2>; 275 gpio-controller; 276 gpio-ranges = <&pfc 0 320 32>; 277 #interrupt-cells = <2>; 278 interrupt-controller; 279 clocks = <&cpg CPG_MOD 914>; 280 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 281 resets = <&cpg 914>; 282 }; 283 284 gpio11: gpio@e6055600 { 285 compatible = "renesas,gpio-r8a7792", 286 "renesas,rcar-gen2-gpio"; 287 reg = <0 0xe6055600 0 0x50>; 288 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 289 #gpio-cells = <2>; 290 gpio-controller; 291 gpio-ranges = <&pfc 0 352 30>; 292 #interrupt-cells = <2>; 293 interrupt-controller; 294 clocks = <&cpg CPG_MOD 913>; 295 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 296 resets = <&cpg 913>; 297 }; 298 299 pfc: pin-controller@e6060000 { 300 compatible = "renesas,pfc-r8a7792"; 301 reg = <0 0xe6060000 0 0x144>; 302 }; 303 304 cpg: clock-controller@e6150000 { 305 compatible = "renesas,r8a7792-cpg-mssr"; 306 reg = <0 0xe6150000 0 0x1000>; 307 clocks = <&extal_clk>; 308 clock-names = "extal"; 309 #clock-cells = <2>; 310 #power-domain-cells = <0>; 311 #reset-cells = <1>; 312 }; 313 314 apmu@e6152000 { 315 compatible = "renesas,r8a7792-apmu", "renesas,apmu"; 316 reg = <0 0xe6152000 0 0x188>; 317 cpus = <&cpu0 &cpu1>; 318 }; 319 320 rst: reset-controller@e6160000 { 321 compatible = "renesas,r8a7792-rst"; 322 reg = <0 0xe6160000 0 0x0100>; 323 }; 324 325 sysc: system-controller@e6180000 { 326 compatible = "renesas,r8a7792-sysc"; 327 reg = <0 0xe6180000 0 0x0200>; 328 #power-domain-cells = <1>; 329 }; 330 331 irqc: interrupt-controller@e61c0000 { 332 compatible = "renesas,irqc-r8a7792", "renesas,irqc"; 333 #interrupt-cells = <2>; 334 interrupt-controller; 335 reg = <0 0xe61c0000 0 0x200>; 336 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 337 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 338 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 339 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 340 clocks = <&cpg CPG_MOD 407>; 341 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 342 resets = <&cpg 407>; 343 }; 344 345 icram0: sram@e63a0000 { 346 compatible = "mmio-sram"; 347 reg = <0 0xe63a0000 0 0x12000>; 348 }; 349 350 icram1: sram@e63c0000 { 351 compatible = "mmio-sram"; 352 reg = <0 0xe63c0000 0 0x1000>; 353 #address-cells = <1>; 354 #size-cells = <1>; 355 ranges = <0 0 0xe63c0000 0x1000>; 356 357 smp-sram@0 { 358 compatible = "renesas,smp-sram"; 359 reg = <0 0x100>; 360 }; 361 }; 362 363 /* I2C doesn't need pinmux */ 364 i2c0: i2c@e6508000 { 365 compatible = "renesas,i2c-r8a7792", 366 "renesas,rcar-gen2-i2c"; 367 reg = <0 0xe6508000 0 0x40>; 368 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 369 clocks = <&cpg CPG_MOD 931>; 370 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 371 resets = <&cpg 931>; 372 i2c-scl-internal-delay-ns = <6>; 373 #address-cells = <1>; 374 #size-cells = <0>; 375 status = "disabled"; 376 }; 377 378 i2c1: i2c@e6518000 { 379 compatible = "renesas,i2c-r8a7792", 380 "renesas,rcar-gen2-i2c"; 381 reg = <0 0xe6518000 0 0x40>; 382 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 383 clocks = <&cpg CPG_MOD 930>; 384 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 385 resets = <&cpg 930>; 386 i2c-scl-internal-delay-ns = <6>; 387 #address-cells = <1>; 388 #size-cells = <0>; 389 status = "disabled"; 390 }; 391 392 i2c2: i2c@e6530000 { 393 compatible = "renesas,i2c-r8a7792", 394 "renesas,rcar-gen2-i2c"; 395 reg = <0 0xe6530000 0 0x40>; 396 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 397 clocks = <&cpg CPG_MOD 929>; 398 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 399 resets = <&cpg 929>; 400 i2c-scl-internal-delay-ns = <6>; 401 #address-cells = <1>; 402 #size-cells = <0>; 403 status = "disabled"; 404 }; 405 406 i2c3: i2c@e6540000 { 407 compatible = "renesas,i2c-r8a7792", 408 "renesas,rcar-gen2-i2c"; 409 reg = <0 0xe6540000 0 0x40>; 410 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 411 clocks = <&cpg CPG_MOD 928>; 412 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 413 resets = <&cpg 928>; 414 i2c-scl-internal-delay-ns = <6>; 415 #address-cells = <1>; 416 #size-cells = <0>; 417 status = "disabled"; 418 }; 419 420 i2c4: i2c@e6520000 { 421 compatible = "renesas,i2c-r8a7792", 422 "renesas,rcar-gen2-i2c"; 423 reg = <0 0xe6520000 0 0x40>; 424 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 425 clocks = <&cpg CPG_MOD 927>; 426 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 427 resets = <&cpg 927>; 428 i2c-scl-internal-delay-ns = <6>; 429 #address-cells = <1>; 430 #size-cells = <0>; 431 status = "disabled"; 432 }; 433 434 i2c5: i2c@e6528000 { 435 compatible = "renesas,i2c-r8a7792", 436 "renesas,rcar-gen2-i2c"; 437 reg = <0 0xe6528000 0 0x40>; 438 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 439 clocks = <&cpg CPG_MOD 925>; 440 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 441 resets = <&cpg 925>; 442 i2c-scl-internal-delay-ns = <110>; 443 #address-cells = <1>; 444 #size-cells = <0>; 445 status = "disabled"; 446 }; 447 448 iic3: i2c@e60b0000 { 449 #address-cells = <1>; 450 #size-cells = <0>; 451 compatible = "renesas,iic-r8a7792", 452 "renesas,rcar-gen2-iic", 453 "renesas,rmobile-iic"; 454 reg = <0 0xe60b0000 0 0x425>; 455 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 456 clocks = <&cpg CPG_MOD 926>; 457 dmas = <&dmac0 0x77>, <&dmac0 0x78>, 458 <&dmac1 0x77>, <&dmac1 0x78>; 459 dma-names = "tx", "rx", "tx", "rx"; 460 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 461 resets = <&cpg 926>; 462 status = "disabled"; 463 }; 464 465 dmac0: dma-controller@e6700000 { 466 compatible = "renesas,dmac-r8a7792", 467 "renesas,rcar-dmac"; 468 reg = <0 0xe6700000 0 0x20000>; 469 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 470 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH 471 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH 472 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 473 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 474 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 475 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 476 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 477 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 478 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 479 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH 480 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH 481 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH 482 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 483 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH 484 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; 485 interrupt-names = "error", 486 "ch0", "ch1", "ch2", "ch3", 487 "ch4", "ch5", "ch6", "ch7", 488 "ch8", "ch9", "ch10", "ch11", 489 "ch12", "ch13", "ch14"; 490 clocks = <&cpg CPG_MOD 219>; 491 clock-names = "fck"; 492 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 493 resets = <&cpg 219>; 494 #dma-cells = <1>; 495 dma-channels = <15>; 496 }; 497 498 dmac1: dma-controller@e6720000 { 499 compatible = "renesas,dmac-r8a7792", 500 "renesas,rcar-dmac"; 501 reg = <0 0xe6720000 0 0x20000>; 502 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 503 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 504 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 505 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 506 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 507 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 508 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 509 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 510 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 511 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 512 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 513 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 514 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 515 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 516 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 517 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; 518 interrupt-names = "error", 519 "ch0", "ch1", "ch2", "ch3", 520 "ch4", "ch5", "ch6", "ch7", 521 "ch8", "ch9", "ch10", "ch11", 522 "ch12", "ch13", "ch14"; 523 clocks = <&cpg CPG_MOD 218>; 524 clock-names = "fck"; 525 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 526 resets = <&cpg 218>; 527 #dma-cells = <1>; 528 dma-channels = <15>; 529 }; 530 531 avb: ethernet@e6800000 { 532 compatible = "renesas,etheravb-r8a7792", 533 "renesas,etheravb-rcar-gen2"; 534 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; 535 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 536 clocks = <&cpg CPG_MOD 812>; 537 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 538 resets = <&cpg 812>; 539 #address-cells = <1>; 540 #size-cells = <0>; 541 status = "disabled"; 542 }; 543 544 qspi: spi@e6b10000 { 545 compatible = "renesas,qspi-r8a7792", "renesas,qspi"; 546 reg = <0 0xe6b10000 0 0x2c>; 547 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 548 clocks = <&cpg CPG_MOD 917>; 549 dmas = <&dmac0 0x17>, <&dmac0 0x18>, 550 <&dmac1 0x17>, <&dmac1 0x18>; 551 dma-names = "tx", "rx", "tx", "rx"; 552 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 553 resets = <&cpg 917>; 554 num-cs = <1>; 555 #address-cells = <1>; 556 #size-cells = <0>; 557 status = "disabled"; 558 }; 559 560 scif0: serial@e6e60000 { 561 compatible = "renesas,scif-r8a7792", 562 "renesas,rcar-gen2-scif", "renesas,scif"; 563 reg = <0 0xe6e60000 0 64>; 564 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 565 clocks = <&cpg CPG_MOD 721>, 566 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; 567 clock-names = "fck", "brg_int", "scif_clk"; 568 dmas = <&dmac0 0x29>, <&dmac0 0x2a>, 569 <&dmac1 0x29>, <&dmac1 0x2a>; 570 dma-names = "tx", "rx", "tx", "rx"; 571 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 572 resets = <&cpg 721>; 573 status = "disabled"; 574 }; 575 576 scif1: serial@e6e68000 { 577 compatible = "renesas,scif-r8a7792", 578 "renesas,rcar-gen2-scif", "renesas,scif"; 579 reg = <0 0xe6e68000 0 64>; 580 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 581 clocks = <&cpg CPG_MOD 720>, 582 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; 583 clock-names = "fck", "brg_int", "scif_clk"; 584 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, 585 <&dmac1 0x2d>, <&dmac1 0x2e>; 586 dma-names = "tx", "rx", "tx", "rx"; 587 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 588 resets = <&cpg 720>; 589 status = "disabled"; 590 }; 591 592 scif2: serial@e6e58000 { 593 compatible = "renesas,scif-r8a7792", 594 "renesas,rcar-gen2-scif", "renesas,scif"; 595 reg = <0 0xe6e58000 0 64>; 596 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 597 clocks = <&cpg CPG_MOD 719>, 598 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; 599 clock-names = "fck", "brg_int", "scif_clk"; 600 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, 601 <&dmac1 0x2b>, <&dmac1 0x2c>; 602 dma-names = "tx", "rx", "tx", "rx"; 603 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 604 resets = <&cpg 719>; 605 status = "disabled"; 606 }; 607 608 scif3: serial@e6ea8000 { 609 compatible = "renesas,scif-r8a7792", 610 "renesas,rcar-gen2-scif", "renesas,scif"; 611 reg = <0 0xe6ea8000 0 64>; 612 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 613 clocks = <&cpg CPG_MOD 718>, 614 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; 615 clock-names = "fck", "brg_int", "scif_clk"; 616 dmas = <&dmac0 0x2f>, <&dmac0 0x30>, 617 <&dmac1 0x2f>, <&dmac1 0x30>; 618 dma-names = "tx", "rx", "tx", "rx"; 619 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 620 resets = <&cpg 718>; 621 status = "disabled"; 622 }; 623 624 hscif0: serial@e62c0000 { 625 compatible = "renesas,hscif-r8a7792", 626 "renesas,rcar-gen2-hscif", "renesas,hscif"; 627 reg = <0 0xe62c0000 0 96>; 628 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 629 clocks = <&cpg CPG_MOD 717>, 630 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; 631 clock-names = "fck", "brg_int", "scif_clk"; 632 dmas = <&dmac0 0x39>, <&dmac0 0x3a>, 633 <&dmac1 0x39>, <&dmac1 0x3a>; 634 dma-names = "tx", "rx", "tx", "rx"; 635 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 636 resets = <&cpg 717>; 637 status = "disabled"; 638 }; 639 640 hscif1: serial@e62c8000 { 641 compatible = "renesas,hscif-r8a7792", 642 "renesas,rcar-gen2-hscif", "renesas,hscif"; 643 reg = <0 0xe62c8000 0 96>; 644 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 645 clocks = <&cpg CPG_MOD 716>, 646 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; 647 clock-names = "fck", "brg_int", "scif_clk"; 648 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, 649 <&dmac1 0x4d>, <&dmac1 0x4e>; 650 dma-names = "tx", "rx", "tx", "rx"; 651 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 652 resets = <&cpg 716>; 653 status = "disabled"; 654 }; 655 656 msiof0: spi@e6e20000 { 657 compatible = "renesas,msiof-r8a7792", 658 "renesas,rcar-gen2-msiof"; 659 reg = <0 0xe6e20000 0 0x0064>; 660 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 661 clocks = <&cpg CPG_MOD 000>; 662 dmas = <&dmac0 0x51>, <&dmac0 0x52>, 663 <&dmac1 0x51>, <&dmac1 0x52>; 664 dma-names = "tx", "rx", "tx", "rx"; 665 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 666 resets = <&cpg 000>; 667 #address-cells = <1>; 668 #size-cells = <0>; 669 status = "disabled"; 670 }; 671 672 msiof1: spi@e6e10000 { 673 compatible = "renesas,msiof-r8a7792", 674 "renesas,rcar-gen2-msiof"; 675 reg = <0 0xe6e10000 0 0x0064>; 676 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 677 clocks = <&cpg CPG_MOD 208>; 678 dmas = <&dmac0 0x55>, <&dmac0 0x56>, 679 <&dmac1 0x55>, <&dmac1 0x56>; 680 dma-names = "tx", "rx", "tx", "rx"; 681 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 682 resets = <&cpg 208>; 683 #address-cells = <1>; 684 #size-cells = <0>; 685 status = "disabled"; 686 }; 687 688 can0: can@e6e80000 { 689 compatible = "renesas,can-r8a7792", 690 "renesas,rcar-gen2-can"; 691 reg = <0 0xe6e80000 0 0x1000>; 692 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 693 clocks = <&cpg CPG_MOD 916>, 694 <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>; 695 clock-names = "clkp1", "clkp2", "can_clk"; 696 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 697 resets = <&cpg 916>; 698 status = "disabled"; 699 }; 700 701 can1: can@e6e88000 { 702 compatible = "renesas,can-r8a7792", 703 "renesas,rcar-gen2-can"; 704 reg = <0 0xe6e88000 0 0x1000>; 705 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 706 clocks = <&cpg CPG_MOD 915>, 707 <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>; 708 clock-names = "clkp1", "clkp2", "can_clk"; 709 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 710 resets = <&cpg 915>; 711 status = "disabled"; 712 }; 713 714 vin0: video@e6ef0000 { 715 compatible = "renesas,vin-r8a7792", 716 "renesas,rcar-gen2-vin"; 717 reg = <0 0xe6ef0000 0 0x1000>; 718 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 719 clocks = <&cpg CPG_MOD 811>; 720 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 721 resets = <&cpg 811>; 722 status = "disabled"; 723 }; 724 725 vin1: video@e6ef1000 { 726 compatible = "renesas,vin-r8a7792", 727 "renesas,rcar-gen2-vin"; 728 reg = <0 0xe6ef1000 0 0x1000>; 729 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 730 clocks = <&cpg CPG_MOD 810>; 731 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 732 resets = <&cpg 810>; 733 status = "disabled"; 734 }; 735 736 vin2: video@e6ef2000 { 737 compatible = "renesas,vin-r8a7792", 738 "renesas,rcar-gen2-vin"; 739 reg = <0 0xe6ef2000 0 0x1000>; 740 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 741 clocks = <&cpg CPG_MOD 809>; 742 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 743 resets = <&cpg 809>; 744 status = "disabled"; 745 }; 746 747 vin3: video@e6ef3000 { 748 compatible = "renesas,vin-r8a7792", 749 "renesas,rcar-gen2-vin"; 750 reg = <0 0xe6ef3000 0 0x1000>; 751 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 752 clocks = <&cpg CPG_MOD 808>; 753 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 754 resets = <&cpg 808>; 755 status = "disabled"; 756 }; 757 758 vin4: video@e6ef4000 { 759 compatible = "renesas,vin-r8a7792", 760 "renesas,rcar-gen2-vin"; 761 reg = <0 0xe6ef4000 0 0x1000>; 762 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 763 clocks = <&cpg CPG_MOD 805>; 764 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 765 resets = <&cpg 805>; 766 status = "disabled"; 767 }; 768 769 vin5: video@e6ef5000 { 770 compatible = "renesas,vin-r8a7792", 771 "renesas,rcar-gen2-vin"; 772 reg = <0 0xe6ef5000 0 0x1000>; 773 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 774 clocks = <&cpg CPG_MOD 804>; 775 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 776 resets = <&cpg 804>; 777 status = "disabled"; 778 }; 779 780 sdhi0: sd@ee100000 { 781 compatible = "renesas,sdhi-r8a7792", 782 "renesas,rcar-gen2-sdhi"; 783 reg = <0 0xee100000 0 0x328>; 784 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; 785 dmas = <&dmac0 0xcd>, <&dmac0 0xce>, 786 <&dmac1 0xcd>, <&dmac1 0xce>; 787 dma-names = "tx", "rx", "tx", "rx"; 788 clocks = <&cpg CPG_MOD 314>; 789 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 790 resets = <&cpg 314>; 791 status = "disabled"; 792 }; 793 794 gic: interrupt-controller@f1001000 { 795 compatible = "arm,gic-400"; 796 #interrupt-cells = <3>; 797 interrupt-controller; 798 reg = <0 0xf1001000 0 0x1000>, 799 <0 0xf1002000 0 0x2000>, 800 <0 0xf1004000 0 0x2000>, 801 <0 0xf1006000 0 0x2000>; 802 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | 803 IRQ_TYPE_LEVEL_HIGH)>; 804 clocks = <&cpg CPG_MOD 408>; 805 clock-names = "clk"; 806 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 807 resets = <&cpg 408>; 808 }; 809 810 vsp@fe928000 { 811 compatible = "renesas,vsp1"; 812 reg = <0 0xfe928000 0 0x8000>; 813 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; 814 clocks = <&cpg CPG_MOD 131>; 815 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 816 resets = <&cpg 131>; 817 }; 818 819 vsp@fe930000 { 820 compatible = "renesas,vsp1"; 821 reg = <0 0xfe930000 0 0x8000>; 822 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 823 clocks = <&cpg CPG_MOD 128>; 824 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 825 resets = <&cpg 128>; 826 }; 827 828 vsp@fe938000 { 829 compatible = "renesas,vsp1"; 830 reg = <0 0xfe938000 0 0x8000>; 831 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 832 clocks = <&cpg CPG_MOD 127>; 833 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 834 resets = <&cpg 127>; 835 }; 836 837 jpu: jpeg-codec@fe980000 { 838 compatible = "renesas,jpu-r8a7792", 839 "renesas,rcar-gen2-jpu"; 840 reg = <0 0xfe980000 0 0x10300>; 841 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 842 clocks = <&cpg CPG_MOD 106>; 843 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 844 resets = <&cpg 106>; 845 }; 846 847 du: display@feb00000 { 848 compatible = "renesas,du-r8a7792"; 849 reg = <0 0xfeb00000 0 0x40000>; 850 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 851 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 852 clocks = <&cpg CPG_MOD 724>, 853 <&cpg CPG_MOD 723>; 854 clock-names = "du.0", "du.1"; 855 status = "disabled"; 856 857 ports { 858 #address-cells = <1>; 859 #size-cells = <0>; 860 861 port@0 { 862 reg = <0>; 863 du_out_rgb0: endpoint { 864 }; 865 }; 866 port@1 { 867 reg = <1>; 868 du_out_rgb1: endpoint { 869 }; 870 }; 871 }; 872 }; 873 874 prr: chipid@ff000044 { 875 compatible = "renesas,prr"; 876 reg = <0 0xff000044 0 4>; 877 }; 878 879 cmt0: timer@ffca0000 { 880 compatible = "renesas,r8a7792-cmt0", 881 "renesas,rcar-gen2-cmt0"; 882 reg = <0 0xffca0000 0 0x1004>; 883 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 884 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 885 clocks = <&cpg CPG_MOD 124>; 886 clock-names = "fck"; 887 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 888 resets = <&cpg 124>; 889 890 status = "disabled"; 891 }; 892 893 cmt1: timer@e6130000 { 894 compatible = "renesas,r8a7792-cmt1", 895 "renesas,rcar-gen2-cmt1"; 896 reg = <0 0xe6130000 0 0x1004>; 897 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 898 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 899 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 900 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 901 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 902 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 903 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 904 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 905 clocks = <&cpg CPG_MOD 329>; 906 clock-names = "fck"; 907 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; 908 resets = <&cpg 329>; 909 910 status = "disabled"; 911 }; 912 }; 913 914 timer { 915 compatible = "arm,armv7-timer"; 916 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 917 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 918 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 919 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 920 }; 921}; 922
