1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r8a7742 SoC 4 * 5 * Copyright (C) 2020 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/r8a7742-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/power/r8a7742-sysc.h> 12 13/ { 14 compatible = "renesas,r8a7742"; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 /* 19 * The external audio clocks are configured as 0 Hz fixed frequency 20 * clocks by default. 21 * Boards that provide audio clocks should override them. 22 */ 23 audio_clk_a: audio_clk_a { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 clock-frequency = <0>; 27 }; 28 audio_clk_b: audio_clk_b { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <0>; 32 }; 33 audio_clk_c: audio_clk_c { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 clock-frequency = <0>; 37 }; 38 39 /* External CAN clock */ 40 can_clk: can { 41 compatible = "fixed-clock"; 42 #clock-cells = <0>; 43 /* This value must be overridden by the board. */ 44 clock-frequency = <0>; 45 }; 46 47 cpus { 48 #address-cells = <1>; 49 #size-cells = <0>; 50 enable-method = "renesas,apmu"; 51 52 cpu0: cpu@0 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a15"; 55 reg = <0>; 56 clock-frequency = <1400000000>; 57 clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; 58 power-domains = <&sysc R8A7742_PD_CA15_CPU0>; 59 next-level-cache = <&L2_CA15>; 60 capacity-dmips-mhz = <1024>; 61 voltage-tolerance = <1>; /* 1% */ 62 clock-latency = <300000>; /* 300 us */ 63 64 /* kHz - uV - OPPs unknown yet */ 65 operating-points = <1400000 1000000>, 66 <1225000 1000000>, 67 <1050000 1000000>, 68 < 875000 1000000>, 69 < 700000 1000000>, 70 < 350000 1000000>; 71 }; 72 73 cpu1: cpu@1 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a15"; 76 reg = <1>; 77 clock-frequency = <1400000000>; 78 clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; 79 power-domains = <&sysc R8A7742_PD_CA15_CPU1>; 80 next-level-cache = <&L2_CA15>; 81 capacity-dmips-mhz = <1024>; 82 voltage-tolerance = <1>; /* 1% */ 83 clock-latency = <300000>; /* 300 us */ 84 85 /* kHz - uV - OPPs unknown yet */ 86 operating-points = <1400000 1000000>, 87 <1225000 1000000>, 88 <1050000 1000000>, 89 < 875000 1000000>, 90 < 700000 1000000>, 91 < 350000 1000000>; 92 }; 93 94 cpu2: cpu@2 { 95 device_type = "cpu"; 96 compatible = "arm,cortex-a15"; 97 reg = <2>; 98 clock-frequency = <1400000000>; 99 clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; 100 power-domains = <&sysc R8A7742_PD_CA15_CPU2>; 101 next-level-cache = <&L2_CA15>; 102 capacity-dmips-mhz = <1024>; 103 voltage-tolerance = <1>; /* 1% */ 104 clock-latency = <300000>; /* 300 us */ 105 106 /* kHz - uV - OPPs unknown yet */ 107 operating-points = <1400000 1000000>, 108 <1225000 1000000>, 109 <1050000 1000000>, 110 < 875000 1000000>, 111 < 700000 1000000>, 112 < 350000 1000000>; 113 }; 114 115 cpu3: cpu@3 { 116 device_type = "cpu"; 117 compatible = "arm,cortex-a15"; 118 reg = <3>; 119 clock-frequency = <1400000000>; 120 clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; 121 power-domains = <&sysc R8A7742_PD_CA15_CPU3>; 122 next-level-cache = <&L2_CA15>; 123 capacity-dmips-mhz = <1024>; 124 voltage-tolerance = <1>; /* 1% */ 125 clock-latency = <300000>; /* 300 us */ 126 127 /* kHz - uV - OPPs unknown yet */ 128 operating-points = <1400000 1000000>, 129 <1225000 1000000>, 130 <1050000 1000000>, 131 < 875000 1000000>, 132 < 700000 1000000>, 133 < 350000 1000000>; 134 }; 135 136 cpu4: cpu@100 { 137 device_type = "cpu"; 138 compatible = "arm,cortex-a7"; 139 reg = <0x100>; 140 clock-frequency = <780000000>; 141 clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>; 142 power-domains = <&sysc R8A7742_PD_CA7_CPU0>; 143 next-level-cache = <&L2_CA7>; 144 }; 145 146 cpu5: cpu@101 { 147 device_type = "cpu"; 148 compatible = "arm,cortex-a7"; 149 reg = <0x101>; 150 clock-frequency = <780000000>; 151 clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>; 152 power-domains = <&sysc R8A7742_PD_CA7_CPU1>; 153 next-level-cache = <&L2_CA7>; 154 }; 155 156 cpu6: cpu@102 { 157 device_type = "cpu"; 158 compatible = "arm,cortex-a7"; 159 reg = <0x102>; 160 clock-frequency = <780000000>; 161 clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>; 162 power-domains = <&sysc R8A7742_PD_CA7_CPU2>; 163 next-level-cache = <&L2_CA7>; 164 }; 165 166 cpu7: cpu@103 { 167 device_type = "cpu"; 168 compatible = "arm,cortex-a7"; 169 reg = <0x103>; 170 clock-frequency = <780000000>; 171 clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>; 172 power-domains = <&sysc R8A7742_PD_CA7_CPU3>; 173 next-level-cache = <&L2_CA7>; 174 }; 175 176 L2_CA15: cache-controller-0 { 177 compatible = "cache"; 178 power-domains = <&sysc R8A7742_PD_CA15_SCU>; 179 cache-unified; 180 cache-level = <2>; 181 }; 182 183 L2_CA7: cache-controller-1 { 184 compatible = "cache"; 185 power-domains = <&sysc R8A7742_PD_CA7_SCU>; 186 cache-unified; 187 cache-level = <2>; 188 }; 189 }; 190 191 /* External root clock */ 192 extal_clk: extal { 193 compatible = "fixed-clock"; 194 #clock-cells = <0>; 195 /* This value must be overridden by the board. */ 196 clock-frequency = <0>; 197 }; 198 199 /* External PCIe clock - can be overridden by the board */ 200 pcie_bus_clk: pcie_bus { 201 compatible = "fixed-clock"; 202 #clock-cells = <0>; 203 clock-frequency = <0>; 204 }; 205 206 pmu-0 { 207 compatible = "arm,cortex-a15-pmu"; 208 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 209 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 210 <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 211 <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 212 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 213 }; 214 215 pmu-1 { 216 compatible = "arm,cortex-a7-pmu"; 217 interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 218 <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 219 <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 220 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 221 interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; 222 }; 223 224 /* External SCIF clock */ 225 scif_clk: scif { 226 compatible = "fixed-clock"; 227 #clock-cells = <0>; 228 /* This value must be overridden by the board. */ 229 clock-frequency = <0>; 230 }; 231 232 soc { 233 compatible = "simple-bus"; 234 interrupt-parent = <&gic>; 235 236 #address-cells = <2>; 237 #size-cells = <2>; 238 ranges; 239 240 rwdt: watchdog@e6020000 { 241 compatible = "renesas,r8a7742-wdt", 242 "renesas,rcar-gen2-wdt"; 243 reg = <0 0xe6020000 0 0x0c>; 244 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 245 clocks = <&cpg CPG_MOD 402>; 246 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 247 resets = <&cpg 402>; 248 status = "disabled"; 249 }; 250 251 gpio0: gpio@e6050000 { 252 compatible = "renesas,gpio-r8a7742", 253 "renesas,rcar-gen2-gpio"; 254 reg = <0 0xe6050000 0 0x50>; 255 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 256 #gpio-cells = <2>; 257 gpio-controller; 258 gpio-ranges = <&pfc 0 0 32>; 259 #interrupt-cells = <2>; 260 interrupt-controller; 261 clocks = <&cpg CPG_MOD 912>; 262 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 263 resets = <&cpg 912>; 264 }; 265 266 gpio1: gpio@e6051000 { 267 compatible = "renesas,gpio-r8a7742", 268 "renesas,rcar-gen2-gpio"; 269 reg = <0 0xe6051000 0 0x50>; 270 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 271 #gpio-cells = <2>; 272 gpio-controller; 273 gpio-ranges = <&pfc 0 32 30>; 274 #interrupt-cells = <2>; 275 interrupt-controller; 276 clocks = <&cpg CPG_MOD 911>; 277 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 278 resets = <&cpg 911>; 279 }; 280 281 gpio2: gpio@e6052000 { 282 compatible = "renesas,gpio-r8a7742", 283 "renesas,rcar-gen2-gpio"; 284 reg = <0 0xe6052000 0 0x50>; 285 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 286 #gpio-cells = <2>; 287 gpio-controller; 288 gpio-ranges = <&pfc 0 64 30>; 289 #interrupt-cells = <2>; 290 interrupt-controller; 291 clocks = <&cpg CPG_MOD 910>; 292 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 293 resets = <&cpg 910>; 294 }; 295 296 gpio3: gpio@e6053000 { 297 compatible = "renesas,gpio-r8a7742", 298 "renesas,rcar-gen2-gpio"; 299 reg = <0 0xe6053000 0 0x50>; 300 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 301 #gpio-cells = <2>; 302 gpio-controller; 303 gpio-ranges = <&pfc 0 96 32>; 304 #interrupt-cells = <2>; 305 interrupt-controller; 306 clocks = <&cpg CPG_MOD 909>; 307 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 308 resets = <&cpg 909>; 309 }; 310 311 gpio4: gpio@e6054000 { 312 compatible = "renesas,gpio-r8a7742", 313 "renesas,rcar-gen2-gpio"; 314 reg = <0 0xe6054000 0 0x50>; 315 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 316 #gpio-cells = <2>; 317 gpio-controller; 318 gpio-ranges = <&pfc 0 128 32>; 319 #interrupt-cells = <2>; 320 interrupt-controller; 321 clocks = <&cpg CPG_MOD 908>; 322 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 323 resets = <&cpg 908>; 324 }; 325 326 gpio5: gpio@e6055000 { 327 compatible = "renesas,gpio-r8a7742", 328 "renesas,rcar-gen2-gpio"; 329 reg = <0 0xe6055000 0 0x50>; 330 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 331 #gpio-cells = <2>; 332 gpio-controller; 333 gpio-ranges = <&pfc 0 160 32>; 334 #interrupt-cells = <2>; 335 interrupt-controller; 336 clocks = <&cpg CPG_MOD 907>; 337 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 338 resets = <&cpg 907>; 339 }; 340 341 pfc: pinctrl@e6060000 { 342 compatible = "renesas,pfc-r8a7742"; 343 reg = <0 0xe6060000 0 0x250>; 344 }; 345 346 tpu: pwm@e60f0000 { 347 compatible = "renesas,tpu-r8a7742", "renesas,tpu"; 348 reg = <0 0xe60f0000 0 0x148>; 349 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 350 clocks = <&cpg CPG_MOD 304>; 351 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 352 resets = <&cpg 304>; 353 #pwm-cells = <3>; 354 status = "disabled"; 355 }; 356 357 cpg: clock-controller@e6150000 { 358 compatible = "renesas,r8a7742-cpg-mssr"; 359 reg = <0 0xe6150000 0 0x1000>; 360 clocks = <&extal_clk>, <&usb_extal_clk>; 361 clock-names = "extal", "usb_extal"; 362 #clock-cells = <2>; 363 #power-domain-cells = <0>; 364 #reset-cells = <1>; 365 }; 366 367 apmu@e6151000 { 368 compatible = "renesas,r8a7742-apmu", "renesas,apmu"; 369 reg = <0 0xe6151000 0 0x188>; 370 cpus = <&cpu4 &cpu5 &cpu6 &cpu7>; 371 }; 372 373 apmu@e6152000 { 374 compatible = "renesas,r8a7742-apmu", "renesas,apmu"; 375 reg = <0 0xe6152000 0 0x188>; 376 cpus = <&cpu0 &cpu1 &cpu2 &cpu3>; 377 }; 378 379 rst: reset-controller@e6160000 { 380 compatible = "renesas,r8a7742-rst"; 381 reg = <0 0xe6160000 0 0x0100>; 382 }; 383 384 sysc: system-controller@e6180000 { 385 compatible = "renesas,r8a7742-sysc"; 386 reg = <0 0xe6180000 0 0x0200>; 387 #power-domain-cells = <1>; 388 }; 389 390 irqc: interrupt-controller@e61c0000 { 391 compatible = "renesas,irqc-r8a7742", "renesas,irqc"; 392 #interrupt-cells = <2>; 393 interrupt-controller; 394 reg = <0 0xe61c0000 0 0x200>; 395 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 396 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 397 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 398 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 399 clocks = <&cpg CPG_MOD 407>; 400 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 401 resets = <&cpg 407>; 402 }; 403 404 thermal: thermal@e61f0000 { 405 compatible = "renesas,thermal-r8a7742", 406 "renesas,rcar-gen2-thermal"; 407 reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>; 408 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 409 clocks = <&cpg CPG_MOD 522>; 410 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 411 resets = <&cpg 522>; 412 #thermal-sensor-cells = <0>; 413 }; 414 415 ipmmu_sy0: iommu@e6280000 { 416 compatible = "renesas,ipmmu-r8a7742", 417 "renesas,ipmmu-vmsa"; 418 reg = <0 0xe6280000 0 0x1000>; 419 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, 420 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 421 #iommu-cells = <1>; 422 status = "disabled"; 423 }; 424 425 ipmmu_sy1: iommu@e6290000 { 426 compatible = "renesas,ipmmu-r8a7742", 427 "renesas,ipmmu-vmsa"; 428 reg = <0 0xe6290000 0 0x1000>; 429 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 430 #iommu-cells = <1>; 431 status = "disabled"; 432 }; 433 434 ipmmu_ds: iommu@e6740000 { 435 compatible = "renesas,ipmmu-r8a7742", 436 "renesas,ipmmu-vmsa"; 437 reg = <0 0xe6740000 0 0x1000>; 438 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 440 #iommu-cells = <1>; 441 status = "disabled"; 442 }; 443 444 ipmmu_mp: iommu@ec680000 { 445 compatible = "renesas,ipmmu-r8a7742", 446 "renesas,ipmmu-vmsa"; 447 reg = <0 0xec680000 0 0x1000>; 448 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 449 #iommu-cells = <1>; 450 status = "disabled"; 451 }; 452 453 ipmmu_mx: iommu@fe951000 { 454 compatible = "renesas,ipmmu-r8a7742", 455 "renesas,ipmmu-vmsa"; 456 reg = <0 0xfe951000 0 0x1000>; 457 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, 458 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 459 #iommu-cells = <1>; 460 status = "disabled"; 461 }; 462 463 icram0: sram@e63a0000 { 464 compatible = "mmio-sram"; 465 reg = <0 0xe63a0000 0 0x12000>; 466 #address-cells = <1>; 467 #size-cells = <1>; 468 ranges = <0 0 0xe63a0000 0x12000>; 469 }; 470 471 icram1: sram@e63c0000 { 472 compatible = "mmio-sram"; 473 reg = <0 0xe63c0000 0 0x1000>; 474 #address-cells = <1>; 475 #size-cells = <1>; 476 ranges = <0 0 0xe63c0000 0x1000>; 477 478 smp-sram@0 { 479 compatible = "renesas,smp-sram"; 480 reg = <0 0x100>; 481 }; 482 }; 483 484 icram2: sram@e6300000 { 485 compatible = "mmio-sram"; 486 reg = <0 0xe6300000 0 0x40000>; 487 #address-cells = <1>; 488 #size-cells = <1>; 489 ranges = <0 0 0xe6300000 0x40000>; 490 }; 491 492 i2c0: i2c@e6508000 { 493 #address-cells = <1>; 494 #size-cells = <0>; 495 compatible = "renesas,i2c-r8a7742", 496 "renesas,rcar-gen2-i2c"; 497 reg = <0 0xe6508000 0 0x40>; 498 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 499 clocks = <&cpg CPG_MOD 931>; 500 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 501 resets = <&cpg 931>; 502 i2c-scl-internal-delay-ns = <110>; 503 status = "disabled"; 504 }; 505 506 i2c1: i2c@e6518000 { 507 #address-cells = <1>; 508 #size-cells = <0>; 509 compatible = "renesas,i2c-r8a7742", 510 "renesas,rcar-gen2-i2c"; 511 reg = <0 0xe6518000 0 0x40>; 512 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 513 clocks = <&cpg CPG_MOD 930>; 514 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 515 resets = <&cpg 930>; 516 i2c-scl-internal-delay-ns = <6>; 517 status = "disabled"; 518 }; 519 520 i2c2: i2c@e6530000 { 521 #address-cells = <1>; 522 #size-cells = <0>; 523 compatible = "renesas,i2c-r8a7742", 524 "renesas,rcar-gen2-i2c"; 525 reg = <0 0xe6530000 0 0x40>; 526 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 527 clocks = <&cpg CPG_MOD 929>; 528 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 529 resets = <&cpg 929>; 530 i2c-scl-internal-delay-ns = <6>; 531 status = "disabled"; 532 }; 533 534 i2c3: i2c@e6540000 { 535 #address-cells = <1>; 536 #size-cells = <0>; 537 compatible = "renesas,i2c-r8a7742", 538 "renesas,rcar-gen2-i2c"; 539 reg = <0 0xe6540000 0 0x40>; 540 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 541 clocks = <&cpg CPG_MOD 928>; 542 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 543 resets = <&cpg 928>; 544 i2c-scl-internal-delay-ns = <110>; 545 status = "disabled"; 546 }; 547 548 iic0: i2c@e6500000 { 549 #address-cells = <1>; 550 #size-cells = <0>; 551 compatible = "renesas,iic-r8a7742", 552 "renesas,rcar-gen2-iic", 553 "renesas,rmobile-iic"; 554 reg = <0 0xe6500000 0 0x425>; 555 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 556 clocks = <&cpg CPG_MOD 318>; 557 dmas = <&dmac0 0x61>, <&dmac0 0x62>, 558 <&dmac1 0x61>, <&dmac1 0x62>; 559 dma-names = "tx", "rx", "tx", "rx"; 560 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 561 resets = <&cpg 318>; 562 status = "disabled"; 563 }; 564 565 iic1: i2c@e6510000 { 566 #address-cells = <1>; 567 #size-cells = <0>; 568 compatible = "renesas,iic-r8a7742", 569 "renesas,rcar-gen2-iic", 570 "renesas,rmobile-iic"; 571 reg = <0 0xe6510000 0 0x425>; 572 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 573 clocks = <&cpg CPG_MOD 323>; 574 dmas = <&dmac0 0x65>, <&dmac0 0x66>, 575 <&dmac1 0x65>, <&dmac1 0x66>; 576 dma-names = "tx", "rx", "tx", "rx"; 577 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 578 resets = <&cpg 323>; 579 status = "disabled"; 580 }; 581 582 iic2: i2c@e6520000 { 583 #address-cells = <1>; 584 #size-cells = <0>; 585 compatible = "renesas,iic-r8a7742", 586 "renesas,rcar-gen2-iic", 587 "renesas,rmobile-iic"; 588 reg = <0 0xe6520000 0 0x425>; 589 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 590 clocks = <&cpg CPG_MOD 300>; 591 dmas = <&dmac0 0x69>, <&dmac0 0x6a>, 592 <&dmac1 0x69>, <&dmac1 0x6a>; 593 dma-names = "tx", "rx", "tx", "rx"; 594 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 595 resets = <&cpg 300>; 596 status = "disabled"; 597 }; 598 599 iic3: i2c@e60b0000 { 600 #address-cells = <1>; 601 #size-cells = <0>; 602 compatible = "renesas,iic-r8a7742"; 603 reg = <0 0xe60b0000 0 0x425>; 604 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 605 clocks = <&cpg CPG_MOD 926>; 606 dmas = <&dmac0 0x77>, <&dmac0 0x78>, 607 <&dmac1 0x77>, <&dmac1 0x78>; 608 dma-names = "tx", "rx", "tx", "rx"; 609 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 610 resets = <&cpg 926>; 611 status = "disabled"; 612 }; 613 614 hsusb: usb@e6590000 { 615 compatible = "renesas,usbhs-r8a7742", 616 "renesas,rcar-gen2-usbhs"; 617 reg = <0 0xe6590000 0 0x100>; 618 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 619 clocks = <&cpg CPG_MOD 704>; 620 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, 621 <&usb_dmac1 0>, <&usb_dmac1 1>; 622 dma-names = "ch0", "ch1", "ch2", "ch3"; 623 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 624 resets = <&cpg 704>; 625 renesas,buswait = <4>; 626 phys = <&usb0 1>; 627 phy-names = "usb"; 628 status = "disabled"; 629 }; 630 631 usbphy: usb-phy@e6590100 { 632 compatible = "renesas,usb-phy-r8a7742", 633 "renesas,rcar-gen2-usb-phy"; 634 reg = <0 0xe6590100 0 0x100>; 635 #address-cells = <1>; 636 #size-cells = <0>; 637 clocks = <&cpg CPG_MOD 704>; 638 clock-names = "usbhs"; 639 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 640 resets = <&cpg 704>; 641 status = "disabled"; 642 643 usb0: usb-channel@0 { 644 reg = <0>; 645 #phy-cells = <1>; 646 }; 647 usb2: usb-channel@2 { 648 reg = <2>; 649 #phy-cells = <1>; 650 }; 651 }; 652 653 usb_dmac0: dma-controller@e65a0000 { 654 compatible = "renesas,r8a7742-usb-dmac", 655 "renesas,usb-dmac"; 656 reg = <0 0xe65a0000 0 0x100>; 657 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 658 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 659 interrupt-names = "ch0", "ch1"; 660 clocks = <&cpg CPG_MOD 330>; 661 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 662 resets = <&cpg 330>; 663 #dma-cells = <1>; 664 dma-channels = <2>; 665 }; 666 667 usb_dmac1: dma-controller@e65b0000 { 668 compatible = "renesas,r8a7742-usb-dmac", 669 "renesas,usb-dmac"; 670 reg = <0 0xe65b0000 0 0x100>; 671 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 672 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 673 interrupt-names = "ch0", "ch1"; 674 clocks = <&cpg CPG_MOD 331>; 675 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 676 resets = <&cpg 331>; 677 #dma-cells = <1>; 678 dma-channels = <2>; 679 }; 680 681 dmac0: dma-controller@e6700000 { 682 compatible = "renesas,dmac-r8a7742", 683 "renesas,rcar-dmac"; 684 reg = <0 0xe6700000 0 0x20000>; 685 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 686 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 687 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 688 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 689 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 690 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 691 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 692 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 693 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 694 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 695 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 696 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 697 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 698 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 699 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 700 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; 701 interrupt-names = "error", 702 "ch0", "ch1", "ch2", "ch3", 703 "ch4", "ch5", "ch6", "ch7", 704 "ch8", "ch9", "ch10", "ch11", 705 "ch12", "ch13", "ch14"; 706 clocks = <&cpg CPG_MOD 219>; 707 clock-names = "fck"; 708 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 709 resets = <&cpg 219>; 710 #dma-cells = <1>; 711 dma-channels = <15>; 712 }; 713 714 dmac1: dma-controller@e6720000 { 715 compatible = "renesas,dmac-r8a7742", 716 "renesas,rcar-dmac"; 717 reg = <0 0xe6720000 0 0x20000>; 718 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 719 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 720 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 721 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 722 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 723 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 724 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 725 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 726 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 727 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 728 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 729 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; 734 interrupt-names = "error", 735 "ch0", "ch1", "ch2", "ch3", 736 "ch4", "ch5", "ch6", "ch7", 737 "ch8", "ch9", "ch10", "ch11", 738 "ch12", "ch13", "ch14"; 739 clocks = <&cpg CPG_MOD 218>; 740 clock-names = "fck"; 741 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 742 resets = <&cpg 218>; 743 #dma-cells = <1>; 744 dma-channels = <15>; 745 }; 746 747 avb: ethernet@e6800000 { 748 compatible = "renesas,etheravb-r8a7742", 749 "renesas,etheravb-rcar-gen2"; 750 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; 751 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 752 clocks = <&cpg CPG_MOD 812>; 753 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 754 resets = <&cpg 812>; 755 #address-cells = <1>; 756 #size-cells = <0>; 757 status = "disabled"; 758 }; 759 760 qspi: spi@e6b10000 { 761 compatible = "renesas,qspi-r8a7742", "renesas,qspi"; 762 reg = <0 0xe6b10000 0 0x2c>; 763 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 764 clocks = <&cpg CPG_MOD 917>; 765 dmas = <&dmac0 0x17>, <&dmac0 0x18>, 766 <&dmac1 0x17>, <&dmac1 0x18>; 767 dma-names = "tx", "rx", "tx", "rx"; 768 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 769 resets = <&cpg 917>; 770 num-cs = <1>; 771 #address-cells = <1>; 772 #size-cells = <0>; 773 status = "disabled"; 774 }; 775 776 scifa0: serial@e6c40000 { 777 compatible = "renesas,scifa-r8a7742", 778 "renesas,rcar-gen2-scifa", "renesas,scifa"; 779 reg = <0 0xe6c40000 0 0x40>; 780 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 781 clocks = <&cpg CPG_MOD 204>; 782 clock-names = "fck"; 783 dmas = <&dmac0 0x21>, <&dmac0 0x22>, 784 <&dmac1 0x21>, <&dmac1 0x22>; 785 dma-names = "tx", "rx", "tx", "rx"; 786 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 787 resets = <&cpg 204>; 788 status = "disabled"; 789 }; 790 791 scifa1: serial@e6c50000 { 792 compatible = "renesas,scifa-r8a7742", 793 "renesas,rcar-gen2-scifa", "renesas,scifa"; 794 reg = <0 0xe6c50000 0 0x40>; 795 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 796 clocks = <&cpg CPG_MOD 203>; 797 clock-names = "fck"; 798 dmas = <&dmac0 0x25>, <&dmac0 0x26>, 799 <&dmac1 0x25>, <&dmac1 0x26>; 800 dma-names = "tx", "rx", "tx", "rx"; 801 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 802 resets = <&cpg 203>; 803 status = "disabled"; 804 }; 805 806 scifa2: serial@e6c60000 { 807 compatible = "renesas,scifa-r8a7742", 808 "renesas,rcar-gen2-scifa", "renesas,scifa"; 809 reg = <0 0xe6c60000 0 0x40>; 810 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 811 clocks = <&cpg CPG_MOD 202>; 812 clock-names = "fck"; 813 dmas = <&dmac0 0x27>, <&dmac0 0x28>, 814 <&dmac1 0x27>, <&dmac1 0x28>; 815 dma-names = "tx", "rx", "tx", "rx"; 816 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 817 resets = <&cpg 202>; 818 status = "disabled"; 819 }; 820 821 scifb0: serial@e6c20000 { 822 compatible = "renesas,scifb-r8a7742", 823 "renesas,rcar-gen2-scifb", "renesas,scifb"; 824 reg = <0 0xe6c20000 0 0x100>; 825 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 826 clocks = <&cpg CPG_MOD 206>; 827 clock-names = "fck"; 828 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, 829 <&dmac1 0x3d>, <&dmac1 0x3e>; 830 dma-names = "tx", "rx", "tx", "rx"; 831 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 832 resets = <&cpg 206>; 833 status = "disabled"; 834 }; 835 836 scifb1: serial@e6c30000 { 837 compatible = "renesas,scifb-r8a7742", 838 "renesas,rcar-gen2-scifb", "renesas,scifb"; 839 reg = <0 0xe6c30000 0 0x100>; 840 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 841 clocks = <&cpg CPG_MOD 207>; 842 clock-names = "fck"; 843 dmas = <&dmac0 0x19>, <&dmac0 0x1a>, 844 <&dmac1 0x19>, <&dmac1 0x1a>; 845 dma-names = "tx", "rx", "tx", "rx"; 846 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 847 resets = <&cpg 207>; 848 status = "disabled"; 849 }; 850 851 scifb2: serial@e6ce0000 { 852 compatible = "renesas,scifb-r8a7742", 853 "renesas,rcar-gen2-scifb", "renesas,scifb"; 854 reg = <0 0xe6ce0000 0 0x100>; 855 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 856 clocks = <&cpg CPG_MOD 216>; 857 clock-names = "fck"; 858 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, 859 <&dmac1 0x1d>, <&dmac1 0x1e>; 860 dma-names = "tx", "rx", "tx", "rx"; 861 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 862 resets = <&cpg 216>; 863 status = "disabled"; 864 }; 865 866 scif0: serial@e6e60000 { 867 compatible = "renesas,scif-r8a7742", 868 "renesas,rcar-gen2-scif", "renesas,scif"; 869 reg = <0 0xe6e60000 0 0x40>; 870 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 871 clocks = <&cpg CPG_MOD 721>, 872 <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>; 873 clock-names = "fck", "brg_int", "scif_clk"; 874 dmas = <&dmac0 0x29>, <&dmac0 0x2a>, 875 <&dmac1 0x29>, <&dmac1 0x2a>; 876 dma-names = "tx", "rx", "tx", "rx"; 877 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 878 resets = <&cpg 721>; 879 status = "disabled"; 880 }; 881 882 scif1: serial@e6e68000 { 883 compatible = "renesas,scif-r8a7742", 884 "renesas,rcar-gen2-scif", "renesas,scif"; 885 reg = <0 0xe6e68000 0 0x40>; 886 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 887 clocks = <&cpg CPG_MOD 720>, 888 <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>; 889 clock-names = "fck", "brg_int", "scif_clk"; 890 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, 891 <&dmac1 0x2d>, <&dmac1 0x2e>; 892 dma-names = "tx", "rx", "tx", "rx"; 893 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 894 resets = <&cpg 720>; 895 status = "disabled"; 896 }; 897 898 scif2: serial@e6e56000 { 899 compatible = "renesas,scif-r8a7742", 900 "renesas,rcar-gen2-scif", "renesas,scif"; 901 reg = <0 0xe6e56000 0 0x40>; 902 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 903 clocks = <&cpg CPG_MOD 310>, 904 <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>; 905 clock-names = "fck", "brg_int", "scif_clk"; 906 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, 907 <&dmac1 0x2b>, <&dmac1 0x2c>; 908 dma-names = "tx", "rx", "tx", "rx"; 909 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 910 resets = <&cpg 310>; 911 status = "disabled"; 912 }; 913 914 hscif0: serial@e62c0000 { 915 compatible = "renesas,hscif-r8a7742", 916 "renesas,rcar-gen2-hscif", "renesas,hscif"; 917 reg = <0 0xe62c0000 0 0x60>; 918 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 919 clocks = <&cpg CPG_MOD 717>, 920 <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>; 921 clock-names = "fck", "brg_int", "scif_clk"; 922 dmas = <&dmac0 0x39>, <&dmac0 0x3a>, 923 <&dmac1 0x39>, <&dmac1 0x3a>; 924 dma-names = "tx", "rx", "tx", "rx"; 925 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 926 resets = <&cpg 717>; 927 status = "disabled"; 928 }; 929 930 hscif1: serial@e62c8000 { 931 compatible = "renesas,hscif-r8a7742", 932 "renesas,rcar-gen2-hscif", "renesas,hscif"; 933 reg = <0 0xe62c8000 0 0x60>; 934 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 935 clocks = <&cpg CPG_MOD 716>, 936 <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>; 937 clock-names = "fck", "brg_int", "scif_clk"; 938 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, 939 <&dmac1 0x4d>, <&dmac1 0x4e>; 940 dma-names = "tx", "rx", "tx", "rx"; 941 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 942 resets = <&cpg 716>; 943 status = "disabled"; 944 }; 945 946 msiof0: spi@e6e20000 { 947 compatible = "renesas,msiof-r8a7742", 948 "renesas,rcar-gen2-msiof"; 949 reg = <0 0xe6e20000 0 0x0064>; 950 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 951 clocks = <&cpg CPG_MOD 0>; 952 dmas = <&dmac0 0x51>, <&dmac0 0x52>, 953 <&dmac1 0x51>, <&dmac1 0x52>; 954 dma-names = "tx", "rx", "tx", "rx"; 955 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 956 resets = <&cpg 0>; 957 #address-cells = <1>; 958 #size-cells = <0>; 959 status = "disabled"; 960 }; 961 962 msiof1: spi@e6e10000 { 963 compatible = "renesas,msiof-r8a7742", 964 "renesas,rcar-gen2-msiof"; 965 reg = <0 0xe6e10000 0 0x0064>; 966 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 967 clocks = <&cpg CPG_MOD 208>; 968 dmas = <&dmac0 0x55>, <&dmac0 0x56>, 969 <&dmac1 0x55>, <&dmac1 0x56>; 970 dma-names = "tx", "rx", "tx", "rx"; 971 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 972 resets = <&cpg 208>; 973 #address-cells = <1>; 974 #size-cells = <0>; 975 status = "disabled"; 976 }; 977 978 msiof2: spi@e6e00000 { 979 compatible = "renesas,msiof-r8a7742", 980 "renesas,rcar-gen2-msiof"; 981 reg = <0 0xe6e00000 0 0x0064>; 982 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 983 clocks = <&cpg CPG_MOD 205>; 984 dmas = <&dmac0 0x41>, <&dmac0 0x42>, 985 <&dmac1 0x41>, <&dmac1 0x42>; 986 dma-names = "tx", "rx", "tx", "rx"; 987 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 988 resets = <&cpg 205>; 989 #address-cells = <1>; 990 #size-cells = <0>; 991 status = "disabled"; 992 }; 993 994 msiof3: spi@e6c90000 { 995 compatible = "renesas,msiof-r8a7742", 996 "renesas,rcar-gen2-msiof"; 997 reg = <0 0xe6c90000 0 0x0064>; 998 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 999 clocks = <&cpg CPG_MOD 215>; 1000 dmas = <&dmac0 0x45>, <&dmac0 0x46>, 1001 <&dmac1 0x45>, <&dmac1 0x46>; 1002 dma-names = "tx", "rx", "tx", "rx"; 1003 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1004 resets = <&cpg 215>; 1005 #address-cells = <1>; 1006 #size-cells = <0>; 1007 status = "disabled"; 1008 }; 1009 1010 can0: can@e6e80000 { 1011 compatible = "renesas,can-r8a7742", 1012 "renesas,rcar-gen2-can"; 1013 reg = <0 0xe6e80000 0 0x1000>; 1014 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1015 clocks = <&cpg CPG_MOD 916>, 1016 <&cpg CPG_CORE R8A7742_CLK_RCAN>, <&can_clk>; 1017 clock-names = "clkp1", "clkp2", "can_clk"; 1018 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1019 resets = <&cpg 916>; 1020 status = "disabled"; 1021 }; 1022 1023 can1: can@e6e88000 { 1024 compatible = "renesas,can-r8a7742", 1025 "renesas,rcar-gen2-can"; 1026 reg = <0 0xe6e88000 0 0x1000>; 1027 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 1028 clocks = <&cpg CPG_MOD 915>, 1029 <&cpg CPG_CORE R8A7742_CLK_RCAN>, <&can_clk>; 1030 clock-names = "clkp1", "clkp2", "can_clk"; 1031 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1032 resets = <&cpg 915>; 1033 status = "disabled"; 1034 }; 1035 1036 pwm0: pwm@e6e30000 { 1037 compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar"; 1038 reg = <0 0xe6e30000 0 0x8>; 1039 clocks = <&cpg CPG_MOD 523>; 1040 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1041 resets = <&cpg 523>; 1042 #pwm-cells = <2>; 1043 status = "disabled"; 1044 }; 1045 1046 pwm1: pwm@e6e31000 { 1047 compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar"; 1048 reg = <0 0xe6e31000 0 0x8>; 1049 clocks = <&cpg CPG_MOD 523>; 1050 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1051 resets = <&cpg 523>; 1052 #pwm-cells = <2>; 1053 status = "disabled"; 1054 }; 1055 1056 pwm2: pwm@e6e32000 { 1057 compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar"; 1058 reg = <0 0xe6e32000 0 0x8>; 1059 clocks = <&cpg CPG_MOD 523>; 1060 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1061 resets = <&cpg 523>; 1062 #pwm-cells = <2>; 1063 status = "disabled"; 1064 }; 1065 1066 pwm3: pwm@e6e33000 { 1067 compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar"; 1068 reg = <0 0xe6e33000 0 0x8>; 1069 clocks = <&cpg CPG_MOD 523>; 1070 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1071 resets = <&cpg 523>; 1072 #pwm-cells = <2>; 1073 status = "disabled"; 1074 }; 1075 1076 pwm4: pwm@e6e34000 { 1077 compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar"; 1078 reg = <0 0xe6e34000 0 0x8>; 1079 clocks = <&cpg CPG_MOD 523>; 1080 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1081 resets = <&cpg 523>; 1082 #pwm-cells = <2>; 1083 status = "disabled"; 1084 }; 1085 1086 pwm5: pwm@e6e35000 { 1087 compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar"; 1088 reg = <0 0xe6e35000 0 0x8>; 1089 clocks = <&cpg CPG_MOD 523>; 1090 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1091 resets = <&cpg 523>; 1092 #pwm-cells = <2>; 1093 status = "disabled"; 1094 }; 1095 1096 pwm6: pwm@e6e36000 { 1097 compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar"; 1098 reg = <0 0xe6e36000 0 0x8>; 1099 clocks = <&cpg CPG_MOD 523>; 1100 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1101 resets = <&cpg 523>; 1102 #pwm-cells = <2>; 1103 status = "disabled"; 1104 }; 1105 1106 vin0: video@e6ef0000 { 1107 compatible = "renesas,vin-r8a7742", 1108 "renesas,rcar-gen2-vin"; 1109 reg = <0 0xe6ef0000 0 0x1000>; 1110 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 1111 clocks = <&cpg CPG_MOD 811>; 1112 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1113 resets = <&cpg 811>; 1114 status = "disabled"; 1115 }; 1116 1117 vin1: video@e6ef1000 { 1118 compatible = "renesas,vin-r8a7742", 1119 "renesas,rcar-gen2-vin"; 1120 reg = <0 0xe6ef1000 0 0x1000>; 1121 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 1122 clocks = <&cpg CPG_MOD 810>; 1123 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1124 resets = <&cpg 810>; 1125 status = "disabled"; 1126 }; 1127 1128 vin2: video@e6ef2000 { 1129 compatible = "renesas,vin-r8a7742", 1130 "renesas,rcar-gen2-vin"; 1131 reg = <0 0xe6ef2000 0 0x1000>; 1132 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1133 clocks = <&cpg CPG_MOD 809>; 1134 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1135 resets = <&cpg 809>; 1136 status = "disabled"; 1137 }; 1138 1139 vin3: video@e6ef3000 { 1140 compatible = "renesas,vin-r8a7742", 1141 "renesas,rcar-gen2-vin"; 1142 reg = <0 0xe6ef3000 0 0x1000>; 1143 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 1144 clocks = <&cpg CPG_MOD 808>; 1145 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1146 resets = <&cpg 808>; 1147 status = "disabled"; 1148 }; 1149 1150 rcar_sound: sound@ec500000 { 1151 /* 1152 * #sound-dai-cells is required 1153 * 1154 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 1155 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 1156 */ 1157 compatible = "renesas,rcar_sound-r8a7742", 1158 "renesas,rcar_sound-gen2"; 1159 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1160 <0 0xec5a0000 0 0x100>, /* ADG */ 1161 <0 0xec540000 0 0x1000>, /* SSIU */ 1162 <0 0xec541000 0 0x280>, /* SSI */ 1163 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ 1164 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 1165 1166 clocks = <&cpg CPG_MOD 1005>, 1167 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, 1168 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, 1169 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, 1170 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, 1171 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, 1172 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, 1173 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, 1174 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, 1175 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, 1176 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, 1177 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, 1178 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, 1179 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 1180 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, 1181 <&cpg CPG_CORE R8A7742_CLK_M2>; 1182 clock-names = "ssi-all", 1183 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1184 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1185 "ssi.1", "ssi.0", 1186 "src.9", "src.8", "src.7", "src.6", 1187 "src.5", "src.4", "src.3", "src.2", 1188 "src.1", "src.0", 1189 "ctu.0", "ctu.1", 1190 "mix.0", "mix.1", 1191 "dvc.0", "dvc.1", 1192 "clk_a", "clk_b", "clk_c", "clk_i"; 1193 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1194 resets = <&cpg 1005>, 1195 <&cpg 1006>, <&cpg 1007>, 1196 <&cpg 1008>, <&cpg 1009>, 1197 <&cpg 1010>, <&cpg 1011>, 1198 <&cpg 1012>, <&cpg 1013>, 1199 <&cpg 1014>, <&cpg 1015>; 1200 reset-names = "ssi-all", 1201 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1202 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1203 "ssi.1", "ssi.0"; 1204 1205 status = "disabled"; 1206 1207 rcar_sound,dvc { 1208 dvc0: dvc-0 { 1209 dmas = <&audma1 0xbc>; 1210 dma-names = "tx"; 1211 }; 1212 dvc1: dvc-1 { 1213 dmas = <&audma1 0xbe>; 1214 dma-names = "tx"; 1215 }; 1216 }; 1217 1218 rcar_sound,mix { 1219 mix0: mix-0 { }; 1220 mix1: mix-1 { }; 1221 }; 1222 1223 rcar_sound,ctu { 1224 ctu00: ctu-0 { }; 1225 ctu01: ctu-1 { }; 1226 ctu02: ctu-2 { }; 1227 ctu03: ctu-3 { }; 1228 ctu10: ctu-4 { }; 1229 ctu11: ctu-5 { }; 1230 ctu12: ctu-6 { }; 1231 ctu13: ctu-7 { }; 1232 }; 1233 1234 rcar_sound,src { 1235 src0: src-0 { 1236 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1237 dmas = <&audma0 0x85>, <&audma1 0x9a>; 1238 dma-names = "rx", "tx"; 1239 }; 1240 src1: src-1 { 1241 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1242 dmas = <&audma0 0x87>, <&audma1 0x9c>; 1243 dma-names = "rx", "tx"; 1244 }; 1245 src2: src-2 { 1246 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1247 dmas = <&audma0 0x89>, <&audma1 0x9e>; 1248 dma-names = "rx", "tx"; 1249 }; 1250 src3: src-3 { 1251 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1252 dmas = <&audma0 0x8b>, <&audma1 0xa0>; 1253 dma-names = "rx", "tx"; 1254 }; 1255 src4: src-4 { 1256 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1257 dmas = <&audma0 0x8d>, <&audma1 0xb0>; 1258 dma-names = "rx", "tx"; 1259 }; 1260 src5: src-5 { 1261 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1262 dmas = <&audma0 0x8f>, <&audma1 0xb2>; 1263 dma-names = "rx", "tx"; 1264 }; 1265 src6: src-6 { 1266 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1267 dmas = <&audma0 0x91>, <&audma1 0xb4>; 1268 dma-names = "rx", "tx"; 1269 }; 1270 src7: src-7 { 1271 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1272 dmas = <&audma0 0x93>, <&audma1 0xb6>; 1273 dma-names = "rx", "tx"; 1274 }; 1275 src8: src-8 { 1276 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1277 dmas = <&audma0 0x95>, <&audma1 0xb8>; 1278 dma-names = "rx", "tx"; 1279 }; 1280 src9: src-9 { 1281 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1282 dmas = <&audma0 0x97>, <&audma1 0xba>; 1283 dma-names = "rx", "tx"; 1284 }; 1285 }; 1286 1287 rcar_sound,ssi { 1288 ssi0: ssi-0 { 1289 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 1290 dmas = <&audma0 0x01>, <&audma1 0x02>, 1291 <&audma0 0x15>, <&audma1 0x16>; 1292 dma-names = "rx", "tx", "rxu", "txu"; 1293 }; 1294 ssi1: ssi-1 { 1295 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 1296 dmas = <&audma0 0x03>, <&audma1 0x04>, 1297 <&audma0 0x49>, <&audma1 0x4a>; 1298 dma-names = "rx", "tx", "rxu", "txu"; 1299 }; 1300 ssi2: ssi-2 { 1301 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 1302 dmas = <&audma0 0x05>, <&audma1 0x06>, 1303 <&audma0 0x63>, <&audma1 0x64>; 1304 dma-names = "rx", "tx", "rxu", "txu"; 1305 }; 1306 ssi3: ssi-3 { 1307 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1308 dmas = <&audma0 0x07>, <&audma1 0x08>, 1309 <&audma0 0x6f>, <&audma1 0x70>; 1310 dma-names = "rx", "tx", "rxu", "txu"; 1311 }; 1312 ssi4: ssi-4 { 1313 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1314 dmas = <&audma0 0x09>, <&audma1 0x0a>, 1315 <&audma0 0x71>, <&audma1 0x72>; 1316 dma-names = "rx", "tx", "rxu", "txu"; 1317 }; 1318 ssi5: ssi-5 { 1319 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1320 dmas = <&audma0 0x0b>, <&audma1 0x0c>, 1321 <&audma0 0x73>, <&audma1 0x74>; 1322 dma-names = "rx", "tx", "rxu", "txu"; 1323 }; 1324 ssi6: ssi-6 { 1325 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; 1326 dmas = <&audma0 0x0d>, <&audma1 0x0e>, 1327 <&audma0 0x75>, <&audma1 0x76>; 1328 dma-names = "rx", "tx", "rxu", "txu"; 1329 }; 1330 ssi7: ssi-7 { 1331 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; 1332 dmas = <&audma0 0x0f>, <&audma1 0x10>, 1333 <&audma0 0x79>, <&audma1 0x7a>; 1334 dma-names = "rx", "tx", "rxu", "txu"; 1335 }; 1336 ssi8: ssi-8 { 1337 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; 1338 dmas = <&audma0 0x11>, <&audma1 0x12>, 1339 <&audma0 0x7b>, <&audma1 0x7c>; 1340 dma-names = "rx", "tx", "rxu", "txu"; 1341 }; 1342 ssi9: ssi-9 { 1343 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 1344 dmas = <&audma0 0x13>, <&audma1 0x14>, 1345 <&audma0 0x7d>, <&audma1 0x7e>; 1346 dma-names = "rx", "tx", "rxu", "txu"; 1347 }; 1348 }; 1349 }; 1350 1351 audma0: dma-controller@ec700000 { 1352 compatible = "renesas,dmac-r8a7742", 1353 "renesas,rcar-dmac"; 1354 reg = <0 0xec700000 0 0x10000>; 1355 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 1356 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1357 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1358 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1359 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1360 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1361 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1362 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1363 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1364 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1365 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1366 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1367 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1368 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1369 interrupt-names = "error", 1370 "ch0", "ch1", "ch2", "ch3", 1371 "ch4", "ch5", "ch6", "ch7", 1372 "ch8", "ch9", "ch10", "ch11", 1373 "ch12"; 1374 clocks = <&cpg CPG_MOD 502>; 1375 clock-names = "fck"; 1376 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1377 resets = <&cpg 502>; 1378 #dma-cells = <1>; 1379 dma-channels = <13>; 1380 }; 1381 1382 audma1: dma-controller@ec720000 { 1383 compatible = "renesas,dmac-r8a7742", 1384 "renesas,rcar-dmac"; 1385 reg = <0 0xec720000 0 0x10000>; 1386 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 1387 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1388 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1389 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1390 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1391 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1392 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1393 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1394 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1395 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1396 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1397 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1398 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 1399 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; 1400 interrupt-names = "error", 1401 "ch0", "ch1", "ch2", "ch3", 1402 "ch4", "ch5", "ch6", "ch7", 1403 "ch8", "ch9", "ch10", "ch11", 1404 "ch12"; 1405 clocks = <&cpg CPG_MOD 501>; 1406 clock-names = "fck"; 1407 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1408 resets = <&cpg 501>; 1409 #dma-cells = <1>; 1410 dma-channels = <13>; 1411 }; 1412 1413 xhci: usb@ee000000 { 1414 compatible = "renesas,xhci-r8a7742", 1415 "renesas,rcar-gen2-xhci"; 1416 reg = <0 0xee000000 0 0xc00>; 1417 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1418 clocks = <&cpg CPG_MOD 328>; 1419 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1420 resets = <&cpg 328>; 1421 phys = <&usb2 1>; 1422 phy-names = "usb"; 1423 status = "disabled"; 1424 }; 1425 1426 pci0: pci@ee090000 { 1427 compatible = "renesas,pci-r8a7742", 1428 "renesas,pci-rcar-gen2"; 1429 device_type = "pci"; 1430 reg = <0 0xee090000 0 0xc00>, 1431 <0 0xee080000 0 0x1100>; 1432 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1433 clocks = <&cpg CPG_MOD 703>; 1434 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1435 resets = <&cpg 703>; 1436 status = "disabled"; 1437 1438 bus-range = <0 0>; 1439 #address-cells = <3>; 1440 #size-cells = <2>; 1441 #interrupt-cells = <1>; 1442 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; 1443 interrupt-map-mask = <0xf800 0 0 0x7>; 1444 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1445 <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1446 <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1447 1448 usb@1,0 { 1449 reg = <0x800 0 0 0 0>; 1450 phys = <&usb0 0>; 1451 phy-names = "usb"; 1452 }; 1453 1454 usb@2,0 { 1455 reg = <0x1000 0 0 0 0>; 1456 phys = <&usb0 0>; 1457 phy-names = "usb"; 1458 }; 1459 }; 1460 1461 pci1: pci@ee0b0000 { 1462 compatible = "renesas,pci-r8a7742", 1463 "renesas,pci-rcar-gen2"; 1464 device_type = "pci"; 1465 reg = <0 0xee0b0000 0 0xc00>, 1466 <0 0xee0a0000 0 0x1100>; 1467 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1468 clocks = <&cpg CPG_MOD 703>; 1469 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1470 resets = <&cpg 703>; 1471 status = "disabled"; 1472 1473 bus-range = <1 1>; 1474 #address-cells = <3>; 1475 #size-cells = <2>; 1476 #interrupt-cells = <1>; 1477 ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>; 1478 interrupt-map-mask = <0xf800 0 0 0x7>; 1479 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1480 <0x0800 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1481 <0x1000 0 0 2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1482 }; 1483 1484 pci2: pci@ee0d0000 { 1485 compatible = "renesas,pci-r8a7742", 1486 "renesas,pci-rcar-gen2"; 1487 device_type = "pci"; 1488 clocks = <&cpg CPG_MOD 703>; 1489 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1490 resets = <&cpg 703>; 1491 reg = <0 0xee0d0000 0 0xc00>, 1492 <0 0xee0c0000 0 0x1100>; 1493 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1494 status = "disabled"; 1495 1496 bus-range = <2 2>; 1497 #address-cells = <3>; 1498 #size-cells = <2>; 1499 #interrupt-cells = <1>; 1500 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; 1501 interrupt-map-mask = <0xf800 0 0 0x7>; 1502 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1503 <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1504 <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1505 1506 usb@1,0 { 1507 reg = <0x20800 0 0 0 0>; 1508 phys = <&usb2 0>; 1509 phy-names = "usb"; 1510 }; 1511 1512 usb@2,0 { 1513 reg = <0x21000 0 0 0 0>; 1514 phys = <&usb2 0>; 1515 phy-names = "usb"; 1516 }; 1517 }; 1518 1519 sdhi0: mmc@ee100000 { 1520 compatible = "renesas,sdhi-r8a7742", 1521 "renesas,rcar-gen2-sdhi"; 1522 reg = <0 0xee100000 0 0x328>; 1523 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 1524 clocks = <&cpg CPG_MOD 314>; 1525 dmas = <&dmac0 0xcd>, <&dmac0 0xce>, 1526 <&dmac1 0xcd>, <&dmac1 0xce>; 1527 dma-names = "tx", "rx", "tx", "rx"; 1528 max-frequency = <195000000>; 1529 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1530 resets = <&cpg 314>; 1531 status = "disabled"; 1532 }; 1533 1534 sdhi1: mmc@ee120000 { 1535 compatible = "renesas,sdhi-r8a7742", 1536 "renesas,rcar-gen2-sdhi"; 1537 reg = <0 0xee120000 0 0x328>; 1538 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1539 clocks = <&cpg CPG_MOD 313>; 1540 dmas = <&dmac0 0xc9>, <&dmac0 0xca>, 1541 <&dmac1 0xc9>, <&dmac1 0xca>; 1542 dma-names = "tx", "rx", "tx", "rx"; 1543 max-frequency = <195000000>; 1544 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1545 resets = <&cpg 313>; 1546 status = "disabled"; 1547 }; 1548 1549 sdhi2: mmc@ee140000 { 1550 compatible = "renesas,sdhi-r8a7742", 1551 "renesas,rcar-gen2-sdhi"; 1552 reg = <0 0xee140000 0 0x100>; 1553 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1554 clocks = <&cpg CPG_MOD 312>; 1555 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, 1556 <&dmac1 0xc1>, <&dmac1 0xc2>; 1557 dma-names = "tx", "rx", "tx", "rx"; 1558 max-frequency = <97500000>; 1559 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1560 resets = <&cpg 312>; 1561 status = "disabled"; 1562 }; 1563 1564 sdhi3: mmc@ee160000 { 1565 compatible = "renesas,sdhi-r8a7742", 1566 "renesas,rcar-gen2-sdhi"; 1567 reg = <0 0xee160000 0 0x100>; 1568 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 1569 clocks = <&cpg CPG_MOD 311>; 1570 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, 1571 <&dmac1 0xd3>, <&dmac1 0xd4>; 1572 dma-names = "tx", "rx", "tx", "rx"; 1573 max-frequency = <97500000>; 1574 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1575 resets = <&cpg 311>; 1576 status = "disabled"; 1577 }; 1578 1579 mmcif0: mmc@ee200000 { 1580 compatible = "renesas,mmcif-r8a7742", 1581 "renesas,sh-mmcif"; 1582 reg = <0 0xee200000 0 0x80>; 1583 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 1584 clocks = <&cpg CPG_MOD 315>; 1585 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, 1586 <&dmac1 0xd1>, <&dmac1 0xd2>; 1587 dma-names = "tx", "rx", "tx", "rx"; 1588 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1589 resets = <&cpg 315>; 1590 reg-io-width = <4>; 1591 status = "disabled"; 1592 max-frequency = <97500000>; 1593 }; 1594 1595 mmcif1: mmc@ee220000 { 1596 compatible = "renesas,mmcif-r8a7742", 1597 "renesas,sh-mmcif"; 1598 reg = <0 0xee220000 0 0x80>; 1599 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1600 clocks = <&cpg CPG_MOD 305>; 1601 dmas = <&dmac0 0xe1>, <&dmac0 0xe2>, 1602 <&dmac1 0xe1>, <&dmac1 0xe2>; 1603 dma-names = "tx", "rx", "tx", "rx"; 1604 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1605 resets = <&cpg 305>; 1606 reg-io-width = <4>; 1607 status = "disabled"; 1608 max-frequency = <97500000>; 1609 }; 1610 1611 sata0: sata@ee300000 { 1612 compatible = "renesas,sata-r8a7742", 1613 "renesas,rcar-gen2-sata"; 1614 reg = <0 0xee300000 0 0x200000>; 1615 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1616 clocks = <&cpg CPG_MOD 815>; 1617 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1618 resets = <&cpg 815>; 1619 status = "disabled"; 1620 }; 1621 1622 sata1: sata@ee500000 { 1623 compatible = "renesas,sata-r8a7742", 1624 "renesas,rcar-gen2-sata"; 1625 reg = <0 0xee500000 0 0x200000>; 1626 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1627 clocks = <&cpg CPG_MOD 814>; 1628 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1629 resets = <&cpg 814>; 1630 status = "disabled"; 1631 }; 1632 1633 ether: ethernet@ee700000 { 1634 compatible = "renesas,ether-r8a7742", 1635 "renesas,rcar-gen2-ether"; 1636 reg = <0 0xee700000 0 0x400>; 1637 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1638 clocks = <&cpg CPG_MOD 813>; 1639 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1640 resets = <&cpg 813>; 1641 phy-mode = "rmii"; 1642 #address-cells = <1>; 1643 #size-cells = <0>; 1644 status = "disabled"; 1645 }; 1646 1647 gic: interrupt-controller@f1001000 { 1648 compatible = "arm,gic-400"; 1649 #interrupt-cells = <3>; 1650 #address-cells = <0>; 1651 interrupt-controller; 1652 reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, 1653 <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; 1654 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 1655 clocks = <&cpg CPG_MOD 408>; 1656 clock-names = "clk"; 1657 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1658 resets = <&cpg 408>; 1659 }; 1660 1661 pciec: pcie@fe000000 { 1662 compatible = "renesas,pcie-r8a7742", 1663 "renesas,pcie-rcar-gen2"; 1664 reg = <0 0xfe000000 0 0x80000>; 1665 #address-cells = <3>; 1666 #size-cells = <2>; 1667 bus-range = <0x00 0xff>; 1668 device_type = "pci"; 1669 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, 1670 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, 1671 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, 1672 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; 1673 /* Map all possible DDR as inbound ranges */ 1674 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>, 1675 <0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>; 1676 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1677 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1678 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1679 #interrupt-cells = <1>; 1680 interrupt-map-mask = <0 0 0 0>; 1681 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 1682 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; 1683 clock-names = "pcie", "pcie_bus"; 1684 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1685 resets = <&cpg 319>; 1686 status = "disabled"; 1687 }; 1688 1689 vsp@fe920000 { 1690 compatible = "renesas,vsp1"; 1691 reg = <0 0xfe920000 0 0x8000>; 1692 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 1693 clocks = <&cpg CPG_MOD 130>; 1694 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1695 resets = <&cpg 130>; 1696 }; 1697 1698 vsp@fe928000 { 1699 compatible = "renesas,vsp1"; 1700 reg = <0 0xfe928000 0 0x8000>; 1701 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; 1702 clocks = <&cpg CPG_MOD 131>; 1703 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1704 resets = <&cpg 131>; 1705 }; 1706 1707 vsp@fe930000 { 1708 compatible = "renesas,vsp1"; 1709 reg = <0 0xfe930000 0 0x8000>; 1710 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 1711 clocks = <&cpg CPG_MOD 128>; 1712 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1713 resets = <&cpg 128>; 1714 }; 1715 1716 vsp@fe938000 { 1717 compatible = "renesas,vsp1"; 1718 reg = <0 0xfe938000 0 0x8000>; 1719 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 1720 clocks = <&cpg CPG_MOD 127>; 1721 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1722 resets = <&cpg 127>; 1723 }; 1724 1725 du: display@feb00000 { 1726 compatible = "renesas,du-r8a7742"; 1727 reg = <0 0xfeb00000 0 0x70000>; 1728 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 1729 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 1730 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 1731 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, 1732 <&cpg CPG_MOD 722>; 1733 clock-names = "du.0", "du.1", "du.2"; 1734 resets = <&cpg 724>; 1735 reset-names = "du.0"; 1736 status = "disabled"; 1737 1738 ports { 1739 #address-cells = <1>; 1740 #size-cells = <0>; 1741 1742 port@0 { 1743 reg = <0>; 1744 du_out_rgb: endpoint { 1745 }; 1746 }; 1747 port@1 { 1748 reg = <1>; 1749 du_out_lvds0: endpoint { 1750 remote-endpoint = <&lvds0_in>; 1751 }; 1752 }; 1753 port@2 { 1754 reg = <2>; 1755 du_out_lvds1: endpoint { 1756 remote-endpoint = <&lvds1_in>; 1757 }; 1758 }; 1759 }; 1760 }; 1761 1762 lvds0: lvds@feb90000 { 1763 compatible = "renesas,r8a7742-lvds"; 1764 reg = <0 0xfeb90000 0 0x14>; 1765 clocks = <&cpg CPG_MOD 726>; 1766 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1767 resets = <&cpg 726>; 1768 status = "disabled"; 1769 1770 ports { 1771 #address-cells = <1>; 1772 #size-cells = <0>; 1773 1774 port@0 { 1775 reg = <0>; 1776 lvds0_in: endpoint { 1777 remote-endpoint = <&du_out_lvds0>; 1778 }; 1779 }; 1780 port@1 { 1781 reg = <1>; 1782 lvds0_out: endpoint { 1783 }; 1784 }; 1785 }; 1786 }; 1787 1788 lvds1: lvds@feb94000 { 1789 compatible = "renesas,r8a7742-lvds"; 1790 reg = <0 0xfeb94000 0 0x14>; 1791 clocks = <&cpg CPG_MOD 725>; 1792 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1793 resets = <&cpg 725>; 1794 status = "disabled"; 1795 1796 ports { 1797 #address-cells = <1>; 1798 #size-cells = <0>; 1799 1800 port@0 { 1801 reg = <0>; 1802 lvds1_in: endpoint { 1803 remote-endpoint = <&du_out_lvds1>; 1804 }; 1805 }; 1806 port@1 { 1807 reg = <1>; 1808 lvds1_out: endpoint { 1809 }; 1810 }; 1811 }; 1812 }; 1813 1814 prr: chipid@ff000044 { 1815 compatible = "renesas,prr"; 1816 reg = <0 0xff000044 0 4>; 1817 }; 1818 1819 cmt0: timer@ffca0000 { 1820 compatible = "renesas,r8a7742-cmt0", 1821 "renesas,rcar-gen2-cmt0"; 1822 reg = <0 0xffca0000 0 0x1004>; 1823 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1824 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 1825 clocks = <&cpg CPG_MOD 124>; 1826 clock-names = "fck"; 1827 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1828 resets = <&cpg 124>; 1829 status = "disabled"; 1830 }; 1831 1832 cmt1: timer@e6130000 { 1833 compatible = "renesas,r8a7742-cmt1", 1834 "renesas,rcar-gen2-cmt1"; 1835 reg = <0 0xe6130000 0 0x1004>; 1836 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1837 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1838 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1839 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1840 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1841 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1842 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1843 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1844 clocks = <&cpg CPG_MOD 329>; 1845 clock-names = "fck"; 1846 power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; 1847 resets = <&cpg 329>; 1848 status = "disabled"; 1849 }; 1850 }; 1851 1852 thermal-zones { 1853 cpu_thermal: cpu-thermal { 1854 polling-delay-passive = <0>; 1855 polling-delay = <0>; 1856 1857 thermal-sensors = <&thermal>; 1858 1859 trips { 1860 cpu-crit { 1861 temperature = <95000>; 1862 hysteresis = <0>; 1863 type = "critical"; 1864 }; 1865 }; 1866 cooling-maps { 1867 }; 1868 }; 1869 }; 1870 1871 timer { 1872 compatible = "arm,armv7-timer"; 1873 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1874 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1875 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1876 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 1877 }; 1878 1879 /* External USB clock - can be overridden by the board */ 1880 usb_extal_clk: usb_extal { 1881 compatible = "fixed-clock"; 1882 #clock-cells = <0>; 1883 clock-frequency = <48000000>; 1884 }; 1885}; 1886
