1 /* 2 * This is part of rtl8187 OpenSource driver. 3 * Copyright (C) Andrea Merello 2004-2005 <andrea.merello@gmail.com> 4 * Released under the terms of GPL (General Public Licence) 5 * 6 * Parts of this driver are based on the GPL part of the 7 * official Realtek driver. 8 * Parts of this driver are based on the rtl8180 driver skeleton 9 * from Patric Schenke & Andres Salomon. 10 * Parts of this driver are based on the Intel Pro Wireless 11 * 2100 GPL driver. 12 * 13 * We want to thank the Authors of those projects 14 * and the Ndiswrapper project Authors. 15 */ 16 17 /* Mariusz Matuszek added full registers definition with Realtek's name */ 18 19 /* this file contains register definitions for the rtl8187 MAC controller */ 20 #ifndef R8192_HW 21 #define R8192_HW 22 23 typedef enum _VERSION_819xU { 24 VERSION_819xU_A, // A-cut 25 VERSION_819xU_B, // B-cut 26 VERSION_819xU_C,// C-cut 27 } VERSION_819xU, *PVERSION_819xU; 28 //added for different RF type 29 typedef enum _RT_RF_TYPE_DEF { 30 RF_1T2R = 0, 31 RF_2T4R, 32 33 RF_819X_MAX_TYPE 34 } RT_RF_TYPE_DEF; 35 36 37 typedef enum _BaseBand_Config_Type { 38 BaseBand_Config_PHY_REG = 0, //Radio Path A 39 BaseBand_Config_AGC_TAB = 1, //Radio Path B 40 } BaseBand_Config_Type, *PBaseBand_Config_Type; 41 #define RTL8187_REQT_READ 0xc0 42 #define RTL8187_REQT_WRITE 0x40 43 #define RTL8187_REQ_GET_REGS 0x05 44 #define RTL8187_REQ_SET_REGS 0x05 45 46 #define MAX_TX_URB 5 47 #define MAX_RX_URB 16 48 49 #define R8180_MAX_RETRY 255 50 //#define MAX_RX_NORMAL_URB 3 51 //#define MAX_RX_COMMAND_URB 2 52 #define RX_URB_SIZE 9100 53 54 #define BB_ANTATTEN_CHAN14 0x0c 55 #define BB_ANTENNA_B 0x40 56 57 #define BB_HOST_BANG BIT(30) 58 #define BB_HOST_BANG_EN BIT(2) 59 #define BB_HOST_BANG_CLK BIT(1) 60 #define BB_HOST_BANG_RW BIT(3) 61 #define BB_HOST_BANG_DATA 1 62 63 //#if (RTL819X_FPGA_VER & RTL819X_FPGA_VIVI_070920) 64 #define AFR 0x010 65 #define AFR_CardBEn BIT(0) 66 #define AFR_CLKRUN_SEL BIT(1) 67 #define AFR_FuncRegEn BIT(2) 68 #define RTL8190_EEPROM_ID 0x8129 69 #define EEPROM_VID 0x02 70 #define EEPROM_PID 0x04 71 #define EEPROM_NODE_ADDRESS_BYTE_0 0x0C 72 73 #define EEPROM_TxPowerDiff 0x1F 74 #define EEPROM_ThermalMeter 0x20 75 #define EEPROM_PwDiff 0x21 //0x21 76 #define EEPROM_CrystalCap 0x22 //0x22 77 78 #define EEPROM_TxPwIndex_CCK 0x23 //0x23 79 #define EEPROM_TxPwIndex_OFDM_24G 0x24 //0x24~0x26 80 #define EEPROM_TxPwIndex_CCK_V1 0x29 //0x29~0x2B 81 #define EEPROM_TxPwIndex_OFDM_24G_V1 0x2C //0x2C~0x2E 82 #define EEPROM_TxPwIndex_Ver 0x27 //0x27 83 84 #define EEPROM_Default_TxPowerDiff 0x0 85 #define EEPROM_Default_ThermalMeter 0x7 86 #define EEPROM_Default_PwDiff 0x4 87 #define EEPROM_Default_CrystalCap 0x5 88 #define EEPROM_Default_TxPower 0x1010 89 #define EEPROM_Customer_ID 0x7B //0x7B:CustomerID 90 #define EEPROM_ChannelPlan 0x16 //0x7C 91 #define EEPROM_IC_VER 0x7d //0x7D 92 #define EEPROM_CRC 0x7e //0x7E~0x7F 93 94 #define EEPROM_CID_DEFAULT 0x0 95 #define EEPROM_CID_CAMEO 0x1 96 #define EEPROM_CID_RUNTOP 0x2 97 #define EEPROM_CID_Senao 0x3 98 #define EEPROM_CID_TOSHIBA 0x4 // Toshiba setting, Merge by Jacken, 2008/01/31 99 #define EEPROM_CID_NetCore 0x5 100 #define EEPROM_CID_Nettronix 0x6 101 #define EEPROM_CID_Pronet 0x7 102 #define EEPROM_CID_DLINK 0x8 103 104 #define AC_PARAM_TXOP_LIMIT_OFFSET 16 105 #define AC_PARAM_ECW_MAX_OFFSET 12 106 #define AC_PARAM_ECW_MIN_OFFSET 8 107 #define AC_PARAM_AIFS_OFFSET 0 108 109 //#endif 110 enum _RTL8192Usb_HW { 111 112 PCIF = 0x009, // PCI Function Register 0x0009h~0x000bh 113 #define BB_GLOBAL_RESET_BIT 0x1 114 BB_GLOBAL_RESET = 0x020, // BasebandGlobal Reset Register 115 BSSIDR = 0x02E, // BSSID Register 116 CMDR = 0x037, // Command register 117 #define CR_RST 0x10 118 #define CR_RE 0x08 119 #define CR_TE 0x04 120 #define CR_MulRW 0x01 121 SIFS = 0x03E, // SIFS register 122 TCR = 0x040, // Transmit Configuration Register 123 124 #define TCR_MXDMA_2048 7 125 #define TCR_LRL_OFFSET 0 126 #define TCR_SRL_OFFSET 8 127 #define TCR_MXDMA_OFFSET 21 128 #define TCR_SAT BIT(24) // Enable Rate depedent ack timeout timer 129 RCR = 0x044, // Receive Configuration Register 130 #define MAC_FILTER_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(5) | \ 131 BIT(12) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | \ 132 BIT(22) | BIT(23)) 133 #define RX_FIFO_THRESHOLD_MASK (BIT(13) | BIT(14) | BIT(15)) 134 #define RX_FIFO_THRESHOLD_SHIFT 13 135 #define RX_FIFO_THRESHOLD_128 3 136 #define RX_FIFO_THRESHOLD_256 4 137 #define RX_FIFO_THRESHOLD_512 5 138 #define RX_FIFO_THRESHOLD_1024 6 139 #define RX_FIFO_THRESHOLD_NONE 7 140 #define MAX_RX_DMA_MASK (BIT(8) | BIT(9) | BIT(10)) 141 #define RCR_MXDMA_OFFSET 8 142 #define RCR_FIFO_OFFSET 13 143 #define RCR_ONLYERLPKT BIT(31) // Early Receiving based on Packet Size. 144 #define RCR_ENCS2 BIT(30) // Enable Carrier Sense Detection Method 2 145 #define RCR_ENCS1 BIT(29) // Enable Carrier Sense Detection Method 1 146 #define RCR_ENMBID BIT(27) // Enable Multiple BssId. 147 #define RCR_ACKTXBW (BIT(24) | BIT(25)) // TXBW Setting of ACK frames 148 #define RCR_CBSSID BIT(23) // Accept BSSID match packet 149 #define RCR_APWRMGT BIT(22) // Accept power management packet 150 #define RCR_ADD3 BIT(21) // Accept address 3 match packet 151 #define RCR_AMF BIT(20) // Accept management type frame 152 #define RCR_ACF BIT(19) // Accept control type frame 153 #define RCR_ADF BIT(18) // Accept data type frame 154 #define RCR_RXFTH BIT(13) // Rx FIFO Threshold 155 #define RCR_AICV BIT(12) // Accept ICV error packet 156 #define RCR_ACRC32 BIT(5) // Accept CRC32 error packet 157 #define RCR_AB BIT(3) // Accept broadcast packet 158 #define RCR_AM BIT(2) // Accept multicast packet 159 #define RCR_APM BIT(1) // Accept physical match packet 160 #define RCR_AAP BIT(0) // Accept all unicast packet 161 SLOT_TIME = 0x049, // Slot Time Register 162 ACK_TIMEOUT = 0x04c, // Ack Timeout Register 163 PIFS_TIME = 0x04d, // PIFS time 164 USTIME = 0x04e, // Microsecond Tuning Register, Sets the microsecond time unit used by MAC clock. 165 EDCAPARA_BE = 0x050, // EDCA Parameter of AC BE 166 EDCAPARA_BK = 0x054, // EDCA Parameter of AC BK 167 EDCAPARA_VO = 0x058, // EDCA Parameter of AC VO 168 EDCAPARA_VI = 0x05C, // EDCA Parameter of AC VI 169 RFPC = 0x05F, // Rx FIFO Packet Count 170 CWRR = 0x060, // Contention Window Report Register 171 BCN_TCFG = 0x062, // Beacon Time Configuration 172 #define BCN_TCFG_CW_SHIFT 8 173 #define BCN_TCFG_IFS 0 174 BCN_INTERVAL = 0x070, // Beacon Interval (TU) 175 ATIMWND = 0x072, // ATIM Window Size (TU) 176 BCN_DRV_EARLY_INT = 0x074, // Driver Early Interrupt Time (TU). Time to send interrupt to notify to change beacon content before TBTT 177 BCN_DMATIME = 0x076, // Beacon DMA and ATIM interrupt time (US). Indicates the time before TBTT to perform beacon queue DMA 178 BCN_ERR_THRESH = 0x078, // Beacon Error Threshold 179 RWCAM = 0x0A0, //IN 8190 Data Sheet is called CAMcmd 180 WCAMI = 0x0A4, // Software write CAM input content 181 RCAMO = 0x0A8, // Software read/write CAM config 182 SECR = 0x0B0, //Security Configuration Register 183 #define SCR_TxUseDK BIT(0) //Force Tx Use Default Key 184 #define SCR_RxUseDK BIT(1) //Force Rx Use Default Key 185 #define SCR_TxEncEnable BIT(2) //Enable Tx Encryption 186 #define SCR_RxDecEnable BIT(3) //Enable Rx Decryption 187 #define SCR_SKByA2 BIT(4) //Search kEY BY A2 188 #define SCR_NoSKMC BIT(5) //No Key Search for Multicast 189 #define SCR_UseDK 0x01 190 #define SCR_TxSecEnable 0x02 191 #define SCR_RxSecEnable 0x04 192 TPPoll = 0x0fd, // Transmit priority polling register 193 PSR = 0x0ff, // Page Select Register 194 #define CPU_CCK_LOOPBACK 0x00030000 195 #define CPU_GEN_SYSTEM_RESET 0x00000001 196 #define CPU_GEN_FIRMWARE_RESET 0x00000008 197 #define CPU_GEN_BOOT_RDY 0x00000010 198 #define CPU_GEN_FIRM_RDY 0x00000020 199 #define CPU_GEN_PUT_CODE_OK 0x00000080 200 #define CPU_GEN_BB_RST 0x00000100 201 #define CPU_GEN_PWR_STB_CPU 0x00000004 202 #define CPU_GEN_NO_LOOPBACK_MSK 0xFFF8FFFF // Set bit18,17,16 to 0. Set bit19 203 #define CPU_GEN_NO_LOOPBACK_SET 0x00080000 // Set BIT19 to 1 204 205 //---------------------------------------------------------------------------- 206 // 8190 CPU General Register (offset 0x100, 4 byte) 207 //---------------------------------------------------------------------------- 208 #define CPU_CCK_LOOPBACK 0x00030000 209 #define CPU_GEN_SYSTEM_RESET 0x00000001 210 #define CPU_GEN_FIRMWARE_RESET 0x00000008 211 #define CPU_GEN_BOOT_RDY 0x00000010 212 #define CPU_GEN_FIRM_RDY 0x00000020 213 #define CPU_GEN_PUT_CODE_OK 0x00000080 214 #define CPU_GEN_BB_RST 0x00000100 215 #define CPU_GEN_PWR_STB_CPU 0x00000004 216 #define CPU_GEN_NO_LOOPBACK_MSK 0xFFF8FFFF // Set bit18,17,16 to 0. Set bit19 217 #define CPU_GEN_NO_LOOPBACK_SET 0x00080000 // Set BIT19 to 1 218 CPU_GEN = 0x100, // CPU Reset Register 219 LED1Cfg = 0x154,// LED1 Configuration Register 220 LED0Cfg = 0x155,// LED0 Configuration Register 221 222 AcmAvg = 0x170, // ACM Average Period Register 223 AcmHwCtrl = 0x171, // ACM Hardware Control Register 224 //---------------------------------------------------------------------------- 225 //// 226 //// 8190 AcmHwCtrl bits (offset 0x171, 1 byte) 227 ////---------------------------------------------------------------------------- 228 // 229 #define AcmHw_HwEn BIT(0) 230 #define AcmHw_BeqEn BIT(1) 231 #define AcmHw_ViqEn BIT(2) 232 #define AcmHw_VoqEn BIT(3) 233 #define AcmHw_BeqStatus BIT(4) 234 #define AcmHw_ViqStatus BIT(5) 235 #define AcmHw_VoqStatus BIT(6) 236 237 AcmFwCtrl = 0x172, // ACM Firmware Control Register 238 AES_11N_FIX = 0x173, 239 VOAdmTime = 0x174, // VO Queue Admitted Time Register 240 VIAdmTime = 0x178, // VI Queue Admitted Time Register 241 BEAdmTime = 0x17C, // BE Queue Admitted Time Register 242 RQPN1 = 0x180, // Reserved Queue Page Number , Vo Vi, Be, Bk 243 RQPN2 = 0x184, // Reserved Queue Page Number, HCCA, Cmd, Mgnt, High 244 RQPN3 = 0x188, // Reserved Queue Page Number, Bcn, Public, 245 // QPRR = 0x1E0, // Queue Page Report per TID 246 QPNR = 0x1D0, //0x1F0, // Queue Packet Number report per TID 247 BQDA = 0x200, // Beacon Queue Descriptor Address 248 HQDA = 0x204, // High Priority Queue Descriptor Address 249 CQDA = 0x208, // Command Queue Descriptor Address 250 MQDA = 0x20C, // Management Queue Descriptor Address 251 HCCAQDA = 0x210, // HCCA Queue Descriptor Address 252 VOQDA = 0x214, // VO Queue Descriptor Address 253 VIQDA = 0x218, // VI Queue Descriptor Address 254 BEQDA = 0x21C, // BE Queue Descriptor Address 255 BKQDA = 0x220, // BK Queue Descriptor Address 256 RCQDA = 0x224, // Receive command Queue Descriptor Address 257 RDQDA = 0x228, // Receive Queue Descriptor Start Address 258 259 MAR0 = 0x240, // Multicast filter. 260 MAR4 = 0x244, 261 262 CCX_PERIOD = 0x250, // CCX Measurement Period Register, in unit of TU. 263 CLM_RESULT = 0x251, // CCA Busy fraction register. 264 NHM_PERIOD = 0x252, // NHM Measurement Period register, in unit of TU. 265 266 NHM_THRESHOLD0 = 0x253, // Noise Histogram Meashorement0. 267 NHM_THRESHOLD1 = 0x254, // Noise Histogram Meashorement1. 268 NHM_THRESHOLD2 = 0x255, // Noise Histogram Meashorement2. 269 NHM_THRESHOLD3 = 0x256, // Noise Histogram Meashorement3. 270 NHM_THRESHOLD4 = 0x257, // Noise Histogram Meashorement4. 271 NHM_THRESHOLD5 = 0x258, // Noise Histogram Meashorement5. 272 NHM_THRESHOLD6 = 0x259, // Noise Histogram Meashorement6 273 274 MCTRL = 0x25A, // Measurement Control 275 276 NHM_RPI_COUNTER0 = 0x264, // Noise Histogram RPI counter0, the fraction of signal strength < NHM_THRESHOLD0. 277 NHM_RPI_COUNTER1 = 0x265, // Noise Histogram RPI counter1, the fraction of signal strength in (NHM_THRESHOLD0, NHM_THRESHOLD1]. 278 NHM_RPI_COUNTER2 = 0x266, // Noise Histogram RPI counter2, the fraction of signal strength in (NHM_THRESHOLD1, NHM_THRESHOLD2]. 279 NHM_RPI_COUNTER3 = 0x267, // Noise Histogram RPI counter3, the fraction of signal strength in (NHM_THRESHOLD2, NHM_THRESHOLD3]. 280 NHM_RPI_COUNTER4 = 0x268, // Noise Histogram RPI counter4, the fraction of signal strength in (NHM_THRESHOLD3, NHM_THRESHOLD4]. 281 NHM_RPI_COUNTER5 = 0x269, // Noise Histogram RPI counter5, the fraction of signal strength in (NHM_THRESHOLD4, NHM_THRESHOLD5]. 282 NHM_RPI_COUNTER6 = 0x26A, // Noise Histogram RPI counter6, the fraction of signal strength in (NHM_THRESHOLD5, NHM_THRESHOLD6]. 283 NHM_RPI_COUNTER7 = 0x26B, // Noise Histogram RPI counter7, the fraction of signal strength in (NHM_THRESHOLD6, NHM_THRESHOLD7]. 284 #define BW_OPMODE_11J BIT(0) 285 #define BW_OPMODE_5G BIT(1) 286 #define BW_OPMODE_20MHZ BIT(2) 287 BW_OPMODE = 0x300, // Bandwidth operation mode 288 MSR = 0x303, // Media Status register 289 #define MSR_LINK_MASK (BIT(0)|BIT(1)) 290 #define MSR_LINK_MANAGED 2 291 #define MSR_LINK_NONE 0 292 #define MSR_LINK_SHIFT 0 293 #define MSR_LINK_ADHOC 1 294 #define MSR_LINK_MASTER 3 295 #define MSR_LINK_ENEDCA BIT(4) 296 RETRY_LIMIT = 0x304, // Retry Limit [15:8]-short, [7:0]-long 297 #define RETRY_LIMIT_SHORT_SHIFT 8 298 #define RETRY_LIMIT_LONG_SHIFT 0 299 TSFR = 0x308, 300 RRSR = 0x310, // Response Rate Set 301 #define RRSR_RSC_OFFSET 21 302 #define RRSR_SHORT_OFFSET 23 303 #define RRSR_RSC_DUPLICATE 0x600000 304 #define RRSR_RSC_LOWSUBCHNL 0x400000 305 #define RRSR_RSC_UPSUBCHANL 0x200000 306 #define RRSR_SHORT 0x800000 307 #define RRSR_1M BIT(0) 308 #define RRSR_2M BIT(1) 309 #define RRSR_5_5M BIT(2) 310 #define RRSR_11M BIT(3) 311 #define RRSR_6M BIT(4) 312 #define RRSR_9M BIT(5) 313 #define RRSR_12M BIT(6) 314 #define RRSR_18M BIT(7) 315 #define RRSR_24M BIT(8) 316 #define RRSR_36M BIT(9) 317 #define RRSR_48M BIT(10) 318 #define RRSR_54M BIT(11) 319 #define RRSR_MCS0 BIT(12) 320 #define RRSR_MCS1 BIT(13) 321 #define RRSR_MCS2 BIT(14) 322 #define RRSR_MCS3 BIT(15) 323 #define RRSR_MCS4 BIT(16) 324 #define RRSR_MCS5 BIT(17) 325 #define RRSR_MCS6 BIT(18) 326 #define RRSR_MCS7 BIT(19) 327 #define BRSR_AckShortPmb BIT(23) // CCK ACK: use Short Preamble or not. 328 RATR0 = 0x320, // Rate Adaptive Table register1 329 UFWP = 0x318, 330 DRIVER_RSSI = 0x32c, // Driver tell Firmware current RSSI 331 //---------------------------------------------------------------------------- 332 // 8190 Rate Adaptive Table Register (offset 0x320, 4 byte) 333 //---------------------------------------------------------------------------- 334 //CCK 335 #define RATR_1M 0x00000001 336 #define RATR_2M 0x00000002 337 #define RATR_55M 0x00000004 338 #define RATR_11M 0x00000008 339 //OFDM 340 #define RATR_6M 0x00000010 341 #define RATR_9M 0x00000020 342 #define RATR_12M 0x00000040 343 #define RATR_18M 0x00000080 344 #define RATR_24M 0x00000100 345 #define RATR_36M 0x00000200 346 #define RATR_48M 0x00000400 347 #define RATR_54M 0x00000800 348 //MCS 1 Spatial Stream 349 #define RATR_MCS0 0x00001000 350 #define RATR_MCS1 0x00002000 351 #define RATR_MCS2 0x00004000 352 #define RATR_MCS3 0x00008000 353 #define RATR_MCS4 0x00010000 354 #define RATR_MCS5 0x00020000 355 #define RATR_MCS6 0x00040000 356 #define RATR_MCS7 0x00080000 357 //MCS 2 Spatial Stream 358 #define RATR_MCS8 0x00100000 359 #define RATR_MCS9 0x00200000 360 #define RATR_MCS10 0x00400000 361 #define RATR_MCS11 0x00800000 362 #define RATR_MCS12 0x01000000 363 #define RATR_MCS13 0x02000000 364 #define RATR_MCS14 0x04000000 365 #define RATR_MCS15 0x08000000 366 // ALL CCK Rate 367 #define RATE_ALL_CCK RATR_1M|RATR_2M|RATR_55M|RATR_11M 368 #define RATE_ALL_OFDM_AG RATR_6M|RATR_9M|RATR_12M|RATR_18M|RATR_24M\ 369 |RATR_36M|RATR_48M|RATR_54M 370 #define RATE_ALL_OFDM_1SS RATR_MCS0|RATR_MCS1|RATR_MCS2|RATR_MCS3 | \ 371 RATR_MCS4|RATR_MCS5|RATR_MCS6|RATR_MCS7 372 #define RATE_ALL_OFDM_2SS RATR_MCS8|RATR_MCS9 |RATR_MCS10|RATR_MCS11| \ 373 RATR_MCS12|RATR_MCS13|RATR_MCS14|RATR_MCS15 374 375 MCS_TXAGC = 0x340, // MCS AGC 376 CCK_TXAGC = 0x348, // CCK AGC 377 // ISR = 0x350, // Interrupt Status Register 378 // IMR = 0x354, // Interrupt Mask Register 379 // IMR_POLL = 0x360, 380 MacBlkCtrl = 0x403, // Mac block on/off control register 381 382 EPROM_CMD = 0xfe58, 383 #define Cmd9346CR_9356SEL BIT(4) 384 #define EPROM_CMD_RESERVED_MASK BIT(5) 385 #define EPROM_CMD_OPERATING_MODE_SHIFT 6 386 #define EPROM_CMD_OPERATING_MODE_MASK (BIT(7) | BIT(6)) 387 #define EPROM_CMD_CONFIG 0x3 388 #define EPROM_CMD_NORMAL 0 389 #define EPROM_CMD_LOAD 1 390 #define EPROM_CMD_PROGRAM 2 391 #define EPROM_CS_BIT BIT(3) 392 #define EPROM_CK_BIT BIT(2) 393 #define EPROM_W_BIT BIT(1) 394 #define EPROM_R_BIT BIT(0) 395 396 MAC0 = 0x000, 397 MAC1 = 0x001, 398 MAC2 = 0x002, 399 MAC3 = 0x003, 400 MAC4 = 0x004, 401 MAC5 = 0x005, 402 403 }; 404 //---------------------------------------------------------------------------- 405 // 818xB AnaParm & AnaParm2 Register 406 //---------------------------------------------------------------------------- 407 //#define ANAPARM_ASIC_ON 0x45090658 408 //#define ANAPARM2_ASIC_ON 0x727f3f52 409 #define GPI 0x108 410 #define GPO 0x109 411 #define GPE 0x10a 412 #endif 413
