1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4#include <dt-bindings/interrupt-controller/arm-gic.h>
5#include <dt-bindings/clock/qcom,gcc-msm8974.h>
6#include <dt-bindings/clock/qcom,mmcc-msm8974.h>
7#include <dt-bindings/clock/qcom,rpmcc.h>
8#include <dt-bindings/reset/qcom,gcc-msm8974.h>
9#include <dt-bindings/gpio/gpio.h>
10
11/ {
12	#address-cells = <1>;
13	#size-cells = <1>;
14	model = "Qualcomm MSM8974";
15	compatible = "qcom,msm8974";
16	interrupt-parent = <&intc>;
17
18	reserved-memory {
19		#address-cells = <1>;
20		#size-cells = <1>;
21		ranges;
22
23		mpss@8000000 {
24			reg = <0x08000000 0x5100000>;
25			no-map;
26		};
27
28		mba@d100000 {
29			reg = <0x0d100000 0x100000>;
30			no-map;
31		};
32
33		reserved@d200000 {
34			reg = <0x0d200000 0xa00000>;
35			no-map;
36		};
37
38		adsp_region: adsp@dc00000 {
39			reg = <0x0dc00000 0x1900000>;
40			no-map;
41		};
42
43		venus@f500000 {
44			reg = <0x0f500000 0x500000>;
45			no-map;
46		};
47
48		smem_region: smem@fa00000 {
49			reg = <0xfa00000 0x200000>;
50			no-map;
51		};
52
53		tz@fc00000 {
54			reg = <0x0fc00000 0x160000>;
55			no-map;
56		};
57
58		rfsa@fd60000 {
59			reg = <0x0fd60000 0x20000>;
60			no-map;
61		};
62
63		rmtfs@fd80000 {
64			reg = <0x0fd80000 0x180000>;
65			no-map;
66		};
67	};
68
69	cpus {
70		#address-cells = <1>;
71		#size-cells = <0>;
72		interrupts = <GIC_PPI 9 0xf04>;
73
74		CPU0: cpu@0 {
75			compatible = "qcom,krait";
76			enable-method = "qcom,kpss-acc-v2";
77			device_type = "cpu";
78			reg = <0>;
79			next-level-cache = <&L2>;
80			qcom,acc = <&acc0>;
81			qcom,saw = <&saw0>;
82			cpu-idle-states = <&CPU_SPC>;
83		};
84
85		CPU1: cpu@1 {
86			compatible = "qcom,krait";
87			enable-method = "qcom,kpss-acc-v2";
88			device_type = "cpu";
89			reg = <1>;
90			next-level-cache = <&L2>;
91			qcom,acc = <&acc1>;
92			qcom,saw = <&saw1>;
93			cpu-idle-states = <&CPU_SPC>;
94		};
95
96		CPU2: cpu@2 {
97			compatible = "qcom,krait";
98			enable-method = "qcom,kpss-acc-v2";
99			device_type = "cpu";
100			reg = <2>;
101			next-level-cache = <&L2>;
102			qcom,acc = <&acc2>;
103			qcom,saw = <&saw2>;
104			cpu-idle-states = <&CPU_SPC>;
105		};
106
107		CPU3: cpu@3 {
108			compatible = "qcom,krait";
109			enable-method = "qcom,kpss-acc-v2";
110			device_type = "cpu";
111			reg = <3>;
112			next-level-cache = <&L2>;
113			qcom,acc = <&acc3>;
114			qcom,saw = <&saw3>;
115			cpu-idle-states = <&CPU_SPC>;
116		};
117
118		L2: l2-cache {
119			compatible = "cache";
120			cache-level = <2>;
121			qcom,saw = <&saw_l2>;
122		};
123
124		idle-states {
125			CPU_SPC: spc {
126				compatible = "qcom,idle-state-spc",
127						"arm,idle-state";
128				entry-latency-us = <150>;
129				exit-latency-us = <200>;
130				min-residency-us = <2000>;
131			};
132		};
133	};
134
135	memory {
136		device_type = "memory";
137		reg = <0x0 0x0>;
138	};
139
140	thermal-zones {
141		cpu-thermal0 {
142			polling-delay-passive = <250>;
143			polling-delay = <1000>;
144
145			thermal-sensors = <&tsens 5>;
146
147			trips {
148				cpu_alert0: trip0 {
149					temperature = <75000>;
150					hysteresis = <2000>;
151					type = "passive";
152				};
153				cpu_crit0: trip1 {
154					temperature = <110000>;
155					hysteresis = <2000>;
156					type = "critical";
157				};
158			};
159		};
160
161		cpu-thermal1 {
162			polling-delay-passive = <250>;
163			polling-delay = <1000>;
164
165			thermal-sensors = <&tsens 6>;
166
167			trips {
168				cpu_alert1: trip0 {
169					temperature = <75000>;
170					hysteresis = <2000>;
171					type = "passive";
172				};
173				cpu_crit1: trip1 {
174					temperature = <110000>;
175					hysteresis = <2000>;
176					type = "critical";
177				};
178			};
179		};
180
181		cpu-thermal2 {
182			polling-delay-passive = <250>;
183			polling-delay = <1000>;
184
185			thermal-sensors = <&tsens 7>;
186
187			trips {
188				cpu_alert2: trip0 {
189					temperature = <75000>;
190					hysteresis = <2000>;
191					type = "passive";
192				};
193				cpu_crit2: trip1 {
194					temperature = <110000>;
195					hysteresis = <2000>;
196					type = "critical";
197				};
198			};
199		};
200
201		cpu-thermal3 {
202			polling-delay-passive = <250>;
203			polling-delay = <1000>;
204
205			thermal-sensors = <&tsens 8>;
206
207			trips {
208				cpu_alert3: trip0 {
209					temperature = <75000>;
210					hysteresis = <2000>;
211					type = "passive";
212				};
213				cpu_crit3: trip1 {
214					temperature = <110000>;
215					hysteresis = <2000>;
216					type = "critical";
217				};
218			};
219		};
220	};
221
222	cpu-pmu {
223		compatible = "qcom,krait-pmu";
224		interrupts = <GIC_PPI 7 0xf04>;
225	};
226
227	clocks {
228		xo_board: xo_board {
229			compatible = "fixed-clock";
230			#clock-cells = <0>;
231			clock-frequency = <19200000>;
232		};
233
234		sleep_clk: sleep_clk {
235			compatible = "fixed-clock";
236			#clock-cells = <0>;
237			clock-frequency = <32768>;
238		};
239	};
240
241	timer {
242		compatible = "arm,armv7-timer";
243		interrupts = <GIC_PPI 2 0xf08>,
244			     <GIC_PPI 3 0xf08>,
245			     <GIC_PPI 4 0xf08>,
246			     <GIC_PPI 1 0xf08>;
247		clock-frequency = <19200000>;
248	};
249
250	adsp-pil {
251		compatible = "qcom,msm8974-adsp-pil";
252
253		interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
254				      <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
255				      <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
256				      <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
257				      <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
258		interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
259
260		cx-supply = <&pm8841_s2>;
261
262		clocks = <&xo_board>;
263		clock-names = "xo";
264
265		memory-region = <&adsp_region>;
266
267		qcom,smem-states = <&adsp_smp2p_out 0>;
268		qcom,smem-state-names = "stop";
269	};
270
271	smem {
272		compatible = "qcom,smem";
273
274		memory-region = <&smem_region>;
275		qcom,rpm-msg-ram = <&rpm_msg_ram>;
276
277		hwlocks = <&tcsr_mutex 3>;
278	};
279
280	smp2p-adsp {
281		compatible = "qcom,smp2p";
282		qcom,smem = <443>, <429>;
283
284		interrupt-parent = <&intc>;
285		interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
286
287		qcom,ipc = <&apcs 8 10>;
288
289		qcom,local-pid = <0>;
290		qcom,remote-pid = <2>;
291
292		adsp_smp2p_out: master-kernel {
293			qcom,entry-name = "master-kernel";
294			#qcom,smem-state-cells = <1>;
295		};
296
297		adsp_smp2p_in: slave-kernel {
298			qcom,entry-name = "slave-kernel";
299
300			interrupt-controller;
301			#interrupt-cells = <2>;
302		};
303	};
304
305	smp2p-modem {
306		compatible = "qcom,smp2p";
307		qcom,smem = <435>, <428>;
308
309		interrupt-parent = <&intc>;
310		interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
311
312		qcom,ipc = <&apcs 8 14>;
313
314		qcom,local-pid = <0>;
315		qcom,remote-pid = <1>;
316
317		modem_smp2p_out: master-kernel {
318			qcom,entry-name = "master-kernel";
319			#qcom,smem-state-cells = <1>;
320		};
321
322		modem_smp2p_in: slave-kernel {
323			qcom,entry-name = "slave-kernel";
324
325			interrupt-controller;
326			#interrupt-cells = <2>;
327		};
328	};
329
330	smp2p-wcnss {
331		compatible = "qcom,smp2p";
332		qcom,smem = <451>, <431>;
333
334		interrupt-parent = <&intc>;
335		interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
336
337		qcom,ipc = <&apcs 8 18>;
338
339		qcom,local-pid = <0>;
340		qcom,remote-pid = <4>;
341
342		wcnss_smp2p_out: master-kernel {
343			qcom,entry-name = "master-kernel";
344
345			#qcom,smem-state-cells = <1>;
346		};
347
348		wcnss_smp2p_in: slave-kernel {
349			qcom,entry-name = "slave-kernel";
350
351			interrupt-controller;
352			#interrupt-cells = <2>;
353		};
354	};
355
356	smsm {
357		compatible = "qcom,smsm";
358
359		#address-cells = <1>;
360		#size-cells = <0>;
361
362		qcom,ipc-1 = <&apcs 8 13>;
363		qcom,ipc-2 = <&apcs 8 9>;
364		qcom,ipc-3 = <&apcs 8 19>;
365
366		apps_smsm: apps@0 {
367			reg = <0>;
368
369			#qcom,smem-state-cells = <1>;
370		};
371
372		modem_smsm: modem@1 {
373			reg = <1>;
374			interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
375
376			interrupt-controller;
377			#interrupt-cells = <2>;
378		};
379
380		adsp_smsm: adsp@2 {
381			reg = <2>;
382			interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
383
384			interrupt-controller;
385			#interrupt-cells = <2>;
386		};
387
388		wcnss_smsm: wcnss@7 {
389			reg = <7>;
390			interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
391
392			interrupt-controller;
393			#interrupt-cells = <2>;
394		};
395	};
396
397	firmware {
398		scm {
399			compatible = "qcom,scm";
400			clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
401			clock-names = "core", "bus", "iface";
402		};
403	};
404
405	soc: soc {
406		#address-cells = <1>;
407		#size-cells = <1>;
408		ranges;
409		compatible = "simple-bus";
410
411		intc: interrupt-controller@f9000000 {
412			compatible = "qcom,msm-qgic2";
413			interrupt-controller;
414			#interrupt-cells = <3>;
415			reg = <0xf9000000 0x1000>,
416			      <0xf9002000 0x1000>;
417		};
418
419		apcs: syscon@f9011000 {
420			compatible = "syscon";
421			reg = <0xf9011000 0x1000>;
422		};
423
424		qfprom: qfprom@fc4bc000 {
425			#address-cells = <1>;
426			#size-cells = <1>;
427			compatible = "qcom,qfprom";
428			reg = <0xfc4bc000 0x1000>;
429			tsens_calib: calib@d0 {
430				reg = <0xd0 0x18>;
431			};
432			tsens_backup: backup@440 {
433				reg = <0x440 0x10>;
434			};
435		};
436
437		tsens: thermal-sensor@fc4a9000 {
438			compatible = "qcom,msm8974-tsens";
439			reg = <0xfc4a9000 0x1000>, /* TM */
440			      <0xfc4a8000 0x1000>; /* SROT */
441			nvmem-cells = <&tsens_calib>, <&tsens_backup>;
442			nvmem-cell-names = "calib", "calib_backup";
443			#qcom,sensors = <11>;
444			#thermal-sensor-cells = <1>;
445		};
446
447		timer@f9020000 {
448			#address-cells = <1>;
449			#size-cells = <1>;
450			ranges;
451			compatible = "arm,armv7-timer-mem";
452			reg = <0xf9020000 0x1000>;
453			clock-frequency = <19200000>;
454
455			frame@f9021000 {
456				frame-number = <0>;
457				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
458					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
459				reg = <0xf9021000 0x1000>,
460				      <0xf9022000 0x1000>;
461			};
462
463			frame@f9023000 {
464				frame-number = <1>;
465				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
466				reg = <0xf9023000 0x1000>;
467				status = "disabled";
468			};
469
470			frame@f9024000 {
471				frame-number = <2>;
472				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
473				reg = <0xf9024000 0x1000>;
474				status = "disabled";
475			};
476
477			frame@f9025000 {
478				frame-number = <3>;
479				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
480				reg = <0xf9025000 0x1000>;
481				status = "disabled";
482			};
483
484			frame@f9026000 {
485				frame-number = <4>;
486				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
487				reg = <0xf9026000 0x1000>;
488				status = "disabled";
489			};
490
491			frame@f9027000 {
492				frame-number = <5>;
493				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
494				reg = <0xf9027000 0x1000>;
495				status = "disabled";
496			};
497
498			frame@f9028000 {
499				frame-number = <6>;
500				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
501				reg = <0xf9028000 0x1000>;
502				status = "disabled";
503			};
504		};
505
506		saw0: power-controller@f9089000 {
507			compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
508			reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
509		};
510
511		saw1: power-controller@f9099000 {
512			compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
513			reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
514		};
515
516		saw2: power-controller@f90a9000 {
517			compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
518			reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
519		};
520
521		saw3: power-controller@f90b9000 {
522			compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
523			reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
524		};
525
526		saw_l2: power-controller@f9012000 {
527			compatible = "qcom,saw2";
528			reg = <0xf9012000 0x1000>;
529			regulator;
530		};
531
532		acc0: clock-controller@f9088000 {
533			compatible = "qcom,kpss-acc-v2";
534			reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
535		};
536
537		acc1: clock-controller@f9098000 {
538			compatible = "qcom,kpss-acc-v2";
539			reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
540		};
541
542		acc2: clock-controller@f90a8000 {
543			compatible = "qcom,kpss-acc-v2";
544			reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
545		};
546
547		acc3: clock-controller@f90b8000 {
548			compatible = "qcom,kpss-acc-v2";
549			reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
550		};
551
552		restart@fc4ab000 {
553			compatible = "qcom,pshold";
554			reg = <0xfc4ab000 0x4>;
555		};
556
557		gcc: clock-controller@fc400000 {
558			compatible = "qcom,gcc-msm8974";
559			#clock-cells = <1>;
560			#reset-cells = <1>;
561			#power-domain-cells = <1>;
562			reg = <0xfc400000 0x4000>;
563		};
564
565		tcsr: syscon@fd4a0000 {
566			compatible = "syscon";
567			reg = <0xfd4a0000 0x10000>;
568		};
569
570		tcsr_mutex_block: syscon@fd484000 {
571			compatible = "syscon";
572			reg = <0xfd484000 0x2000>;
573		};
574
575		mmcc: clock-controller@fd8c0000 {
576			compatible = "qcom,mmcc-msm8974";
577			#clock-cells = <1>;
578			#reset-cells = <1>;
579			#power-domain-cells = <1>;
580			reg = <0xfd8c0000 0x6000>;
581		};
582
583		tcsr_mutex: tcsr-mutex {
584			compatible = "qcom,tcsr-mutex";
585			syscon = <&tcsr_mutex_block 0 0x80>;
586
587			#hwlock-cells = <1>;
588		};
589
590		rpm_msg_ram: memory@fc428000 {
591			compatible = "qcom,rpm-msg-ram";
592			reg = <0xfc428000 0x4000>;
593		};
594
595		blsp1_uart1: serial@f991d000 {
596			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
597			reg = <0xf991d000 0x1000>;
598			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
599			clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
600			clock-names = "core", "iface";
601			status = "disabled";
602		};
603
604		blsp1_uart2: serial@f991e000 {
605			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
606			reg = <0xf991e000 0x1000>;
607			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
608			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
609			clock-names = "core", "iface";
610			status = "disabled";
611		};
612
613		sdhci@f9824900 {
614			compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
615			reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
616			reg-names = "hc_mem", "core_mem";
617			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
618				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
619			interrupt-names = "hc_irq", "pwr_irq";
620			clocks = <&gcc GCC_SDCC1_APPS_CLK>,
621				 <&gcc GCC_SDCC1_AHB_CLK>,
622				 <&xo_board>;
623			clock-names = "core", "iface", "xo";
624			status = "disabled";
625		};
626
627		sdhci@f9864900 {
628			compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
629			reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
630			reg-names = "hc_mem", "core_mem";
631			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
632				     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
633			interrupt-names = "hc_irq", "pwr_irq";
634			clocks = <&gcc GCC_SDCC3_APPS_CLK>,
635				 <&gcc GCC_SDCC3_AHB_CLK>,
636				 <&xo_board>;
637			clock-names = "core", "iface", "xo";
638			status = "disabled";
639		};
640
641		sdhci@f98a4900 {
642			compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
643			reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
644			reg-names = "hc_mem", "core_mem";
645			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
646				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
647			interrupt-names = "hc_irq", "pwr_irq";
648			clocks = <&gcc GCC_SDCC2_APPS_CLK>,
649				 <&gcc GCC_SDCC2_AHB_CLK>,
650				 <&xo_board>;
651			clock-names = "core", "iface", "xo";
652			status = "disabled";
653		};
654
655		otg: usb@f9a55000 {
656			compatible = "qcom,ci-hdrc";
657			reg = <0xf9a55000 0x200>,
658			      <0xf9a55200 0x200>;
659			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
660			clocks = <&gcc GCC_USB_HS_AHB_CLK>,
661				 <&gcc GCC_USB_HS_SYSTEM_CLK>;
662			clock-names = "iface", "core";
663			assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
664			assigned-clock-rates = <75000000>;
665			resets = <&gcc GCC_USB_HS_BCR>;
666			reset-names = "core";
667			phy_type = "ulpi";
668			dr_mode = "otg";
669			ahb-burst-config = <0>;
670			phy-names = "usb-phy";
671			status = "disabled";
672			#reset-cells = <1>;
673
674			ulpi {
675				usb_hs1_phy: phy@a {
676					compatible = "qcom,usb-hs-phy-msm8974",
677						     "qcom,usb-hs-phy";
678					#phy-cells = <0>;
679					clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
680					clock-names = "ref", "sleep";
681					resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>;
682					reset-names = "phy", "por";
683					status = "disabled";
684				};
685
686				usb_hs2_phy: phy@b {
687					compatible = "qcom,usb-hs-phy-msm8974",
688						     "qcom,usb-hs-phy";
689					#phy-cells = <0>;
690					clocks = <&xo_board>, <&gcc GCC_USB2B_PHY_SLEEP_CLK>;
691					clock-names = "ref", "sleep";
692					resets = <&gcc GCC_USB2B_PHY_BCR>, <&otg 1>;
693					reset-names = "phy", "por";
694					status = "disabled";
695				};
696			};
697		};
698
699		rng@f9bff000 {
700			compatible = "qcom,prng";
701			reg = <0xf9bff000 0x200>;
702			clocks = <&gcc GCC_PRNG_AHB_CLK>;
703			clock-names = "core";
704		};
705
706		msmgpio: pinctrl@fd510000 {
707			compatible = "qcom,msm8974-pinctrl";
708			reg = <0xfd510000 0x4000>;
709			gpio-controller;
710			#gpio-cells = <2>;
711			interrupt-controller;
712			#interrupt-cells = <2>;
713			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
714		};
715
716		i2c@f9923000 {
717			status = "disabled";
718			compatible = "qcom,i2c-qup-v2.1.1";
719			reg = <0xf9923000 0x1000>;
720			interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
721			clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
722			clock-names = "core", "iface";
723			#address-cells = <1>;
724			#size-cells = <0>;
725		};
726
727		i2c@f9924000 {
728			status = "disabled";
729			compatible = "qcom,i2c-qup-v2.1.1";
730			reg = <0xf9924000 0x1000>;
731			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
732			clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
733			clock-names = "core", "iface";
734			#address-cells = <1>;
735			#size-cells = <0>;
736		};
737
738		blsp_i2c3: i2c@f9925000 {
739			status = "disabled";
740			compatible = "qcom,i2c-qup-v2.1.1";
741			reg = <0xf9925000 0x1000>;
742			interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
743			clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
744			clock-names = "core", "iface";
745			#address-cells = <1>;
746			#size-cells = <0>;
747		};
748
749		blsp_i2c8: i2c@f9964000 {
750			status = "disabled";
751			compatible = "qcom,i2c-qup-v2.1.1";
752			reg = <0xf9964000 0x1000>;
753			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
754			clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
755			clock-names = "core", "iface";
756			#address-cells = <1>;
757			#size-cells = <0>;
758		};
759
760		blsp_i2c11: i2c@f9967000 {
761			status = "disabled";
762			compatible = "qcom,i2c-qup-v2.1.1";
763			reg = <0xf9967000 0x1000>;
764			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
765			clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
766			clock-names = "core", "iface";
767			#address-cells = <1>;
768			#size-cells = <0>;
769			dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
770			dma-names = "tx", "rx";
771		};
772
773		blsp_i2c12: i2c@f9968000 {
774			status = "disabled";
775			compatible = "qcom,i2c-qup-v2.1.1";
776			reg = <0xf9968000 0x1000>;
777			interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
778			clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
779			clock-names = "core", "iface";
780			#address-cells = <1>;
781			#size-cells = <0>;
782		};
783
784		spmi_bus: spmi@fc4cf000 {
785			compatible = "qcom,spmi-pmic-arb";
786			reg-names = "core", "intr", "cnfg";
787			reg = <0xfc4cf000 0x1000>,
788			      <0xfc4cb000 0x1000>,
789			      <0xfc4ca000 0x1000>;
790			interrupt-names = "periph_irq";
791			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
792			qcom,ee = <0>;
793			qcom,channel = <0>;
794			#address-cells = <2>;
795			#size-cells = <0>;
796			interrupt-controller;
797			#interrupt-cells = <4>;
798		};
799
800		blsp2_dma: dma-controller@f9944000 {
801			compatible = "qcom,bam-v1.4.0";
802			reg = <0xf9944000 0x19000>;
803			interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
804			clocks = <&gcc GCC_BLSP2_AHB_CLK>;
805			clock-names = "bam_clk";
806			#dma-cells = <1>;
807			qcom,ee = <0>;
808		};
809
810		etr@fc322000 {
811			compatible = "arm,coresight-tmc", "arm,primecell";
812			reg = <0xfc322000 0x1000>;
813
814			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
815			clock-names = "apb_pclk", "atclk";
816
817			in-ports {
818				port {
819					etr_in: endpoint {
820						remote-endpoint = <&replicator_out0>;
821					};
822				};
823			};
824		};
825
826		tpiu@fc318000 {
827			compatible = "arm,coresight-tpiu", "arm,primecell";
828			reg = <0xfc318000 0x1000>;
829
830			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
831			clock-names = "apb_pclk", "atclk";
832
833			in-ports {
834				port {
835					tpiu_in: endpoint {
836						remote-endpoint = <&replicator_out1>;
837					};
838				 };
839			};
840		};
841
842		replicator@fc31c000 {
843			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
844			reg = <0xfc31c000 0x1000>;
845
846			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
847			clock-names = "apb_pclk", "atclk";
848
849			out-ports {
850				#address-cells = <1>;
851				#size-cells = <0>;
852
853				port@0 {
854					reg = <0>;
855					replicator_out0: endpoint {
856						remote-endpoint = <&etr_in>;
857					};
858				};
859				port@1 {
860					reg = <1>;
861					replicator_out1: endpoint {
862						remote-endpoint = <&tpiu_in>;
863					};
864				};
865			};
866
867			in-ports {
868				port {
869					replicator_in: endpoint {
870						remote-endpoint = <&etf_out>;
871					};
872				};
873			};
874		};
875
876		etf@fc307000 {
877			compatible = "arm,coresight-tmc", "arm,primecell";
878			reg = <0xfc307000 0x1000>;
879
880			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
881			clock-names = "apb_pclk", "atclk";
882
883			out-ports {
884				port {
885					etf_out: endpoint {
886						remote-endpoint = <&replicator_in>;
887					};
888				};
889			};
890
891			in-ports {
892				port {
893					etf_in: endpoint {
894						remote-endpoint = <&merger_out>;
895					};
896				};
897			};
898		};
899
900		funnel@fc31b000 {
901			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
902			reg = <0xfc31b000 0x1000>;
903
904			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
905			clock-names = "apb_pclk", "atclk";
906
907			in-ports {
908				#address-cells = <1>;
909				#size-cells = <0>;
910
911				/*
912				 * Not described input ports:
913				 * 0 - connected trought funnel to Audio, Modem and
914				 *     Resource and Power Manager CPU's
915				 * 2...7 - not-connected
916				 */
917				port@1 {
918					reg = <1>;
919					merger_in1: endpoint {
920						remote-endpoint = <&funnel1_out>;
921					};
922				};
923			};
924
925			out-ports {
926				port {
927					merger_out: endpoint {
928						remote-endpoint = <&etf_in>;
929					};
930				};
931			};
932		};
933
934		funnel@fc31a000 {
935			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
936			reg = <0xfc31a000 0x1000>;
937
938			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
939			clock-names = "apb_pclk", "atclk";
940
941			in-ports {
942				#address-cells = <1>;
943				#size-cells = <0>;
944
945				/*
946				 * Not described input ports:
947				 * 0 - not-connected
948				 * 1 - connected trought funnel to Multimedia CPU
949				 * 2 - connected to Wireless CPU
950				 * 3 - not-connected
951				 * 4 - not-connected
952				 * 6 - not-connected
953				 * 7 - connected to STM
954				 */
955				port@5 {
956					reg = <5>;
957					funnel1_in5: endpoint {
958						remote-endpoint = <&kpss_out>;
959					};
960				};
961			};
962
963			out-ports {
964				port {
965					funnel1_out: endpoint {
966						remote-endpoint = <&merger_in1>;
967					};
968				};
969			};
970		};
971
972		funnel@fc345000 { /* KPSS funnel only 4 inputs are used */
973			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
974			reg = <0xfc345000 0x1000>;
975
976			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
977			clock-names = "apb_pclk", "atclk";
978
979			in-ports {
980				#address-cells = <1>;
981				#size-cells = <0>;
982
983				port@0 {
984					reg = <0>;
985					kpss_in0: endpoint {
986						remote-endpoint = <&etm0_out>;
987					};
988				};
989				port@1 {
990					reg = <1>;
991					kpss_in1: endpoint {
992						remote-endpoint = <&etm1_out>;
993					};
994				};
995				port@2 {
996					reg = <2>;
997					kpss_in2: endpoint {
998						remote-endpoint = <&etm2_out>;
999					};
1000				};
1001				port@3 {
1002					reg = <3>;
1003					kpss_in3: endpoint {
1004						remote-endpoint = <&etm3_out>;
1005					};
1006				};
1007			};
1008
1009			out-ports {
1010				port {
1011					kpss_out: endpoint {
1012						remote-endpoint = <&funnel1_in5>;
1013					};
1014				};
1015			};
1016		};
1017
1018		etm@fc33c000 {
1019			compatible = "arm,coresight-etm4x", "arm,primecell";
1020			reg = <0xfc33c000 0x1000>;
1021
1022			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1023			clock-names = "apb_pclk", "atclk";
1024
1025			cpu = <&CPU0>;
1026
1027			out-ports {
1028				port {
1029					etm0_out: endpoint {
1030						remote-endpoint = <&kpss_in0>;
1031					};
1032				};
1033			};
1034		};
1035
1036		etm@fc33d000 {
1037			compatible = "arm,coresight-etm4x", "arm,primecell";
1038			reg = <0xfc33d000 0x1000>;
1039
1040			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1041			clock-names = "apb_pclk", "atclk";
1042
1043			cpu = <&CPU1>;
1044
1045			out-ports {
1046				port {
1047					etm1_out: endpoint {
1048						remote-endpoint = <&kpss_in1>;
1049					};
1050				};
1051			};
1052		};
1053
1054		etm@fc33e000 {
1055			compatible = "arm,coresight-etm4x", "arm,primecell";
1056			reg = <0xfc33e000 0x1000>;
1057
1058			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1059			clock-names = "apb_pclk", "atclk";
1060
1061			cpu = <&CPU2>;
1062
1063			out-ports {
1064				port {
1065					etm2_out: endpoint {
1066						remote-endpoint = <&kpss_in2>;
1067					};
1068				};
1069			};
1070		};
1071
1072		etm@fc33f000 {
1073			compatible = "arm,coresight-etm4x", "arm,primecell";
1074			reg = <0xfc33f000 0x1000>;
1075
1076			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1077			clock-names = "apb_pclk", "atclk";
1078
1079			cpu = <&CPU3>;
1080
1081			out-ports {
1082				port {
1083					etm3_out: endpoint {
1084						remote-endpoint = <&kpss_in3>;
1085					};
1086				};
1087			};
1088		};
1089
1090		mdss: mdss@fd900000 {
1091			status = "disabled";
1092
1093			compatible = "qcom,mdss";
1094			reg = <0xfd900000 0x100>,
1095			      <0xfd924000 0x1000>;
1096			reg-names = "mdss_phys",
1097			            "vbif_phys";
1098
1099			power-domains = <&mmcc MDSS_GDSC>;
1100
1101			clocks = <&mmcc MDSS_AHB_CLK>,
1102			         <&mmcc MDSS_AXI_CLK>,
1103			         <&mmcc MDSS_VSYNC_CLK>;
1104			clock-names = "iface",
1105			              "bus",
1106			              "vsync";
1107
1108			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1109
1110			interrupt-controller;
1111			#interrupt-cells = <1>;
1112
1113			#address-cells = <1>;
1114			#size-cells = <1>;
1115			ranges;
1116
1117			mdp: mdp@fd900000 {
1118				status = "disabled";
1119
1120				compatible = "qcom,mdp5";
1121				reg = <0xfd900100 0x22000>;
1122				reg-names = "mdp_phys";
1123
1124				interrupt-parent = <&mdss>;
1125				interrupts = <0 0>;
1126
1127				clocks = <&mmcc MDSS_AHB_CLK>,
1128					 <&mmcc MDSS_AXI_CLK>,
1129					 <&mmcc MDSS_MDP_CLK>,
1130					 <&mmcc MDSS_VSYNC_CLK>;
1131				clock-names = "iface",
1132				              "bus",
1133				              "core",
1134				              "vsync";
1135
1136				ports {
1137					#address-cells = <1>;
1138					#size-cells = <0>;
1139
1140					port@0 {
1141						reg = <0>;
1142						mdp5_intf1_out: endpoint {
1143							remote-endpoint = <&dsi0_in>;
1144						};
1145					};
1146				};
1147			};
1148
1149			dsi0: dsi@fd922800 {
1150				status = "disabled";
1151
1152				compatible = "qcom,mdss-dsi-ctrl";
1153				reg = <0xfd922800 0x1f8>;
1154				reg-names = "dsi_ctrl";
1155
1156				interrupt-parent = <&mdss>;
1157				interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
1158
1159				assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
1160				                  <&mmcc PCLK0_CLK_SRC>;
1161				assigned-clock-parents = <&dsi_phy0 0>,
1162				                         <&dsi_phy0 1>;
1163
1164				clocks = <&mmcc MDSS_MDP_CLK>,
1165				         <&mmcc MDSS_AHB_CLK>,
1166				         <&mmcc MDSS_AXI_CLK>,
1167				         <&mmcc MDSS_BYTE0_CLK>,
1168				         <&mmcc MDSS_PCLK0_CLK>,
1169				         <&mmcc MDSS_ESC0_CLK>,
1170				         <&mmcc MMSS_MISC_AHB_CLK>;
1171				clock-names = "mdp_core",
1172				              "iface",
1173				              "bus",
1174				              "byte",
1175				              "pixel",
1176				              "core",
1177				              "core_mmss";
1178
1179				phys = <&dsi_phy0>;
1180				phy-names = "dsi-phy";
1181
1182				ports {
1183					#address-cells = <1>;
1184					#size-cells = <0>;
1185
1186					port@0 {
1187						reg = <0>;
1188						dsi0_in: endpoint {
1189							remote-endpoint = <&mdp5_intf1_out>;
1190						};
1191					};
1192
1193					port@1 {
1194						reg = <1>;
1195						dsi0_out: endpoint {
1196						};
1197					};
1198				};
1199			};
1200
1201			dsi_phy0: dsi-phy@fd922a00 {
1202				status = "disabled";
1203
1204				compatible = "qcom,dsi-phy-28nm-hpm";
1205				reg = <0xfd922a00 0xd4>,
1206				      <0xfd922b00 0x280>,
1207				      <0xfd922d80 0x30>;
1208				reg-names = "dsi_pll",
1209				            "dsi_phy",
1210				            "dsi_phy_regulator";
1211
1212				#clock-cells = <1>;
1213				#phy-cells = <0>;
1214				qcom,dsi-phy-index = <0>;
1215
1216				clocks = <&mmcc MDSS_AHB_CLK>;
1217				clock-names = "iface";
1218			};
1219		};
1220	};
1221
1222	smd {
1223		compatible = "qcom,smd";
1224
1225		adsp {
1226			interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
1227
1228			qcom,ipc = <&apcs 8 8>;
1229			qcom,smd-edge = <1>;
1230		};
1231
1232		modem {
1233			interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
1234
1235			qcom,ipc = <&apcs 8 12>;
1236			qcom,smd-edge = <0>;
1237		};
1238
1239		rpm {
1240			interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
1241			qcom,ipc = <&apcs 8 0>;
1242			qcom,smd-edge = <15>;
1243
1244			rpm_requests {
1245				compatible = "qcom,rpm-msm8974";
1246				qcom,smd-channels = "rpm_requests";
1247
1248				rpmcc: clock-controller {
1249					compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc";
1250					#clock-cells = <1>;
1251				};
1252
1253				pm8841-regulators {
1254					compatible = "qcom,rpm-pm8841-regulators";
1255
1256					pm8841_s1: s1 {};
1257					pm8841_s2: s2 {};
1258					pm8841_s3: s3 {};
1259					pm8841_s4: s4 {};
1260					pm8841_s5: s5 {};
1261					pm8841_s6: s6 {};
1262					pm8841_s7: s7 {};
1263					pm8841_s8: s8 {};
1264				};
1265
1266				pm8941-regulators {
1267					compatible = "qcom,rpm-pm8941-regulators";
1268
1269					pm8941_s1: s1 {};
1270					pm8941_s2: s2 {};
1271					pm8941_s3: s3 {};
1272
1273					pm8941_l1: l1 {};
1274					pm8941_l2: l2 {};
1275					pm8941_l3: l3 {};
1276					pm8941_l4: l4 {};
1277					pm8941_l5: l5 {};
1278					pm8941_l6: l6 {};
1279					pm8941_l7: l7 {};
1280					pm8941_l8: l8 {};
1281					pm8941_l9: l9 {};
1282					pm8941_l10: l10 {};
1283					pm8941_l11: l11 {};
1284					pm8941_l12: l12 {};
1285					pm8941_l13: l13 {};
1286					pm8941_l14: l14 {};
1287					pm8941_l15: l15 {};
1288					pm8941_l16: l16 {};
1289					pm8941_l17: l17 {};
1290					pm8941_l18: l18 {};
1291					pm8941_l19: l19 {};
1292					pm8941_l20: l20 {};
1293					pm8941_l21: l21 {};
1294					pm8941_l22: l22 {};
1295					pm8941_l23: l23 {};
1296					pm8941_l24: l24 {};
1297
1298					pm8941_lvs1: lvs1 {};
1299					pm8941_lvs2: lvs2 {};
1300					pm8941_lvs3: lvs3 {};
1301				};
1302			};
1303		};
1304	};
1305
1306	vreg_boost: vreg-boost {
1307		compatible = "regulator-fixed";
1308
1309		regulator-name = "vreg-boost";
1310		regulator-min-microvolt = <3150000>;
1311		regulator-max-microvolt = <3150000>;
1312
1313		regulator-always-on;
1314		regulator-boot-on;
1315
1316		gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>;
1317		enable-active-high;
1318
1319		pinctrl-names = "default";
1320		pinctrl-0 = <&boost_bypass_n_pin>;
1321	};
1322	vreg_vph_pwr: vreg-vph-pwr {
1323		compatible = "regulator-fixed";
1324		regulator-name = "vph-pwr";
1325
1326		regulator-min-microvolt = <3600000>;
1327		regulator-max-microvolt = <3600000>;
1328
1329		regulator-always-on;
1330	};
1331};
1332