1/* 2 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 and 6 * only version 2 as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14/dts-v1/; 15 16#include "skeleton.dtsi" 17#include <dt-bindings/clock/qcom,gcc-ipq4019.h> 18#include <dt-bindings/interrupt-controller/arm-gic.h> 19#include <dt-bindings/interrupt-controller/irq.h> 20 21/ { 22 model = "Qualcomm Technologies, Inc. IPQ4019"; 23 compatible = "qcom,ipq4019"; 24 interrupt-parent = <&intc>; 25 26 reserved-memory { 27 #address-cells = <0x1>; 28 #size-cells = <0x1>; 29 ranges; 30 31 smem_region: smem@87e00000 { 32 reg = <0x87e00000 0x080000>; 33 no-map; 34 }; 35 36 tz@87e80000 { 37 reg = <0x87e80000 0x180000>; 38 no-map; 39 }; 40 }; 41 42 aliases { 43 spi0 = &blsp1_spi1; 44 spi1 = &blsp1_spi2; 45 i2c0 = &blsp1_i2c3; 46 i2c1 = &blsp1_i2c4; 47 }; 48 49 cpus { 50 #address-cells = <1>; 51 #size-cells = <0>; 52 cpu@0 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a7"; 55 enable-method = "qcom,kpss-acc-v1"; 56 qcom,acc = <&acc0>; 57 qcom,saw = <&saw0>; 58 reg = <0x0>; 59 clocks = <&gcc GCC_APPS_CLK_SRC>; 60 clock-frequency = <0>; 61 operating-points = < 62 /* kHz uV (fixed) */ 63 48000 1100000 64 200000 1100000 65 500000 1100000 66 716000 1100000 67 >; 68 clock-latency = <256000>; 69 }; 70 71 cpu@1 { 72 device_type = "cpu"; 73 compatible = "arm,cortex-a7"; 74 enable-method = "qcom,kpss-acc-v1"; 75 qcom,acc = <&acc1>; 76 qcom,saw = <&saw1>; 77 reg = <0x1>; 78 clocks = <&gcc GCC_APPS_CLK_SRC>; 79 clock-frequency = <0>; 80 operating-points = < 81 /* kHz uV (fixed) */ 82 48000 1100000 83 200000 1100000 84 500000 1100000 85 666000 1100000 86 >; 87 clock-latency = <256000>; 88 }; 89 90 cpu@2 { 91 device_type = "cpu"; 92 compatible = "arm,cortex-a7"; 93 enable-method = "qcom,kpss-acc-v1"; 94 qcom,acc = <&acc2>; 95 qcom,saw = <&saw2>; 96 reg = <0x2>; 97 clocks = <&gcc GCC_APPS_CLK_SRC>; 98 clock-frequency = <0>; 99 operating-points = < 100 /* kHz uV (fixed) */ 101 48000 1100000 102 200000 1100000 103 500000 1100000 104 666000 1100000 105 >; 106 clock-latency = <256000>; 107 }; 108 109 cpu@3 { 110 device_type = "cpu"; 111 compatible = "arm,cortex-a7"; 112 enable-method = "qcom,kpss-acc-v1"; 113 qcom,acc = <&acc3>; 114 qcom,saw = <&saw3>; 115 reg = <0x3>; 116 clocks = <&gcc GCC_APPS_CLK_SRC>; 117 clock-frequency = <0>; 118 operating-points = < 119 /* kHz uV (fixed) */ 120 48000 1100000 121 200000 1100000 122 500000 1100000 123 666000 1100000 124 >; 125 clock-latency = <256000>; 126 }; 127 }; 128 129 pmu { 130 compatible = "arm,cortex-a7-pmu"; 131 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | 132 IRQ_TYPE_LEVEL_HIGH)>; 133 }; 134 135 clocks { 136 sleep_clk: sleep_clk { 137 compatible = "fixed-clock"; 138 clock-frequency = <32768>; 139 #clock-cells = <0>; 140 }; 141 142 xo: xo { 143 compatible = "fixed-clock"; 144 clock-frequency = <48000000>; 145 #clock-cells = <0>; 146 }; 147 }; 148 149 firmware { 150 scm { 151 compatible = "qcom,scm-ipq4019"; 152 }; 153 }; 154 155 timer { 156 compatible = "arm,armv7-timer"; 157 interrupts = <1 2 0xf08>, 158 <1 3 0xf08>, 159 <1 4 0xf08>, 160 <1 1 0xf08>; 161 clock-frequency = <48000000>; 162 }; 163 164 soc { 165 #address-cells = <1>; 166 #size-cells = <1>; 167 ranges; 168 compatible = "simple-bus"; 169 170 intc: interrupt-controller@b000000 { 171 compatible = "qcom,msm-qgic2"; 172 interrupt-controller; 173 #interrupt-cells = <3>; 174 reg = <0x0b000000 0x1000>, 175 <0x0b002000 0x1000>; 176 }; 177 178 gcc: clock-controller@1800000 { 179 compatible = "qcom,gcc-ipq4019"; 180 #clock-cells = <1>; 181 #reset-cells = <1>; 182 reg = <0x1800000 0x60000>; 183 }; 184 185 rng@22000 { 186 compatible = "qcom,prng"; 187 reg = <0x22000 0x140>; 188 clocks = <&gcc GCC_PRNG_AHB_CLK>; 189 clock-names = "core"; 190 status = "disabled"; 191 }; 192 193 tlmm: pinctrl@1000000 { 194 compatible = "qcom,ipq4019-pinctrl"; 195 reg = <0x01000000 0x300000>; 196 gpio-controller; 197 #gpio-cells = <2>; 198 interrupt-controller; 199 #interrupt-cells = <2>; 200 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 201 }; 202 203 blsp_dma: dma@7884000 { 204 compatible = "qcom,bam-v1.7.0"; 205 reg = <0x07884000 0x23000>; 206 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 207 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 208 clock-names = "bam_clk"; 209 #dma-cells = <1>; 210 qcom,ee = <0>; 211 status = "disabled"; 212 }; 213 214 blsp1_spi1: spi@78b5000 { /* BLSP1 QUP1 */ 215 compatible = "qcom,spi-qup-v2.2.1"; 216 reg = <0x78b5000 0x600>; 217 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 218 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 219 <&gcc GCC_BLSP1_AHB_CLK>; 220 clock-names = "core", "iface"; 221 #address-cells = <1>; 222 #size-cells = <0>; 223 dmas = <&blsp_dma 5>, <&blsp_dma 4>; 224 dma-names = "rx", "tx"; 225 status = "disabled"; 226 }; 227 228 blsp1_spi2: spi@78b6000 { /* BLSP1 QUP2 */ 229 compatible = "qcom,spi-qup-v2.2.1"; 230 reg = <0x78b6000 0x600>; 231 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 232 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 233 <&gcc GCC_BLSP1_AHB_CLK>; 234 clock-names = "core", "iface"; 235 #address-cells = <1>; 236 #size-cells = <0>; 237 dmas = <&blsp_dma 7>, <&blsp_dma 6>; 238 dma-names = "rx", "tx"; 239 status = "disabled"; 240 }; 241 242 blsp1_i2c3: i2c@78b7000 { /* BLSP1 QUP3 */ 243 compatible = "qcom,i2c-qup-v2.2.1"; 244 reg = <0x78b7000 0x600>; 245 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 246 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 247 <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; 248 clock-names = "iface", "core"; 249 #address-cells = <1>; 250 #size-cells = <0>; 251 dmas = <&blsp_dma 9>, <&blsp_dma 8>; 252 dma-names = "rx", "tx"; 253 status = "disabled"; 254 }; 255 256 blsp1_i2c4: i2c@78b8000 { /* BLSP1 QUP4 */ 257 compatible = "qcom,i2c-qup-v2.2.1"; 258 reg = <0x78b8000 0x600>; 259 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 260 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 261 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; 262 clock-names = "iface", "core"; 263 #address-cells = <1>; 264 #size-cells = <0>; 265 dmas = <&blsp_dma 11>, <&blsp_dma 10>; 266 dma-names = "rx", "tx"; 267 status = "disabled"; 268 }; 269 270 cryptobam: dma@8e04000 { 271 compatible = "qcom,bam-v1.7.0"; 272 reg = <0x08e04000 0x20000>; 273 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 274 clocks = <&gcc GCC_CRYPTO_AHB_CLK>; 275 clock-names = "bam_clk"; 276 #dma-cells = <1>; 277 qcom,ee = <1>; 278 qcom,controlled-remotely; 279 status = "disabled"; 280 }; 281 282 crypto@8e3a000 { 283 compatible = "qcom,crypto-v5.1"; 284 reg = <0x08e3a000 0x6000>; 285 clocks = <&gcc GCC_CRYPTO_AHB_CLK>, 286 <&gcc GCC_CRYPTO_AXI_CLK>, 287 <&gcc GCC_CRYPTO_CLK>; 288 clock-names = "iface", "bus", "core"; 289 dmas = <&cryptobam 2>, <&cryptobam 3>; 290 dma-names = "rx", "tx"; 291 status = "disabled"; 292 }; 293 294 acc0: clock-controller@b088000 { 295 compatible = "qcom,kpss-acc-v1"; 296 reg = <0x0b088000 0x1000>, <0xb008000 0x1000>; 297 }; 298 299 acc1: clock-controller@b098000 { 300 compatible = "qcom,kpss-acc-v1"; 301 reg = <0x0b098000 0x1000>, <0xb008000 0x1000>; 302 }; 303 304 acc2: clock-controller@b0a8000 { 305 compatible = "qcom,kpss-acc-v1"; 306 reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>; 307 }; 308 309 acc3: clock-controller@b0b8000 { 310 compatible = "qcom,kpss-acc-v1"; 311 reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>; 312 }; 313 314 saw0: regulator@b089000 { 315 compatible = "qcom,saw2"; 316 reg = <0x02089000 0x1000>, <0x0b009000 0x1000>; 317 regulator; 318 }; 319 320 saw1: regulator@b099000 { 321 compatible = "qcom,saw2"; 322 reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>; 323 regulator; 324 }; 325 326 saw2: regulator@b0a9000 { 327 compatible = "qcom,saw2"; 328 reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>; 329 regulator; 330 }; 331 332 saw3: regulator@b0b9000 { 333 compatible = "qcom,saw2"; 334 reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>; 335 regulator; 336 }; 337 338 blsp1_uart1: serial@78af000 { 339 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 340 reg = <0x78af000 0x200>; 341 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 342 status = "disabled"; 343 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 344 <&gcc GCC_BLSP1_AHB_CLK>; 345 clock-names = "core", "iface"; 346 dmas = <&blsp_dma 1>, <&blsp_dma 0>; 347 dma-names = "rx", "tx"; 348 }; 349 350 blsp1_uart2: serial@78b0000 { 351 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 352 reg = <0x78b0000 0x200>; 353 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 354 status = "disabled"; 355 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 356 <&gcc GCC_BLSP1_AHB_CLK>; 357 clock-names = "core", "iface"; 358 dmas = <&blsp_dma 3>, <&blsp_dma 2>; 359 dma-names = "rx", "tx"; 360 }; 361 362 watchdog@b017000 { 363 compatible = "qcom,kpss-wdt", "qcom,kpss-wdt-ipq4019"; 364 reg = <0xb017000 0x40>; 365 clocks = <&sleep_clk>; 366 timeout-sec = <10>; 367 status = "disabled"; 368 }; 369 370 restart@4ab000 { 371 compatible = "qcom,pshold"; 372 reg = <0x4ab000 0x4>; 373 }; 374 375 pcie0: pci@40000000 { 376 compatible = "qcom,pcie-ipq4019", "snps,dw-pcie"; 377 reg = <0x40000000 0xf1d 378 0x40000f20 0xa8 379 0x80000 0x2000 380 0x40100000 0x1000>; 381 reg-names = "dbi", "elbi", "parf", "config"; 382 device_type = "pci"; 383 linux,pci-domain = <0>; 384 bus-range = <0x00 0xff>; 385 num-lanes = <1>; 386 #address-cells = <3>; 387 #size-cells = <2>; 388 389 ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000 390 0x82000000 0 0x48000000 0x48000000 0 0x10000000>; 391 392 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>; 393 interrupt-names = "msi"; 394 #interrupt-cells = <1>; 395 interrupt-map-mask = <0 0 0 0x7>; 396 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 397 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 398 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 399 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 400 clocks = <&gcc GCC_PCIE_AHB_CLK>, 401 <&gcc GCC_PCIE_AXI_M_CLK>, 402 <&gcc GCC_PCIE_AXI_S_CLK>; 403 clock-names = "aux", 404 "master_bus", 405 "slave_bus"; 406 407 resets = <&gcc PCIE_AXI_M_ARES>, 408 <&gcc PCIE_AXI_S_ARES>, 409 <&gcc PCIE_PIPE_ARES>, 410 <&gcc PCIE_AXI_M_VMIDMT_ARES>, 411 <&gcc PCIE_AXI_S_XPU_ARES>, 412 <&gcc PCIE_PARF_XPU_ARES>, 413 <&gcc PCIE_PHY_ARES>, 414 <&gcc PCIE_AXI_M_STICKY_ARES>, 415 <&gcc PCIE_PIPE_STICKY_ARES>, 416 <&gcc PCIE_PWR_ARES>, 417 <&gcc PCIE_AHB_ARES>, 418 <&gcc PCIE_PHY_AHB_ARES>; 419 reset-names = "axi_m", 420 "axi_s", 421 "pipe", 422 "axi_m_vmid", 423 "axi_s_xpu", 424 "parf", 425 "phy", 426 "axi_m_sticky", 427 "pipe_sticky", 428 "pwr", 429 "ahb", 430 "phy_ahb"; 431 432 status = "disabled"; 433 }; 434 435 qpic_bam: dma@7984000 { 436 compatible = "qcom,bam-v1.7.0"; 437 reg = <0x7984000 0x1a000>; 438 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 439 clocks = <&gcc GCC_QPIC_CLK>; 440 clock-names = "bam_clk"; 441 #dma-cells = <1>; 442 qcom,ee = <0>; 443 status = "disabled"; 444 }; 445 446 nand: qpic-nand@79b0000 { 447 compatible = "qcom,ipq4019-nand"; 448 reg = <0x79b0000 0x1000>; 449 #address-cells = <1>; 450 #size-cells = <0>; 451 clocks = <&gcc GCC_QPIC_CLK>, 452 <&gcc GCC_QPIC_AHB_CLK>; 453 clock-names = "core", "aon"; 454 455 dmas = <&qpic_bam 0>, 456 <&qpic_bam 1>, 457 <&qpic_bam 2>; 458 dma-names = "tx", "rx", "cmd"; 459 status = "disabled"; 460 461 nand@0 { 462 reg = <0>; 463 464 nand-ecc-strength = <4>; 465 nand-ecc-step-size = <512>; 466 nand-bus-width = <8>; 467 }; 468 }; 469 470 wifi0: wifi@a000000 { 471 compatible = "qcom,ipq4019-wifi"; 472 reg = <0xa000000 0x200000>; 473 resets = <&gcc WIFI0_CPU_INIT_RESET>, 474 <&gcc WIFI0_RADIO_SRIF_RESET>, 475 <&gcc WIFI0_RADIO_WARM_RESET>, 476 <&gcc WIFI0_RADIO_COLD_RESET>, 477 <&gcc WIFI0_CORE_WARM_RESET>, 478 <&gcc WIFI0_CORE_COLD_RESET>; 479 reset-names = "wifi_cpu_init", "wifi_radio_srif", 480 "wifi_radio_warm", "wifi_radio_cold", 481 "wifi_core_warm", "wifi_core_cold"; 482 clocks = <&gcc GCC_WCSS2G_CLK>, 483 <&gcc GCC_WCSS2G_REF_CLK>, 484 <&gcc GCC_WCSS2G_RTC_CLK>; 485 clock-names = "wifi_wcss_cmd", "wifi_wcss_ref", 486 "wifi_wcss_rtc"; 487 interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>, 488 <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>, 489 <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>, 490 <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>, 491 <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>, 492 <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>, 493 <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>, 494 <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>, 495 <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>, 496 <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>, 497 <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>, 498 <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>, 499 <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>, 500 <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>, 501 <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>, 502 <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>, 503 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 504 interrupt-names = "msi0", "msi1", "msi2", "msi3", 505 "msi4", "msi5", "msi6", "msi7", 506 "msi8", "msi9", "msi10", "msi11", 507 "msi12", "msi13", "msi14", "msi15", 508 "legacy"; 509 status = "disabled"; 510 }; 511 512 wifi1: wifi@a800000 { 513 compatible = "qcom,ipq4019-wifi"; 514 reg = <0xa800000 0x200000>; 515 resets = <&gcc WIFI1_CPU_INIT_RESET>, 516 <&gcc WIFI1_RADIO_SRIF_RESET>, 517 <&gcc WIFI1_RADIO_WARM_RESET>, 518 <&gcc WIFI1_RADIO_COLD_RESET>, 519 <&gcc WIFI1_CORE_WARM_RESET>, 520 <&gcc WIFI1_CORE_COLD_RESET>; 521 reset-names = "wifi_cpu_init", "wifi_radio_srif", 522 "wifi_radio_warm", "wifi_radio_cold", 523 "wifi_core_warm", "wifi_core_cold"; 524 clocks = <&gcc GCC_WCSS5G_CLK>, 525 <&gcc GCC_WCSS5G_REF_CLK>, 526 <&gcc GCC_WCSS5G_RTC_CLK>; 527 clock-names = "wifi_wcss_cmd", "wifi_wcss_ref", 528 "wifi_wcss_rtc"; 529 interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>, 530 <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>, 531 <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>, 532 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>, 533 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, 534 <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>, 535 <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>, 536 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>, 537 <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>, 538 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>, 539 <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>, 540 <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>, 541 <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>, 542 <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>, 543 <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>, 544 <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>, 545 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 546 interrupt-names = "msi0", "msi1", "msi2", "msi3", 547 "msi4", "msi5", "msi6", "msi7", 548 "msi8", "msi9", "msi10", "msi11", 549 "msi12", "msi13", "msi14", "msi15", 550 "legacy"; 551 status = "disabled"; 552 }; 553 }; 554}; 555
