1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /****************************************************************************** 3 * 4 * Copyright(c) 2007 - 2016 Realtek Corporation. 5 * 6 * Contact Information: 7 * wlanfae <wlanfae@realtek.com> 8 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 9 * Hsinchu 300, Taiwan. 10 * 11 * Larry Finger <Larry.Finger@lwfinger.net> 12 * 13 *****************************************************************************/ 14 15 #ifndef __ODM_REGDEFINE11N_H__ 16 #define __ODM_REGDEFINE11N_H__ 17 18 /* 2 RF REG LIST */ 19 #define ODM_REG_RF_MODE_11N 0x00 20 #define ODM_REG_RF_0B_11N 0x0B 21 #define ODM_REG_CHNBW_11N 0x18 22 #define ODM_REG_T_METER_11N 0x24 23 #define ODM_REG_RF_25_11N 0x25 24 #define ODM_REG_RF_26_11N 0x26 25 #define ODM_REG_RF_27_11N 0x27 26 #define ODM_REG_RF_2B_11N 0x2B 27 #define ODM_REG_RF_2C_11N 0x2C 28 #define ODM_REG_RXRF_A3_11N 0x3C 29 #define ODM_REG_T_METER_92D_11N 0x42 30 #define ODM_REG_T_METER_88E_11N 0x42 31 32 /* 2 BB REG LIST */ 33 /* PAGE 8 */ 34 #define ODM_REG_BB_CTRL_11N 0x800 35 #define ODM_REG_RF_PIN_11N 0x804 36 #define ODM_REG_PSD_CTRL_11N 0x808 37 #define ODM_REG_TX_ANT_CTRL_11N 0x80C 38 #define ODM_REG_BB_PWR_SAV5_11N 0x818 39 #define ODM_REG_CCK_RPT_FORMAT_11N 0x824 40 #define ODM_REG_CCK_RPT_FORMAT_11N_B 0x82C 41 #define ODM_REG_RX_DEFAULT_A_11N 0x858 42 #define ODM_REG_RX_DEFAULT_B_11N 0x85A 43 #define ODM_REG_BB_PWR_SAV3_11N 0x85C 44 #define ODM_REG_ANTSEL_CTRL_11N 0x860 45 #define ODM_REG_RX_ANT_CTRL_11N 0x864 46 #define ODM_REG_PIN_CTRL_11N 0x870 47 #define ODM_REG_BB_PWR_SAV1_11N 0x874 48 #define ODM_REG_ANTSEL_PATH_11N 0x878 49 #define ODM_REG_BB_3WIRE_11N 0x88C 50 #define ODM_REG_SC_CNT_11N 0x8C4 51 #define ODM_REG_PSD_DATA_11N 0x8B4 52 #define ODM_REG_CCX_PERIOD_11N 0x894 53 #define ODM_REG_NHM_TH9_TH10_11N 0x890 54 #define ODM_REG_CLM_11N 0x890 55 #define ODM_REG_NHM_TH3_TO_TH0_11N 0x898 56 #define ODM_REG_NHM_TH7_TO_TH4_11N 0x89c 57 #define ODM_REG_NHM_TH8_11N 0xe28 58 #define ODM_REG_CLM_READY_11N 0x8b4 59 #define ODM_REG_CLM_RESULT_11N 0x8d0 60 #define ODM_REG_NHM_CNT_11N 0x8d8 61 62 /* For struct acs_info, Jeffery, 2014-12-26 */ 63 #define ODM_REG_NHM_CNT7_TO_CNT4_11N 0x8dc 64 #define ODM_REG_NHM_CNT9_TO_CNT8_11N 0x8d0 65 #define ODM_REG_NHM_CNT10_TO_CNT11_11N 0x8d4 66 67 /* PAGE 9 */ 68 #define ODM_REG_BB_CTRL_PAGE9_11N 0x900 69 #define ODM_REG_DBG_RPT_11N 0x908 70 #define ODM_REG_BB_TX_PATH_11N 0x90c 71 #define ODM_REG_ANT_MAPPING1_11N 0x914 72 #define ODM_REG_ANT_MAPPING2_11N 0x918 73 #define ODM_REG_EDCCA_DOWN_OPT_11N 0x948 74 #define ODM_REG_RX_DFIR_MOD_97F 0x948 75 76 /* PAGE A */ 77 #define ODM_REG_CCK_ANTDIV_PARA1_11N 0xA00 78 #define ODM_REG_CCK_ANT_SEL_11N 0xA04 79 #define ODM_REG_CCK_CCA_11N 0xA0A 80 #define ODM_REG_CCK_ANTDIV_PARA2_11N 0xA0C 81 #define ODM_REG_CCK_ANTDIV_PARA3_11N 0xA10 82 #define ODM_REG_CCK_ANTDIV_PARA4_11N 0xA14 83 #define ODM_REG_CCK_FILTER_PARA1_11N 0xA22 84 #define ODM_REG_CCK_FILTER_PARA2_11N 0xA23 85 #define ODM_REG_CCK_FILTER_PARA3_11N 0xA24 86 #define ODM_REG_CCK_FILTER_PARA4_11N 0xA25 87 #define ODM_REG_CCK_FILTER_PARA5_11N 0xA26 88 #define ODM_REG_CCK_FILTER_PARA6_11N 0xA27 89 #define ODM_REG_CCK_FILTER_PARA7_11N 0xA28 90 #define ODM_REG_CCK_FILTER_PARA8_11N 0xA29 91 #define ODM_REG_CCK_FA_RST_11N 0xA2C 92 #define ODM_REG_CCK_FA_MSB_11N 0xA58 93 #define ODM_REG_CCK_FA_LSB_11N 0xA5C 94 #define ODM_REG_CCK_CCA_CNT_11N 0xA60 95 #define ODM_REG_BB_PWR_SAV4_11N 0xA74 96 /* PAGE B */ 97 #define ODM_REG_LNA_SWITCH_11N 0xB2C 98 #define ODM_REG_PATH_SWITCH_11N 0xB30 99 #define ODM_REG_RSSI_CTRL_11N 0xB38 100 #define ODM_REG_CONFIG_ANTA_11N 0xB68 101 #define ODM_REG_RSSI_BT_11N 0xB9C 102 #define ODM_REG_RXCK_RFMOD 0xBB0 103 #define ODM_REG_EDCCA_DCNF_97F 0xBC0 104 105 /* PAGE C */ 106 #define ODM_REG_OFDM_FA_HOLDC_11N 0xC00 107 #define ODM_REG_BB_RX_PATH_11N 0xC04 108 #define ODM_REG_TRMUX_11N 0xC08 109 #define ODM_REG_OFDM_FA_RSTC_11N 0xC0C 110 #define ODM_REG_DOWNSAM_FACTOR_11N 0xC10 111 #define ODM_REG_RXIQI_MATRIX_11N 0xC14 112 #define ODM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C 113 #define ODM_REG_IGI_A_11N 0xC50 114 #define ODM_REG_ANTDIV_PARA2_11N 0xC54 115 #define ODM_REG_IGI_B_11N 0xC58 116 #define ODM_REG_ANTDIV_PARA3_11N 0xC5C 117 #define ODM_REG_L1SBD_PD_CH_11N 0XC6C 118 #define ODM_REG_BB_PWR_SAV2_11N 0xC70 119 #define ODM_REG_BB_AGC_SET_2_11N 0xc74 120 #define ODM_REG_RX_OFF_11N 0xC7C 121 #define ODM_REG_TXIQK_MATRIXA_11N 0xC80 122 #define ODM_REG_TXIQK_MATRIXB_11N 0xC88 123 #define ODM_REG_TXIQK_MATRIXA_LSB2_11N 0xC94 124 #define ODM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C 125 #define ODM_REG_RXIQK_MATRIX_LSB_11N 0xCA0 126 #define ODM_REG_ANTDIV_PARA1_11N 0xCA4 127 #define ODM_REG_SMALL_BANDWIDTH_11N 0xCE4 128 #define ODM_REG_OFDM_FA_TYPE1_11N 0xCF0 129 /* PAGE D */ 130 #define ODM_REG_OFDM_FA_RSTD_11N 0xD00 131 #define ODM_REG_BB_RX_ANT_11N 0xD04 132 #define ODM_REG_BB_ATC_11N 0xD2C 133 #define ODM_REG_OFDM_FA_TYPE2_11N 0xDA0 134 #define ODM_REG_OFDM_FA_TYPE3_11N 0xDA4 135 #define ODM_REG_OFDM_FA_TYPE4_11N 0xDA8 136 #define ODM_REG_RPT_11N 0xDF4 137 /* PAGE E */ 138 #define ODM_REG_TXAGC_A_6_18_11N 0xE00 139 #define ODM_REG_TXAGC_A_24_54_11N 0xE04 140 #define ODM_REG_TXAGC_A_1_MCS32_11N 0xE08 141 #define ODM_REG_TXAGC_A_MCS0_3_11N 0xE10 142 #define ODM_REG_TXAGC_A_MCS4_7_11N 0xE14 143 #define ODM_REG_TXAGC_A_MCS8_11_11N 0xE18 144 #define ODM_REG_TXAGC_A_MCS12_15_11N 0xE1C 145 #define ODM_REG_EDCCA_DCNF_11N 0xE24 146 #define ODM_REG_TAP_UPD_97F 0xE24 147 #define ODM_REG_FPGA0_IQK_11N 0xE28 148 #define ODM_REG_PAGE_B1_97F 0xE28 149 #define ODM_REG_TXIQK_TONE_A_11N 0xE30 150 #define ODM_REG_RXIQK_TONE_A_11N 0xE34 151 #define ODM_REG_TXIQK_PI_A_11N 0xE38 152 #define ODM_REG_RXIQK_PI_A_11N 0xE3C 153 #define ODM_REG_TXIQK_11N 0xE40 154 #define ODM_REG_RXIQK_11N 0xE44 155 #define ODM_REG_IQK_AGC_PTS_11N 0xE48 156 #define ODM_REG_IQK_AGC_RSP_11N 0xE4C 157 #define ODM_REG_BLUETOOTH_11N 0xE6C 158 #define ODM_REG_RX_WAIT_CCA_11N 0xE70 159 #define ODM_REG_TX_CCK_RFON_11N 0xE74 160 #define ODM_REG_TX_CCK_BBON_11N 0xE78 161 #define ODM_REG_OFDM_RFON_11N 0xE7C 162 #define ODM_REG_OFDM_BBON_11N 0xE80 163 #define ODM_REG_TX2RX_11N 0xE84 164 #define ODM_REG_TX2TX_11N 0xE88 165 #define ODM_REG_RX_CCK_11N 0xE8C 166 #define ODM_REG_RX_OFDM_11N 0xED0 167 #define ODM_REG_RX_WAIT_RIFS_11N 0xED4 168 #define ODM_REG_RX2RX_11N 0xED8 169 #define ODM_REG_STANDBY_11N 0xEDC 170 #define ODM_REG_SLEEP_11N 0xEE0 171 #define ODM_REG_PMPD_ANAEN_11N 0xEEC 172 /* PAGE F */ 173 #define ODM_REG_PAGE_F_RST_11N 0xF14 174 #define ODM_REG_IGI_C_11N 0xF84 175 #define ODM_REG_IGI_D_11N 0xF88 176 #define ODM_REG_CCK_CRC32_ERROR_CNT_11N 0xF84 177 #define ODM_REG_CCK_CRC32_OK_CNT_11N 0xF88 178 #define ODM_REG_HT_CRC32_CNT_11N 0xF90 179 #define ODM_REG_OFDM_CRC32_CNT_11N 0xF94 180 181 /* 2 MAC REG LIST */ 182 #define ODM_REG_BB_RST_11N 0x02 183 #define ODM_REG_ANTSEL_PIN_11N 0x4C 184 #define ODM_REG_EARLY_MODE_11N 0x4D0 185 #define ODM_REG_RSSI_MONITOR_11N 0x4FE 186 #define ODM_REG_EDCA_VO_11N 0x500 187 #define ODM_REG_EDCA_VI_11N 0x504 188 #define ODM_REG_EDCA_BE_11N 0x508 189 #define ODM_REG_EDCA_BK_11N 0x50C 190 #define ODM_REG_TXPAUSE_11N 0x522 191 #define ODM_REG_RESP_TX_11N 0x6D8 192 #define ODM_REG_ANT_TRAIN_PARA1_11N 0x7b0 193 #define ODM_REG_ANT_TRAIN_PARA2_11N 0x7b4 194 195 /* DIG Related */ 196 #define ODM_BIT_IGI_11N 0x0000007F 197 #define ODM_BIT_CCK_RPT_FORMAT_11N BIT(9) 198 #define ODM_BIT_BB_RX_PATH_11N 0xF 199 #define ODM_BIT_BB_TX_PATH_11N 0xF 200 #define ODM_BIT_BB_ATC_11N BIT(11) 201 202 #endif 203
