1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2013-2015, Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef UFS_QCOM_PHY_I_H_ 7 #define UFS_QCOM_PHY_I_H_ 8 9 #include <linux/module.h> 10 #include <linux/clk.h> 11 #include <linux/phy/phy.h> 12 #include <linux/regulator/consumer.h> 13 #include <linux/reset.h> 14 #include <linux/slab.h> 15 #include <linux/platform_device.h> 16 #include <linux/io.h> 17 #include <linux/delay.h> 18 #include <linux/iopoll.h> 19 20 #define UFS_QCOM_PHY_CAL_ENTRY(reg, val) \ 21 { \ 22 .reg_offset = reg, \ 23 .cfg_value = val, \ 24 } 25 26 #define UFS_QCOM_PHY_NAME_LEN 30 27 28 enum { 29 MASK_SERDES_START = 0x1, 30 MASK_PCS_READY = 0x1, 31 }; 32 33 enum { 34 OFFSET_SERDES_START = 0x0, 35 }; 36 37 struct ufs_qcom_phy_stored_attributes { 38 u32 att; 39 u32 value; 40 }; 41 42 43 struct ufs_qcom_phy_calibration { 44 u32 reg_offset; 45 u32 cfg_value; 46 }; 47 48 struct ufs_qcom_phy_vreg { 49 const char *name; 50 struct regulator *reg; 51 int max_uA; 52 int min_uV; 53 int max_uV; 54 bool enabled; 55 }; 56 57 struct ufs_qcom_phy { 58 struct list_head list; 59 struct device *dev; 60 void __iomem *mmio; 61 void __iomem *dev_ref_clk_ctrl_mmio; 62 struct clk *tx_iface_clk; 63 struct clk *rx_iface_clk; 64 bool is_iface_clk_enabled; 65 struct clk *ref_clk_src; 66 struct clk *ref_clk_parent; 67 struct clk *ref_clk; 68 bool is_ref_clk_enabled; 69 bool is_dev_ref_clk_enabled; 70 struct ufs_qcom_phy_vreg vdda_pll; 71 struct ufs_qcom_phy_vreg vdda_phy; 72 struct ufs_qcom_phy_vreg vddp_ref_clk; 73 unsigned int quirks; 74 75 /* 76 * If UFS link is put into Hibern8 and if UFS PHY analog hardware is 77 * power collapsed (by clearing UFS_PHY_POWER_DOWN_CONTROL), Hibern8 78 * exit might fail even after powering on UFS PHY analog hardware. 79 * Enabling this quirk will help to solve above issue by doing 80 * custom PHY settings just before PHY analog power collapse. 81 */ 82 #define UFS_QCOM_PHY_QUIRK_HIBERN8_EXIT_AFTER_PHY_PWR_COLLAPSE BIT(0) 83 84 u8 host_ctrl_rev_major; 85 u16 host_ctrl_rev_minor; 86 u16 host_ctrl_rev_step; 87 88 char name[UFS_QCOM_PHY_NAME_LEN]; 89 struct ufs_qcom_phy_calibration *cached_regs; 90 int cached_regs_table_size; 91 struct ufs_qcom_phy_specific_ops *phy_spec_ops; 92 93 enum phy_mode mode; 94 struct reset_control *ufs_reset; 95 }; 96 97 /** 98 * struct ufs_qcom_phy_specific_ops - set of pointers to functions which have a 99 * specific implementation per phy. Each UFS phy, should implement 100 * those functions according to its spec and requirements 101 * @start_serdes: pointer to a function that starts the serdes 102 * @is_physical_coding_sublayer_ready: pointer to a function that 103 * checks pcs readiness. returns 0 for success and non-zero for error. 104 * @set_tx_lane_enable: pointer to a function that enable tx lanes 105 * @power_control: pointer to a function that controls analog rail of phy 106 * and writes to QSERDES_RX_SIGDET_CNTRL attribute 107 */ 108 struct ufs_qcom_phy_specific_ops { 109 int (*calibrate)(struct ufs_qcom_phy *ufs_qcom_phy, bool is_rate_B); 110 void (*start_serdes)(struct ufs_qcom_phy *phy); 111 int (*is_physical_coding_sublayer_ready)(struct ufs_qcom_phy *phy); 112 void (*set_tx_lane_enable)(struct ufs_qcom_phy *phy, u32 val); 113 void (*power_control)(struct ufs_qcom_phy *phy, bool val); 114 }; 115 116 struct ufs_qcom_phy *get_ufs_qcom_phy(struct phy *generic_phy); 117 int ufs_qcom_phy_power_on(struct phy *generic_phy); 118 int ufs_qcom_phy_power_off(struct phy *generic_phy); 119 int ufs_qcom_phy_init_clks(struct ufs_qcom_phy *phy_common); 120 int ufs_qcom_phy_init_vregulators(struct ufs_qcom_phy *phy_common); 121 int ufs_qcom_phy_remove(struct phy *generic_phy, 122 struct ufs_qcom_phy *ufs_qcom_phy); 123 struct phy *ufs_qcom_phy_generic_probe(struct platform_device *pdev, 124 struct ufs_qcom_phy *common_cfg, 125 const struct phy_ops *ufs_qcom_phy_gen_ops, 126 struct ufs_qcom_phy_specific_ops *phy_spec_ops); 127 int ufs_qcom_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy, 128 struct ufs_qcom_phy_calibration *tbl_A, int tbl_size_A, 129 struct ufs_qcom_phy_calibration *tbl_B, int tbl_size_B, 130 bool is_rate_B); 131 #endif 132
