1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef __DSI_PHY_H__ 7 #define __DSI_PHY_H__ 8 9 #include <linux/clk-provider.h> 10 #include <linux/delay.h> 11 #include <linux/regulator/consumer.h> 12 13 #include "dsi.h" 14 15 #define dsi_phy_read(offset) msm_readl((offset)) 16 #define dsi_phy_write(offset, data) msm_writel((data), (offset)) 17 #define dsi_phy_write_udelay(offset, data, delay_us) { msm_writel((data), (offset)); udelay(delay_us); } 18 #define dsi_phy_write_ndelay(offset, data, delay_ns) { msm_writel((data), (offset)); ndelay(delay_ns); } 19 20 struct msm_dsi_phy_ops { 21 int (*pll_init)(struct msm_dsi_phy *phy); 22 int (*enable)(struct msm_dsi_phy *phy, 23 struct msm_dsi_phy_clk_request *clk_req); 24 void (*disable)(struct msm_dsi_phy *phy); 25 void (*save_pll_state)(struct msm_dsi_phy *phy); 26 int (*restore_pll_state)(struct msm_dsi_phy *phy); 27 bool (*set_continuous_clock)(struct msm_dsi_phy *phy, bool enable); 28 int (*parse_dt_properties)(struct msm_dsi_phy *phy); 29 }; 30 31 struct msm_dsi_phy_cfg { 32 const struct regulator_bulk_data *regulator_data; 33 int num_regulators; 34 struct msm_dsi_phy_ops ops; 35 36 unsigned long min_pll_rate; 37 unsigned long max_pll_rate; 38 39 const resource_size_t io_start[DSI_MAX]; 40 const int num_dsi_phy; 41 const int quirks; 42 bool has_phy_regulator; 43 bool has_phy_lane; 44 }; 45 46 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs; 47 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs; 48 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs; 49 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8226_cfgs; 50 extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs; 51 extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs; 52 extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs; 53 extern const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs; 54 extern const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs; 55 extern const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs; 56 extern const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs; 57 extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs; 58 extern const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs; 59 extern const struct msm_dsi_phy_cfg dsi_phy_7nm_6375_cfgs; 60 extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs; 61 extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs; 62 extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs; 63 extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs; 64 extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs; 65 66 struct msm_dsi_dphy_timing { 67 u32 clk_zero; 68 u32 clk_trail; 69 u32 clk_prepare; 70 u32 hs_exit; 71 u32 hs_zero; 72 u32 hs_prepare; 73 u32 hs_trail; 74 u32 hs_rqst; 75 u32 ta_go; 76 u32 ta_sure; 77 u32 ta_get; 78 79 struct msm_dsi_phy_shared_timings shared_timings; 80 81 /* For PHY v2 only */ 82 u32 hs_rqst_ckln; 83 u32 hs_prep_dly; 84 u32 hs_prep_dly_ckln; 85 u8 hs_halfbyte_en; 86 u8 hs_halfbyte_en_ckln; 87 }; 88 89 #define DSI_BYTE_PLL_CLK 0 90 #define DSI_PIXEL_PLL_CLK 1 91 #define NUM_PROVIDED_CLKS 2 92 93 #define DSI_LANE_MAX 5 94 95 struct msm_dsi_phy { 96 struct platform_device *pdev; 97 void __iomem *base; 98 void __iomem *pll_base; 99 void __iomem *reg_base; 100 void __iomem *lane_base; 101 phys_addr_t base_size; 102 phys_addr_t pll_size; 103 phys_addr_t reg_size; 104 phys_addr_t lane_size; 105 int id; 106 107 struct clk *ahb_clk; 108 struct regulator_bulk_data *supplies; 109 110 struct msm_dsi_dphy_timing timing; 111 const struct msm_dsi_phy_cfg *cfg; 112 void *tuning_cfg; 113 114 enum msm_dsi_phy_usecase usecase; 115 bool regulator_ldo_mode; 116 bool cphy_mode; 117 118 struct clk_hw *vco_hw; 119 bool pll_on; 120 121 struct clk_hw_onecell_data *provided_clocks; 122 123 bool state_saved; 124 }; 125 126 /* 127 * PHY internal functions 128 */ 129 int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing, 130 struct msm_dsi_phy_clk_request *clk_req); 131 int msm_dsi_dphy_timing_calc_v2(struct msm_dsi_dphy_timing *timing, 132 struct msm_dsi_phy_clk_request *clk_req); 133 int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing, 134 struct msm_dsi_phy_clk_request *clk_req); 135 int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing, 136 struct msm_dsi_phy_clk_request *clk_req); 137 int msm_dsi_cphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing, 138 struct msm_dsi_phy_clk_request *clk_req); 139 140 #endif /* __DSI_PHY_H__ */ 141
