1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* (C) COPYRIGHT 2014-2018 ARM Limited. All rights reserved. */
3 /* Copyright 2019 Linaro, Ltd., Rob Herring <robh@kernel.org> */
4 #ifndef __PANFROST_ISSUES_H__
5 #define __PANFROST_ISSUES_H__
6
7 #include <linux/bitops.h>
8
9 #include "panfrost_device.h"
10
11 /*
12 * This is not a complete list of issues, but only the ones the driver needs
13 * to care about.
14 */
15 enum panfrost_hw_issue {
16 /* Need way to guarantee that all previously-translated memory accesses
17 * are commited */
18 HW_ISSUE_6367,
19
20 /* On job complete with non-done the cache is not flushed */
21 HW_ISSUE_6787,
22
23 /* Write of PRFCNT_CONFIG_MODE_MANUAL to PRFCNT_CONFIG causes a
24 * instrumentation dump if PRFCNT_TILER_EN is enabled */
25 HW_ISSUE_8186,
26
27 /* TIB: Reports faults from a vtile which has not yet been allocated */
28 HW_ISSUE_8245,
29
30 /* uTLB deadlock could occur when writing to an invalid page at the
31 * same time as access to a valid page in the same uTLB cache line ( ==
32 * 4 PTEs == 16K block of mapping) */
33 HW_ISSUE_8316,
34
35 /* HT: TERMINATE for RUN command ignored if previous LOAD_DESCRIPTOR is
36 * still executing */
37 HW_ISSUE_8394,
38
39 /* CSE: Sends a TERMINATED response for a task that should not be
40 * terminated */
41 HW_ISSUE_8401,
42
43 /* Repeatedly Soft-stopping a job chain consisting of (Vertex Shader,
44 * Cache Flush, Tiler) jobs causes DATA_INVALID_FAULT on tiler job. */
45 HW_ISSUE_8408,
46
47 /* Disable the Pause Buffer in the LS pipe. */
48 HW_ISSUE_8443,
49
50 /* Change in RMUs in use causes problems related with the core's SDC */
51 HW_ISSUE_8987,
52
53 /* Compute endpoint has a 4-deep queue of tasks, meaning a soft stop
54 * won't complete until all 4 tasks have completed */
55 HW_ISSUE_9435,
56
57 /* HT: Tiler returns TERMINATED for non-terminated command */
58 HW_ISSUE_9510,
59
60 /* Occasionally the GPU will issue multiple page faults for the same
61 * address before the MMU page table has been read by the GPU */
62 HW_ISSUE_9630,
63
64 /* RA DCD load request to SDC returns invalid load ignore causing
65 * colour buffer mismatch */
66 HW_ISSUE_10327,
67
68 /* MMU TLB invalidation hazards */
69 HW_ISSUE_10649,
70
71 /* Missing cache flush in multi core-group configuration */
72 HW_ISSUE_10676,
73
74 /* Chicken bit on T72X for a hardware workaround in compiler */
75 HW_ISSUE_10797,
76
77 /* Soft-stopping fragment jobs might fail with TILE_RANGE_FAULT */
78 HW_ISSUE_10817,
79
80 /* Intermittent missing interrupt on job completion */
81 HW_ISSUE_10883,
82
83 /* Soft-stopping fragment jobs might fail with TILE_RANGE_ERROR
84 * (similar to issue 10817) and can use #10817 workaround */
85 HW_ISSUE_10959,
86
87 /* Soft-stopped fragment shader job can restart with out-of-bound
88 * restart index */
89 HW_ISSUE_10969,
90
91 /* Race condition can cause tile list corruption */
92 HW_ISSUE_11020,
93
94 /* Write buffer can cause tile list corruption */
95 HW_ISSUE_11024,
96
97 /* Pause buffer can cause a fragment job hang */
98 HW_ISSUE_11035,
99
100 /* Dynamic Core Scaling not supported due to errata */
101 HW_ISSUE_11056,
102
103 /* Clear encoder state for a hard stopped fragment job which is AFBC
104 * encoded by soft resetting the GPU. Only for T76X r0p0, r0p1 and
105 * r0p1_50rel0 */
106 HW_ISSUE_T76X_3542,
107
108 /* Keep tiler module clock on to prevent GPU stall */
109 HW_ISSUE_T76X_3953,
110
111 /* Must ensure L2 is not transitioning when we reset. Workaround with a
112 * busy wait until L2 completes transition; ensure there is a maximum
113 * loop count as she may never complete her transition. (On chips
114 * without this errata, it's totally okay if L2 transitions.) */
115 HW_ISSUE_TMIX_8463,
116
117 /* Don't set SC_LS_ATTR_CHECK_DISABLE/SC_LS_ALLOW_ATTR_TYPES */
118 GPUCORE_1619,
119
120 /* When a hard-stop follows close after a soft-stop, the completion
121 * code for the terminated job may be incorrectly set to STOPPED */
122 HW_ISSUE_TMIX_8438,
123
124 /* "Protected mode" is buggy on Mali-G31 some Bifrost chips, so the
125 * kernel must fiddle with L2 caches to prevent data leakage */
126 HW_ISSUE_TGOX_R1_1234,
127
128 HW_ISSUE_END
129 };
130
131 #define hw_issues_all (\
132 BIT_ULL(HW_ISSUE_9435))
133
134 #define hw_issues_t600 (\
135 BIT_ULL(HW_ISSUE_6367) | \
136 BIT_ULL(HW_ISSUE_6787) | \
137 BIT_ULL(HW_ISSUE_8408) | \
138 BIT_ULL(HW_ISSUE_9510) | \
139 BIT_ULL(HW_ISSUE_10649) | \
140 BIT_ULL(HW_ISSUE_10676) | \
141 BIT_ULL(HW_ISSUE_10883) | \
142 BIT_ULL(HW_ISSUE_11020) | \
143 BIT_ULL(HW_ISSUE_11035) | \
144 BIT_ULL(HW_ISSUE_11056) | \
145 BIT_ULL(HW_ISSUE_TMIX_8438))
146
147 #define hw_issues_t600_r0p0_15dev0 (\
148 BIT_ULL(HW_ISSUE_8186) | \
149 BIT_ULL(HW_ISSUE_8245) | \
150 BIT_ULL(HW_ISSUE_8316) | \
151 BIT_ULL(HW_ISSUE_8394) | \
152 BIT_ULL(HW_ISSUE_8401) | \
153 BIT_ULL(HW_ISSUE_8443) | \
154 BIT_ULL(HW_ISSUE_8987) | \
155 BIT_ULL(HW_ISSUE_9630) | \
156 BIT_ULL(HW_ISSUE_10969) | \
157 BIT_ULL(GPUCORE_1619))
158
159 #define hw_issues_t620 (\
160 BIT_ULL(HW_ISSUE_10649) | \
161 BIT_ULL(HW_ISSUE_10883) | \
162 BIT_ULL(HW_ISSUE_10959) | \
163 BIT_ULL(HW_ISSUE_11056) | \
164 BIT_ULL(HW_ISSUE_TMIX_8438))
165
166 #define hw_issues_t620_r0p1 (\
167 BIT_ULL(HW_ISSUE_10327) | \
168 BIT_ULL(HW_ISSUE_10676) | \
169 BIT_ULL(HW_ISSUE_10817) | \
170 BIT_ULL(HW_ISSUE_11020) | \
171 BIT_ULL(HW_ISSUE_11024) | \
172 BIT_ULL(HW_ISSUE_11035))
173
174 #define hw_issues_t620_r1p0 (\
175 BIT_ULL(HW_ISSUE_11020) | \
176 BIT_ULL(HW_ISSUE_11024))
177
178 #define hw_issues_t720 (\
179 BIT_ULL(HW_ISSUE_10649) | \
180 BIT_ULL(HW_ISSUE_10797) | \
181 BIT_ULL(HW_ISSUE_10883) | \
182 BIT_ULL(HW_ISSUE_11056) | \
183 BIT_ULL(HW_ISSUE_TMIX_8438))
184
185 #define hw_issues_t760 (\
186 BIT_ULL(HW_ISSUE_10883) | \
187 BIT_ULL(HW_ISSUE_T76X_3953) | \
188 BIT_ULL(HW_ISSUE_TMIX_8438))
189
190 #define hw_issues_t760_r0p0 (\
191 BIT_ULL(HW_ISSUE_11020) | \
192 BIT_ULL(HW_ISSUE_11024) | \
193 BIT_ULL(HW_ISSUE_T76X_3542))
194
195 #define hw_issues_t760_r0p1 (\
196 BIT_ULL(HW_ISSUE_11020) | \
197 BIT_ULL(HW_ISSUE_11024) | \
198 BIT_ULL(HW_ISSUE_T76X_3542))
199
200 #define hw_issues_t760_r0p1_50rel0 (\
201 BIT_ULL(HW_ISSUE_T76X_3542))
202
203 #define hw_issues_t760_r0p2 (\
204 BIT_ULL(HW_ISSUE_11020) | \
205 BIT_ULL(HW_ISSUE_11024) | \
206 BIT_ULL(HW_ISSUE_T76X_3542))
207
208 #define hw_issues_t760_r0p3 (\
209 BIT_ULL(HW_ISSUE_T76X_3542))
210
211 #define hw_issues_t820 (\
212 BIT_ULL(HW_ISSUE_10883) | \
213 BIT_ULL(HW_ISSUE_T76X_3953) | \
214 BIT_ULL(HW_ISSUE_TMIX_8438))
215
216 #define hw_issues_t830 (\
217 BIT_ULL(HW_ISSUE_10883) | \
218 BIT_ULL(HW_ISSUE_T76X_3953) | \
219 BIT_ULL(HW_ISSUE_TMIX_8438))
220
221 #define hw_issues_t860 (\
222 BIT_ULL(HW_ISSUE_10883) | \
223 BIT_ULL(HW_ISSUE_T76X_3953) | \
224 BIT_ULL(HW_ISSUE_TMIX_8438))
225
226 #define hw_issues_t880 (\
227 BIT_ULL(HW_ISSUE_10883) | \
228 BIT_ULL(HW_ISSUE_T76X_3953) | \
229 BIT_ULL(HW_ISSUE_TMIX_8438))
230
231 #define hw_issues_g31 0
232
233 #define hw_issues_g31_r1p0 (\
234 BIT_ULL(HW_ISSUE_TGOX_R1_1234))
235
236 #define hw_issues_g51 0
237
238 #define hw_issues_g52 0
239
240 #define hw_issues_g71 (\
241 BIT_ULL(HW_ISSUE_TMIX_8463) | \
242 BIT_ULL(HW_ISSUE_TMIX_8438))
243
244 #define hw_issues_g71_r0p0_05dev0 (\
245 BIT_ULL(HW_ISSUE_T76X_3953))
246
247 #define hw_issues_g72 0
248
249 #define hw_issues_g76 0
250
panfrost_has_hw_issue(struct panfrost_device * pfdev,enum panfrost_hw_issue issue)251 static inline bool panfrost_has_hw_issue(struct panfrost_device *pfdev,
252 enum panfrost_hw_issue issue)
253 {
254 return test_bit(issue, pfdev->features.hw_issues);
255 }
256
257 #endif /* __PANFROST_ISSUES_H__ */
258
