1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef _osssys_6_0_0_OFFSET_HEADER 24 #define _osssys_6_0_0_OFFSET_HEADER 25 26 27 28 // addressBlock: osssys_osssysdec 29 // base address: 0x4280 30 #define regIH_VMID_0_LUT 0x0000 31 #define regIH_VMID_0_LUT_BASE_IDX 0 32 #define regIH_VMID_1_LUT 0x0001 33 #define regIH_VMID_1_LUT_BASE_IDX 0 34 #define regIH_VMID_2_LUT 0x0002 35 #define regIH_VMID_2_LUT_BASE_IDX 0 36 #define regIH_VMID_3_LUT 0x0003 37 #define regIH_VMID_3_LUT_BASE_IDX 0 38 #define regIH_VMID_4_LUT 0x0004 39 #define regIH_VMID_4_LUT_BASE_IDX 0 40 #define regIH_VMID_5_LUT 0x0005 41 #define regIH_VMID_5_LUT_BASE_IDX 0 42 #define regIH_VMID_6_LUT 0x0006 43 #define regIH_VMID_6_LUT_BASE_IDX 0 44 #define regIH_VMID_7_LUT 0x0007 45 #define regIH_VMID_7_LUT_BASE_IDX 0 46 #define regIH_VMID_8_LUT 0x0008 47 #define regIH_VMID_8_LUT_BASE_IDX 0 48 #define regIH_VMID_9_LUT 0x0009 49 #define regIH_VMID_9_LUT_BASE_IDX 0 50 #define regIH_VMID_10_LUT 0x000a 51 #define regIH_VMID_10_LUT_BASE_IDX 0 52 #define regIH_VMID_11_LUT 0x000b 53 #define regIH_VMID_11_LUT_BASE_IDX 0 54 #define regIH_VMID_12_LUT 0x000c 55 #define regIH_VMID_12_LUT_BASE_IDX 0 56 #define regIH_VMID_13_LUT 0x000d 57 #define regIH_VMID_13_LUT_BASE_IDX 0 58 #define regIH_VMID_14_LUT 0x000e 59 #define regIH_VMID_14_LUT_BASE_IDX 0 60 #define regIH_VMID_15_LUT 0x000f 61 #define regIH_VMID_15_LUT_BASE_IDX 0 62 #define regIH_VMID_0_LUT_MM 0x0010 63 #define regIH_VMID_0_LUT_MM_BASE_IDX 0 64 #define regIH_VMID_1_LUT_MM 0x0011 65 #define regIH_VMID_1_LUT_MM_BASE_IDX 0 66 #define regIH_VMID_2_LUT_MM 0x0012 67 #define regIH_VMID_2_LUT_MM_BASE_IDX 0 68 #define regIH_VMID_3_LUT_MM 0x0013 69 #define regIH_VMID_3_LUT_MM_BASE_IDX 0 70 #define regIH_VMID_4_LUT_MM 0x0014 71 #define regIH_VMID_4_LUT_MM_BASE_IDX 0 72 #define regIH_VMID_5_LUT_MM 0x0015 73 #define regIH_VMID_5_LUT_MM_BASE_IDX 0 74 #define regIH_VMID_6_LUT_MM 0x0016 75 #define regIH_VMID_6_LUT_MM_BASE_IDX 0 76 #define regIH_VMID_7_LUT_MM 0x0017 77 #define regIH_VMID_7_LUT_MM_BASE_IDX 0 78 #define regIH_VMID_8_LUT_MM 0x0018 79 #define regIH_VMID_8_LUT_MM_BASE_IDX 0 80 #define regIH_VMID_9_LUT_MM 0x0019 81 #define regIH_VMID_9_LUT_MM_BASE_IDX 0 82 #define regIH_VMID_10_LUT_MM 0x001a 83 #define regIH_VMID_10_LUT_MM_BASE_IDX 0 84 #define regIH_VMID_11_LUT_MM 0x001b 85 #define regIH_VMID_11_LUT_MM_BASE_IDX 0 86 #define regIH_VMID_12_LUT_MM 0x001c 87 #define regIH_VMID_12_LUT_MM_BASE_IDX 0 88 #define regIH_VMID_13_LUT_MM 0x001d 89 #define regIH_VMID_13_LUT_MM_BASE_IDX 0 90 #define regIH_VMID_14_LUT_MM 0x001e 91 #define regIH_VMID_14_LUT_MM_BASE_IDX 0 92 #define regIH_VMID_15_LUT_MM 0x001f 93 #define regIH_VMID_15_LUT_MM_BASE_IDX 0 94 #define regIH_COOKIE_0 0x0020 95 #define regIH_COOKIE_0_BASE_IDX 0 96 #define regIH_COOKIE_1 0x0021 97 #define regIH_COOKIE_1_BASE_IDX 0 98 #define regIH_COOKIE_2 0x0022 99 #define regIH_COOKIE_2_BASE_IDX 0 100 #define regIH_COOKIE_3 0x0023 101 #define regIH_COOKIE_3_BASE_IDX 0 102 #define regIH_COOKIE_4 0x0024 103 #define regIH_COOKIE_4_BASE_IDX 0 104 #define regIH_COOKIE_5 0x0025 105 #define regIH_COOKIE_5_BASE_IDX 0 106 #define regIH_COOKIE_6 0x0026 107 #define regIH_COOKIE_6_BASE_IDX 0 108 #define regIH_COOKIE_7 0x0027 109 #define regIH_COOKIE_7_BASE_IDX 0 110 #define regIH_REGISTER_LAST_PART0 0x003f 111 #define regIH_REGISTER_LAST_PART0_BASE_IDX 0 112 #define regIH_RB_CNTL 0x0080 113 #define regIH_RB_CNTL_BASE_IDX 0 114 #define regIH_RB_BASE 0x0081 115 #define regIH_RB_BASE_BASE_IDX 0 116 #define regIH_RB_BASE_HI 0x0082 117 #define regIH_RB_BASE_HI_BASE_IDX 0 118 #define regIH_RB_RPTR 0x0083 119 #define regIH_RB_RPTR_BASE_IDX 0 120 #define regIH_RB_WPTR 0x0084 121 #define regIH_RB_WPTR_BASE_IDX 0 122 #define regIH_RB_WPTR_ADDR_HI 0x0085 123 #define regIH_RB_WPTR_ADDR_HI_BASE_IDX 0 124 #define regIH_RB_WPTR_ADDR_LO 0x0086 125 #define regIH_RB_WPTR_ADDR_LO_BASE_IDX 0 126 #define regIH_DOORBELL_RPTR 0x0087 127 #define regIH_DOORBELL_RPTR_BASE_IDX 0 128 #define regIH_DOORBELL_RETRY_CAM 0x0088 129 #define regIH_DOORBELL_RETRY_CAM_BASE_IDX 0 130 #define regIH_RB_CNTL_RING1 0x008c 131 #define regIH_RB_CNTL_RING1_BASE_IDX 0 132 #define regIH_RB_BASE_RING1 0x008d 133 #define regIH_RB_BASE_RING1_BASE_IDX 0 134 #define regIH_RB_BASE_HI_RING1 0x008e 135 #define regIH_RB_BASE_HI_RING1_BASE_IDX 0 136 #define regIH_RB_RPTR_RING1 0x008f 137 #define regIH_RB_RPTR_RING1_BASE_IDX 0 138 #define regIH_RB_WPTR_RING1 0x0090 139 #define regIH_RB_WPTR_RING1_BASE_IDX 0 140 #define regIH_DOORBELL_RPTR_RING1 0x0093 141 #define regIH_DOORBELL_RPTR_RING1_BASE_IDX 0 142 #define regIH_RETRY_CAM_ACK 0x00a4 143 #define regIH_RETRY_CAM_ACK_BASE_IDX 0 144 #define regIH_VERSION 0x00a5 145 #define regIH_VERSION_BASE_IDX 0 146 #define regIH_CNTL 0x00c0 147 #define regIH_CNTL_BASE_IDX 0 148 #define regIH_CNTL2 0x00c1 149 #define regIH_CNTL2_BASE_IDX 0 150 #define regIH_STATUS 0x00c2 151 #define regIH_STATUS_BASE_IDX 0 152 #define regIH_PERFMON_CNTL 0x00c3 153 #define regIH_PERFMON_CNTL_BASE_IDX 0 154 #define regIH_PERFCOUNTER0_RESULT 0x00c4 155 #define regIH_PERFCOUNTER0_RESULT_BASE_IDX 0 156 #define regIH_PERFCOUNTER1_RESULT 0x00c5 157 #define regIH_PERFCOUNTER1_RESULT_BASE_IDX 0 158 #define regIH_DSM_MATCH_VALUE_BIT_31_0 0x00c7 159 #define regIH_DSM_MATCH_VALUE_BIT_31_0_BASE_IDX 0 160 #define regIH_DSM_MATCH_VALUE_BIT_63_32 0x00c8 161 #define regIH_DSM_MATCH_VALUE_BIT_63_32_BASE_IDX 0 162 #define regIH_DSM_MATCH_VALUE_BIT_95_64 0x00c9 163 #define regIH_DSM_MATCH_VALUE_BIT_95_64_BASE_IDX 0 164 #define regIH_DSM_MATCH_FIELD_CONTROL 0x00ca 165 #define regIH_DSM_MATCH_FIELD_CONTROL_BASE_IDX 0 166 #define regIH_DSM_MATCH_DATA_CONTROL 0x00cb 167 #define regIH_DSM_MATCH_DATA_CONTROL_BASE_IDX 0 168 #define regIH_DSM_MATCH_FCN_ID 0x00cc 169 #define regIH_DSM_MATCH_FCN_ID_BASE_IDX 0 170 #define regIH_LIMIT_INT_RATE_CNTL 0x00cd 171 #define regIH_LIMIT_INT_RATE_CNTL_BASE_IDX 0 172 #define regIH_VF_RB_STATUS 0x00ce 173 #define regIH_VF_RB_STATUS_BASE_IDX 0 174 #define regIH_VF_RB_STATUS2 0x00cf 175 #define regIH_VF_RB_STATUS2_BASE_IDX 0 176 #define regIH_VF_RB1_STATUS 0x00d0 177 #define regIH_VF_RB1_STATUS_BASE_IDX 0 178 #define regIH_VF_RB1_STATUS2 0x00d1 179 #define regIH_VF_RB1_STATUS2_BASE_IDX 0 180 #define regIH_RB_STATUS 0x00d4 181 #define regIH_RB_STATUS_BASE_IDX 0 182 #define regIH_INT_FLOOD_CNTL 0x00d5 183 #define regIH_INT_FLOOD_CNTL_BASE_IDX 0 184 #define regIH_RB0_INT_FLOOD_STATUS 0x00d6 185 #define regIH_RB0_INT_FLOOD_STATUS_BASE_IDX 0 186 #define regIH_RB1_INT_FLOOD_STATUS 0x00d7 187 #define regIH_RB1_INT_FLOOD_STATUS_BASE_IDX 0 188 #define regIH_INT_FLOOD_STATUS 0x00d9 189 #define regIH_INT_FLOOD_STATUS_BASE_IDX 0 190 #define regIH_STORM_CLIENT_LIST_CNTL 0x00da 191 #define regIH_STORM_CLIENT_LIST_CNTL_BASE_IDX 0 192 #define regIH_CLK_CTRL 0x00db 193 #define regIH_CLK_CTRL_BASE_IDX 0 194 #define regIH_INT_FLAGS 0x00dc 195 #define regIH_INT_FLAGS_BASE_IDX 0 196 #define regIH_LAST_INT_INFO0 0x00dd 197 #define regIH_LAST_INT_INFO0_BASE_IDX 0 198 #define regIH_LAST_INT_INFO1 0x00de 199 #define regIH_LAST_INT_INFO1_BASE_IDX 0 200 #define regIH_LAST_INT_INFO2 0x00df 201 #define regIH_LAST_INT_INFO2_BASE_IDX 0 202 #define regIH_SCRATCH 0x00e0 203 #define regIH_SCRATCH_BASE_IDX 0 204 #define regIH_CLIENT_CREDIT_ERROR 0x00e1 205 #define regIH_CLIENT_CREDIT_ERROR_BASE_IDX 0 206 #define regIH_COOKIE_REC_VIOLATION_LOG 0x00e4 207 #define regIH_COOKIE_REC_VIOLATION_LOG_BASE_IDX 0 208 #define regIH_CREDIT_STATUS 0x00e5 209 #define regIH_CREDIT_STATUS_BASE_IDX 0 210 #define regIH_MMHUB_ERROR 0x00e6 211 #define regIH_MMHUB_ERROR_BASE_IDX 0 212 #define regIH_MEM_POWER_CTRL 0x00e9 213 #define regIH_MEM_POWER_CTRL_BASE_IDX 0 214 #define regIH_VF_RB_STATUS3 0x00ea 215 #define regIH_VF_RB_STATUS3_BASE_IDX 0 216 #define regIH_VF_RB_STATUS4 0x00eb 217 #define regIH_VF_RB_STATUS4_BASE_IDX 0 218 #define regIH_VF_RB1_STATUS3 0x00ec 219 #define regIH_VF_RB1_STATUS3_BASE_IDX 0 220 #define regIH_RETRY_INT_CAM_CNTL 0x00ef 221 #define regIH_RETRY_INT_CAM_CNTL_BASE_IDX 0 222 #define regIH_MEM_POWER_CTRL2 0x00f0 223 #define regIH_MEM_POWER_CTRL2_BASE_IDX 0 224 #define regIH_MSI_STORM_CTRL 0x00f1 225 #define regIH_MSI_STORM_CTRL_BASE_IDX 0 226 #define regIH_MSI_STORM_CLIENT_INDEX 0x00f2 227 #define regIH_MSI_STORM_CLIENT_INDEX_BASE_IDX 0 228 #define regIH_MSI_STORM_CLIENT_DATA 0x00f3 229 #define regIH_MSI_STORM_CLIENT_DATA_BASE_IDX 0 230 #define regIH_REGISTER_LAST_PART2 0x00ff 231 #define regIH_REGISTER_LAST_PART2_BASE_IDX 0 232 #define regSEM_MAILBOX 0x010a 233 #define regSEM_MAILBOX_BASE_IDX 0 234 #define regSEM_MAILBOX_CLEAR 0x010b 235 #define regSEM_MAILBOX_CLEAR_BASE_IDX 0 236 #define regSEM_REGISTER_LAST_PART2 0x017f 237 #define regSEM_REGISTER_LAST_PART2_BASE_IDX 0 238 #define regIH_CLIENT_CFG 0x0184 239 #define regIH_CLIENT_CFG_BASE_IDX 0 240 #define regIH_CLIENT_CFG_INDEX 0x0188 241 #define regIH_CLIENT_CFG_INDEX_BASE_IDX 0 242 #define regIH_CLIENT_CFG_DATA 0x0189 243 #define regIH_CLIENT_CFG_DATA_BASE_IDX 0 244 #define regIH_CID_REMAP_INDEX 0x018b 245 #define regIH_CID_REMAP_INDEX_BASE_IDX 0 246 #define regIH_CID_REMAP_DATA 0x018c 247 #define regIH_CID_REMAP_DATA_BASE_IDX 0 248 #define regIH_CHICKEN 0x018d 249 #define regIH_CHICKEN_BASE_IDX 0 250 #define regIH_INT_DROP_CNTL 0x018f 251 #define regIH_INT_DROP_CNTL_BASE_IDX 0 252 #define regIH_INT_DROP_MATCH_VALUE0 0x0190 253 #define regIH_INT_DROP_MATCH_VALUE0_BASE_IDX 0 254 #define regIH_INT_DROP_MATCH_VALUE1 0x0191 255 #define regIH_INT_DROP_MATCH_VALUE1_BASE_IDX 0 256 #define regIH_INT_DROP_MATCH_MASK0 0x0192 257 #define regIH_INT_DROP_MATCH_MASK0_BASE_IDX 0 258 #define regIH_INT_DROP_MATCH_MASK1 0x0193 259 #define regIH_INT_DROP_MATCH_MASK1_BASE_IDX 0 260 #define regIH_REGISTER_LAST_PART1 0x019f 261 #define regIH_REGISTER_LAST_PART1_BASE_IDX 0 262 263 #endif 264
