1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
4 *
5 * Copyright (C) 2009-2011 Nokia Corporation
6 * Copyright (C) 2012 Texas Instruments, Inc.
7 * Paul Walmsley
8 *
9 * The data in this file should be completely autogeneratable from
10 * the TI hardware database or other technical documentation.
11 *
12 * XXX these should be marked initdata for multi-OMAP kernels
13 */
14
15 #include <linux/platform_data/i2c-omap.h>
16 #include <linux/power/smartreflex.h>
17 #include <linux/platform_data/hsmmc-omap.h>
18
19 #include <linux/omap-dma.h>
20 #include "l3_3xxx.h"
21 #include "l4_3xxx.h"
22
23 #include "soc.h"
24 #include "omap_hwmod.h"
25 #include "omap_hwmod_common_data.h"
26 #include "prm-regbits-34xx.h"
27 #include "cm-regbits-34xx.h"
28
29 #include "i2c.h"
30 #include "wd_timer.h"
31 #include "serial.h"
32
33 /*
34 * OMAP3xxx hardware module integration data
35 *
36 * All of the data in this section should be autogeneratable from the
37 * TI hardware database or other technical documentation. Data that
38 * is driver-specific or driver-kernel integration-specific belongs
39 * elsewhere.
40 */
41
42 #define AM35XX_IPSS_USBOTGSS_BASE 0x5C040000
43
44 /*
45 * IP blocks
46 */
47
48 /* L3 */
49
50 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
51 .name = "l3_main",
52 .class = &l3_hwmod_class,
53 .flags = HWMOD_NO_IDLEST,
54 };
55
56 /* L4 CORE */
57 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
58 .name = "l4_core",
59 .class = &l4_hwmod_class,
60 .flags = HWMOD_NO_IDLEST,
61 };
62
63 /* L4 PER */
64 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
65 .name = "l4_per",
66 .class = &l4_hwmod_class,
67 .flags = HWMOD_NO_IDLEST,
68 };
69
70 /* L4 WKUP */
71 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
72 .name = "l4_wkup",
73 .class = &l4_hwmod_class,
74 .flags = HWMOD_NO_IDLEST,
75 };
76
77 /* L4 SEC */
78 static struct omap_hwmod omap3xxx_l4_sec_hwmod = {
79 .name = "l4_sec",
80 .class = &l4_hwmod_class,
81 .flags = HWMOD_NO_IDLEST,
82 };
83
84 /* MPU */
85
86 static struct omap_hwmod omap3xxx_mpu_hwmod = {
87 .name = "mpu",
88 .class = &mpu_hwmod_class,
89 .main_clk = "arm_fck",
90 };
91
92 /* IVA2 (IVA2) */
93 static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = {
94 { .name = "logic", .rst_shift = 0, .st_shift = 8 },
95 { .name = "seq0", .rst_shift = 1, .st_shift = 9 },
96 { .name = "seq1", .rst_shift = 2, .st_shift = 10 },
97 };
98
99 static struct omap_hwmod omap3xxx_iva_hwmod = {
100 .name = "iva",
101 .class = &iva_hwmod_class,
102 .clkdm_name = "iva2_clkdm",
103 .rst_lines = omap3xxx_iva_resets,
104 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_iva_resets),
105 .main_clk = "iva2_ck",
106 .prcm = {
107 .omap2 = {
108 .module_offs = OMAP3430_IVA2_MOD,
109 .idlest_reg_id = 1,
110 .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
111 },
112 },
113 };
114
115 /*
116 * 'debugss' class
117 * debug and emulation sub system
118 */
119
120 static struct omap_hwmod_class omap3xxx_debugss_hwmod_class = {
121 .name = "debugss",
122 };
123
124 /* debugss */
125 static struct omap_hwmod omap3xxx_debugss_hwmod = {
126 .name = "debugss",
127 .class = &omap3xxx_debugss_hwmod_class,
128 .clkdm_name = "emu_clkdm",
129 .main_clk = "emu_src_ck",
130 .flags = HWMOD_NO_IDLEST,
131 };
132
133 /* timer class */
134 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
135 .rev_offs = 0x0000,
136 .sysc_offs = 0x0010,
137 .syss_offs = 0x0014,
138 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
139 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
140 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
141 SYSS_HAS_RESET_STATUS),
142 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
143 .sysc_fields = &omap_hwmod_sysc_type1,
144 };
145
146 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
147 .name = "timer",
148 .sysc = &omap3xxx_timer_sysc,
149 };
150
151 /* timer1 */
152 static struct omap_hwmod omap3xxx_timer1_hwmod = {
153 .name = "timer1",
154 .main_clk = "gpt1_fck",
155 .prcm = {
156 .omap2 = {
157 .module_offs = WKUP_MOD,
158 .idlest_reg_id = 1,
159 .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
160 },
161 },
162 .class = &omap3xxx_timer_hwmod_class,
163 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
164 };
165
166 /* timer2 */
167 static struct omap_hwmod omap3xxx_timer2_hwmod = {
168 .name = "timer2",
169 .main_clk = "gpt2_fck",
170 .prcm = {
171 .omap2 = {
172 .module_offs = OMAP3430_PER_MOD,
173 .idlest_reg_id = 1,
174 .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
175 },
176 },
177 .class = &omap3xxx_timer_hwmod_class,
178 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
179 };
180
181 /* timer3 */
182 static struct omap_hwmod omap3xxx_timer3_hwmod = {
183 .name = "timer3",
184 .main_clk = "gpt3_fck",
185 .prcm = {
186 .omap2 = {
187 .module_offs = OMAP3430_PER_MOD,
188 .idlest_reg_id = 1,
189 .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
190 },
191 },
192 .class = &omap3xxx_timer_hwmod_class,
193 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
194 };
195
196 /* timer4 */
197 static struct omap_hwmod omap3xxx_timer4_hwmod = {
198 .name = "timer4",
199 .main_clk = "gpt4_fck",
200 .prcm = {
201 .omap2 = {
202 .module_offs = OMAP3430_PER_MOD,
203 .idlest_reg_id = 1,
204 .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
205 },
206 },
207 .class = &omap3xxx_timer_hwmod_class,
208 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
209 };
210
211 /* timer5 */
212 static struct omap_hwmod omap3xxx_timer5_hwmod = {
213 .name = "timer5",
214 .main_clk = "gpt5_fck",
215 .prcm = {
216 .omap2 = {
217 .module_offs = OMAP3430_PER_MOD,
218 .idlest_reg_id = 1,
219 .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
220 },
221 },
222 .class = &omap3xxx_timer_hwmod_class,
223 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
224 };
225
226 /* timer6 */
227 static struct omap_hwmod omap3xxx_timer6_hwmod = {
228 .name = "timer6",
229 .main_clk = "gpt6_fck",
230 .prcm = {
231 .omap2 = {
232 .module_offs = OMAP3430_PER_MOD,
233 .idlest_reg_id = 1,
234 .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
235 },
236 },
237 .class = &omap3xxx_timer_hwmod_class,
238 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
239 };
240
241 /* timer7 */
242 static struct omap_hwmod omap3xxx_timer7_hwmod = {
243 .name = "timer7",
244 .main_clk = "gpt7_fck",
245 .prcm = {
246 .omap2 = {
247 .module_offs = OMAP3430_PER_MOD,
248 .idlest_reg_id = 1,
249 .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
250 },
251 },
252 .class = &omap3xxx_timer_hwmod_class,
253 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
254 };
255
256 /* timer8 */
257 static struct omap_hwmod omap3xxx_timer8_hwmod = {
258 .name = "timer8",
259 .main_clk = "gpt8_fck",
260 .prcm = {
261 .omap2 = {
262 .module_offs = OMAP3430_PER_MOD,
263 .idlest_reg_id = 1,
264 .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
265 },
266 },
267 .class = &omap3xxx_timer_hwmod_class,
268 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
269 };
270
271 /* timer9 */
272 static struct omap_hwmod omap3xxx_timer9_hwmod = {
273 .name = "timer9",
274 .main_clk = "gpt9_fck",
275 .prcm = {
276 .omap2 = {
277 .module_offs = OMAP3430_PER_MOD,
278 .idlest_reg_id = 1,
279 .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
280 },
281 },
282 .class = &omap3xxx_timer_hwmod_class,
283 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
284 };
285
286 /* timer10 */
287 static struct omap_hwmod omap3xxx_timer10_hwmod = {
288 .name = "timer10",
289 .main_clk = "gpt10_fck",
290 .prcm = {
291 .omap2 = {
292 .module_offs = CORE_MOD,
293 .idlest_reg_id = 1,
294 .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
295 },
296 },
297 .class = &omap3xxx_timer_hwmod_class,
298 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
299 };
300
301 /* timer11 */
302 static struct omap_hwmod omap3xxx_timer11_hwmod = {
303 .name = "timer11",
304 .main_clk = "gpt11_fck",
305 .prcm = {
306 .omap2 = {
307 .module_offs = CORE_MOD,
308 .idlest_reg_id = 1,
309 .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
310 },
311 },
312 .class = &omap3xxx_timer_hwmod_class,
313 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
314 };
315
316 /* timer12 */
317 static struct omap_hwmod omap3xxx_timer12_hwmod = {
318 .name = "timer12",
319 .main_clk = "gpt12_fck",
320 .prcm = {
321 .omap2 = {
322 .module_offs = WKUP_MOD,
323 .idlest_reg_id = 1,
324 .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
325 },
326 },
327 .class = &omap3xxx_timer_hwmod_class,
328 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
329 };
330
331 /*
332 * 'wd_timer' class
333 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
334 * overflow condition
335 */
336
337 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
338 .rev_offs = 0x0000,
339 .sysc_offs = 0x0010,
340 .syss_offs = 0x0014,
341 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
342 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
343 SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
344 SYSS_HAS_RESET_STATUS),
345 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
346 .sysc_fields = &omap_hwmod_sysc_type1,
347 };
348
349 /* I2C common */
350 static struct omap_hwmod_class_sysconfig i2c_sysc = {
351 .rev_offs = 0x00,
352 .sysc_offs = 0x20,
353 .syss_offs = 0x10,
354 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
355 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
356 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
357 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
358 .sysc_fields = &omap_hwmod_sysc_type1,
359 };
360
361 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
362 .name = "wd_timer",
363 .sysc = &omap3xxx_wd_timer_sysc,
364 .pre_shutdown = &omap2_wd_timer_disable,
365 .reset = &omap2_wd_timer_reset,
366 };
367
368 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
369 .name = "wd_timer2",
370 .class = &omap3xxx_wd_timer_hwmod_class,
371 .main_clk = "wdt2_fck",
372 .prcm = {
373 .omap2 = {
374 .module_offs = WKUP_MOD,
375 .idlest_reg_id = 1,
376 .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
377 },
378 },
379 /*
380 * XXX: Use software supervised mode, HW supervised smartidle seems to
381 * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
382 */
383 .flags = HWMOD_SWSUP_SIDLE,
384 };
385
386 /* UART1 */
387 static struct omap_hwmod omap3xxx_uart1_hwmod = {
388 .name = "uart1",
389 .main_clk = "uart1_fck",
390 .flags = DEBUG_TI81XXUART1_FLAGS | HWMOD_SWSUP_SIDLE,
391 .prcm = {
392 .omap2 = {
393 .module_offs = CORE_MOD,
394 .idlest_reg_id = 1,
395 .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
396 },
397 },
398 .class = &omap2_uart_class,
399 };
400
401 /* UART2 */
402 static struct omap_hwmod omap3xxx_uart2_hwmod = {
403 .name = "uart2",
404 .main_clk = "uart2_fck",
405 .flags = DEBUG_TI81XXUART2_FLAGS | HWMOD_SWSUP_SIDLE,
406 .prcm = {
407 .omap2 = {
408 .module_offs = CORE_MOD,
409 .idlest_reg_id = 1,
410 .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
411 },
412 },
413 .class = &omap2_uart_class,
414 };
415
416 /* UART3 */
417 static struct omap_hwmod omap3xxx_uart3_hwmod = {
418 .name = "uart3",
419 .main_clk = "uart3_fck",
420 .flags = DEBUG_OMAP3UART3_FLAGS | DEBUG_TI81XXUART3_FLAGS |
421 HWMOD_SWSUP_SIDLE,
422 .prcm = {
423 .omap2 = {
424 .module_offs = OMAP3430_PER_MOD,
425 .idlest_reg_id = 1,
426 .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
427 },
428 },
429 .class = &omap2_uart_class,
430 };
431
432 /* UART4 */
433
434
435 static struct omap_hwmod omap36xx_uart4_hwmod = {
436 .name = "uart4",
437 .main_clk = "uart4_fck",
438 .flags = DEBUG_OMAP3UART4_FLAGS | HWMOD_SWSUP_SIDLE,
439 .prcm = {
440 .omap2 = {
441 .module_offs = OMAP3430_PER_MOD,
442 .idlest_reg_id = 1,
443 .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
444 },
445 },
446 .class = &omap2_uart_class,
447 };
448
449
450
451 /*
452 * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or
453 * uart2_fck being enabled. So we add uart1_fck as an optional clock,
454 * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET. This really
455 * should not be needed. The functional clock structure of the AM35xx
456 * UART4 is extremely unclear and opaque; it is unclear what the role
457 * of uart1/2_fck is for the UART4. Any clarification from either
458 * empirical testing or the AM3505/3517 hardware designers would be
459 * most welcome.
460 */
461 static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = {
462 { .role = "softreset_uart1_fck", .clk = "uart1_fck" },
463 };
464
465 static struct omap_hwmod am35xx_uart4_hwmod = {
466 .name = "uart4",
467 .main_clk = "uart4_fck",
468 .prcm = {
469 .omap2 = {
470 .module_offs = CORE_MOD,
471 .idlest_reg_id = 1,
472 .idlest_idle_bit = AM35XX_ST_UART4_SHIFT,
473 },
474 },
475 .opt_clks = am35xx_uart4_opt_clks,
476 .opt_clks_cnt = ARRAY_SIZE(am35xx_uart4_opt_clks),
477 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
478 .class = &omap2_uart_class,
479 };
480
481 static struct omap_hwmod_class i2c_class = {
482 .name = "i2c",
483 .sysc = &i2c_sysc,
484 .reset = &omap_i2c_reset,
485 };
486
487 /* dss */
488 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
489 /*
490 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
491 * driver does not use these clocks.
492 */
493 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
494 { .role = "tv_clk", .clk = "dss_tv_fck" },
495 /* required only on OMAP3430 */
496 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
497 };
498
499 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
500 .name = "dss_core",
501 .class = &omap2_dss_hwmod_class,
502 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
503 .prcm = {
504 .omap2 = {
505 .module_offs = OMAP3430_DSS_MOD,
506 .idlest_reg_id = 1,
507 },
508 },
509 .opt_clks = dss_opt_clks,
510 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
511 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
512 };
513
514 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
515 .name = "dss_core",
516 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
517 .class = &omap2_dss_hwmod_class,
518 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
519 .prcm = {
520 .omap2 = {
521 .module_offs = OMAP3430_DSS_MOD,
522 .idlest_reg_id = 1,
523 .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
524 },
525 },
526 .opt_clks = dss_opt_clks,
527 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
528 };
529
530 /*
531 * 'dispc' class
532 * display controller
533 */
534
535 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
536 .rev_offs = 0x0000,
537 .sysc_offs = 0x0010,
538 .syss_offs = 0x0014,
539 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
540 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
541 SYSC_HAS_ENAWAKEUP),
542 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
543 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
544 .sysc_fields = &omap_hwmod_sysc_type1,
545 };
546
547 static struct omap_hwmod_class omap3_dispc_hwmod_class = {
548 .name = "dispc",
549 .sysc = &omap3_dispc_sysc,
550 };
551
552 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
553 .name = "dss_dispc",
554 .class = &omap3_dispc_hwmod_class,
555 .main_clk = "dss1_alwon_fck",
556 .prcm = {
557 .omap2 = {
558 .module_offs = OMAP3430_DSS_MOD,
559 },
560 },
561 .flags = HWMOD_NO_IDLEST,
562 .dev_attr = &omap2_3_dss_dispc_dev_attr,
563 };
564
565 /*
566 * 'dsi' class
567 * display serial interface controller
568 */
569
570 static struct omap_hwmod_class_sysconfig omap3xxx_dsi_sysc = {
571 .rev_offs = 0x0000,
572 .sysc_offs = 0x0010,
573 .syss_offs = 0x0014,
574 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
575 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
576 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
577 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
578 .sysc_fields = &omap_hwmod_sysc_type1,
579 };
580
581 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
582 .name = "dsi",
583 .sysc = &omap3xxx_dsi_sysc,
584 };
585
586 /* dss_dsi1 */
587 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
588 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
589 };
590
591 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
592 .name = "dss_dsi1",
593 .class = &omap3xxx_dsi_hwmod_class,
594 .main_clk = "dss1_alwon_fck",
595 .prcm = {
596 .omap2 = {
597 .module_offs = OMAP3430_DSS_MOD,
598 },
599 },
600 .opt_clks = dss_dsi1_opt_clks,
601 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
602 .flags = HWMOD_NO_IDLEST,
603 };
604
605 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
606 { .role = "ick", .clk = "dss_ick" },
607 };
608
609 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
610 .name = "dss_rfbi",
611 .class = &omap2_rfbi_hwmod_class,
612 .main_clk = "dss1_alwon_fck",
613 .prcm = {
614 .omap2 = {
615 .module_offs = OMAP3430_DSS_MOD,
616 },
617 },
618 .opt_clks = dss_rfbi_opt_clks,
619 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
620 .flags = HWMOD_NO_IDLEST,
621 };
622
623 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
624 /* required only on OMAP3430 */
625 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
626 };
627
628 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
629 .name = "dss_venc",
630 .class = &omap2_venc_hwmod_class,
631 .main_clk = "dss_tv_fck",
632 .prcm = {
633 .omap2 = {
634 .module_offs = OMAP3430_DSS_MOD,
635 },
636 },
637 .opt_clks = dss_venc_opt_clks,
638 .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks),
639 .flags = HWMOD_NO_IDLEST,
640 };
641
642 /* I2C1 */
643 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
644 .name = "i2c1",
645 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
646 .main_clk = "i2c1_fck",
647 .prcm = {
648 .omap2 = {
649 .module_offs = CORE_MOD,
650 .idlest_reg_id = 1,
651 .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
652 },
653 },
654 .class = &i2c_class,
655 };
656
657 /* I2C2 */
658 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
659 .name = "i2c2",
660 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
661 .main_clk = "i2c2_fck",
662 .prcm = {
663 .omap2 = {
664 .module_offs = CORE_MOD,
665 .idlest_reg_id = 1,
666 .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
667 },
668 },
669 .class = &i2c_class,
670 };
671
672 /* I2C3 */
673 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
674 .name = "i2c3",
675 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
676 .main_clk = "i2c3_fck",
677 .prcm = {
678 .omap2 = {
679 .module_offs = CORE_MOD,
680 .idlest_reg_id = 1,
681 .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
682 },
683 },
684 .class = &i2c_class,
685 };
686
687 /*
688 * 'gpio' class
689 * general purpose io module
690 */
691
692 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
693 .rev_offs = 0x0000,
694 .sysc_offs = 0x0010,
695 .syss_offs = 0x0014,
696 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
697 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
698 SYSS_HAS_RESET_STATUS),
699 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
700 .sysc_fields = &omap_hwmod_sysc_type1,
701 };
702
703 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
704 .name = "gpio",
705 .sysc = &omap3xxx_gpio_sysc,
706 };
707
708 /* gpio1 */
709 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
710 { .role = "dbclk", .clk = "gpio1_dbck", },
711 };
712
713 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
714 .name = "gpio1",
715 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
716 .main_clk = "gpio1_ick",
717 .opt_clks = gpio1_opt_clks,
718 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
719 .prcm = {
720 .omap2 = {
721 .module_offs = WKUP_MOD,
722 .idlest_reg_id = 1,
723 .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
724 },
725 },
726 .class = &omap3xxx_gpio_hwmod_class,
727 };
728
729 /* gpio2 */
730 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
731 { .role = "dbclk", .clk = "gpio2_dbck", },
732 };
733
734 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
735 .name = "gpio2",
736 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
737 .main_clk = "gpio2_ick",
738 .opt_clks = gpio2_opt_clks,
739 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
740 .prcm = {
741 .omap2 = {
742 .module_offs = OMAP3430_PER_MOD,
743 .idlest_reg_id = 1,
744 .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
745 },
746 },
747 .class = &omap3xxx_gpio_hwmod_class,
748 };
749
750 /* gpio3 */
751 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
752 { .role = "dbclk", .clk = "gpio3_dbck", },
753 };
754
755 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
756 .name = "gpio3",
757 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
758 .main_clk = "gpio3_ick",
759 .opt_clks = gpio3_opt_clks,
760 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
761 .prcm = {
762 .omap2 = {
763 .module_offs = OMAP3430_PER_MOD,
764 .idlest_reg_id = 1,
765 .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
766 },
767 },
768 .class = &omap3xxx_gpio_hwmod_class,
769 };
770
771 /* gpio4 */
772 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
773 { .role = "dbclk", .clk = "gpio4_dbck", },
774 };
775
776 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
777 .name = "gpio4",
778 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
779 .main_clk = "gpio4_ick",
780 .opt_clks = gpio4_opt_clks,
781 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
782 .prcm = {
783 .omap2 = {
784 .module_offs = OMAP3430_PER_MOD,
785 .idlest_reg_id = 1,
786 .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
787 },
788 },
789 .class = &omap3xxx_gpio_hwmod_class,
790 };
791
792 /* gpio5 */
793
794 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
795 { .role = "dbclk", .clk = "gpio5_dbck", },
796 };
797
798 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
799 .name = "gpio5",
800 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
801 .main_clk = "gpio5_ick",
802 .opt_clks = gpio5_opt_clks,
803 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
804 .prcm = {
805 .omap2 = {
806 .module_offs = OMAP3430_PER_MOD,
807 .idlest_reg_id = 1,
808 .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
809 },
810 },
811 .class = &omap3xxx_gpio_hwmod_class,
812 };
813
814 /* gpio6 */
815
816 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
817 { .role = "dbclk", .clk = "gpio6_dbck", },
818 };
819
820 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
821 .name = "gpio6",
822 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
823 .main_clk = "gpio6_ick",
824 .opt_clks = gpio6_opt_clks,
825 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
826 .prcm = {
827 .omap2 = {
828 .module_offs = OMAP3430_PER_MOD,
829 .idlest_reg_id = 1,
830 .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
831 },
832 },
833 .class = &omap3xxx_gpio_hwmod_class,
834 };
835
836 /* dma attributes */
837 static struct omap_dma_dev_attr dma_dev_attr = {
838 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
839 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
840 .lch_count = 32,
841 };
842
843 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
844 .rev_offs = 0x0000,
845 .sysc_offs = 0x002c,
846 .syss_offs = 0x0028,
847 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
848 SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
849 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
850 SYSS_HAS_RESET_STATUS),
851 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
852 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
853 .sysc_fields = &omap_hwmod_sysc_type1,
854 };
855
856 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
857 .name = "dma",
858 .sysc = &omap3xxx_dma_sysc,
859 };
860
861 /* dma_system */
862 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
863 .name = "dma",
864 .class = &omap3xxx_dma_hwmod_class,
865 .main_clk = "core_l3_ick",
866 .prcm = {
867 .omap2 = {
868 .module_offs = CORE_MOD,
869 .idlest_reg_id = 1,
870 .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT,
871 },
872 },
873 .dev_attr = &dma_dev_attr,
874 .flags = HWMOD_NO_IDLEST,
875 };
876
877 /*
878 * 'mcbsp' class
879 * multi channel buffered serial port controller
880 */
881
882 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
883 .rev_offs = -ENODEV,
884 .sysc_offs = 0x008c,
885 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
886 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
887 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
888 .sysc_fields = &omap_hwmod_sysc_type1,
889 };
890
891 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
892 .name = "mcbsp",
893 .sysc = &omap3xxx_mcbsp_sysc,
894 };
895
896 /* McBSP functional clock mapping */
897 static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = {
898 { .role = "pad_fck", .clk = "mcbsp_clks" },
899 { .role = "prcm_fck", .clk = "core_96m_fck" },
900 };
901
902 static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = {
903 { .role = "pad_fck", .clk = "mcbsp_clks" },
904 { .role = "prcm_fck", .clk = "per_96m_fck" },
905 };
906
907 /* mcbsp1 */
908 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
909 .name = "mcbsp1",
910 .class = &omap3xxx_mcbsp_hwmod_class,
911 .main_clk = "mcbsp1_fck",
912 .prcm = {
913 .omap2 = {
914 .module_offs = CORE_MOD,
915 .idlest_reg_id = 1,
916 .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
917 },
918 },
919 .opt_clks = mcbsp15_opt_clks,
920 .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks),
921 };
922
923 /* mcbsp2 */
924 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
925 .name = "mcbsp2",
926 .class = &omap3xxx_mcbsp_hwmod_class,
927 .main_clk = "mcbsp2_fck",
928 .prcm = {
929 .omap2 = {
930 .module_offs = OMAP3430_PER_MOD,
931 .idlest_reg_id = 1,
932 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
933 },
934 },
935 .opt_clks = mcbsp234_opt_clks,
936 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
937 };
938
939 /* mcbsp3 */
940 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
941 .name = "mcbsp3",
942 .class = &omap3xxx_mcbsp_hwmod_class,
943 .main_clk = "mcbsp3_fck",
944 .prcm = {
945 .omap2 = {
946 .module_offs = OMAP3430_PER_MOD,
947 .idlest_reg_id = 1,
948 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
949 },
950 },
951 .opt_clks = mcbsp234_opt_clks,
952 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
953 };
954
955 /* mcbsp4 */
956 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
957 .name = "mcbsp4",
958 .class = &omap3xxx_mcbsp_hwmod_class,
959 .main_clk = "mcbsp4_fck",
960 .prcm = {
961 .omap2 = {
962 .module_offs = OMAP3430_PER_MOD,
963 .idlest_reg_id = 1,
964 .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
965 },
966 },
967 .opt_clks = mcbsp234_opt_clks,
968 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
969 };
970
971 /* mcbsp5 */
972 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
973 .name = "mcbsp5",
974 .class = &omap3xxx_mcbsp_hwmod_class,
975 .main_clk = "mcbsp5_fck",
976 .prcm = {
977 .omap2 = {
978 .module_offs = CORE_MOD,
979 .idlest_reg_id = 1,
980 .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
981 },
982 },
983 .opt_clks = mcbsp15_opt_clks,
984 .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks),
985 };
986
987 /* 'mcbsp sidetone' class */
988 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
989 .rev_offs = -ENODEV,
990 .sysc_offs = 0x0010,
991 .sysc_flags = SYSC_HAS_AUTOIDLE,
992 .sysc_fields = &omap_hwmod_sysc_type1,
993 };
994
995 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
996 .name = "mcbsp_sidetone",
997 .sysc = &omap3xxx_mcbsp_sidetone_sysc,
998 };
999
1000 /* mcbsp2_sidetone */
1001 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
1002 .name = "mcbsp2_sidetone",
1003 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
1004 .main_clk = "mcbsp2_ick",
1005 .flags = HWMOD_NO_IDLEST,
1006 };
1007
1008 /* mcbsp3_sidetone */
1009 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
1010 .name = "mcbsp3_sidetone",
1011 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
1012 .main_clk = "mcbsp3_ick",
1013 .flags = HWMOD_NO_IDLEST,
1014 };
1015
1016 /* SR common */
1017 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
1018 .rev_offs = -ENODEV,
1019 .sysc_offs = 0x24,
1020 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
1021 .sysc_fields = &omap34xx_sr_sysc_fields,
1022 };
1023
1024 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
1025 .name = "smartreflex",
1026 .sysc = &omap34xx_sr_sysc,
1027 };
1028
1029 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
1030 .rev_offs = -ENODEV,
1031 .sysc_offs = 0x38,
1032 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1033 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1034 SYSC_NO_CACHE),
1035 .sysc_fields = &omap36xx_sr_sysc_fields,
1036 };
1037
1038 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
1039 .name = "smartreflex",
1040 .sysc = &omap36xx_sr_sysc,
1041 };
1042
1043 /* SR1 */
1044 static struct omap_smartreflex_dev_attr sr1_dev_attr = {
1045 .sensor_voltdm_name = "mpu_iva",
1046 };
1047
1048
1049 static struct omap_hwmod omap34xx_sr1_hwmod = {
1050 .name = "smartreflex_mpu_iva",
1051 .class = &omap34xx_smartreflex_hwmod_class,
1052 .main_clk = "sr1_fck",
1053 .prcm = {
1054 .omap2 = {
1055 .module_offs = WKUP_MOD,
1056 .idlest_reg_id = 1,
1057 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1058 },
1059 },
1060 .dev_attr = &sr1_dev_attr,
1061 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1062 };
1063
1064 static struct omap_hwmod omap36xx_sr1_hwmod = {
1065 .name = "smartreflex_mpu_iva",
1066 .class = &omap36xx_smartreflex_hwmod_class,
1067 .main_clk = "sr1_fck",
1068 .prcm = {
1069 .omap2 = {
1070 .module_offs = WKUP_MOD,
1071 .idlest_reg_id = 1,
1072 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1073 },
1074 },
1075 .dev_attr = &sr1_dev_attr,
1076 };
1077
1078 /* SR2 */
1079 static struct omap_smartreflex_dev_attr sr2_dev_attr = {
1080 .sensor_voltdm_name = "core",
1081 };
1082
1083
1084 static struct omap_hwmod omap34xx_sr2_hwmod = {
1085 .name = "smartreflex_core",
1086 .class = &omap34xx_smartreflex_hwmod_class,
1087 .main_clk = "sr2_fck",
1088 .prcm = {
1089 .omap2 = {
1090 .module_offs = WKUP_MOD,
1091 .idlest_reg_id = 1,
1092 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1093 },
1094 },
1095 .dev_attr = &sr2_dev_attr,
1096 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1097 };
1098
1099 static struct omap_hwmod omap36xx_sr2_hwmod = {
1100 .name = "smartreflex_core",
1101 .class = &omap36xx_smartreflex_hwmod_class,
1102 .main_clk = "sr2_fck",
1103 .prcm = {
1104 .omap2 = {
1105 .module_offs = WKUP_MOD,
1106 .idlest_reg_id = 1,
1107 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1108 },
1109 },
1110 .dev_attr = &sr2_dev_attr,
1111 };
1112
1113 /*
1114 * 'mailbox' class
1115 * mailbox module allowing communication between the on-chip processors
1116 * using a queued mailbox-interrupt mechanism.
1117 */
1118
1119 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
1120 .rev_offs = 0x000,
1121 .sysc_offs = 0x010,
1122 .syss_offs = 0x014,
1123 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1124 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1125 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1126 .sysc_fields = &omap_hwmod_sysc_type1,
1127 };
1128
1129 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
1130 .name = "mailbox",
1131 .sysc = &omap3xxx_mailbox_sysc,
1132 };
1133
1134 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
1135 .name = "mailbox",
1136 .class = &omap3xxx_mailbox_hwmod_class,
1137 .main_clk = "mailboxes_ick",
1138 .prcm = {
1139 .omap2 = {
1140 .module_offs = CORE_MOD,
1141 .idlest_reg_id = 1,
1142 .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
1143 },
1144 },
1145 };
1146
1147 /*
1148 * 'mcspi' class
1149 * multichannel serial port interface (mcspi) / master/slave synchronous serial
1150 * bus
1151 */
1152
1153 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
1154 .rev_offs = 0x0000,
1155 .sysc_offs = 0x0010,
1156 .syss_offs = 0x0014,
1157 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1158 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1159 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1160 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1161 .sysc_fields = &omap_hwmod_sysc_type1,
1162 };
1163
1164 static struct omap_hwmod_class omap34xx_mcspi_class = {
1165 .name = "mcspi",
1166 .sysc = &omap34xx_mcspi_sysc,
1167 };
1168
1169 /* mcspi1 */
1170 static struct omap_hwmod omap34xx_mcspi1 = {
1171 .name = "mcspi1",
1172 .main_clk = "mcspi1_fck",
1173 .prcm = {
1174 .omap2 = {
1175 .module_offs = CORE_MOD,
1176 .idlest_reg_id = 1,
1177 .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
1178 },
1179 },
1180 .class = &omap34xx_mcspi_class,
1181 };
1182
1183 /* mcspi2 */
1184 static struct omap_hwmod omap34xx_mcspi2 = {
1185 .name = "mcspi2",
1186 .main_clk = "mcspi2_fck",
1187 .prcm = {
1188 .omap2 = {
1189 .module_offs = CORE_MOD,
1190 .idlest_reg_id = 1,
1191 .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
1192 },
1193 },
1194 .class = &omap34xx_mcspi_class,
1195 };
1196
1197 /* mcspi3 */
1198 static struct omap_hwmod omap34xx_mcspi3 = {
1199 .name = "mcspi3",
1200 .main_clk = "mcspi3_fck",
1201 .prcm = {
1202 .omap2 = {
1203 .module_offs = CORE_MOD,
1204 .idlest_reg_id = 1,
1205 .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
1206 },
1207 },
1208 .class = &omap34xx_mcspi_class,
1209 };
1210
1211 /* mcspi4 */
1212 static struct omap_hwmod omap34xx_mcspi4 = {
1213 .name = "mcspi4",
1214 .main_clk = "mcspi4_fck",
1215 .prcm = {
1216 .omap2 = {
1217 .module_offs = CORE_MOD,
1218 .idlest_reg_id = 1,
1219 .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
1220 },
1221 },
1222 .class = &omap34xx_mcspi_class,
1223 };
1224
1225 /* usbhsotg */
1226 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
1227 .rev_offs = 0x0400,
1228 .sysc_offs = 0x0404,
1229 .syss_offs = 0x0408,
1230 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
1231 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1232 SYSC_HAS_AUTOIDLE),
1233 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1234 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1235 .sysc_fields = &omap_hwmod_sysc_type1,
1236 };
1237
1238 static struct omap_hwmod_class usbotg_class = {
1239 .name = "usbotg",
1240 .sysc = &omap3xxx_usbhsotg_sysc,
1241 };
1242
1243 /* usb_otg_hs */
1244
1245 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
1246 .name = "usb_otg_hs",
1247 .main_clk = "hsotgusb_ick",
1248 .prcm = {
1249 .omap2 = {
1250 .module_offs = CORE_MOD,
1251 .idlest_reg_id = 1,
1252 .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
1253 },
1254 },
1255 .class = &usbotg_class,
1256
1257 /*
1258 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
1259 * broken when autoidle is enabled
1260 * workaround is to disable the autoidle bit at module level.
1261 *
1262 * Enabling the device in any other MIDLEMODE setting but force-idle
1263 * causes core_pwrdm not enter idle states at least on OMAP3630.
1264 * Note that musb has OTG_FORCESTDBY register that controls MSTANDBY
1265 * signal when MIDLEMODE is set to force-idle.
1266 */
1267 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE |
1268 HWMOD_FORCE_MSTANDBY | HWMOD_RECONFIG_IO_CHAIN,
1269 };
1270
1271 /* usb_otg_hs */
1272
1273 static struct omap_hwmod_class am35xx_usbotg_class = {
1274 .name = "am35xx_usbotg",
1275 };
1276
1277 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
1278 .name = "am35x_otg_hs",
1279 .main_clk = "hsotgusb_fck",
1280 .class = &am35xx_usbotg_class,
1281 .flags = HWMOD_NO_IDLEST,
1282 };
1283
1284 /* MMC/SD/SDIO common */
1285 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
1286 .rev_offs = 0x1fc,
1287 .sysc_offs = 0x10,
1288 .syss_offs = 0x14,
1289 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1290 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1291 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1292 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1293 .sysc_fields = &omap_hwmod_sysc_type1,
1294 };
1295
1296 static struct omap_hwmod_class omap34xx_mmc_class = {
1297 .name = "mmc",
1298 .sysc = &omap34xx_mmc_sysc,
1299 };
1300
1301 /* MMC/SD/SDIO1 */
1302
1303
1304
1305 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
1306 { .role = "dbck", .clk = "omap_32k_fck", },
1307 };
1308
1309 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
1310 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1311 };
1312
1313 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1314 static struct omap_hsmmc_dev_attr mmc1_pre_es3_dev_attr = {
1315 .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
1316 OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
1317 };
1318
1319 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
1320 .name = "mmc1",
1321 .opt_clks = omap34xx_mmc1_opt_clks,
1322 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1323 .main_clk = "mmchs1_fck",
1324 .prcm = {
1325 .omap2 = {
1326 .module_offs = CORE_MOD,
1327 .idlest_reg_id = 1,
1328 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1329 },
1330 },
1331 .dev_attr = &mmc1_pre_es3_dev_attr,
1332 .class = &omap34xx_mmc_class,
1333 };
1334
1335 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
1336 .name = "mmc1",
1337 .opt_clks = omap34xx_mmc1_opt_clks,
1338 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1339 .main_clk = "mmchs1_fck",
1340 .prcm = {
1341 .omap2 = {
1342 .module_offs = CORE_MOD,
1343 .idlest_reg_id = 1,
1344 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1345 },
1346 },
1347 .dev_attr = &mmc1_dev_attr,
1348 .class = &omap34xx_mmc_class,
1349 };
1350
1351 /* MMC/SD/SDIO2 */
1352
1353
1354
1355 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
1356 { .role = "dbck", .clk = "omap_32k_fck", },
1357 };
1358
1359 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1360 static struct omap_hsmmc_dev_attr mmc2_pre_es3_dev_attr = {
1361 .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1362 };
1363
1364 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
1365 .name = "mmc2",
1366 .opt_clks = omap34xx_mmc2_opt_clks,
1367 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1368 .main_clk = "mmchs2_fck",
1369 .prcm = {
1370 .omap2 = {
1371 .module_offs = CORE_MOD,
1372 .idlest_reg_id = 1,
1373 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1374 },
1375 },
1376 .dev_attr = &mmc2_pre_es3_dev_attr,
1377 .class = &omap34xx_mmc_class,
1378 };
1379
1380 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
1381 .name = "mmc2",
1382 .opt_clks = omap34xx_mmc2_opt_clks,
1383 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1384 .main_clk = "mmchs2_fck",
1385 .prcm = {
1386 .omap2 = {
1387 .module_offs = CORE_MOD,
1388 .idlest_reg_id = 1,
1389 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1390 },
1391 },
1392 .class = &omap34xx_mmc_class,
1393 };
1394
1395 /* MMC/SD/SDIO3 */
1396
1397
1398
1399 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
1400 { .role = "dbck", .clk = "omap_32k_fck", },
1401 };
1402
1403 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
1404 .name = "mmc3",
1405 .opt_clks = omap34xx_mmc3_opt_clks,
1406 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
1407 .main_clk = "mmchs3_fck",
1408 .prcm = {
1409 .omap2 = {
1410 .module_offs = CORE_MOD,
1411 .idlest_reg_id = 1,
1412 .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
1413 },
1414 },
1415 .class = &omap34xx_mmc_class,
1416 };
1417
1418 /*
1419 * 'usb_host_hs' class
1420 * high-speed multi-port usb host controller
1421 */
1422
1423 static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
1424 .rev_offs = 0x0000,
1425 .sysc_offs = 0x0010,
1426 .syss_offs = 0x0014,
1427 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1428 SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1429 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1430 SYSS_HAS_RESET_STATUS),
1431 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1432 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1433 .sysc_fields = &omap_hwmod_sysc_type1,
1434 };
1435
1436 static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
1437 .name = "usb_host_hs",
1438 .sysc = &omap3xxx_usb_host_hs_sysc,
1439 };
1440
1441
1442 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
1443 .name = "usb_host_hs",
1444 .class = &omap3xxx_usb_host_hs_hwmod_class,
1445 .clkdm_name = "usbhost_clkdm",
1446 .main_clk = "usbhost_48m_fck",
1447 .prcm = {
1448 .omap2 = {
1449 .module_offs = OMAP3430ES2_USBHOST_MOD,
1450 .idlest_reg_id = 1,
1451 .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
1452 },
1453 },
1454
1455 /*
1456 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1457 * id: i660
1458 *
1459 * Description:
1460 * In the following configuration :
1461 * - USBHOST module is set to smart-idle mode
1462 * - PRCM asserts idle_req to the USBHOST module ( This typically
1463 * happens when the system is going to a low power mode : all ports
1464 * have been suspended, the master part of the USBHOST module has
1465 * entered the standby state, and SW has cut the functional clocks)
1466 * - an USBHOST interrupt occurs before the module is able to answer
1467 * idle_ack, typically a remote wakeup IRQ.
1468 * Then the USB HOST module will enter a deadlock situation where it
1469 * is no more accessible nor functional.
1470 *
1471 * Workaround:
1472 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1473 */
1474
1475 /*
1476 * Errata: USB host EHCI may stall when entering smart-standby mode
1477 * Id: i571
1478 *
1479 * Description:
1480 * When the USBHOST module is set to smart-standby mode, and when it is
1481 * ready to enter the standby state (i.e. all ports are suspended and
1482 * all attached devices are in suspend mode), then it can wrongly assert
1483 * the Mstandby signal too early while there are still some residual OCP
1484 * transactions ongoing. If this condition occurs, the internal state
1485 * machine may go to an undefined state and the USB link may be stuck
1486 * upon the next resume.
1487 *
1488 * Workaround:
1489 * Don't use smart standby; use only force standby,
1490 * hence HWMOD_SWSUP_MSTANDBY
1491 */
1492
1493 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1494 };
1495
1496 /*
1497 * 'usb_tll_hs' class
1498 * usb_tll_hs module is the adapter on the usb_host_hs ports
1499 */
1500 static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = {
1501 .rev_offs = 0x0000,
1502 .sysc_offs = 0x0010,
1503 .syss_offs = 0x0014,
1504 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1505 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1506 SYSC_HAS_AUTOIDLE),
1507 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1508 .sysc_fields = &omap_hwmod_sysc_type1,
1509 };
1510
1511 static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
1512 .name = "usb_tll_hs",
1513 .sysc = &omap3xxx_usb_tll_hs_sysc,
1514 };
1515
1516
1517 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
1518 .name = "usb_tll_hs",
1519 .class = &omap3xxx_usb_tll_hs_hwmod_class,
1520 .clkdm_name = "core_l4_clkdm",
1521 .main_clk = "usbtll_fck",
1522 .prcm = {
1523 .omap2 = {
1524 .module_offs = CORE_MOD,
1525 .idlest_reg_id = 3,
1526 .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
1527 },
1528 },
1529 };
1530
1531 static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
1532 .name = "hdq1w",
1533 .main_clk = "hdq_fck",
1534 .prcm = {
1535 .omap2 = {
1536 .module_offs = CORE_MOD,
1537 .idlest_reg_id = 1,
1538 .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT,
1539 },
1540 },
1541 .class = &omap2_hdq1w_class,
1542 };
1543
1544 /* SAD2D */
1545 static struct omap_hwmod_rst_info omap3xxx_sad2d_resets[] = {
1546 { .name = "rst_modem_pwron_sw", .rst_shift = 0 },
1547 { .name = "rst_modem_sw", .rst_shift = 1 },
1548 };
1549
1550 static struct omap_hwmod_class omap3xxx_sad2d_class = {
1551 .name = "sad2d",
1552 };
1553
1554 static struct omap_hwmod omap3xxx_sad2d_hwmod = {
1555 .name = "sad2d",
1556 .rst_lines = omap3xxx_sad2d_resets,
1557 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_sad2d_resets),
1558 .main_clk = "sad2d_ick",
1559 .prcm = {
1560 .omap2 = {
1561 .module_offs = CORE_MOD,
1562 .idlest_reg_id = 1,
1563 .idlest_idle_bit = OMAP3430_ST_SAD2D_SHIFT,
1564 },
1565 },
1566 .class = &omap3xxx_sad2d_class,
1567 };
1568
1569 /*
1570 * '32K sync counter' class
1571 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
1572 */
1573 static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = {
1574 .rev_offs = 0x0000,
1575 .sysc_offs = 0x0004,
1576 .sysc_flags = SYSC_HAS_SIDLEMODE,
1577 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
1578 .sysc_fields = &omap_hwmod_sysc_type1,
1579 };
1580
1581 static struct omap_hwmod_class omap3xxx_counter_hwmod_class = {
1582 .name = "counter",
1583 .sysc = &omap3xxx_counter_sysc,
1584 };
1585
1586 static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
1587 .name = "counter_32k",
1588 .class = &omap3xxx_counter_hwmod_class,
1589 .clkdm_name = "wkup_clkdm",
1590 .flags = HWMOD_SWSUP_SIDLE,
1591 .main_clk = "wkup_32k_fck",
1592 .prcm = {
1593 .omap2 = {
1594 .module_offs = WKUP_MOD,
1595 .idlest_reg_id = 1,
1596 .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT,
1597 },
1598 },
1599 };
1600
1601 /*
1602 * 'gpmc' class
1603 * general purpose memory controller
1604 */
1605
1606 static struct omap_hwmod_class_sysconfig omap3xxx_gpmc_sysc = {
1607 .rev_offs = 0x0000,
1608 .sysc_offs = 0x0010,
1609 .syss_offs = 0x0014,
1610 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1611 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1612 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1613 .sysc_fields = &omap_hwmod_sysc_type1,
1614 };
1615
1616 static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = {
1617 .name = "gpmc",
1618 .sysc = &omap3xxx_gpmc_sysc,
1619 };
1620
1621 static struct omap_hwmod omap3xxx_gpmc_hwmod = {
1622 .name = "gpmc",
1623 .class = &omap3xxx_gpmc_hwmod_class,
1624 .clkdm_name = "core_l3_clkdm",
1625 .main_clk = "gpmc_fck",
1626 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
1627 .flags = HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS,
1628 };
1629
1630 /*
1631 * interfaces
1632 */
1633
1634 /* L3 -> L4_CORE interface */
1635 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
1636 .master = &omap3xxx_l3_main_hwmod,
1637 .slave = &omap3xxx_l4_core_hwmod,
1638 .user = OCP_USER_MPU | OCP_USER_SDMA,
1639 };
1640
1641 /* L3 -> L4_PER interface */
1642 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
1643 .master = &omap3xxx_l3_main_hwmod,
1644 .slave = &omap3xxx_l4_per_hwmod,
1645 .user = OCP_USER_MPU | OCP_USER_SDMA,
1646 };
1647
1648
1649 /* MPU -> L3 interface */
1650 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
1651 .master = &omap3xxx_mpu_hwmod,
1652 .slave = &omap3xxx_l3_main_hwmod,
1653 .user = OCP_USER_MPU,
1654 };
1655
1656
1657 /* l3 -> debugss */
1658 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_debugss = {
1659 .master = &omap3xxx_l3_main_hwmod,
1660 .slave = &omap3xxx_debugss_hwmod,
1661 .user = OCP_USER_MPU,
1662 };
1663
1664 /* DSS -> l3 */
1665 static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = {
1666 .master = &omap3430es1_dss_core_hwmod,
1667 .slave = &omap3xxx_l3_main_hwmod,
1668 .user = OCP_USER_MPU | OCP_USER_SDMA,
1669 };
1670
1671 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
1672 .master = &omap3xxx_dss_core_hwmod,
1673 .slave = &omap3xxx_l3_main_hwmod,
1674 .fw = {
1675 .omap2 = {
1676 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS,
1677 .flags = OMAP_FIREWALL_L3,
1678 },
1679 },
1680 .user = OCP_USER_MPU | OCP_USER_SDMA,
1681 };
1682
1683 /* l3_core -> usbhsotg interface */
1684 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
1685 .master = &omap3xxx_usbhsotg_hwmod,
1686 .slave = &omap3xxx_l3_main_hwmod,
1687 .clk = "core_l3_ick",
1688 .user = OCP_USER_MPU,
1689 };
1690
1691 /* l3_core -> am35xx_usbhsotg interface */
1692 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
1693 .master = &am35xx_usbhsotg_hwmod,
1694 .slave = &omap3xxx_l3_main_hwmod,
1695 .clk = "hsotgusb_ick",
1696 .user = OCP_USER_MPU,
1697 };
1698
1699 /* l3_core -> sad2d interface */
1700 static struct omap_hwmod_ocp_if omap3xxx_sad2d__l3 = {
1701 .master = &omap3xxx_sad2d_hwmod,
1702 .slave = &omap3xxx_l3_main_hwmod,
1703 .clk = "core_l3_ick",
1704 .user = OCP_USER_MPU,
1705 };
1706
1707 /* L4_CORE -> L4_WKUP interface */
1708 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
1709 .master = &omap3xxx_l4_core_hwmod,
1710 .slave = &omap3xxx_l4_wkup_hwmod,
1711 .user = OCP_USER_MPU | OCP_USER_SDMA,
1712 };
1713
1714 /* L4 CORE -> MMC1 interface */
1715 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = {
1716 .master = &omap3xxx_l4_core_hwmod,
1717 .slave = &omap3xxx_pre_es3_mmc1_hwmod,
1718 .clk = "mmchs1_ick",
1719 .user = OCP_USER_MPU | OCP_USER_SDMA,
1720 .flags = OMAP_FIREWALL_L4,
1721 };
1722
1723 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = {
1724 .master = &omap3xxx_l4_core_hwmod,
1725 .slave = &omap3xxx_es3plus_mmc1_hwmod,
1726 .clk = "mmchs1_ick",
1727 .user = OCP_USER_MPU | OCP_USER_SDMA,
1728 .flags = OMAP_FIREWALL_L4,
1729 };
1730
1731 /* L4 CORE -> MMC2 interface */
1732 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = {
1733 .master = &omap3xxx_l4_core_hwmod,
1734 .slave = &omap3xxx_pre_es3_mmc2_hwmod,
1735 .clk = "mmchs2_ick",
1736 .user = OCP_USER_MPU | OCP_USER_SDMA,
1737 .flags = OMAP_FIREWALL_L4,
1738 };
1739
1740 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = {
1741 .master = &omap3xxx_l4_core_hwmod,
1742 .slave = &omap3xxx_es3plus_mmc2_hwmod,
1743 .clk = "mmchs2_ick",
1744 .user = OCP_USER_MPU | OCP_USER_SDMA,
1745 .flags = OMAP_FIREWALL_L4,
1746 };
1747
1748 /* L4 CORE -> MMC3 interface */
1749
1750 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
1751 .master = &omap3xxx_l4_core_hwmod,
1752 .slave = &omap3xxx_mmc3_hwmod,
1753 .clk = "mmchs3_ick",
1754 .user = OCP_USER_MPU | OCP_USER_SDMA,
1755 .flags = OMAP_FIREWALL_L4,
1756 };
1757
1758 /* L4 CORE -> UART1 interface */
1759
1760 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
1761 .master = &omap3xxx_l4_core_hwmod,
1762 .slave = &omap3xxx_uart1_hwmod,
1763 .clk = "uart1_ick",
1764 .user = OCP_USER_MPU | OCP_USER_SDMA,
1765 };
1766
1767 /* L4 CORE -> UART2 interface */
1768
1769 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
1770 .master = &omap3xxx_l4_core_hwmod,
1771 .slave = &omap3xxx_uart2_hwmod,
1772 .clk = "uart2_ick",
1773 .user = OCP_USER_MPU | OCP_USER_SDMA,
1774 };
1775
1776 /* L4 PER -> UART3 interface */
1777
1778 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
1779 .master = &omap3xxx_l4_per_hwmod,
1780 .slave = &omap3xxx_uart3_hwmod,
1781 .clk = "uart3_ick",
1782 .user = OCP_USER_MPU | OCP_USER_SDMA,
1783 };
1784
1785 /* L4 PER -> UART4 interface */
1786
1787 static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
1788 .master = &omap3xxx_l4_per_hwmod,
1789 .slave = &omap36xx_uart4_hwmod,
1790 .clk = "uart4_ick",
1791 .user = OCP_USER_MPU | OCP_USER_SDMA,
1792 };
1793
1794 /* AM35xx: L4 CORE -> UART4 interface */
1795
1796 static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
1797 .master = &omap3xxx_l4_core_hwmod,
1798 .slave = &am35xx_uart4_hwmod,
1799 .clk = "uart4_ick",
1800 .user = OCP_USER_MPU | OCP_USER_SDMA,
1801 };
1802
1803 /* L4 CORE -> I2C1 interface */
1804 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
1805 .master = &omap3xxx_l4_core_hwmod,
1806 .slave = &omap3xxx_i2c1_hwmod,
1807 .clk = "i2c1_ick",
1808 .fw = {
1809 .omap2 = {
1810 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
1811 .l4_prot_group = 7,
1812 .flags = OMAP_FIREWALL_L4,
1813 },
1814 },
1815 .user = OCP_USER_MPU | OCP_USER_SDMA,
1816 };
1817
1818 /* L4 CORE -> I2C2 interface */
1819 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
1820 .master = &omap3xxx_l4_core_hwmod,
1821 .slave = &omap3xxx_i2c2_hwmod,
1822 .clk = "i2c2_ick",
1823 .fw = {
1824 .omap2 = {
1825 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
1826 .l4_prot_group = 7,
1827 .flags = OMAP_FIREWALL_L4,
1828 },
1829 },
1830 .user = OCP_USER_MPU | OCP_USER_SDMA,
1831 };
1832
1833 /* L4 CORE -> I2C3 interface */
1834
1835 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
1836 .master = &omap3xxx_l4_core_hwmod,
1837 .slave = &omap3xxx_i2c3_hwmod,
1838 .clk = "i2c3_ick",
1839 .fw = {
1840 .omap2 = {
1841 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
1842 .l4_prot_group = 7,
1843 .flags = OMAP_FIREWALL_L4,
1844 },
1845 },
1846 .user = OCP_USER_MPU | OCP_USER_SDMA,
1847 };
1848
1849 /* L4 CORE -> SR1 interface */
1850 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
1851 .master = &omap3xxx_l4_core_hwmod,
1852 .slave = &omap34xx_sr1_hwmod,
1853 .clk = "sr_l4_ick",
1854 .user = OCP_USER_MPU,
1855 };
1856
1857 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
1858 .master = &omap3xxx_l4_core_hwmod,
1859 .slave = &omap36xx_sr1_hwmod,
1860 .clk = "sr_l4_ick",
1861 .user = OCP_USER_MPU,
1862 };
1863
1864 /* L4 CORE -> SR2 interface */
1865
1866 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
1867 .master = &omap3xxx_l4_core_hwmod,
1868 .slave = &omap34xx_sr2_hwmod,
1869 .clk = "sr_l4_ick",
1870 .user = OCP_USER_MPU,
1871 };
1872
1873 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
1874 .master = &omap3xxx_l4_core_hwmod,
1875 .slave = &omap36xx_sr2_hwmod,
1876 .clk = "sr_l4_ick",
1877 .user = OCP_USER_MPU,
1878 };
1879
1880
1881 /* l4_core -> usbhsotg */
1882 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
1883 .master = &omap3xxx_l4_core_hwmod,
1884 .slave = &omap3xxx_usbhsotg_hwmod,
1885 .clk = "l4_ick",
1886 .user = OCP_USER_MPU,
1887 };
1888
1889
1890 /* l4_core -> usbhsotg */
1891 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
1892 .master = &omap3xxx_l4_core_hwmod,
1893 .slave = &am35xx_usbhsotg_hwmod,
1894 .clk = "hsotgusb_ick",
1895 .user = OCP_USER_MPU,
1896 };
1897
1898 /* L4_WKUP -> L4_SEC interface */
1899 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = {
1900 .master = &omap3xxx_l4_wkup_hwmod,
1901 .slave = &omap3xxx_l4_sec_hwmod,
1902 .user = OCP_USER_MPU | OCP_USER_SDMA,
1903 };
1904
1905 /* IVA2 <- L3 interface */
1906 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
1907 .master = &omap3xxx_l3_main_hwmod,
1908 .slave = &omap3xxx_iva_hwmod,
1909 .clk = "core_l3_ick",
1910 .user = OCP_USER_MPU | OCP_USER_SDMA,
1911 };
1912
1913
1914 /* l4_wkup -> timer1 */
1915 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
1916 .master = &omap3xxx_l4_wkup_hwmod,
1917 .slave = &omap3xxx_timer1_hwmod,
1918 .clk = "gpt1_ick",
1919 .user = OCP_USER_MPU | OCP_USER_SDMA,
1920 };
1921
1922
1923 /* l4_per -> timer2 */
1924 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
1925 .master = &omap3xxx_l4_per_hwmod,
1926 .slave = &omap3xxx_timer2_hwmod,
1927 .clk = "gpt2_ick",
1928 .user = OCP_USER_MPU | OCP_USER_SDMA,
1929 };
1930
1931
1932 /* l4_per -> timer3 */
1933 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
1934 .master = &omap3xxx_l4_per_hwmod,
1935 .slave = &omap3xxx_timer3_hwmod,
1936 .clk = "gpt3_ick",
1937 .user = OCP_USER_MPU | OCP_USER_SDMA,
1938 };
1939
1940
1941 /* l4_per -> timer4 */
1942 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
1943 .master = &omap3xxx_l4_per_hwmod,
1944 .slave = &omap3xxx_timer4_hwmod,
1945 .clk = "gpt4_ick",
1946 .user = OCP_USER_MPU | OCP_USER_SDMA,
1947 };
1948
1949
1950 /* l4_per -> timer5 */
1951 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
1952 .master = &omap3xxx_l4_per_hwmod,
1953 .slave = &omap3xxx_timer5_hwmod,
1954 .clk = "gpt5_ick",
1955 .user = OCP_USER_MPU | OCP_USER_SDMA,
1956 };
1957
1958
1959 /* l4_per -> timer6 */
1960 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
1961 .master = &omap3xxx_l4_per_hwmod,
1962 .slave = &omap3xxx_timer6_hwmod,
1963 .clk = "gpt6_ick",
1964 .user = OCP_USER_MPU | OCP_USER_SDMA,
1965 };
1966
1967
1968 /* l4_per -> timer7 */
1969 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
1970 .master = &omap3xxx_l4_per_hwmod,
1971 .slave = &omap3xxx_timer7_hwmod,
1972 .clk = "gpt7_ick",
1973 .user = OCP_USER_MPU | OCP_USER_SDMA,
1974 };
1975
1976
1977 /* l4_per -> timer8 */
1978 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
1979 .master = &omap3xxx_l4_per_hwmod,
1980 .slave = &omap3xxx_timer8_hwmod,
1981 .clk = "gpt8_ick",
1982 .user = OCP_USER_MPU | OCP_USER_SDMA,
1983 };
1984
1985
1986 /* l4_per -> timer9 */
1987 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
1988 .master = &omap3xxx_l4_per_hwmod,
1989 .slave = &omap3xxx_timer9_hwmod,
1990 .clk = "gpt9_ick",
1991 .user = OCP_USER_MPU | OCP_USER_SDMA,
1992 };
1993
1994 /* l4_core -> timer10 */
1995 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
1996 .master = &omap3xxx_l4_core_hwmod,
1997 .slave = &omap3xxx_timer10_hwmod,
1998 .clk = "gpt10_ick",
1999 .user = OCP_USER_MPU | OCP_USER_SDMA,
2000 };
2001
2002 /* l4_core -> timer11 */
2003 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
2004 .master = &omap3xxx_l4_core_hwmod,
2005 .slave = &omap3xxx_timer11_hwmod,
2006 .clk = "gpt11_ick",
2007 .user = OCP_USER_MPU | OCP_USER_SDMA,
2008 };
2009
2010
2011 /* l4_core -> timer12 */
2012 static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
2013 .master = &omap3xxx_l4_sec_hwmod,
2014 .slave = &omap3xxx_timer12_hwmod,
2015 .clk = "gpt12_ick",
2016 .user = OCP_USER_MPU | OCP_USER_SDMA,
2017 };
2018
2019 /* l4_wkup -> wd_timer2 */
2020
2021 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
2022 .master = &omap3xxx_l4_wkup_hwmod,
2023 .slave = &omap3xxx_wd_timer2_hwmod,
2024 .clk = "wdt2_ick",
2025 .user = OCP_USER_MPU | OCP_USER_SDMA,
2026 };
2027
2028 /* l4_core -> dss */
2029 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
2030 .master = &omap3xxx_l4_core_hwmod,
2031 .slave = &omap3430es1_dss_core_hwmod,
2032 .clk = "dss_ick",
2033 .fw = {
2034 .omap2 = {
2035 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
2036 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2037 .flags = OMAP_FIREWALL_L4,
2038 },
2039 },
2040 .user = OCP_USER_MPU | OCP_USER_SDMA,
2041 };
2042
2043 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
2044 .master = &omap3xxx_l4_core_hwmod,
2045 .slave = &omap3xxx_dss_core_hwmod,
2046 .clk = "dss_ick",
2047 .fw = {
2048 .omap2 = {
2049 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
2050 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2051 .flags = OMAP_FIREWALL_L4,
2052 },
2053 },
2054 .user = OCP_USER_MPU | OCP_USER_SDMA,
2055 };
2056
2057 /* l4_core -> dss_dispc */
2058 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
2059 .master = &omap3xxx_l4_core_hwmod,
2060 .slave = &omap3xxx_dss_dispc_hwmod,
2061 .clk = "dss_ick",
2062 .fw = {
2063 .omap2 = {
2064 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
2065 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2066 .flags = OMAP_FIREWALL_L4,
2067 },
2068 },
2069 .user = OCP_USER_MPU | OCP_USER_SDMA,
2070 };
2071
2072 /* l4_core -> dss_dsi1 */
2073 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
2074 .master = &omap3xxx_l4_core_hwmod,
2075 .slave = &omap3xxx_dss_dsi1_hwmod,
2076 .clk = "dss_ick",
2077 .fw = {
2078 .omap2 = {
2079 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
2080 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2081 .flags = OMAP_FIREWALL_L4,
2082 },
2083 },
2084 .user = OCP_USER_MPU | OCP_USER_SDMA,
2085 };
2086
2087 /* l4_core -> dss_rfbi */
2088 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
2089 .master = &omap3xxx_l4_core_hwmod,
2090 .slave = &omap3xxx_dss_rfbi_hwmod,
2091 .clk = "dss_ick",
2092 .fw = {
2093 .omap2 = {
2094 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
2095 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
2096 .flags = OMAP_FIREWALL_L4,
2097 },
2098 },
2099 .user = OCP_USER_MPU | OCP_USER_SDMA,
2100 };
2101
2102 /* l4_core -> dss_venc */
2103 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
2104 .master = &omap3xxx_l4_core_hwmod,
2105 .slave = &omap3xxx_dss_venc_hwmod,
2106 .clk = "dss_ick",
2107 .fw = {
2108 .omap2 = {
2109 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
2110 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2111 .flags = OMAP_FIREWALL_L4,
2112 },
2113 },
2114 .flags = OCPIF_SWSUP_IDLE,
2115 .user = OCP_USER_MPU | OCP_USER_SDMA,
2116 };
2117
2118 /* l4_wkup -> gpio1 */
2119
2120 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
2121 .master = &omap3xxx_l4_wkup_hwmod,
2122 .slave = &omap3xxx_gpio1_hwmod,
2123 .user = OCP_USER_MPU | OCP_USER_SDMA,
2124 };
2125
2126 /* l4_per -> gpio2 */
2127
2128 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
2129 .master = &omap3xxx_l4_per_hwmod,
2130 .slave = &omap3xxx_gpio2_hwmod,
2131 .user = OCP_USER_MPU | OCP_USER_SDMA,
2132 };
2133
2134 /* l4_per -> gpio3 */
2135
2136 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
2137 .master = &omap3xxx_l4_per_hwmod,
2138 .slave = &omap3xxx_gpio3_hwmod,
2139 .user = OCP_USER_MPU | OCP_USER_SDMA,
2140 };
2141
2142 /*
2143 * 'mmu' class
2144 * The memory management unit performs virtual to physical address translation
2145 * for its requestors.
2146 */
2147
2148 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2149 .rev_offs = 0x000,
2150 .sysc_offs = 0x010,
2151 .syss_offs = 0x014,
2152 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2153 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2154 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2155 .sysc_fields = &omap_hwmod_sysc_type1,
2156 };
2157
2158 static struct omap_hwmod_class omap3xxx_mmu_hwmod_class = {
2159 .name = "mmu",
2160 .sysc = &mmu_sysc,
2161 };
2162
2163 /* mmu isp */
2164 static struct omap_hwmod omap3xxx_mmu_isp_hwmod;
2165
2166 /* l4_core -> mmu isp */
2167 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmu_isp = {
2168 .master = &omap3xxx_l4_core_hwmod,
2169 .slave = &omap3xxx_mmu_isp_hwmod,
2170 .user = OCP_USER_MPU | OCP_USER_SDMA,
2171 };
2172
2173 static struct omap_hwmod omap3xxx_mmu_isp_hwmod = {
2174 .name = "mmu_isp",
2175 .class = &omap3xxx_mmu_hwmod_class,
2176 .main_clk = "cam_ick",
2177 .flags = HWMOD_NO_IDLEST,
2178 };
2179
2180 /* mmu iva */
2181
2182 static struct omap_hwmod omap3xxx_mmu_iva_hwmod;
2183
2184 static struct omap_hwmod_rst_info omap3xxx_mmu_iva_resets[] = {
2185 { .name = "mmu", .rst_shift = 1, .st_shift = 9 },
2186 };
2187
2188 /* l3_main -> iva mmu */
2189 static struct omap_hwmod_ocp_if omap3xxx_l3_main__mmu_iva = {
2190 .master = &omap3xxx_l3_main_hwmod,
2191 .slave = &omap3xxx_mmu_iva_hwmod,
2192 .user = OCP_USER_MPU | OCP_USER_SDMA,
2193 };
2194
2195 static struct omap_hwmod omap3xxx_mmu_iva_hwmod = {
2196 .name = "mmu_iva",
2197 .class = &omap3xxx_mmu_hwmod_class,
2198 .clkdm_name = "iva2_clkdm",
2199 .rst_lines = omap3xxx_mmu_iva_resets,
2200 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_mmu_iva_resets),
2201 .main_clk = "iva2_ck",
2202 .prcm = {
2203 .omap2 = {
2204 .module_offs = OMAP3430_IVA2_MOD,
2205 .idlest_reg_id = 1,
2206 .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
2207 },
2208 },
2209 .flags = HWMOD_NO_IDLEST,
2210 };
2211
2212 /* l4_per -> gpio4 */
2213
2214 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
2215 .master = &omap3xxx_l4_per_hwmod,
2216 .slave = &omap3xxx_gpio4_hwmod,
2217 .user = OCP_USER_MPU | OCP_USER_SDMA,
2218 };
2219
2220 /* l4_per -> gpio5 */
2221
2222 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
2223 .master = &omap3xxx_l4_per_hwmod,
2224 .slave = &omap3xxx_gpio5_hwmod,
2225 .user = OCP_USER_MPU | OCP_USER_SDMA,
2226 };
2227
2228 /* l4_per -> gpio6 */
2229
2230 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
2231 .master = &omap3xxx_l4_per_hwmod,
2232 .slave = &omap3xxx_gpio6_hwmod,
2233 .user = OCP_USER_MPU | OCP_USER_SDMA,
2234 };
2235
2236 /* dma_system -> L3 */
2237 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2238 .master = &omap3xxx_dma_system_hwmod,
2239 .slave = &omap3xxx_l3_main_hwmod,
2240 .clk = "core_l3_ick",
2241 .user = OCP_USER_MPU | OCP_USER_SDMA,
2242 };
2243
2244 /* l4_cfg -> dma_system */
2245 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2246 .master = &omap3xxx_l4_core_hwmod,
2247 .slave = &omap3xxx_dma_system_hwmod,
2248 .clk = "core_l4_ick",
2249 .user = OCP_USER_MPU | OCP_USER_SDMA,
2250 };
2251
2252
2253 /* l4_core -> mcbsp1 */
2254 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2255 .master = &omap3xxx_l4_core_hwmod,
2256 .slave = &omap3xxx_mcbsp1_hwmod,
2257 .clk = "mcbsp1_ick",
2258 .user = OCP_USER_MPU | OCP_USER_SDMA,
2259 };
2260
2261
2262 /* l4_per -> mcbsp2 */
2263 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2264 .master = &omap3xxx_l4_per_hwmod,
2265 .slave = &omap3xxx_mcbsp2_hwmod,
2266 .clk = "mcbsp2_ick",
2267 .user = OCP_USER_MPU | OCP_USER_SDMA,
2268 };
2269
2270
2271 /* l4_per -> mcbsp3 */
2272 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2273 .master = &omap3xxx_l4_per_hwmod,
2274 .slave = &omap3xxx_mcbsp3_hwmod,
2275 .clk = "mcbsp3_ick",
2276 .user = OCP_USER_MPU | OCP_USER_SDMA,
2277 };
2278
2279
2280 /* l4_per -> mcbsp4 */
2281 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2282 .master = &omap3xxx_l4_per_hwmod,
2283 .slave = &omap3xxx_mcbsp4_hwmod,
2284 .clk = "mcbsp4_ick",
2285 .user = OCP_USER_MPU | OCP_USER_SDMA,
2286 };
2287
2288
2289 /* l4_core -> mcbsp5 */
2290 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2291 .master = &omap3xxx_l4_core_hwmod,
2292 .slave = &omap3xxx_mcbsp5_hwmod,
2293 .clk = "mcbsp5_ick",
2294 .user = OCP_USER_MPU | OCP_USER_SDMA,
2295 };
2296
2297
2298 /* l4_per -> mcbsp2_sidetone */
2299 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2300 .master = &omap3xxx_l4_per_hwmod,
2301 .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
2302 .clk = "mcbsp2_ick",
2303 .user = OCP_USER_MPU,
2304 };
2305
2306
2307 /* l4_per -> mcbsp3_sidetone */
2308 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2309 .master = &omap3xxx_l4_per_hwmod,
2310 .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
2311 .clk = "mcbsp3_ick",
2312 .user = OCP_USER_MPU,
2313 };
2314
2315 /* l4_core -> mailbox */
2316 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
2317 .master = &omap3xxx_l4_core_hwmod,
2318 .slave = &omap3xxx_mailbox_hwmod,
2319 .user = OCP_USER_MPU | OCP_USER_SDMA,
2320 };
2321
2322 /* l4 core -> mcspi1 interface */
2323 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
2324 .master = &omap3xxx_l4_core_hwmod,
2325 .slave = &omap34xx_mcspi1,
2326 .clk = "mcspi1_ick",
2327 .user = OCP_USER_MPU | OCP_USER_SDMA,
2328 };
2329
2330 /* l4 core -> mcspi2 interface */
2331 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
2332 .master = &omap3xxx_l4_core_hwmod,
2333 .slave = &omap34xx_mcspi2,
2334 .clk = "mcspi2_ick",
2335 .user = OCP_USER_MPU | OCP_USER_SDMA,
2336 };
2337
2338 /* l4 core -> mcspi3 interface */
2339 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
2340 .master = &omap3xxx_l4_core_hwmod,
2341 .slave = &omap34xx_mcspi3,
2342 .clk = "mcspi3_ick",
2343 .user = OCP_USER_MPU | OCP_USER_SDMA,
2344 };
2345
2346 /* l4 core -> mcspi4 interface */
2347
2348 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
2349 .master = &omap3xxx_l4_core_hwmod,
2350 .slave = &omap34xx_mcspi4,
2351 .clk = "mcspi4_ick",
2352 .user = OCP_USER_MPU | OCP_USER_SDMA,
2353 };
2354
2355 static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
2356 .master = &omap3xxx_usb_host_hs_hwmod,
2357 .slave = &omap3xxx_l3_main_hwmod,
2358 .clk = "core_l3_ick",
2359 .user = OCP_USER_MPU,
2360 };
2361
2362
2363 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
2364 .master = &omap3xxx_l4_core_hwmod,
2365 .slave = &omap3xxx_usb_host_hs_hwmod,
2366 .clk = "usbhost_ick",
2367 .user = OCP_USER_MPU | OCP_USER_SDMA,
2368 };
2369
2370
2371 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
2372 .master = &omap3xxx_l4_core_hwmod,
2373 .slave = &omap3xxx_usb_tll_hs_hwmod,
2374 .clk = "usbtll_ick",
2375 .user = OCP_USER_MPU | OCP_USER_SDMA,
2376 };
2377
2378 /* l4_core -> hdq1w interface */
2379 static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = {
2380 .master = &omap3xxx_l4_core_hwmod,
2381 .slave = &omap3xxx_hdq1w_hwmod,
2382 .clk = "hdq_ick",
2383 .user = OCP_USER_MPU | OCP_USER_SDMA,
2384 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
2385 };
2386
2387 /* l4_wkup -> 32ksync_counter */
2388
2389
2390 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
2391 .master = &omap3xxx_l4_wkup_hwmod,
2392 .slave = &omap3xxx_counter_32k_hwmod,
2393 .clk = "omap_32ksync_ick",
2394 .user = OCP_USER_MPU | OCP_USER_SDMA,
2395 };
2396
2397 /* am35xx has Davinci MDIO & EMAC */
2398 static struct omap_hwmod_class am35xx_mdio_class = {
2399 .name = "davinci_mdio",
2400 };
2401
2402 static struct omap_hwmod am35xx_mdio_hwmod = {
2403 .name = "davinci_mdio",
2404 .class = &am35xx_mdio_class,
2405 .flags = HWMOD_NO_IDLEST,
2406 };
2407
2408 /*
2409 * XXX Should be connected to an IPSS hwmod, not the L3 directly;
2410 * but this will probably require some additional hwmod core support,
2411 * so is left as a future to-do item.
2412 */
2413 static struct omap_hwmod_ocp_if am35xx_mdio__l3 = {
2414 .master = &am35xx_mdio_hwmod,
2415 .slave = &omap3xxx_l3_main_hwmod,
2416 .clk = "emac_fck",
2417 .user = OCP_USER_MPU,
2418 };
2419
2420 /* l4_core -> davinci mdio */
2421 /*
2422 * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
2423 * but this will probably require some additional hwmod core support,
2424 * so is left as a future to-do item.
2425 */
2426 static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = {
2427 .master = &omap3xxx_l4_core_hwmod,
2428 .slave = &am35xx_mdio_hwmod,
2429 .clk = "emac_fck",
2430 .user = OCP_USER_MPU,
2431 };
2432
2433 static struct omap_hwmod_class am35xx_emac_class = {
2434 .name = "davinci_emac",
2435 };
2436
2437 static struct omap_hwmod am35xx_emac_hwmod = {
2438 .name = "davinci_emac",
2439 .class = &am35xx_emac_class,
2440 /*
2441 * According to Mark Greer, the MPU will not return from WFI
2442 * when the EMAC signals an interrupt.
2443 * http://www.spinics.net/lists/arm-kernel/msg174734.html
2444 */
2445 .flags = (HWMOD_NO_IDLEST | HWMOD_BLOCK_WFI),
2446 };
2447
2448 /* l3_core -> davinci emac interface */
2449 /*
2450 * XXX Should be connected to an IPSS hwmod, not the L3 directly;
2451 * but this will probably require some additional hwmod core support,
2452 * so is left as a future to-do item.
2453 */
2454 static struct omap_hwmod_ocp_if am35xx_emac__l3 = {
2455 .master = &am35xx_emac_hwmod,
2456 .slave = &omap3xxx_l3_main_hwmod,
2457 .clk = "emac_ick",
2458 .user = OCP_USER_MPU,
2459 };
2460
2461 /* l4_core -> davinci emac */
2462 /*
2463 * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
2464 * but this will probably require some additional hwmod core support,
2465 * so is left as a future to-do item.
2466 */
2467 static struct omap_hwmod_ocp_if am35xx_l4_core__emac = {
2468 .master = &omap3xxx_l4_core_hwmod,
2469 .slave = &am35xx_emac_hwmod,
2470 .clk = "emac_ick",
2471 .user = OCP_USER_MPU,
2472 };
2473
2474 static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = {
2475 .master = &omap3xxx_l3_main_hwmod,
2476 .slave = &omap3xxx_gpmc_hwmod,
2477 .clk = "core_l3_ick",
2478 .user = OCP_USER_MPU | OCP_USER_SDMA,
2479 };
2480
2481 /* l4_core -> SHAM2 (SHA1/MD5) (similar to omap24xx) */
2482 static struct omap_hwmod_class_sysconfig omap3_sham_sysc = {
2483 .rev_offs = 0x5c,
2484 .sysc_offs = 0x60,
2485 .syss_offs = 0x64,
2486 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2487 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2488 .sysc_fields = &omap3_sham_sysc_fields,
2489 };
2490
2491 static struct omap_hwmod_class omap3xxx_sham_class = {
2492 .name = "sham",
2493 .sysc = &omap3_sham_sysc,
2494 };
2495
2496
2497
2498 static struct omap_hwmod omap3xxx_sham_hwmod = {
2499 .name = "sham",
2500 .main_clk = "sha12_ick",
2501 .prcm = {
2502 .omap2 = {
2503 .module_offs = CORE_MOD,
2504 .idlest_reg_id = 1,
2505 .idlest_idle_bit = OMAP3430_ST_SHA12_SHIFT,
2506 },
2507 },
2508 .class = &omap3xxx_sham_class,
2509 };
2510
2511
2512 static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = {
2513 .master = &omap3xxx_l4_core_hwmod,
2514 .slave = &omap3xxx_sham_hwmod,
2515 .clk = "sha12_ick",
2516 .user = OCP_USER_MPU | OCP_USER_SDMA,
2517 };
2518
2519 /* l4_core -> AES */
2520 static struct omap_hwmod_class_sysconfig omap3_aes_sysc = {
2521 .rev_offs = 0x44,
2522 .sysc_offs = 0x48,
2523 .syss_offs = 0x4c,
2524 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2525 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2526 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2527 .sysc_fields = &omap3xxx_aes_sysc_fields,
2528 };
2529
2530 static struct omap_hwmod_class omap3xxx_aes_class = {
2531 .name = "aes",
2532 .sysc = &omap3_aes_sysc,
2533 };
2534
2535
2536 static struct omap_hwmod omap3xxx_aes_hwmod = {
2537 .name = "aes",
2538 .main_clk = "aes2_ick",
2539 .prcm = {
2540 .omap2 = {
2541 .module_offs = CORE_MOD,
2542 .idlest_reg_id = 1,
2543 .idlest_idle_bit = OMAP3430_ST_AES2_SHIFT,
2544 },
2545 },
2546 .class = &omap3xxx_aes_class,
2547 };
2548
2549
2550 static struct omap_hwmod_ocp_if omap3xxx_l4_core__aes = {
2551 .master = &omap3xxx_l4_core_hwmod,
2552 .slave = &omap3xxx_aes_hwmod,
2553 .clk = "aes2_ick",
2554 .user = OCP_USER_MPU | OCP_USER_SDMA,
2555 };
2556
2557 /*
2558 * 'ssi' class
2559 * synchronous serial interface (multichannel and full-duplex serial if)
2560 */
2561
2562 static struct omap_hwmod_class_sysconfig omap34xx_ssi_sysc = {
2563 .rev_offs = 0x0000,
2564 .sysc_offs = 0x0010,
2565 .syss_offs = 0x0014,
2566 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_MIDLEMODE |
2567 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2568 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2569 .sysc_fields = &omap_hwmod_sysc_type1,
2570 };
2571
2572 static struct omap_hwmod_class omap3xxx_ssi_hwmod_class = {
2573 .name = "ssi",
2574 .sysc = &omap34xx_ssi_sysc,
2575 };
2576
2577 static struct omap_hwmod omap3xxx_ssi_hwmod = {
2578 .name = "ssi",
2579 .class = &omap3xxx_ssi_hwmod_class,
2580 .clkdm_name = "core_l4_clkdm",
2581 .main_clk = "ssi_ssr_fck",
2582 .prcm = {
2583 .omap2 = {
2584 .module_offs = CORE_MOD,
2585 .idlest_reg_id = 1,
2586 .idlest_idle_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT,
2587 },
2588 },
2589 };
2590
2591 /* L4 CORE -> SSI */
2592 static struct omap_hwmod_ocp_if omap3xxx_l4_core__ssi = {
2593 .master = &omap3xxx_l4_core_hwmod,
2594 .slave = &omap3xxx_ssi_hwmod,
2595 .clk = "ssi_ick",
2596 .user = OCP_USER_MPU | OCP_USER_SDMA,
2597 };
2598
2599 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
2600 &omap3xxx_l3_main__l4_core,
2601 &omap3xxx_l3_main__l4_per,
2602 &omap3xxx_mpu__l3_main,
2603 &omap3xxx_l3_main__l4_debugss,
2604 &omap3xxx_l4_core__l4_wkup,
2605 &omap3xxx_l4_core__mmc3,
2606 &omap3_l4_core__uart1,
2607 &omap3_l4_core__uart2,
2608 &omap3_l4_per__uart3,
2609 &omap3_l4_core__i2c1,
2610 &omap3_l4_core__i2c2,
2611 &omap3_l4_core__i2c3,
2612 &omap3xxx_l4_wkup__l4_sec,
2613 &omap3xxx_l4_wkup__timer1,
2614 &omap3xxx_l4_per__timer2,
2615 &omap3xxx_l4_per__timer3,
2616 &omap3xxx_l4_per__timer4,
2617 &omap3xxx_l4_per__timer5,
2618 &omap3xxx_l4_per__timer6,
2619 &omap3xxx_l4_per__timer7,
2620 &omap3xxx_l4_per__timer8,
2621 &omap3xxx_l4_per__timer9,
2622 &omap3xxx_l4_core__timer10,
2623 &omap3xxx_l4_core__timer11,
2624 &omap3xxx_l4_wkup__wd_timer2,
2625 &omap3xxx_l4_wkup__gpio1,
2626 &omap3xxx_l4_per__gpio2,
2627 &omap3xxx_l4_per__gpio3,
2628 &omap3xxx_l4_per__gpio4,
2629 &omap3xxx_l4_per__gpio5,
2630 &omap3xxx_l4_per__gpio6,
2631 &omap3xxx_dma_system__l3,
2632 &omap3xxx_l4_core__dma_system,
2633 &omap3xxx_l4_core__mcbsp1,
2634 &omap3xxx_l4_per__mcbsp2,
2635 &omap3xxx_l4_per__mcbsp3,
2636 &omap3xxx_l4_per__mcbsp4,
2637 &omap3xxx_l4_core__mcbsp5,
2638 &omap3xxx_l4_per__mcbsp2_sidetone,
2639 &omap3xxx_l4_per__mcbsp3_sidetone,
2640 &omap34xx_l4_core__mcspi1,
2641 &omap34xx_l4_core__mcspi2,
2642 &omap34xx_l4_core__mcspi3,
2643 &omap34xx_l4_core__mcspi4,
2644 &omap3xxx_l4_wkup__counter_32k,
2645 &omap3xxx_l3_main__gpmc,
2646 NULL,
2647 };
2648
2649 /* GP-only hwmod links */
2650 static struct omap_hwmod_ocp_if *omap34xx_gp_hwmod_ocp_ifs[] __initdata = {
2651 &omap3xxx_l4_sec__timer12,
2652 NULL,
2653 };
2654
2655 static struct omap_hwmod_ocp_if *omap36xx_gp_hwmod_ocp_ifs[] __initdata = {
2656 &omap3xxx_l4_sec__timer12,
2657 NULL,
2658 };
2659
2660 static struct omap_hwmod_ocp_if *am35xx_gp_hwmod_ocp_ifs[] __initdata = {
2661 &omap3xxx_l4_sec__timer12,
2662 NULL,
2663 };
2664
2665 /* crypto hwmod links */
2666 static struct omap_hwmod_ocp_if *omap34xx_sham_hwmod_ocp_ifs[] __initdata = {
2667 &omap3xxx_l4_core__sham,
2668 NULL,
2669 };
2670
2671 static struct omap_hwmod_ocp_if *omap34xx_aes_hwmod_ocp_ifs[] __initdata = {
2672 &omap3xxx_l4_core__aes,
2673 NULL,
2674 };
2675
2676 static struct omap_hwmod_ocp_if *omap36xx_sham_hwmod_ocp_ifs[] __initdata = {
2677 &omap3xxx_l4_core__sham,
2678 NULL
2679 };
2680
2681 static struct omap_hwmod_ocp_if *omap36xx_aes_hwmod_ocp_ifs[] __initdata = {
2682 &omap3xxx_l4_core__aes,
2683 NULL
2684 };
2685
2686 /*
2687 * Apparently the SHA/MD5 and AES accelerator IP blocks are
2688 * only present on some AM35xx chips, and no one knows which
2689 * ones. See
2690 * http://www.spinics.net/lists/arm-kernel/msg215466.html So
2691 * if you need these IP blocks on an AM35xx, try uncommenting
2692 * the following lines.
2693 */
2694 static struct omap_hwmod_ocp_if *am35xx_sham_hwmod_ocp_ifs[] __initdata = {
2695 /* &omap3xxx_l4_core__sham, */
2696 NULL
2697 };
2698
2699 static struct omap_hwmod_ocp_if *am35xx_aes_hwmod_ocp_ifs[] __initdata = {
2700 /* &omap3xxx_l4_core__aes, */
2701 NULL,
2702 };
2703
2704 /* 3430ES1-only hwmod links */
2705 static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
2706 &omap3430es1_dss__l3,
2707 &omap3430es1_l4_core__dss,
2708 NULL,
2709 };
2710
2711 /* 3430ES2+-only hwmod links */
2712 static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = {
2713 &omap3xxx_dss__l3,
2714 &omap3xxx_l4_core__dss,
2715 &omap3xxx_usbhsotg__l3,
2716 &omap3xxx_l4_core__usbhsotg,
2717 &omap3xxx_usb_host_hs__l3_main_2,
2718 &omap3xxx_l4_core__usb_host_hs,
2719 &omap3xxx_l4_core__usb_tll_hs,
2720 NULL,
2721 };
2722
2723 /* <= 3430ES3-only hwmod links */
2724 static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = {
2725 &omap3xxx_l4_core__pre_es3_mmc1,
2726 &omap3xxx_l4_core__pre_es3_mmc2,
2727 NULL,
2728 };
2729
2730 /* 3430ES3+-only hwmod links */
2731 static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = {
2732 &omap3xxx_l4_core__es3plus_mmc1,
2733 &omap3xxx_l4_core__es3plus_mmc2,
2734 NULL,
2735 };
2736
2737 /* 34xx-only hwmod links (all ES revisions) */
2738 static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
2739 &omap3xxx_l3__iva,
2740 &omap34xx_l4_core__sr1,
2741 &omap34xx_l4_core__sr2,
2742 &omap3xxx_l4_core__mailbox,
2743 &omap3xxx_l4_core__hdq1w,
2744 &omap3xxx_sad2d__l3,
2745 &omap3xxx_l4_core__mmu_isp,
2746 &omap3xxx_l3_main__mmu_iva,
2747 &omap3xxx_l4_core__ssi,
2748 NULL,
2749 };
2750
2751 /* 36xx-only hwmod links (all ES revisions) */
2752 static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
2753 &omap3xxx_l3__iva,
2754 &omap36xx_l4_per__uart4,
2755 &omap3xxx_dss__l3,
2756 &omap3xxx_l4_core__dss,
2757 &omap36xx_l4_core__sr1,
2758 &omap36xx_l4_core__sr2,
2759 &omap3xxx_usbhsotg__l3,
2760 &omap3xxx_l4_core__usbhsotg,
2761 &omap3xxx_l4_core__mailbox,
2762 &omap3xxx_usb_host_hs__l3_main_2,
2763 &omap3xxx_l4_core__usb_host_hs,
2764 &omap3xxx_l4_core__usb_tll_hs,
2765 &omap3xxx_l4_core__es3plus_mmc1,
2766 &omap3xxx_l4_core__es3plus_mmc2,
2767 &omap3xxx_l4_core__hdq1w,
2768 &omap3xxx_sad2d__l3,
2769 &omap3xxx_l4_core__mmu_isp,
2770 &omap3xxx_l3_main__mmu_iva,
2771 &omap3xxx_l4_core__ssi,
2772 NULL,
2773 };
2774
2775 static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
2776 &omap3xxx_dss__l3,
2777 &omap3xxx_l4_core__dss,
2778 &am35xx_usbhsotg__l3,
2779 &am35xx_l4_core__usbhsotg,
2780 &am35xx_l4_core__uart4,
2781 &omap3xxx_usb_host_hs__l3_main_2,
2782 &omap3xxx_l4_core__usb_host_hs,
2783 &omap3xxx_l4_core__usb_tll_hs,
2784 &omap3xxx_l4_core__es3plus_mmc1,
2785 &omap3xxx_l4_core__es3plus_mmc2,
2786 &omap3xxx_l4_core__hdq1w,
2787 &am35xx_mdio__l3,
2788 &am35xx_l4_core__mdio,
2789 &am35xx_emac__l3,
2790 &am35xx_l4_core__emac,
2791 NULL,
2792 };
2793
2794 static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
2795 &omap3xxx_l4_core__dss_dispc,
2796 &omap3xxx_l4_core__dss_dsi1,
2797 &omap3xxx_l4_core__dss_rfbi,
2798 &omap3xxx_l4_core__dss_venc,
2799 NULL,
2800 };
2801
2802 /**
2803 * omap3xxx_hwmod_is_hs_ip_block_usable - is a security IP block accessible?
2804 * @bus: struct device_node * for the top-level OMAP DT data
2805 * @dev_name: device name used in the DT file
2806 *
2807 * Determine whether a "secure" IP block @dev_name is usable by Linux.
2808 * There doesn't appear to be a 100% reliable way to determine this,
2809 * so we rely on heuristics. If @bus is null, meaning there's no DT
2810 * data, then we only assume the IP block is accessible if the OMAP is
2811 * fused as a 'general-purpose' SoC. If however DT data is present,
2812 * test to see if the IP block is described in the DT data and set to
2813 * 'status = "okay"'. If so then we assume the ODM has configured the
2814 * OMAP firewalls to allow access to the IP block.
2815 *
2816 * Return: 0 if device named @dev_name is not likely to be accessible,
2817 * or 1 if it is likely to be accessible.
2818 */
omap3xxx_hwmod_is_hs_ip_block_usable(struct device_node * bus,const char * dev_name)2819 static bool __init omap3xxx_hwmod_is_hs_ip_block_usable(struct device_node *bus,
2820 const char *dev_name)
2821 {
2822 struct device_node *node;
2823 bool available;
2824
2825 if (!bus)
2826 return omap_type() == OMAP2_DEVICE_TYPE_GP;
2827
2828 node = of_get_child_by_name(bus, dev_name);
2829 available = of_device_is_available(node);
2830 of_node_put(node);
2831
2832 return available;
2833 }
2834
omap3xxx_hwmod_init(void)2835 int __init omap3xxx_hwmod_init(void)
2836 {
2837 int r;
2838 struct omap_hwmod_ocp_if **h = NULL, **h_gp = NULL, **h_sham = NULL;
2839 struct omap_hwmod_ocp_if **h_aes = NULL;
2840 struct device_node *bus;
2841 unsigned int rev;
2842
2843 omap_hwmod_init();
2844
2845 /* Register hwmod links common to all OMAP3 */
2846 r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs);
2847 if (r < 0)
2848 return r;
2849
2850 rev = omap_rev();
2851
2852 /*
2853 * Register hwmod links common to individual OMAP3 families, all
2854 * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
2855 * All possible revisions should be included in this conditional.
2856 */
2857 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
2858 rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
2859 rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
2860 h = omap34xx_hwmod_ocp_ifs;
2861 h_gp = omap34xx_gp_hwmod_ocp_ifs;
2862 h_sham = omap34xx_sham_hwmod_ocp_ifs;
2863 h_aes = omap34xx_aes_hwmod_ocp_ifs;
2864 } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
2865 h = am35xx_hwmod_ocp_ifs;
2866 h_gp = am35xx_gp_hwmod_ocp_ifs;
2867 h_sham = am35xx_sham_hwmod_ocp_ifs;
2868 h_aes = am35xx_aes_hwmod_ocp_ifs;
2869 } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
2870 rev == OMAP3630_REV_ES1_2) {
2871 h = omap36xx_hwmod_ocp_ifs;
2872 h_gp = omap36xx_gp_hwmod_ocp_ifs;
2873 h_sham = omap36xx_sham_hwmod_ocp_ifs;
2874 h_aes = omap36xx_aes_hwmod_ocp_ifs;
2875 } else {
2876 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
2877 return -EINVAL;
2878 }
2879
2880 r = omap_hwmod_register_links(h);
2881 if (r < 0)
2882 return r;
2883
2884 /* Register GP-only hwmod links. */
2885 if (h_gp && omap_type() == OMAP2_DEVICE_TYPE_GP) {
2886 r = omap_hwmod_register_links(h_gp);
2887 if (r < 0)
2888 return r;
2889 }
2890
2891 /*
2892 * Register crypto hwmod links only if they are not disabled in DT.
2893 * If DT information is missing, enable them only for GP devices.
2894 */
2895
2896 bus = of_find_node_by_name(NULL, "ocp");
2897
2898 if (h_sham && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "sham")) {
2899 r = omap_hwmod_register_links(h_sham);
2900 if (r < 0)
2901 goto put_node;
2902 }
2903
2904 if (h_aes && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "aes")) {
2905 r = omap_hwmod_register_links(h_aes);
2906 if (r < 0)
2907 goto put_node;
2908 }
2909 of_node_put(bus);
2910
2911 /*
2912 * Register hwmod links specific to certain ES levels of a
2913 * particular family of silicon (e.g., 34xx ES1.0)
2914 */
2915 h = NULL;
2916 if (rev == OMAP3430_REV_ES1_0) {
2917 h = omap3430es1_hwmod_ocp_ifs;
2918 } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
2919 rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
2920 rev == OMAP3430_REV_ES3_1_2) {
2921 h = omap3430es2plus_hwmod_ocp_ifs;
2922 }
2923
2924 if (h) {
2925 r = omap_hwmod_register_links(h);
2926 if (r < 0)
2927 return r;
2928 }
2929
2930 h = NULL;
2931 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
2932 rev == OMAP3430_REV_ES2_1) {
2933 h = omap3430_pre_es3_hwmod_ocp_ifs;
2934 } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
2935 rev == OMAP3430_REV_ES3_1_2) {
2936 h = omap3430_es3plus_hwmod_ocp_ifs;
2937 }
2938
2939 if (h)
2940 r = omap_hwmod_register_links(h);
2941 if (r < 0)
2942 return r;
2943
2944 /*
2945 * DSS code presumes that dss_core hwmod is handled first,
2946 * _before_ any other DSS related hwmods so register common
2947 * DSS hwmod links last to ensure that dss_core is already
2948 * registered. Otherwise some change things may happen, for
2949 * ex. if dispc is handled before dss_core and DSS is enabled
2950 * in bootloader DISPC will be reset with outputs enabled
2951 * which sometimes leads to unrecoverable L3 error. XXX The
2952 * long-term fix to this is to ensure hwmods are set up in
2953 * dependency order in the hwmod core code.
2954 */
2955 r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs);
2956
2957 return r;
2958
2959 put_node:
2960 of_node_put(bus);
2961 return r;
2962 }
2963
