1/* 2 * Device Tree Source for OMAP5 clock data 3 * 4 * Copyright (C) 2013 Texas Instruments, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10&cm_core_aon_clocks { 11 pad_clks_src_ck: pad_clks_src_ck { 12 #clock-cells = <0>; 13 compatible = "fixed-clock"; 14 clock-frequency = <12000000>; 15 }; 16 17 pad_clks_ck: pad_clks_ck@108 { 18 #clock-cells = <0>; 19 compatible = "ti,gate-clock"; 20 clocks = <&pad_clks_src_ck>; 21 ti,bit-shift = <8>; 22 reg = <0x0108>; 23 }; 24 25 secure_32k_clk_src_ck: secure_32k_clk_src_ck { 26 #clock-cells = <0>; 27 compatible = "fixed-clock"; 28 clock-frequency = <32768>; 29 }; 30 31 slimbus_src_clk: slimbus_src_clk { 32 #clock-cells = <0>; 33 compatible = "fixed-clock"; 34 clock-frequency = <12000000>; 35 }; 36 37 slimbus_clk: slimbus_clk@108 { 38 #clock-cells = <0>; 39 compatible = "ti,gate-clock"; 40 clocks = <&slimbus_src_clk>; 41 ti,bit-shift = <10>; 42 reg = <0x0108>; 43 }; 44 45 sys_32k_ck: sys_32k_ck { 46 #clock-cells = <0>; 47 compatible = "fixed-clock"; 48 clock-frequency = <32768>; 49 }; 50 51 virt_12000000_ck: virt_12000000_ck { 52 #clock-cells = <0>; 53 compatible = "fixed-clock"; 54 clock-frequency = <12000000>; 55 }; 56 57 virt_13000000_ck: virt_13000000_ck { 58 #clock-cells = <0>; 59 compatible = "fixed-clock"; 60 clock-frequency = <13000000>; 61 }; 62 63 virt_16800000_ck: virt_16800000_ck { 64 #clock-cells = <0>; 65 compatible = "fixed-clock"; 66 clock-frequency = <16800000>; 67 }; 68 69 virt_19200000_ck: virt_19200000_ck { 70 #clock-cells = <0>; 71 compatible = "fixed-clock"; 72 clock-frequency = <19200000>; 73 }; 74 75 virt_26000000_ck: virt_26000000_ck { 76 #clock-cells = <0>; 77 compatible = "fixed-clock"; 78 clock-frequency = <26000000>; 79 }; 80 81 virt_27000000_ck: virt_27000000_ck { 82 #clock-cells = <0>; 83 compatible = "fixed-clock"; 84 clock-frequency = <27000000>; 85 }; 86 87 virt_38400000_ck: virt_38400000_ck { 88 #clock-cells = <0>; 89 compatible = "fixed-clock"; 90 clock-frequency = <38400000>; 91 }; 92 93 xclk60mhsp1_ck: xclk60mhsp1_ck { 94 #clock-cells = <0>; 95 compatible = "fixed-clock"; 96 clock-frequency = <60000000>; 97 }; 98 99 xclk60mhsp2_ck: xclk60mhsp2_ck { 100 #clock-cells = <0>; 101 compatible = "fixed-clock"; 102 clock-frequency = <60000000>; 103 }; 104 105 dpll_abe_ck: dpll_abe_ck@1e0 { 106 #clock-cells = <0>; 107 compatible = "ti,omap4-dpll-m4xen-clock"; 108 clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>; 109 reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>; 110 }; 111 112 dpll_abe_x2_ck: dpll_abe_x2_ck { 113 #clock-cells = <0>; 114 compatible = "ti,omap4-dpll-x2-clock"; 115 clocks = <&dpll_abe_ck>; 116 }; 117 118 dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 { 119 #clock-cells = <0>; 120 compatible = "ti,divider-clock"; 121 clocks = <&dpll_abe_x2_ck>; 122 ti,max-div = <31>; 123 reg = <0x01f0>; 124 ti,index-starts-at-one; 125 }; 126 127 abe_24m_fclk: abe_24m_fclk { 128 #clock-cells = <0>; 129 compatible = "fixed-factor-clock"; 130 clocks = <&dpll_abe_m2x2_ck>; 131 clock-mult = <1>; 132 clock-div = <8>; 133 }; 134 135 abe_clk: abe_clk@108 { 136 #clock-cells = <0>; 137 compatible = "ti,divider-clock"; 138 clocks = <&dpll_abe_m2x2_ck>; 139 ti,max-div = <4>; 140 reg = <0x0108>; 141 ti,index-power-of-two; 142 }; 143 144 abe_iclk: abe_iclk@528 { 145 #clock-cells = <0>; 146 compatible = "ti,divider-clock"; 147 clocks = <&aess_fclk>; 148 ti,bit-shift = <24>; 149 reg = <0x0528>; 150 ti,dividers = <2>, <1>; 151 }; 152 153 abe_lp_clk_div: abe_lp_clk_div { 154 #clock-cells = <0>; 155 compatible = "fixed-factor-clock"; 156 clocks = <&dpll_abe_m2x2_ck>; 157 clock-mult = <1>; 158 clock-div = <16>; 159 }; 160 161 dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 { 162 #clock-cells = <0>; 163 compatible = "ti,divider-clock"; 164 clocks = <&dpll_abe_x2_ck>; 165 ti,max-div = <31>; 166 reg = <0x01f4>; 167 ti,index-starts-at-one; 168 }; 169 170 dpll_core_byp_mux: dpll_core_byp_mux@12c { 171 #clock-cells = <0>; 172 compatible = "ti,mux-clock"; 173 clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>; 174 ti,bit-shift = <23>; 175 reg = <0x012c>; 176 }; 177 178 dpll_core_ck: dpll_core_ck@120 { 179 #clock-cells = <0>; 180 compatible = "ti,omap4-dpll-core-clock"; 181 clocks = <&sys_clkin>, <&dpll_core_byp_mux>; 182 reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>; 183 }; 184 185 dpll_core_x2_ck: dpll_core_x2_ck { 186 #clock-cells = <0>; 187 compatible = "ti,omap4-dpll-x2-clock"; 188 clocks = <&dpll_core_ck>; 189 }; 190 191 dpll_core_h21x2_ck: dpll_core_h21x2_ck@150 { 192 #clock-cells = <0>; 193 compatible = "ti,divider-clock"; 194 clocks = <&dpll_core_x2_ck>; 195 ti,max-div = <63>; 196 reg = <0x0150>; 197 ti,index-starts-at-one; 198 }; 199 200 c2c_fclk: c2c_fclk { 201 #clock-cells = <0>; 202 compatible = "fixed-factor-clock"; 203 clocks = <&dpll_core_h21x2_ck>; 204 clock-mult = <1>; 205 clock-div = <1>; 206 }; 207 208 c2c_iclk: c2c_iclk { 209 #clock-cells = <0>; 210 compatible = "fixed-factor-clock"; 211 clocks = <&c2c_fclk>; 212 clock-mult = <1>; 213 clock-div = <2>; 214 }; 215 216 dpll_core_h11x2_ck: dpll_core_h11x2_ck@138 { 217 #clock-cells = <0>; 218 compatible = "ti,divider-clock"; 219 clocks = <&dpll_core_x2_ck>; 220 ti,max-div = <63>; 221 reg = <0x0138>; 222 ti,index-starts-at-one; 223 }; 224 225 dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c { 226 #clock-cells = <0>; 227 compatible = "ti,divider-clock"; 228 clocks = <&dpll_core_x2_ck>; 229 ti,max-div = <63>; 230 reg = <0x013c>; 231 ti,index-starts-at-one; 232 }; 233 234 dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 { 235 #clock-cells = <0>; 236 compatible = "ti,divider-clock"; 237 clocks = <&dpll_core_x2_ck>; 238 ti,max-div = <63>; 239 reg = <0x0140>; 240 ti,index-starts-at-one; 241 }; 242 243 dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 { 244 #clock-cells = <0>; 245 compatible = "ti,divider-clock"; 246 clocks = <&dpll_core_x2_ck>; 247 ti,max-div = <63>; 248 reg = <0x0144>; 249 ti,index-starts-at-one; 250 }; 251 252 dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 { 253 #clock-cells = <0>; 254 compatible = "ti,divider-clock"; 255 clocks = <&dpll_core_x2_ck>; 256 ti,max-div = <63>; 257 reg = <0x0154>; 258 ti,index-starts-at-one; 259 }; 260 261 dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 { 262 #clock-cells = <0>; 263 compatible = "ti,divider-clock"; 264 clocks = <&dpll_core_x2_ck>; 265 ti,max-div = <63>; 266 reg = <0x0158>; 267 ti,index-starts-at-one; 268 }; 269 270 dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c { 271 #clock-cells = <0>; 272 compatible = "ti,divider-clock"; 273 clocks = <&dpll_core_x2_ck>; 274 ti,max-div = <63>; 275 reg = <0x015c>; 276 ti,index-starts-at-one; 277 }; 278 279 dpll_core_m2_ck: dpll_core_m2_ck@130 { 280 #clock-cells = <0>; 281 compatible = "ti,divider-clock"; 282 clocks = <&dpll_core_ck>; 283 ti,max-div = <31>; 284 reg = <0x0130>; 285 ti,index-starts-at-one; 286 }; 287 288 dpll_core_m3x2_ck: dpll_core_m3x2_ck@134 { 289 #clock-cells = <0>; 290 compatible = "ti,divider-clock"; 291 clocks = <&dpll_core_x2_ck>; 292 ti,max-div = <31>; 293 reg = <0x0134>; 294 ti,index-starts-at-one; 295 }; 296 297 iva_dpll_hs_clk_div: iva_dpll_hs_clk_div { 298 #clock-cells = <0>; 299 compatible = "fixed-factor-clock"; 300 clocks = <&dpll_core_h12x2_ck>; 301 clock-mult = <1>; 302 clock-div = <1>; 303 }; 304 305 dpll_iva_byp_mux: dpll_iva_byp_mux@1ac { 306 #clock-cells = <0>; 307 compatible = "ti,mux-clock"; 308 clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>; 309 ti,bit-shift = <23>; 310 reg = <0x01ac>; 311 }; 312 313 dpll_iva_ck: dpll_iva_ck@1a0 { 314 #clock-cells = <0>; 315 compatible = "ti,omap4-dpll-clock"; 316 clocks = <&sys_clkin>, <&dpll_iva_byp_mux>; 317 reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; 318 assigned-clocks = <&dpll_iva_ck>; 319 assigned-clock-rates = <1165000000>; 320 }; 321 322 dpll_iva_x2_ck: dpll_iva_x2_ck { 323 #clock-cells = <0>; 324 compatible = "ti,omap4-dpll-x2-clock"; 325 clocks = <&dpll_iva_ck>; 326 }; 327 328 dpll_iva_h11x2_ck: dpll_iva_h11x2_ck@1b8 { 329 #clock-cells = <0>; 330 compatible = "ti,divider-clock"; 331 clocks = <&dpll_iva_x2_ck>; 332 ti,max-div = <63>; 333 reg = <0x01b8>; 334 ti,index-starts-at-one; 335 assigned-clocks = <&dpll_iva_h11x2_ck>; 336 assigned-clock-rates = <465920000>; 337 }; 338 339 dpll_iva_h12x2_ck: dpll_iva_h12x2_ck@1bc { 340 #clock-cells = <0>; 341 compatible = "ti,divider-clock"; 342 clocks = <&dpll_iva_x2_ck>; 343 ti,max-div = <63>; 344 reg = <0x01bc>; 345 ti,index-starts-at-one; 346 assigned-clocks = <&dpll_iva_h12x2_ck>; 347 assigned-clock-rates = <388300000>; 348 }; 349 350 mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div { 351 #clock-cells = <0>; 352 compatible = "fixed-factor-clock"; 353 clocks = <&dpll_core_h12x2_ck>; 354 clock-mult = <1>; 355 clock-div = <1>; 356 }; 357 358 dpll_mpu_ck: dpll_mpu_ck@160 { 359 #clock-cells = <0>; 360 compatible = "ti,omap5-mpu-dpll-clock"; 361 clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>; 362 reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; 363 }; 364 365 dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 { 366 #clock-cells = <0>; 367 compatible = "ti,divider-clock"; 368 clocks = <&dpll_mpu_ck>; 369 ti,max-div = <31>; 370 reg = <0x0170>; 371 ti,index-starts-at-one; 372 }; 373 374 per_dpll_hs_clk_div: per_dpll_hs_clk_div { 375 #clock-cells = <0>; 376 compatible = "fixed-factor-clock"; 377 clocks = <&dpll_abe_m3x2_ck>; 378 clock-mult = <1>; 379 clock-div = <2>; 380 }; 381 382 usb_dpll_hs_clk_div: usb_dpll_hs_clk_div { 383 #clock-cells = <0>; 384 compatible = "fixed-factor-clock"; 385 clocks = <&dpll_abe_m3x2_ck>; 386 clock-mult = <1>; 387 clock-div = <3>; 388 }; 389 390 l3_iclk_div: l3_iclk_div@100 { 391 #clock-cells = <0>; 392 compatible = "ti,divider-clock"; 393 ti,max-div = <2>; 394 ti,bit-shift = <4>; 395 reg = <0x100>; 396 clocks = <&dpll_core_h12x2_ck>; 397 ti,index-power-of-two; 398 }; 399 400 gpu_l3_iclk: gpu_l3_iclk { 401 #clock-cells = <0>; 402 compatible = "fixed-factor-clock"; 403 clocks = <&l3_iclk_div>; 404 clock-mult = <1>; 405 clock-div = <1>; 406 }; 407 408 l4_root_clk_div: l4_root_clk_div@100 { 409 #clock-cells = <0>; 410 compatible = "ti,divider-clock"; 411 ti,max-div = <2>; 412 ti,bit-shift = <8>; 413 reg = <0x100>; 414 clocks = <&l3_iclk_div>; 415 ti,index-power-of-two; 416 }; 417 418 slimbus1_slimbus_clk: slimbus1_slimbus_clk@560 { 419 #clock-cells = <0>; 420 compatible = "ti,gate-clock"; 421 clocks = <&slimbus_clk>; 422 ti,bit-shift = <11>; 423 reg = <0x0560>; 424 }; 425 426 aess_fclk: aess_fclk@528 { 427 #clock-cells = <0>; 428 compatible = "ti,divider-clock"; 429 clocks = <&abe_clk>; 430 ti,bit-shift = <24>; 431 ti,max-div = <2>; 432 reg = <0x0528>; 433 }; 434 435 mcasp_sync_mux_ck: mcasp_sync_mux_ck@540 { 436 #clock-cells = <0>; 437 compatible = "ti,mux-clock"; 438 clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; 439 ti,bit-shift = <26>; 440 reg = <0x0540>; 441 }; 442 443 mcasp_gfclk: mcasp_gfclk@540 { 444 #clock-cells = <0>; 445 compatible = "ti,mux-clock"; 446 clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; 447 ti,bit-shift = <24>; 448 reg = <0x0540>; 449 }; 450 451 dummy_ck: dummy_ck { 452 #clock-cells = <0>; 453 compatible = "fixed-clock"; 454 clock-frequency = <0>; 455 }; 456}; 457&prm_clocks { 458 sys_clkin: sys_clkin@110 { 459 #clock-cells = <0>; 460 compatible = "ti,mux-clock"; 461 clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; 462 reg = <0x0110>; 463 ti,index-starts-at-one; 464 }; 465 466 abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@108 { 467 #clock-cells = <0>; 468 compatible = "ti,mux-clock"; 469 clocks = <&sys_clkin>, <&sys_32k_ck>; 470 reg = <0x0108>; 471 }; 472 473 abe_dpll_clk_mux: abe_dpll_clk_mux@10c { 474 #clock-cells = <0>; 475 compatible = "ti,mux-clock"; 476 clocks = <&sys_clkin>, <&sys_32k_ck>; 477 reg = <0x010c>; 478 }; 479 480 custefuse_sys_gfclk_div: custefuse_sys_gfclk_div { 481 #clock-cells = <0>; 482 compatible = "fixed-factor-clock"; 483 clocks = <&sys_clkin>; 484 clock-mult = <1>; 485 clock-div = <2>; 486 }; 487 488 dss_syc_gfclk_div: dss_syc_gfclk_div { 489 #clock-cells = <0>; 490 compatible = "fixed-factor-clock"; 491 clocks = <&sys_clkin>; 492 clock-mult = <1>; 493 clock-div = <1>; 494 }; 495 496 wkupaon_iclk_mux: wkupaon_iclk_mux@108 { 497 #clock-cells = <0>; 498 compatible = "ti,mux-clock"; 499 clocks = <&sys_clkin>, <&abe_lp_clk_div>; 500 reg = <0x0108>; 501 }; 502 503 l3instr_ts_gclk_div: l3instr_ts_gclk_div { 504 #clock-cells = <0>; 505 compatible = "fixed-factor-clock"; 506 clocks = <&wkupaon_iclk_mux>; 507 clock-mult = <1>; 508 clock-div = <1>; 509 }; 510}; 511 512&cm_core_clocks { 513 514 dpll_per_byp_mux: dpll_per_byp_mux@14c { 515 #clock-cells = <0>; 516 compatible = "ti,mux-clock"; 517 clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>; 518 ti,bit-shift = <23>; 519 reg = <0x014c>; 520 }; 521 522 dpll_per_ck: dpll_per_ck@140 { 523 #clock-cells = <0>; 524 compatible = "ti,omap4-dpll-clock"; 525 clocks = <&sys_clkin>, <&dpll_per_byp_mux>; 526 reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; 527 }; 528 529 dpll_per_x2_ck: dpll_per_x2_ck { 530 #clock-cells = <0>; 531 compatible = "ti,omap4-dpll-x2-clock"; 532 clocks = <&dpll_per_ck>; 533 }; 534 535 dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 { 536 #clock-cells = <0>; 537 compatible = "ti,divider-clock"; 538 clocks = <&dpll_per_x2_ck>; 539 ti,max-div = <63>; 540 reg = <0x0158>; 541 ti,index-starts-at-one; 542 }; 543 544 dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c { 545 #clock-cells = <0>; 546 compatible = "ti,divider-clock"; 547 clocks = <&dpll_per_x2_ck>; 548 ti,max-div = <63>; 549 reg = <0x015c>; 550 ti,index-starts-at-one; 551 }; 552 553 dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 { 554 #clock-cells = <0>; 555 compatible = "ti,divider-clock"; 556 clocks = <&dpll_per_x2_ck>; 557 ti,max-div = <63>; 558 reg = <0x0164>; 559 ti,index-starts-at-one; 560 }; 561 562 dpll_per_m2_ck: dpll_per_m2_ck@150 { 563 #clock-cells = <0>; 564 compatible = "ti,divider-clock"; 565 clocks = <&dpll_per_ck>; 566 ti,max-div = <31>; 567 reg = <0x0150>; 568 ti,index-starts-at-one; 569 }; 570 571 dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 { 572 #clock-cells = <0>; 573 compatible = "ti,divider-clock"; 574 clocks = <&dpll_per_x2_ck>; 575 ti,max-div = <31>; 576 reg = <0x0150>; 577 ti,index-starts-at-one; 578 }; 579 580 dpll_per_m3x2_ck: dpll_per_m3x2_ck@154 { 581 #clock-cells = <0>; 582 compatible = "ti,divider-clock"; 583 clocks = <&dpll_per_x2_ck>; 584 ti,max-div = <31>; 585 reg = <0x0154>; 586 ti,index-starts-at-one; 587 }; 588 589 dpll_unipro1_ck: dpll_unipro1_ck@200 { 590 #clock-cells = <0>; 591 compatible = "ti,omap4-dpll-clock"; 592 clocks = <&sys_clkin>, <&sys_clkin>; 593 reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>; 594 }; 595 596 dpll_unipro1_clkdcoldo: dpll_unipro1_clkdcoldo { 597 #clock-cells = <0>; 598 compatible = "fixed-factor-clock"; 599 clocks = <&dpll_unipro1_ck>; 600 clock-mult = <1>; 601 clock-div = <1>; 602 }; 603 604 dpll_unipro1_m2_ck: dpll_unipro1_m2_ck@210 { 605 #clock-cells = <0>; 606 compatible = "ti,divider-clock"; 607 clocks = <&dpll_unipro1_ck>; 608 ti,max-div = <127>; 609 reg = <0x0210>; 610 ti,index-starts-at-one; 611 }; 612 613 dpll_unipro2_ck: dpll_unipro2_ck@1c0 { 614 #clock-cells = <0>; 615 compatible = "ti,omap4-dpll-clock"; 616 clocks = <&sys_clkin>, <&sys_clkin>; 617 reg = <0x01c0>, <0x01c4>, <0x01cc>, <0x01c8>; 618 }; 619 620 dpll_unipro2_clkdcoldo: dpll_unipro2_clkdcoldo { 621 #clock-cells = <0>; 622 compatible = "fixed-factor-clock"; 623 clocks = <&dpll_unipro2_ck>; 624 clock-mult = <1>; 625 clock-div = <1>; 626 }; 627 628 dpll_unipro2_m2_ck: dpll_unipro2_m2_ck@1d0 { 629 #clock-cells = <0>; 630 compatible = "ti,divider-clock"; 631 clocks = <&dpll_unipro2_ck>; 632 ti,max-div = <127>; 633 reg = <0x01d0>; 634 ti,index-starts-at-one; 635 }; 636 637 dpll_usb_byp_mux: dpll_usb_byp_mux@18c { 638 #clock-cells = <0>; 639 compatible = "ti,mux-clock"; 640 clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>; 641 ti,bit-shift = <23>; 642 reg = <0x018c>; 643 }; 644 645 dpll_usb_ck: dpll_usb_ck@180 { 646 #clock-cells = <0>; 647 compatible = "ti,omap4-dpll-j-type-clock"; 648 clocks = <&sys_clkin>, <&dpll_usb_byp_mux>; 649 reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; 650 }; 651 652 dpll_usb_clkdcoldo: dpll_usb_clkdcoldo { 653 #clock-cells = <0>; 654 compatible = "fixed-factor-clock"; 655 clocks = <&dpll_usb_ck>; 656 clock-mult = <1>; 657 clock-div = <1>; 658 }; 659 660 dpll_usb_m2_ck: dpll_usb_m2_ck@190 { 661 #clock-cells = <0>; 662 compatible = "ti,divider-clock"; 663 clocks = <&dpll_usb_ck>; 664 ti,max-div = <127>; 665 reg = <0x0190>; 666 ti,index-starts-at-one; 667 }; 668 669 func_128m_clk: func_128m_clk { 670 #clock-cells = <0>; 671 compatible = "fixed-factor-clock"; 672 clocks = <&dpll_per_h11x2_ck>; 673 clock-mult = <1>; 674 clock-div = <2>; 675 }; 676 677 func_12m_fclk: func_12m_fclk { 678 #clock-cells = <0>; 679 compatible = "fixed-factor-clock"; 680 clocks = <&dpll_per_m2x2_ck>; 681 clock-mult = <1>; 682 clock-div = <16>; 683 }; 684 685 func_24m_clk: func_24m_clk { 686 #clock-cells = <0>; 687 compatible = "fixed-factor-clock"; 688 clocks = <&dpll_per_m2_ck>; 689 clock-mult = <1>; 690 clock-div = <4>; 691 }; 692 693 func_48m_fclk: func_48m_fclk { 694 #clock-cells = <0>; 695 compatible = "fixed-factor-clock"; 696 clocks = <&dpll_per_m2x2_ck>; 697 clock-mult = <1>; 698 clock-div = <4>; 699 }; 700 701 func_96m_fclk: func_96m_fclk { 702 #clock-cells = <0>; 703 compatible = "fixed-factor-clock"; 704 clocks = <&dpll_per_m2x2_ck>; 705 clock-mult = <1>; 706 clock-div = <2>; 707 }; 708 709 l3init_60m_fclk: l3init_60m_fclk@104 { 710 #clock-cells = <0>; 711 compatible = "ti,divider-clock"; 712 clocks = <&dpll_usb_m2_ck>; 713 reg = <0x0104>; 714 ti,dividers = <1>, <8>; 715 }; 716 717 iss_ctrlclk: iss_ctrlclk@1320 { 718 #clock-cells = <0>; 719 compatible = "ti,gate-clock"; 720 clocks = <&func_96m_fclk>; 721 ti,bit-shift = <8>; 722 reg = <0x1320>; 723 }; 724 725 lli_txphy_clk: lli_txphy_clk@f20 { 726 #clock-cells = <0>; 727 compatible = "ti,gate-clock"; 728 clocks = <&dpll_unipro1_clkdcoldo>; 729 ti,bit-shift = <8>; 730 reg = <0x0f20>; 731 }; 732 733 lli_txphy_ls_clk: lli_txphy_ls_clk@f20 { 734 #clock-cells = <0>; 735 compatible = "ti,gate-clock"; 736 clocks = <&dpll_unipro1_m2_ck>; 737 ti,bit-shift = <9>; 738 reg = <0x0f20>; 739 }; 740 741 usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 { 742 #clock-cells = <0>; 743 compatible = "ti,gate-clock"; 744 clocks = <&sys_32k_ck>; 745 ti,bit-shift = <8>; 746 reg = <0x0640>; 747 }; 748 749 fdif_fclk: fdif_fclk@1328 { 750 #clock-cells = <0>; 751 compatible = "ti,divider-clock"; 752 clocks = <&dpll_per_h11x2_ck>; 753 ti,bit-shift = <24>; 754 ti,max-div = <2>; 755 reg = <0x1328>; 756 }; 757 758 gpu_core_gclk_mux: gpu_core_gclk_mux@1520 { 759 #clock-cells = <0>; 760 compatible = "ti,mux-clock"; 761 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>; 762 ti,bit-shift = <24>; 763 reg = <0x1520>; 764 }; 765 766 gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1520 { 767 #clock-cells = <0>; 768 compatible = "ti,mux-clock"; 769 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>; 770 ti,bit-shift = <25>; 771 reg = <0x1520>; 772 }; 773 774 hsi_fclk: hsi_fclk@1638 { 775 #clock-cells = <0>; 776 compatible = "ti,divider-clock"; 777 clocks = <&dpll_per_m2x2_ck>; 778 ti,bit-shift = <24>; 779 ti,max-div = <2>; 780 reg = <0x1638>; 781 }; 782}; 783 784&cm_core_clockdomains { 785 l3init_clkdm: l3init_clkdm { 786 compatible = "ti,clockdomain"; 787 clocks = <&dpll_usb_ck>; 788 }; 789}; 790 791&scrm_clocks { 792 auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 { 793 #clock-cells = <0>; 794 compatible = "ti,composite-no-wait-gate-clock"; 795 clocks = <&dpll_core_m3x2_ck>; 796 ti,bit-shift = <8>; 797 reg = <0x0310>; 798 }; 799 800 auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 { 801 #clock-cells = <0>; 802 compatible = "ti,composite-mux-clock"; 803 clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; 804 ti,bit-shift = <1>; 805 reg = <0x0310>; 806 }; 807 808 auxclk0_src_ck: auxclk0_src_ck { 809 #clock-cells = <0>; 810 compatible = "ti,composite-clock"; 811 clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>; 812 }; 813 814 auxclk0_ck: auxclk0_ck@310 { 815 #clock-cells = <0>; 816 compatible = "ti,divider-clock"; 817 clocks = <&auxclk0_src_ck>; 818 ti,bit-shift = <16>; 819 ti,max-div = <16>; 820 reg = <0x0310>; 821 }; 822 823 auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 { 824 #clock-cells = <0>; 825 compatible = "ti,composite-no-wait-gate-clock"; 826 clocks = <&dpll_core_m3x2_ck>; 827 ti,bit-shift = <8>; 828 reg = <0x0314>; 829 }; 830 831 auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 { 832 #clock-cells = <0>; 833 compatible = "ti,composite-mux-clock"; 834 clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; 835 ti,bit-shift = <1>; 836 reg = <0x0314>; 837 }; 838 839 auxclk1_src_ck: auxclk1_src_ck { 840 #clock-cells = <0>; 841 compatible = "ti,composite-clock"; 842 clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>; 843 }; 844 845 auxclk1_ck: auxclk1_ck@314 { 846 #clock-cells = <0>; 847 compatible = "ti,divider-clock"; 848 clocks = <&auxclk1_src_ck>; 849 ti,bit-shift = <16>; 850 ti,max-div = <16>; 851 reg = <0x0314>; 852 }; 853 854 auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 { 855 #clock-cells = <0>; 856 compatible = "ti,composite-no-wait-gate-clock"; 857 clocks = <&dpll_core_m3x2_ck>; 858 ti,bit-shift = <8>; 859 reg = <0x0318>; 860 }; 861 862 auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 { 863 #clock-cells = <0>; 864 compatible = "ti,composite-mux-clock"; 865 clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; 866 ti,bit-shift = <1>; 867 reg = <0x0318>; 868 }; 869 870 auxclk2_src_ck: auxclk2_src_ck { 871 #clock-cells = <0>; 872 compatible = "ti,composite-clock"; 873 clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>; 874 }; 875 876 auxclk2_ck: auxclk2_ck@318 { 877 #clock-cells = <0>; 878 compatible = "ti,divider-clock"; 879 clocks = <&auxclk2_src_ck>; 880 ti,bit-shift = <16>; 881 ti,max-div = <16>; 882 reg = <0x0318>; 883 }; 884 885 auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c { 886 #clock-cells = <0>; 887 compatible = "ti,composite-no-wait-gate-clock"; 888 clocks = <&dpll_core_m3x2_ck>; 889 ti,bit-shift = <8>; 890 reg = <0x031c>; 891 }; 892 893 auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c { 894 #clock-cells = <0>; 895 compatible = "ti,composite-mux-clock"; 896 clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; 897 ti,bit-shift = <1>; 898 reg = <0x031c>; 899 }; 900 901 auxclk3_src_ck: auxclk3_src_ck { 902 #clock-cells = <0>; 903 compatible = "ti,composite-clock"; 904 clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>; 905 }; 906 907 auxclk3_ck: auxclk3_ck@31c { 908 #clock-cells = <0>; 909 compatible = "ti,divider-clock"; 910 clocks = <&auxclk3_src_ck>; 911 ti,bit-shift = <16>; 912 ti,max-div = <16>; 913 reg = <0x031c>; 914 }; 915 916 auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 { 917 #clock-cells = <0>; 918 compatible = "ti,composite-no-wait-gate-clock"; 919 clocks = <&dpll_core_m3x2_ck>; 920 ti,bit-shift = <8>; 921 reg = <0x0320>; 922 }; 923 924 auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 { 925 #clock-cells = <0>; 926 compatible = "ti,composite-mux-clock"; 927 clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; 928 ti,bit-shift = <1>; 929 reg = <0x0320>; 930 }; 931 932 auxclk4_src_ck: auxclk4_src_ck { 933 #clock-cells = <0>; 934 compatible = "ti,composite-clock"; 935 clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>; 936 }; 937 938 auxclk4_ck: auxclk4_ck@320 { 939 #clock-cells = <0>; 940 compatible = "ti,divider-clock"; 941 clocks = <&auxclk4_src_ck>; 942 ti,bit-shift = <16>; 943 ti,max-div = <16>; 944 reg = <0x0320>; 945 }; 946 947 auxclkreq0_ck: auxclkreq0_ck@210 { 948 #clock-cells = <0>; 949 compatible = "ti,mux-clock"; 950 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; 951 ti,bit-shift = <2>; 952 reg = <0x0210>; 953 }; 954 955 auxclkreq1_ck: auxclkreq1_ck@214 { 956 #clock-cells = <0>; 957 compatible = "ti,mux-clock"; 958 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; 959 ti,bit-shift = <2>; 960 reg = <0x0214>; 961 }; 962 963 auxclkreq2_ck: auxclkreq2_ck@218 { 964 #clock-cells = <0>; 965 compatible = "ti,mux-clock"; 966 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; 967 ti,bit-shift = <2>; 968 reg = <0x0218>; 969 }; 970 971 auxclkreq3_ck: auxclkreq3_ck@21c { 972 #clock-cells = <0>; 973 compatible = "ti,mux-clock"; 974 clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; 975 ti,bit-shift = <2>; 976 reg = <0x021c>; 977 }; 978}; 979 980&cm_core_aon { 981 mpu_cm: mpu_cm@300 { 982 compatible = "ti,omap4-cm"; 983 reg = <0x300 0x100>; 984 #address-cells = <1>; 985 #size-cells = <1>; 986 ranges = <0 0x300 0x100>; 987 988 mpu_clkctrl: clk@20 { 989 compatible = "ti,clkctrl"; 990 reg = <0x20 0x4>; 991 #clock-cells = <2>; 992 }; 993 }; 994 995 dsp_cm: dsp_cm@400 { 996 compatible = "ti,omap4-cm"; 997 reg = <0x400 0x100>; 998 #address-cells = <1>; 999 #size-cells = <1>; 1000 ranges = <0 0x400 0x100>; 1001 1002 dsp_clkctrl: clk@20 { 1003 compatible = "ti,clkctrl"; 1004 reg = <0x20 0x4>; 1005 #clock-cells = <2>; 1006 }; 1007 }; 1008 1009 abe_cm: abe_cm@500 { 1010 compatible = "ti,omap4-cm"; 1011 reg = <0x500 0x100>; 1012 #address-cells = <1>; 1013 #size-cells = <1>; 1014 ranges = <0 0x500 0x100>; 1015 1016 abe_clkctrl: clk@20 { 1017 compatible = "ti,clkctrl"; 1018 reg = <0x20 0x64>; 1019 #clock-cells = <2>; 1020 }; 1021 }; 1022 1023}; 1024 1025&cm_core { 1026 l3main1_cm: l3main1_cm@700 { 1027 compatible = "ti,omap4-cm"; 1028 reg = <0x700 0x100>; 1029 #address-cells = <1>; 1030 #size-cells = <1>; 1031 ranges = <0 0x700 0x100>; 1032 1033 l3main1_clkctrl: clk@20 { 1034 compatible = "ti,clkctrl"; 1035 reg = <0x20 0x4>; 1036 #clock-cells = <2>; 1037 }; 1038 }; 1039 1040 l3main2_cm: l3main2_cm@800 { 1041 compatible = "ti,omap4-cm"; 1042 reg = <0x800 0x100>; 1043 #address-cells = <1>; 1044 #size-cells = <1>; 1045 ranges = <0 0x800 0x100>; 1046 1047 l3main2_clkctrl: clk@20 { 1048 compatible = "ti,clkctrl"; 1049 reg = <0x20 0x4>; 1050 #clock-cells = <2>; 1051 }; 1052 }; 1053 1054 ipu_cm: ipu_cm@900 { 1055 compatible = "ti,omap4-cm"; 1056 reg = <0x900 0x100>; 1057 #address-cells = <1>; 1058 #size-cells = <1>; 1059 ranges = <0 0x900 0x100>; 1060 1061 ipu_clkctrl: clk@20 { 1062 compatible = "ti,clkctrl"; 1063 reg = <0x20 0x4>; 1064 #clock-cells = <2>; 1065 }; 1066 }; 1067 1068 dma_cm: dma_cm@a00 { 1069 compatible = "ti,omap4-cm"; 1070 reg = <0xa00 0x100>; 1071 #address-cells = <1>; 1072 #size-cells = <1>; 1073 ranges = <0 0xa00 0x100>; 1074 1075 dma_clkctrl: clk@20 { 1076 compatible = "ti,clkctrl"; 1077 reg = <0x20 0x4>; 1078 #clock-cells = <2>; 1079 }; 1080 }; 1081 1082 emif_cm: emif_cm@b00 { 1083 compatible = "ti,omap4-cm"; 1084 reg = <0xb00 0x100>; 1085 #address-cells = <1>; 1086 #size-cells = <1>; 1087 ranges = <0 0xb00 0x100>; 1088 1089 emif_clkctrl: clk@20 { 1090 compatible = "ti,clkctrl"; 1091 reg = <0x20 0x1c>; 1092 #clock-cells = <2>; 1093 }; 1094 }; 1095 1096 l4cfg_cm: l4cfg_cm@d00 { 1097 compatible = "ti,omap4-cm"; 1098 reg = <0xd00 0x100>; 1099 #address-cells = <1>; 1100 #size-cells = <1>; 1101 ranges = <0 0xd00 0x100>; 1102 1103 l4cfg_clkctrl: clk@20 { 1104 compatible = "ti,clkctrl"; 1105 reg = <0x20 0x14>; 1106 #clock-cells = <2>; 1107 }; 1108 }; 1109 1110 l3instr_cm: l3instr_cm@e00 { 1111 compatible = "ti,omap4-cm"; 1112 reg = <0xe00 0x100>; 1113 #address-cells = <1>; 1114 #size-cells = <1>; 1115 ranges = <0 0xe00 0x100>; 1116 1117 l3instr_clkctrl: clk@20 { 1118 compatible = "ti,clkctrl"; 1119 reg = <0x20 0xc>; 1120 #clock-cells = <2>; 1121 }; 1122 }; 1123 1124 l4per_cm: l4per_cm@1000 { 1125 compatible = "ti,omap4-cm"; 1126 reg = <0x1000 0x200>; 1127 #address-cells = <1>; 1128 #size-cells = <1>; 1129 ranges = <0 0x1000 0x200>; 1130 1131 l4per_clkctrl: clk@20 { 1132 compatible = "ti,clkctrl"; 1133 reg = <0x20 0x15c>; 1134 #clock-cells = <2>; 1135 }; 1136 }; 1137 1138 dss_cm: dss_cm@1400 { 1139 compatible = "ti,omap4-cm"; 1140 reg = <0x1400 0x100>; 1141 #address-cells = <1>; 1142 #size-cells = <1>; 1143 ranges = <0 0x1400 0x100>; 1144 1145 dss_clkctrl: clk@20 { 1146 compatible = "ti,clkctrl"; 1147 reg = <0x20 0x4>; 1148 #clock-cells = <2>; 1149 }; 1150 }; 1151 1152 l3init_cm: l3init_cm@1600 { 1153 compatible = "ti,omap4-cm"; 1154 reg = <0x1600 0x100>; 1155 #address-cells = <1>; 1156 #size-cells = <1>; 1157 ranges = <0 0x1600 0x100>; 1158 1159 l3init_clkctrl: clk@20 { 1160 compatible = "ti,clkctrl"; 1161 reg = <0x20 0xd4>; 1162 #clock-cells = <2>; 1163 }; 1164 }; 1165}; 1166 1167&prm { 1168 wkupaon_cm: wkupaon_cm@1900 { 1169 compatible = "ti,omap4-cm"; 1170 reg = <0x1900 0x100>; 1171 #address-cells = <1>; 1172 #size-cells = <1>; 1173 ranges = <0 0x1900 0x100>; 1174 1175 wkupaon_clkctrl: clk@20 { 1176 compatible = "ti,clkctrl"; 1177 reg = <0x20 0x5c>; 1178 #clock-cells = <2>; 1179 }; 1180 }; 1181}; 1182 1183&scm_wkup_pad_conf_clocks { 1184 fref_xtal_ck: fref_xtal_ck { 1185 #clock-cells = <0>; 1186 compatible = "ti,gate-clock"; 1187 clocks = <&sys_clkin>; 1188 ti,bit-shift = <28>; 1189 reg = <0x14>; 1190 }; 1191}; 1192
