1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * OHCI HCD(Host Controller Driver) for USB.
4 *
5 *(C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
6 *(C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
7 *(C) Copyright 2002 Hewlett-Packard Company
8 *
9 * Bus glue for Toshiba Mobile IO(TMIO) Controller's OHCI core
10 * (C) Copyright 2005 Chris Humbert <mahadri-usb@drigon.com>
11 * (C) Copyright 2007, 2008 Dmitry Baryshkov <dbaryshkov@gmail.com>
12 *
13 * This is known to work with the following variants:
14 * TC6393XB revision 3 (32kB SRAM)
15 *
16 * The TMIO's OHCI core DMAs through a small internal buffer that
17 * is directly addressable by the CPU.
18 *
19 * Written from sparse documentation from Toshiba and Sharp's driver
20 * for the 2.4 kernel,
21 * usb-ohci-tc6393.c(C) Copyright 2004 Lineo Solutions, Inc.
22 */
23
24 /*#include <linux/fs.h>
25 #include <linux/mount.h>
26 #include <linux/pagemap.h>
27 #include <linux/namei.h>
28 #include <linux/sched.h>*/
29 #include <linux/platform_device.h>
30 #include <linux/mfd/core.h>
31 #include <linux/mfd/tmio.h>
32 #include <linux/dma-mapping.h>
33
34 /*-------------------------------------------------------------------------*/
35
36 /*
37 * USB Host Controller Configuration Register
38 */
39 #define CCR_REVID 0x08 /* b Revision ID */
40 #define CCR_BASE 0x10 /* l USB Control Register Base Address Low */
41 #define CCR_ILME 0x40 /* b Internal Local Memory Enable */
42 #define CCR_PM 0x4c /* w Power Management */
43 #define CCR_INTC 0x50 /* b INT Control */
44 #define CCR_LMW1L 0x54 /* w Local Memory Window 1 LMADRS Low */
45 #define CCR_LMW1H 0x56 /* w Local Memory Window 1 LMADRS High */
46 #define CCR_LMW1BL 0x58 /* w Local Memory Window 1 Base Address Low */
47 #define CCR_LMW1BH 0x5A /* w Local Memory Window 1 Base Address High */
48 #define CCR_LMW2L 0x5C /* w Local Memory Window 2 LMADRS Low */
49 #define CCR_LMW2H 0x5E /* w Local Memory Window 2 LMADRS High */
50 #define CCR_LMW2BL 0x60 /* w Local Memory Window 2 Base Address Low */
51 #define CCR_LMW2BH 0x62 /* w Local Memory Window 2 Base Address High */
52 #define CCR_MISC 0xFC /* b MISC */
53
54 #define CCR_PM_GKEN 0x0001
55 #define CCR_PM_CKRNEN 0x0002
56 #define CCR_PM_USBPW1 0x0004
57 #define CCR_PM_USBPW2 0x0008
58 #define CCR_PM_USBPW3 0x0010
59 #define CCR_PM_PMEE 0x0100
60 #define CCR_PM_PMES 0x8000
61
62 /*-------------------------------------------------------------------------*/
63
64 struct tmio_hcd {
65 void __iomem *ccr;
66 spinlock_t lock; /* protects RMW cycles */
67 };
68
69 #define hcd_to_tmio(hcd) ((struct tmio_hcd *)(hcd_to_ohci(hcd) + 1))
70
71 /*-------------------------------------------------------------------------*/
72
tmio_write_pm(struct platform_device * dev)73 static void tmio_write_pm(struct platform_device *dev)
74 {
75 struct usb_hcd *hcd = platform_get_drvdata(dev);
76 struct tmio_hcd *tmio = hcd_to_tmio(hcd);
77 u16 pm;
78 unsigned long flags;
79
80 spin_lock_irqsave(&tmio->lock, flags);
81
82 pm = CCR_PM_GKEN | CCR_PM_CKRNEN |
83 CCR_PM_PMEE | CCR_PM_PMES;
84
85 tmio_iowrite16(pm, tmio->ccr + CCR_PM);
86 spin_unlock_irqrestore(&tmio->lock, flags);
87 }
88
tmio_stop_hc(struct platform_device * dev)89 static void tmio_stop_hc(struct platform_device *dev)
90 {
91 struct usb_hcd *hcd = platform_get_drvdata(dev);
92 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
93 struct tmio_hcd *tmio = hcd_to_tmio(hcd);
94 u16 pm;
95
96 pm = CCR_PM_GKEN | CCR_PM_CKRNEN;
97 switch (ohci->num_ports) {
98 default:
99 dev_err(&dev->dev, "Unsupported amount of ports: %d\n", ohci->num_ports);
100 case 3:
101 pm |= CCR_PM_USBPW3;
102 case 2:
103 pm |= CCR_PM_USBPW2;
104 case 1:
105 pm |= CCR_PM_USBPW1;
106 }
107 tmio_iowrite8(0, tmio->ccr + CCR_INTC);
108 tmio_iowrite8(0, tmio->ccr + CCR_ILME);
109 tmio_iowrite16(0, tmio->ccr + CCR_BASE);
110 tmio_iowrite16(0, tmio->ccr + CCR_BASE + 2);
111 tmio_iowrite16(pm, tmio->ccr + CCR_PM);
112 }
113
tmio_start_hc(struct platform_device * dev)114 static void tmio_start_hc(struct platform_device *dev)
115 {
116 struct usb_hcd *hcd = platform_get_drvdata(dev);
117 struct tmio_hcd *tmio = hcd_to_tmio(hcd);
118 unsigned long base = hcd->rsrc_start;
119
120 tmio_write_pm(dev);
121 tmio_iowrite16(base, tmio->ccr + CCR_BASE);
122 tmio_iowrite16(base >> 16, tmio->ccr + CCR_BASE + 2);
123 tmio_iowrite8(1, tmio->ccr + CCR_ILME);
124 tmio_iowrite8(2, tmio->ccr + CCR_INTC);
125
126 dev_info(&dev->dev, "revision %d @ 0x%08llx, irq %d\n",
127 tmio_ioread8(tmio->ccr + CCR_REVID),
128 (u64) hcd->rsrc_start, hcd->irq);
129 }
130
ohci_tmio_start(struct usb_hcd * hcd)131 static int ohci_tmio_start(struct usb_hcd *hcd)
132 {
133 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
134 int ret;
135
136 if ((ret = ohci_init(ohci)) < 0)
137 return ret;
138
139 if ((ret = ohci_run(ohci)) < 0) {
140 dev_err(hcd->self.controller, "can't start %s\n",
141 hcd->self.bus_name);
142 ohci_stop(hcd);
143 return ret;
144 }
145
146 return 0;
147 }
148
149 static const struct hc_driver ohci_tmio_hc_driver = {
150 .description = hcd_name,
151 .product_desc = "TMIO OHCI USB Host Controller",
152 .hcd_priv_size = sizeof(struct ohci_hcd) + sizeof (struct tmio_hcd),
153
154 /* generic hardware linkage */
155 .irq = ohci_irq,
156 .flags = HCD_USB11 | HCD_MEMORY | HCD_LOCAL_MEM,
157
158 /* basic lifecycle operations */
159 .start = ohci_tmio_start,
160 .stop = ohci_stop,
161 .shutdown = ohci_shutdown,
162
163 /* managing i/o requests and associated device resources */
164 .urb_enqueue = ohci_urb_enqueue,
165 .urb_dequeue = ohci_urb_dequeue,
166 .endpoint_disable = ohci_endpoint_disable,
167
168 /* scheduling support */
169 .get_frame_number = ohci_get_frame,
170
171 /* root hub support */
172 .hub_status_data = ohci_hub_status_data,
173 .hub_control = ohci_hub_control,
174 #ifdef CONFIG_PM
175 .bus_suspend = ohci_bus_suspend,
176 .bus_resume = ohci_bus_resume,
177 #endif
178 .start_port_reset = ohci_start_port_reset,
179 };
180
181 /*-------------------------------------------------------------------------*/
182 static struct platform_driver ohci_hcd_tmio_driver;
183
ohci_hcd_tmio_drv_probe(struct platform_device * dev)184 static int ohci_hcd_tmio_drv_probe(struct platform_device *dev)
185 {
186 const struct mfd_cell *cell = mfd_get_cell(dev);
187 struct resource *regs = platform_get_resource(dev, IORESOURCE_MEM, 0);
188 struct resource *config = platform_get_resource(dev, IORESOURCE_MEM, 1);
189 struct resource *sram = platform_get_resource(dev, IORESOURCE_MEM, 2);
190 int irq = platform_get_irq(dev, 0);
191 struct tmio_hcd *tmio;
192 struct ohci_hcd *ohci;
193 struct usb_hcd *hcd;
194 int ret;
195
196 if (usb_disabled())
197 return -ENODEV;
198
199 if (!cell)
200 return -EINVAL;
201
202 hcd = usb_create_hcd(&ohci_tmio_hc_driver, &dev->dev, dev_name(&dev->dev));
203 if (!hcd) {
204 ret = -ENOMEM;
205 goto err_usb_create_hcd;
206 }
207
208 hcd->rsrc_start = regs->start;
209 hcd->rsrc_len = resource_size(regs);
210
211 tmio = hcd_to_tmio(hcd);
212
213 spin_lock_init(&tmio->lock);
214
215 tmio->ccr = ioremap(config->start, resource_size(config));
216 if (!tmio->ccr) {
217 ret = -ENOMEM;
218 goto err_ioremap_ccr;
219 }
220
221 hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
222 if (!hcd->regs) {
223 ret = -ENOMEM;
224 goto err_ioremap_regs;
225 }
226
227 ret = dma_declare_coherent_memory(&dev->dev, sram->start, sram->start,
228 resource_size(sram), DMA_MEMORY_EXCLUSIVE);
229 if (ret)
230 goto err_dma_declare;
231
232 if (cell->enable) {
233 ret = cell->enable(dev);
234 if (ret)
235 goto err_enable;
236 }
237
238 tmio_start_hc(dev);
239 ohci = hcd_to_ohci(hcd);
240 ohci_hcd_init(ohci);
241
242 ret = usb_add_hcd(hcd, irq, 0);
243 if (ret)
244 goto err_add_hcd;
245
246 device_wakeup_enable(hcd->self.controller);
247 if (ret == 0)
248 return ret;
249
250 usb_remove_hcd(hcd);
251
252 err_add_hcd:
253 tmio_stop_hc(dev);
254 if (cell->disable)
255 cell->disable(dev);
256 err_enable:
257 dma_release_declared_memory(&dev->dev);
258 err_dma_declare:
259 iounmap(hcd->regs);
260 err_ioremap_regs:
261 iounmap(tmio->ccr);
262 err_ioremap_ccr:
263 usb_put_hcd(hcd);
264 err_usb_create_hcd:
265
266 return ret;
267 }
268
ohci_hcd_tmio_drv_remove(struct platform_device * dev)269 static int ohci_hcd_tmio_drv_remove(struct platform_device *dev)
270 {
271 struct usb_hcd *hcd = platform_get_drvdata(dev);
272 struct tmio_hcd *tmio = hcd_to_tmio(hcd);
273 const struct mfd_cell *cell = mfd_get_cell(dev);
274
275 usb_remove_hcd(hcd);
276 tmio_stop_hc(dev);
277 if (cell->disable)
278 cell->disable(dev);
279 dma_release_declared_memory(&dev->dev);
280 iounmap(hcd->regs);
281 iounmap(tmio->ccr);
282 usb_put_hcd(hcd);
283
284 return 0;
285 }
286
287 #ifdef CONFIG_PM
ohci_hcd_tmio_drv_suspend(struct platform_device * dev,pm_message_t state)288 static int ohci_hcd_tmio_drv_suspend(struct platform_device *dev, pm_message_t state)
289 {
290 const struct mfd_cell *cell = mfd_get_cell(dev);
291 struct usb_hcd *hcd = platform_get_drvdata(dev);
292 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
293 struct tmio_hcd *tmio = hcd_to_tmio(hcd);
294 unsigned long flags;
295 u8 misc;
296 int ret;
297
298 if (time_before(jiffies, ohci->next_statechange))
299 msleep(5);
300 ohci->next_statechange = jiffies;
301
302 spin_lock_irqsave(&tmio->lock, flags);
303
304 misc = tmio_ioread8(tmio->ccr + CCR_MISC);
305 misc |= 1 << 3; /* USSUSP */
306 tmio_iowrite8(misc, tmio->ccr + CCR_MISC);
307
308 spin_unlock_irqrestore(&tmio->lock, flags);
309
310 if (cell->suspend) {
311 ret = cell->suspend(dev);
312 if (ret)
313 return ret;
314 }
315 return 0;
316 }
317
ohci_hcd_tmio_drv_resume(struct platform_device * dev)318 static int ohci_hcd_tmio_drv_resume(struct platform_device *dev)
319 {
320 const struct mfd_cell *cell = mfd_get_cell(dev);
321 struct usb_hcd *hcd = platform_get_drvdata(dev);
322 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
323 struct tmio_hcd *tmio = hcd_to_tmio(hcd);
324 unsigned long flags;
325 u8 misc;
326 int ret;
327
328 if (time_before(jiffies, ohci->next_statechange))
329 msleep(5);
330 ohci->next_statechange = jiffies;
331
332 if (cell->resume) {
333 ret = cell->resume(dev);
334 if (ret)
335 return ret;
336 }
337
338 tmio_start_hc(dev);
339
340 spin_lock_irqsave(&tmio->lock, flags);
341
342 misc = tmio_ioread8(tmio->ccr + CCR_MISC);
343 misc &= ~(1 << 3); /* USSUSP */
344 tmio_iowrite8(misc, tmio->ccr + CCR_MISC);
345
346 spin_unlock_irqrestore(&tmio->lock, flags);
347
348 ohci_resume(hcd, false);
349
350 return 0;
351 }
352 #else
353 #define ohci_hcd_tmio_drv_suspend NULL
354 #define ohci_hcd_tmio_drv_resume NULL
355 #endif
356
357 static struct platform_driver ohci_hcd_tmio_driver = {
358 .probe = ohci_hcd_tmio_drv_probe,
359 .remove = ohci_hcd_tmio_drv_remove,
360 .shutdown = usb_hcd_platform_shutdown,
361 .suspend = ohci_hcd_tmio_drv_suspend,
362 .resume = ohci_hcd_tmio_drv_resume,
363 .driver = {
364 .name = "tmio-ohci",
365 },
366 };
367
