1 #define CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE 512
2 #define XKPHYS_TO_PHYS(p) (p)
3
4 #define OCTEON_IRQ_WORKQ0 0
5 #define OCTEON_IRQ_RML 0
6 #define OCTEON_IRQ_TIMER1 0
7 #define OCTEON_IS_MODEL(x) 0
8 #define octeon_has_feature(x) 0
9 #define octeon_get_clock_rate() 0
10
11 #define CVMX_SYNCIOBDMA do { } while(0)
12
13 #define CVMX_HELPER_INPUT_TAG_TYPE 0
14 #define CVMX_HELPER_FIRST_MBUFF_SKIP 7
15 #define CVMX_FAU_REG_END (2048)
16 #define CVMX_FPA_OUTPUT_BUFFER_POOL (2)
17 #define CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE 16
18 #define CVMX_FPA_PACKET_POOL (0)
19 #define CVMX_FPA_PACKET_POOL_SIZE 16
20 #define CVMX_FPA_WQE_POOL (1)
21 #define CVMX_FPA_WQE_POOL_SIZE 16
22 #define CVMX_GMXX_RXX_ADR_CAM_EN(a, b) ((a)+(b))
23 #define CVMX_GMXX_RXX_ADR_CTL(a, b) ((a)+(b))
24 #define CVMX_GMXX_PRTX_CFG(a, b) ((a)+(b))
25 #define CVMX_GMXX_RXX_FRM_MAX(a, b) ((a)+(b))
26 #define CVMX_GMXX_RXX_JABBER(a, b) ((a)+(b))
27 #define CVMX_IPD_CTL_STATUS 0
28 #define CVMX_PIP_FRM_LEN_CHKX(a) (a)
29 #define CVMX_PIP_NUM_INPUT_PORTS 1
30 #define CVMX_SCR_SCRATCH 0
31 #define CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 2
32 #define CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 2
33 #define CVMX_IPD_SUB_PORT_FCS 0
34 #define CVMX_SSO_WQ_IQ_DIS 0
35 #define CVMX_SSO_WQ_INT 0
36 #define CVMX_POW_WQ_INT 0
37 #define CVMX_SSO_WQ_INT_PC 0
38 #define CVMX_NPI_RSL_INT_BLOCKS 0
39 #define CVMX_POW_WQ_INT_PC 0
40
41 typedef union {
42 uint64_t u64;
43 struct {
44 uint64_t bufs:8;
45 uint64_t ip_offset:8;
46 uint64_t vlan_valid:1;
47 uint64_t vlan_stacked:1;
48 uint64_t unassigned:1;
49 uint64_t vlan_cfi:1;
50 uint64_t vlan_id:12;
51 uint64_t pr:4;
52 uint64_t unassigned2:8;
53 uint64_t dec_ipcomp:1;
54 uint64_t tcp_or_udp:1;
55 uint64_t dec_ipsec:1;
56 uint64_t is_v6:1;
57 uint64_t software:1;
58 uint64_t L4_error:1;
59 uint64_t is_frag:1;
60 uint64_t IP_exc:1;
61 uint64_t is_bcast:1;
62 uint64_t is_mcast:1;
63 uint64_t not_IP:1;
64 uint64_t rcv_error:1;
65 uint64_t err_code:8;
66 } s;
67 struct {
68 uint64_t bufs:8;
69 uint64_t ip_offset:8;
70 uint64_t vlan_valid:1;
71 uint64_t vlan_stacked:1;
72 uint64_t unassigned:1;
73 uint64_t vlan_cfi:1;
74 uint64_t vlan_id:12;
75 uint64_t port:12;
76 uint64_t dec_ipcomp:1;
77 uint64_t tcp_or_udp:1;
78 uint64_t dec_ipsec:1;
79 uint64_t is_v6:1;
80 uint64_t software:1;
81 uint64_t L4_error:1;
82 uint64_t is_frag:1;
83 uint64_t IP_exc:1;
84 uint64_t is_bcast:1;
85 uint64_t is_mcast:1;
86 uint64_t not_IP:1;
87 uint64_t rcv_error:1;
88 uint64_t err_code:8;
89 } s_cn68xx;
90
91 struct {
92 uint64_t unused1:16;
93 uint64_t vlan:16;
94 uint64_t unused2:32;
95 } svlan;
96 struct {
97 uint64_t bufs:8;
98 uint64_t unused:8;
99 uint64_t vlan_valid:1;
100 uint64_t vlan_stacked:1;
101 uint64_t unassigned:1;
102 uint64_t vlan_cfi:1;
103 uint64_t vlan_id:12;
104 uint64_t pr:4;
105 uint64_t unassigned2:12;
106 uint64_t software:1;
107 uint64_t unassigned3:1;
108 uint64_t is_rarp:1;
109 uint64_t is_arp:1;
110 uint64_t is_bcast:1;
111 uint64_t is_mcast:1;
112 uint64_t not_IP:1;
113 uint64_t rcv_error:1;
114 uint64_t err_code:8;
115 } snoip;
116
117 } cvmx_pip_wqe_word2;
118
119 union cvmx_pip_wqe_word0 {
120 struct {
121 uint64_t next_ptr:40;
122 uint8_t unused;
123 uint16_t hw_chksum;
124 } cn38xx;
125 struct {
126 uint64_t pknd:6; /* 0..5 */
127 uint64_t unused2:2; /* 6..7 */
128 uint64_t bpid:6; /* 8..13 */
129 uint64_t unused1:18; /* 14..31 */
130 uint64_t l2ptr:8; /* 32..39 */
131 uint64_t l3ptr:8; /* 40..47 */
132 uint64_t unused0:8; /* 48..55 */
133 uint64_t l4ptr:8; /* 56..63 */
134 } cn68xx;
135 };
136
137 union cvmx_wqe_word0 {
138 uint64_t u64;
139 union cvmx_pip_wqe_word0 pip;
140 };
141
142 union cvmx_wqe_word1 {
143 uint64_t u64;
144 struct {
145 uint64_t tag:32;
146 uint64_t tag_type:2;
147 uint64_t varies:14;
148 uint64_t len:16;
149 };
150 struct {
151 uint64_t tag:32;
152 uint64_t tag_type:2;
153 uint64_t zero_2:3;
154 uint64_t grp:6;
155 uint64_t zero_1:1;
156 uint64_t qos:3;
157 uint64_t zero_0:1;
158 uint64_t len:16;
159 } cn68xx;
160 struct {
161 uint64_t tag:32;
162 uint64_t tag_type:2;
163 uint64_t zero_2:1;
164 uint64_t grp:4;
165 uint64_t qos:3;
166 uint64_t ipprt:6;
167 uint64_t len:16;
168 } cn38xx;
169 };
170
171 union cvmx_buf_ptr {
172 void *ptr;
173 uint64_t u64;
174 struct {
175 uint64_t i:1;
176 uint64_t back:4;
177 uint64_t pool:3;
178 uint64_t size:16;
179 uint64_t addr:40;
180 } s;
181 };
182
183 typedef struct {
184 union cvmx_wqe_word0 word0;
185 union cvmx_wqe_word1 word1;
186 cvmx_pip_wqe_word2 word2;
187 union cvmx_buf_ptr packet_ptr;
188 uint8_t packet_data[96];
189 } cvmx_wqe_t;
190
191 typedef union {
192 uint64_t u64;
193 struct {
194 uint64_t reserved_20_63:44;
195 uint64_t link_up:1; /**< Is the physical link up? */
196 uint64_t full_duplex:1; /**< 1 if the link is full duplex */
197 uint64_t speed:18; /**< Speed of the link in Mbps */
198 } s;
199 } cvmx_helper_link_info_t;
200
201 typedef enum {
202 CVMX_FAU_REG_32_START = 0,
203 } cvmx_fau_reg_32_t;
204
205 typedef enum {
206 CVMX_FAU_OP_SIZE_8 = 0,
207 CVMX_FAU_OP_SIZE_16 = 1,
208 CVMX_FAU_OP_SIZE_32 = 2,
209 CVMX_FAU_OP_SIZE_64 = 3
210 } cvmx_fau_op_size_t;
211
212 typedef enum {
213 CVMX_SPI_MODE_UNKNOWN = 0,
214 CVMX_SPI_MODE_TX_HALFPLEX = 1,
215 CVMX_SPI_MODE_RX_HALFPLEX = 2,
216 CVMX_SPI_MODE_DUPLEX = 3
217 } cvmx_spi_mode_t;
218
219 typedef enum {
220 CVMX_HELPER_INTERFACE_MODE_DISABLED,
221 CVMX_HELPER_INTERFACE_MODE_RGMII,
222 CVMX_HELPER_INTERFACE_MODE_GMII,
223 CVMX_HELPER_INTERFACE_MODE_SPI,
224 CVMX_HELPER_INTERFACE_MODE_PCIE,
225 CVMX_HELPER_INTERFACE_MODE_XAUI,
226 CVMX_HELPER_INTERFACE_MODE_SGMII,
227 CVMX_HELPER_INTERFACE_MODE_PICMG,
228 CVMX_HELPER_INTERFACE_MODE_NPI,
229 CVMX_HELPER_INTERFACE_MODE_LOOP,
230 } cvmx_helper_interface_mode_t;
231
232 typedef enum {
233 CVMX_POW_WAIT = 1,
234 CVMX_POW_NO_WAIT = 0,
235 } cvmx_pow_wait_t;
236
237 typedef enum {
238 CVMX_PKO_LOCK_NONE = 0,
239 CVMX_PKO_LOCK_ATOMIC_TAG = 1,
240 CVMX_PKO_LOCK_CMD_QUEUE = 2,
241 } cvmx_pko_lock_t;
242
243 typedef enum {
244 CVMX_PKO_SUCCESS,
245 CVMX_PKO_INVALID_PORT,
246 CVMX_PKO_INVALID_QUEUE,
247 CVMX_PKO_INVALID_PRIORITY,
248 CVMX_PKO_NO_MEMORY,
249 CVMX_PKO_PORT_ALREADY_SETUP,
250 CVMX_PKO_CMD_QUEUE_INIT_ERROR
251 } cvmx_pko_status_t;
252
253 enum cvmx_pow_tag_type {
254 CVMX_POW_TAG_TYPE_ORDERED = 0L,
255 CVMX_POW_TAG_TYPE_ATOMIC = 1L,
256 CVMX_POW_TAG_TYPE_NULL = 2L,
257 CVMX_POW_TAG_TYPE_NULL_NULL = 3L
258 };
259
260 union cvmx_ipd_ctl_status {
261 uint64_t u64;
262 struct cvmx_ipd_ctl_status_s {
263 uint64_t reserved_18_63:46;
264 uint64_t use_sop:1;
265 uint64_t rst_done:1;
266 uint64_t clken:1;
267 uint64_t no_wptr:1;
268 uint64_t pq_apkt:1;
269 uint64_t pq_nabuf:1;
270 uint64_t ipd_full:1;
271 uint64_t pkt_off:1;
272 uint64_t len_m8:1;
273 uint64_t reset:1;
274 uint64_t addpkt:1;
275 uint64_t naddbuf:1;
276 uint64_t pkt_lend:1;
277 uint64_t wqe_lend:1;
278 uint64_t pbp_en:1;
279 uint64_t opc_mode:2;
280 uint64_t ipd_en:1;
281 } s;
282 struct cvmx_ipd_ctl_status_cn30xx {
283 uint64_t reserved_10_63:54;
284 uint64_t len_m8:1;
285 uint64_t reset:1;
286 uint64_t addpkt:1;
287 uint64_t naddbuf:1;
288 uint64_t pkt_lend:1;
289 uint64_t wqe_lend:1;
290 uint64_t pbp_en:1;
291 uint64_t opc_mode:2;
292 uint64_t ipd_en:1;
293 } cn30xx;
294 struct cvmx_ipd_ctl_status_cn38xxp2 {
295 uint64_t reserved_9_63:55;
296 uint64_t reset:1;
297 uint64_t addpkt:1;
298 uint64_t naddbuf:1;
299 uint64_t pkt_lend:1;
300 uint64_t wqe_lend:1;
301 uint64_t pbp_en:1;
302 uint64_t opc_mode:2;
303 uint64_t ipd_en:1;
304 } cn38xxp2;
305 struct cvmx_ipd_ctl_status_cn50xx {
306 uint64_t reserved_15_63:49;
307 uint64_t no_wptr:1;
308 uint64_t pq_apkt:1;
309 uint64_t pq_nabuf:1;
310 uint64_t ipd_full:1;
311 uint64_t pkt_off:1;
312 uint64_t len_m8:1;
313 uint64_t reset:1;
314 uint64_t addpkt:1;
315 uint64_t naddbuf:1;
316 uint64_t pkt_lend:1;
317 uint64_t wqe_lend:1;
318 uint64_t pbp_en:1;
319 uint64_t opc_mode:2;
320 uint64_t ipd_en:1;
321 } cn50xx;
322 struct cvmx_ipd_ctl_status_cn58xx {
323 uint64_t reserved_12_63:52;
324 uint64_t ipd_full:1;
325 uint64_t pkt_off:1;
326 uint64_t len_m8:1;
327 uint64_t reset:1;
328 uint64_t addpkt:1;
329 uint64_t naddbuf:1;
330 uint64_t pkt_lend:1;
331 uint64_t wqe_lend:1;
332 uint64_t pbp_en:1;
333 uint64_t opc_mode:2;
334 uint64_t ipd_en:1;
335 } cn58xx;
336 struct cvmx_ipd_ctl_status_cn63xxp1 {
337 uint64_t reserved_16_63:48;
338 uint64_t clken:1;
339 uint64_t no_wptr:1;
340 uint64_t pq_apkt:1;
341 uint64_t pq_nabuf:1;
342 uint64_t ipd_full:1;
343 uint64_t pkt_off:1;
344 uint64_t len_m8:1;
345 uint64_t reset:1;
346 uint64_t addpkt:1;
347 uint64_t naddbuf:1;
348 uint64_t pkt_lend:1;
349 uint64_t wqe_lend:1;
350 uint64_t pbp_en:1;
351 uint64_t opc_mode:2;
352 uint64_t ipd_en:1;
353 } cn63xxp1;
354 };
355
356 union cvmx_ipd_sub_port_fcs {
357 uint64_t u64;
358 struct cvmx_ipd_sub_port_fcs_s {
359 uint64_t port_bit:32;
360 uint64_t reserved_32_35:4;
361 uint64_t port_bit2:4;
362 uint64_t reserved_40_63:24;
363 } s;
364 struct cvmx_ipd_sub_port_fcs_cn30xx {
365 uint64_t port_bit:3;
366 uint64_t reserved_3_63:61;
367 } cn30xx;
368 struct cvmx_ipd_sub_port_fcs_cn38xx {
369 uint64_t port_bit:32;
370 uint64_t reserved_32_63:32;
371 } cn38xx;
372 };
373
374 union cvmx_ipd_sub_port_qos_cnt {
375 uint64_t u64;
376 struct cvmx_ipd_sub_port_qos_cnt_s {
377 uint64_t cnt:32;
378 uint64_t port_qos:9;
379 uint64_t reserved_41_63:23;
380 } s;
381 };
382 typedef struct {
383 uint32_t dropped_octets;
384 uint32_t dropped_packets;
385 uint32_t pci_raw_packets;
386 uint32_t octets;
387 uint32_t packets;
388 uint32_t multicast_packets;
389 uint32_t broadcast_packets;
390 uint32_t len_64_packets;
391 uint32_t len_65_127_packets;
392 uint32_t len_128_255_packets;
393 uint32_t len_256_511_packets;
394 uint32_t len_512_1023_packets;
395 uint32_t len_1024_1518_packets;
396 uint32_t len_1519_max_packets;
397 uint32_t fcs_align_err_packets;
398 uint32_t runt_packets;
399 uint32_t runt_crc_packets;
400 uint32_t oversize_packets;
401 uint32_t oversize_crc_packets;
402 uint32_t inb_packets;
403 uint64_t inb_octets;
404 uint16_t inb_errors;
405 } cvmx_pip_port_status_t;
406
407 typedef struct {
408 uint32_t packets;
409 uint64_t octets;
410 uint64_t doorbell;
411 } cvmx_pko_port_status_t;
412
413 union cvmx_pip_frm_len_chkx {
414 uint64_t u64;
415 struct cvmx_pip_frm_len_chkx_s {
416 uint64_t reserved_32_63:32;
417 uint64_t maxlen:16;
418 uint64_t minlen:16;
419 } s;
420 };
421
422 union cvmx_gmxx_rxx_frm_ctl {
423 uint64_t u64;
424 struct cvmx_gmxx_rxx_frm_ctl_s {
425 uint64_t pre_chk:1;
426 uint64_t pre_strp:1;
427 uint64_t ctl_drp:1;
428 uint64_t ctl_bck:1;
429 uint64_t ctl_mcst:1;
430 uint64_t ctl_smac:1;
431 uint64_t pre_free:1;
432 uint64_t vlan_len:1;
433 uint64_t pad_len:1;
434 uint64_t pre_align:1;
435 uint64_t null_dis:1;
436 uint64_t reserved_11_11:1;
437 uint64_t ptp_mode:1;
438 uint64_t reserved_13_63:51;
439 } s;
440 struct cvmx_gmxx_rxx_frm_ctl_cn30xx {
441 uint64_t pre_chk:1;
442 uint64_t pre_strp:1;
443 uint64_t ctl_drp:1;
444 uint64_t ctl_bck:1;
445 uint64_t ctl_mcst:1;
446 uint64_t ctl_smac:1;
447 uint64_t pre_free:1;
448 uint64_t vlan_len:1;
449 uint64_t pad_len:1;
450 uint64_t reserved_9_63:55;
451 } cn30xx;
452 struct cvmx_gmxx_rxx_frm_ctl_cn31xx {
453 uint64_t pre_chk:1;
454 uint64_t pre_strp:1;
455 uint64_t ctl_drp:1;
456 uint64_t ctl_bck:1;
457 uint64_t ctl_mcst:1;
458 uint64_t ctl_smac:1;
459 uint64_t pre_free:1;
460 uint64_t vlan_len:1;
461 uint64_t reserved_8_63:56;
462 } cn31xx;
463 struct cvmx_gmxx_rxx_frm_ctl_cn50xx {
464 uint64_t pre_chk:1;
465 uint64_t pre_strp:1;
466 uint64_t ctl_drp:1;
467 uint64_t ctl_bck:1;
468 uint64_t ctl_mcst:1;
469 uint64_t ctl_smac:1;
470 uint64_t pre_free:1;
471 uint64_t reserved_7_8:2;
472 uint64_t pre_align:1;
473 uint64_t null_dis:1;
474 uint64_t reserved_11_63:53;
475 } cn50xx;
476 struct cvmx_gmxx_rxx_frm_ctl_cn56xxp1 {
477 uint64_t pre_chk:1;
478 uint64_t pre_strp:1;
479 uint64_t ctl_drp:1;
480 uint64_t ctl_bck:1;
481 uint64_t ctl_mcst:1;
482 uint64_t ctl_smac:1;
483 uint64_t pre_free:1;
484 uint64_t reserved_7_8:2;
485 uint64_t pre_align:1;
486 uint64_t reserved_10_63:54;
487 } cn56xxp1;
488 struct cvmx_gmxx_rxx_frm_ctl_cn58xx {
489 uint64_t pre_chk:1;
490 uint64_t pre_strp:1;
491 uint64_t ctl_drp:1;
492 uint64_t ctl_bck:1;
493 uint64_t ctl_mcst:1;
494 uint64_t ctl_smac:1;
495 uint64_t pre_free:1;
496 uint64_t vlan_len:1;
497 uint64_t pad_len:1;
498 uint64_t pre_align:1;
499 uint64_t null_dis:1;
500 uint64_t reserved_11_63:53;
501 } cn58xx;
502 struct cvmx_gmxx_rxx_frm_ctl_cn61xx {
503 uint64_t pre_chk:1;
504 uint64_t pre_strp:1;
505 uint64_t ctl_drp:1;
506 uint64_t ctl_bck:1;
507 uint64_t ctl_mcst:1;
508 uint64_t ctl_smac:1;
509 uint64_t pre_free:1;
510 uint64_t reserved_7_8:2;
511 uint64_t pre_align:1;
512 uint64_t null_dis:1;
513 uint64_t reserved_11_11:1;
514 uint64_t ptp_mode:1;
515 uint64_t reserved_13_63:51;
516 } cn61xx;
517 };
518
519 union cvmx_gmxx_rxx_int_reg {
520 uint64_t u64;
521 struct cvmx_gmxx_rxx_int_reg_s {
522 uint64_t minerr:1;
523 uint64_t carext:1;
524 uint64_t maxerr:1;
525 uint64_t jabber:1;
526 uint64_t fcserr:1;
527 uint64_t alnerr:1;
528 uint64_t lenerr:1;
529 uint64_t rcverr:1;
530 uint64_t skperr:1;
531 uint64_t niberr:1;
532 uint64_t ovrerr:1;
533 uint64_t pcterr:1;
534 uint64_t rsverr:1;
535 uint64_t falerr:1;
536 uint64_t coldet:1;
537 uint64_t ifgerr:1;
538 uint64_t phy_link:1;
539 uint64_t phy_spd:1;
540 uint64_t phy_dupx:1;
541 uint64_t pause_drp:1;
542 uint64_t loc_fault:1;
543 uint64_t rem_fault:1;
544 uint64_t bad_seq:1;
545 uint64_t bad_term:1;
546 uint64_t unsop:1;
547 uint64_t uneop:1;
548 uint64_t undat:1;
549 uint64_t hg2fld:1;
550 uint64_t hg2cc:1;
551 uint64_t reserved_29_63:35;
552 } s;
553 struct cvmx_gmxx_rxx_int_reg_cn30xx {
554 uint64_t minerr:1;
555 uint64_t carext:1;
556 uint64_t maxerr:1;
557 uint64_t jabber:1;
558 uint64_t fcserr:1;
559 uint64_t alnerr:1;
560 uint64_t lenerr:1;
561 uint64_t rcverr:1;
562 uint64_t skperr:1;
563 uint64_t niberr:1;
564 uint64_t ovrerr:1;
565 uint64_t pcterr:1;
566 uint64_t rsverr:1;
567 uint64_t falerr:1;
568 uint64_t coldet:1;
569 uint64_t ifgerr:1;
570 uint64_t phy_link:1;
571 uint64_t phy_spd:1;
572 uint64_t phy_dupx:1;
573 uint64_t reserved_19_63:45;
574 } cn30xx;
575 struct cvmx_gmxx_rxx_int_reg_cn50xx {
576 uint64_t reserved_0_0:1;
577 uint64_t carext:1;
578 uint64_t reserved_2_2:1;
579 uint64_t jabber:1;
580 uint64_t fcserr:1;
581 uint64_t alnerr:1;
582 uint64_t reserved_6_6:1;
583 uint64_t rcverr:1;
584 uint64_t skperr:1;
585 uint64_t niberr:1;
586 uint64_t ovrerr:1;
587 uint64_t pcterr:1;
588 uint64_t rsverr:1;
589 uint64_t falerr:1;
590 uint64_t coldet:1;
591 uint64_t ifgerr:1;
592 uint64_t phy_link:1;
593 uint64_t phy_spd:1;
594 uint64_t phy_dupx:1;
595 uint64_t pause_drp:1;
596 uint64_t reserved_20_63:44;
597 } cn50xx;
598 struct cvmx_gmxx_rxx_int_reg_cn52xx {
599 uint64_t reserved_0_0:1;
600 uint64_t carext:1;
601 uint64_t reserved_2_2:1;
602 uint64_t jabber:1;
603 uint64_t fcserr:1;
604 uint64_t reserved_5_6:2;
605 uint64_t rcverr:1;
606 uint64_t skperr:1;
607 uint64_t reserved_9_9:1;
608 uint64_t ovrerr:1;
609 uint64_t pcterr:1;
610 uint64_t rsverr:1;
611 uint64_t falerr:1;
612 uint64_t coldet:1;
613 uint64_t ifgerr:1;
614 uint64_t reserved_16_18:3;
615 uint64_t pause_drp:1;
616 uint64_t loc_fault:1;
617 uint64_t rem_fault:1;
618 uint64_t bad_seq:1;
619 uint64_t bad_term:1;
620 uint64_t unsop:1;
621 uint64_t uneop:1;
622 uint64_t undat:1;
623 uint64_t hg2fld:1;
624 uint64_t hg2cc:1;
625 uint64_t reserved_29_63:35;
626 } cn52xx;
627 struct cvmx_gmxx_rxx_int_reg_cn56xxp1 {
628 uint64_t reserved_0_0:1;
629 uint64_t carext:1;
630 uint64_t reserved_2_2:1;
631 uint64_t jabber:1;
632 uint64_t fcserr:1;
633 uint64_t reserved_5_6:2;
634 uint64_t rcverr:1;
635 uint64_t skperr:1;
636 uint64_t reserved_9_9:1;
637 uint64_t ovrerr:1;
638 uint64_t pcterr:1;
639 uint64_t rsverr:1;
640 uint64_t falerr:1;
641 uint64_t coldet:1;
642 uint64_t ifgerr:1;
643 uint64_t reserved_16_18:3;
644 uint64_t pause_drp:1;
645 uint64_t loc_fault:1;
646 uint64_t rem_fault:1;
647 uint64_t bad_seq:1;
648 uint64_t bad_term:1;
649 uint64_t unsop:1;
650 uint64_t uneop:1;
651 uint64_t undat:1;
652 uint64_t reserved_27_63:37;
653 } cn56xxp1;
654 struct cvmx_gmxx_rxx_int_reg_cn58xx {
655 uint64_t minerr:1;
656 uint64_t carext:1;
657 uint64_t maxerr:1;
658 uint64_t jabber:1;
659 uint64_t fcserr:1;
660 uint64_t alnerr:1;
661 uint64_t lenerr:1;
662 uint64_t rcverr:1;
663 uint64_t skperr:1;
664 uint64_t niberr:1;
665 uint64_t ovrerr:1;
666 uint64_t pcterr:1;
667 uint64_t rsverr:1;
668 uint64_t falerr:1;
669 uint64_t coldet:1;
670 uint64_t ifgerr:1;
671 uint64_t phy_link:1;
672 uint64_t phy_spd:1;
673 uint64_t phy_dupx:1;
674 uint64_t pause_drp:1;
675 uint64_t reserved_20_63:44;
676 } cn58xx;
677 struct cvmx_gmxx_rxx_int_reg_cn61xx {
678 uint64_t minerr:1;
679 uint64_t carext:1;
680 uint64_t reserved_2_2:1;
681 uint64_t jabber:1;
682 uint64_t fcserr:1;
683 uint64_t reserved_5_6:2;
684 uint64_t rcverr:1;
685 uint64_t skperr:1;
686 uint64_t reserved_9_9:1;
687 uint64_t ovrerr:1;
688 uint64_t pcterr:1;
689 uint64_t rsverr:1;
690 uint64_t falerr:1;
691 uint64_t coldet:1;
692 uint64_t ifgerr:1;
693 uint64_t reserved_16_18:3;
694 uint64_t pause_drp:1;
695 uint64_t loc_fault:1;
696 uint64_t rem_fault:1;
697 uint64_t bad_seq:1;
698 uint64_t bad_term:1;
699 uint64_t unsop:1;
700 uint64_t uneop:1;
701 uint64_t undat:1;
702 uint64_t hg2fld:1;
703 uint64_t hg2cc:1;
704 uint64_t reserved_29_63:35;
705 } cn61xx;
706 };
707
708 union cvmx_gmxx_prtx_cfg {
709 uint64_t u64;
710 struct cvmx_gmxx_prtx_cfg_s {
711 uint64_t reserved_22_63:42;
712 uint64_t pknd:6;
713 uint64_t reserved_14_15:2;
714 uint64_t tx_idle:1;
715 uint64_t rx_idle:1;
716 uint64_t reserved_9_11:3;
717 uint64_t speed_msb:1;
718 uint64_t reserved_4_7:4;
719 uint64_t slottime:1;
720 uint64_t duplex:1;
721 uint64_t speed:1;
722 uint64_t en:1;
723 } s;
724 struct cvmx_gmxx_prtx_cfg_cn30xx {
725 uint64_t reserved_4_63:60;
726 uint64_t slottime:1;
727 uint64_t duplex:1;
728 uint64_t speed:1;
729 uint64_t en:1;
730 } cn30xx;
731 struct cvmx_gmxx_prtx_cfg_cn52xx {
732 uint64_t reserved_14_63:50;
733 uint64_t tx_idle:1;
734 uint64_t rx_idle:1;
735 uint64_t reserved_9_11:3;
736 uint64_t speed_msb:1;
737 uint64_t reserved_4_7:4;
738 uint64_t slottime:1;
739 uint64_t duplex:1;
740 uint64_t speed:1;
741 uint64_t en:1;
742 } cn52xx;
743 };
744
745 union cvmx_gmxx_rxx_adr_ctl {
746 uint64_t u64;
747 struct cvmx_gmxx_rxx_adr_ctl_s {
748 uint64_t reserved_4_63:60;
749 uint64_t cam_mode:1;
750 uint64_t mcst:2;
751 uint64_t bcst:1;
752 } s;
753 };
754
755 union cvmx_pip_prt_tagx {
756 uint64_t u64;
757 struct cvmx_pip_prt_tagx_s {
758 uint64_t reserved_54_63:10;
759 uint64_t portadd_en:1;
760 uint64_t inc_hwchk:1;
761 uint64_t reserved_50_51:2;
762 uint64_t grptagbase_msb:2;
763 uint64_t reserved_46_47:2;
764 uint64_t grptagmask_msb:2;
765 uint64_t reserved_42_43:2;
766 uint64_t grp_msb:2;
767 uint64_t grptagbase:4;
768 uint64_t grptagmask:4;
769 uint64_t grptag:1;
770 uint64_t grptag_mskip:1;
771 uint64_t tag_mode:2;
772 uint64_t inc_vs:2;
773 uint64_t inc_vlan:1;
774 uint64_t inc_prt_flag:1;
775 uint64_t ip6_dprt_flag:1;
776 uint64_t ip4_dprt_flag:1;
777 uint64_t ip6_sprt_flag:1;
778 uint64_t ip4_sprt_flag:1;
779 uint64_t ip6_nxth_flag:1;
780 uint64_t ip4_pctl_flag:1;
781 uint64_t ip6_dst_flag:1;
782 uint64_t ip4_dst_flag:1;
783 uint64_t ip6_src_flag:1;
784 uint64_t ip4_src_flag:1;
785 uint64_t tcp6_tag_type:2;
786 uint64_t tcp4_tag_type:2;
787 uint64_t ip6_tag_type:2;
788 uint64_t ip4_tag_type:2;
789 uint64_t non_tag_type:2;
790 uint64_t grp:4;
791 } s;
792 struct cvmx_pip_prt_tagx_cn30xx {
793 uint64_t reserved_40_63:24;
794 uint64_t grptagbase:4;
795 uint64_t grptagmask:4;
796 uint64_t grptag:1;
797 uint64_t reserved_30_30:1;
798 uint64_t tag_mode:2;
799 uint64_t inc_vs:2;
800 uint64_t inc_vlan:1;
801 uint64_t inc_prt_flag:1;
802 uint64_t ip6_dprt_flag:1;
803 uint64_t ip4_dprt_flag:1;
804 uint64_t ip6_sprt_flag:1;
805 uint64_t ip4_sprt_flag:1;
806 uint64_t ip6_nxth_flag:1;
807 uint64_t ip4_pctl_flag:1;
808 uint64_t ip6_dst_flag:1;
809 uint64_t ip4_dst_flag:1;
810 uint64_t ip6_src_flag:1;
811 uint64_t ip4_src_flag:1;
812 uint64_t tcp6_tag_type:2;
813 uint64_t tcp4_tag_type:2;
814 uint64_t ip6_tag_type:2;
815 uint64_t ip4_tag_type:2;
816 uint64_t non_tag_type:2;
817 uint64_t grp:4;
818 } cn30xx;
819 struct cvmx_pip_prt_tagx_cn50xx {
820 uint64_t reserved_40_63:24;
821 uint64_t grptagbase:4;
822 uint64_t grptagmask:4;
823 uint64_t grptag:1;
824 uint64_t grptag_mskip:1;
825 uint64_t tag_mode:2;
826 uint64_t inc_vs:2;
827 uint64_t inc_vlan:1;
828 uint64_t inc_prt_flag:1;
829 uint64_t ip6_dprt_flag:1;
830 uint64_t ip4_dprt_flag:1;
831 uint64_t ip6_sprt_flag:1;
832 uint64_t ip4_sprt_flag:1;
833 uint64_t ip6_nxth_flag:1;
834 uint64_t ip4_pctl_flag:1;
835 uint64_t ip6_dst_flag:1;
836 uint64_t ip4_dst_flag:1;
837 uint64_t ip6_src_flag:1;
838 uint64_t ip4_src_flag:1;
839 uint64_t tcp6_tag_type:2;
840 uint64_t tcp4_tag_type:2;
841 uint64_t ip6_tag_type:2;
842 uint64_t ip4_tag_type:2;
843 uint64_t non_tag_type:2;
844 uint64_t grp:4;
845 } cn50xx;
846 };
847
848 union cvmx_spxx_int_reg {
849 uint64_t u64;
850 struct cvmx_spxx_int_reg_s {
851 uint64_t reserved_32_63:32;
852 uint64_t spf:1;
853 uint64_t reserved_12_30:19;
854 uint64_t calerr:1;
855 uint64_t syncerr:1;
856 uint64_t diperr:1;
857 uint64_t tpaovr:1;
858 uint64_t rsverr:1;
859 uint64_t drwnng:1;
860 uint64_t clserr:1;
861 uint64_t spiovr:1;
862 uint64_t reserved_2_3:2;
863 uint64_t abnorm:1;
864 uint64_t prtnxa:1;
865 } s;
866 };
867
868 union cvmx_spxx_int_msk {
869 uint64_t u64;
870 struct cvmx_spxx_int_msk_s {
871 uint64_t reserved_12_63:52;
872 uint64_t calerr:1;
873 uint64_t syncerr:1;
874 uint64_t diperr:1;
875 uint64_t tpaovr:1;
876 uint64_t rsverr:1;
877 uint64_t drwnng:1;
878 uint64_t clserr:1;
879 uint64_t spiovr:1;
880 uint64_t reserved_2_3:2;
881 uint64_t abnorm:1;
882 uint64_t prtnxa:1;
883 } s;
884 };
885
886 union cvmx_pow_wq_int {
887 uint64_t u64;
888 struct cvmx_pow_wq_int_s {
889 uint64_t wq_int:16;
890 uint64_t iq_dis:16;
891 uint64_t reserved_32_63:32;
892 } s;
893 };
894
895 union cvmx_sso_wq_int_thrx {
896 uint64_t u64;
897 struct {
898 uint64_t iq_thr:12;
899 uint64_t reserved_12_13:2;
900 uint64_t ds_thr:12;
901 uint64_t reserved_26_27:2;
902 uint64_t tc_thr:4;
903 uint64_t tc_en:1;
904 uint64_t reserved_33_63:31;
905 } s;
906 };
907
908 union cvmx_stxx_int_reg {
909 uint64_t u64;
910 struct cvmx_stxx_int_reg_s {
911 uint64_t reserved_9_63:55;
912 uint64_t syncerr:1;
913 uint64_t frmerr:1;
914 uint64_t unxfrm:1;
915 uint64_t nosync:1;
916 uint64_t diperr:1;
917 uint64_t datovr:1;
918 uint64_t ovrbst:1;
919 uint64_t calpar1:1;
920 uint64_t calpar0:1;
921 } s;
922 };
923
924 union cvmx_stxx_int_msk {
925 uint64_t u64;
926 struct cvmx_stxx_int_msk_s {
927 uint64_t reserved_8_63:56;
928 uint64_t frmerr:1;
929 uint64_t unxfrm:1;
930 uint64_t nosync:1;
931 uint64_t diperr:1;
932 uint64_t datovr:1;
933 uint64_t ovrbst:1;
934 uint64_t calpar1:1;
935 uint64_t calpar0:1;
936 } s;
937 };
938
939 union cvmx_pow_wq_int_pc {
940 uint64_t u64;
941 struct cvmx_pow_wq_int_pc_s {
942 uint64_t reserved_0_7:8;
943 uint64_t pc_thr:20;
944 uint64_t reserved_28_31:4;
945 uint64_t pc:28;
946 uint64_t reserved_60_63:4;
947 } s;
948 };
949
950 union cvmx_pow_wq_int_thrx {
951 uint64_t u64;
952 struct cvmx_pow_wq_int_thrx_s {
953 uint64_t reserved_29_63:35;
954 uint64_t tc_en:1;
955 uint64_t tc_thr:4;
956 uint64_t reserved_23_23:1;
957 uint64_t ds_thr:11;
958 uint64_t reserved_11_11:1;
959 uint64_t iq_thr:11;
960 } s;
961 struct cvmx_pow_wq_int_thrx_cn30xx {
962 uint64_t reserved_29_63:35;
963 uint64_t tc_en:1;
964 uint64_t tc_thr:4;
965 uint64_t reserved_18_23:6;
966 uint64_t ds_thr:6;
967 uint64_t reserved_6_11:6;
968 uint64_t iq_thr:6;
969 } cn30xx;
970 struct cvmx_pow_wq_int_thrx_cn31xx {
971 uint64_t reserved_29_63:35;
972 uint64_t tc_en:1;
973 uint64_t tc_thr:4;
974 uint64_t reserved_20_23:4;
975 uint64_t ds_thr:8;
976 uint64_t reserved_8_11:4;
977 uint64_t iq_thr:8;
978 } cn31xx;
979 struct cvmx_pow_wq_int_thrx_cn52xx {
980 uint64_t reserved_29_63:35;
981 uint64_t tc_en:1;
982 uint64_t tc_thr:4;
983 uint64_t reserved_21_23:3;
984 uint64_t ds_thr:9;
985 uint64_t reserved_9_11:3;
986 uint64_t iq_thr:9;
987 } cn52xx;
988 struct cvmx_pow_wq_int_thrx_cn63xx {
989 uint64_t reserved_29_63:35;
990 uint64_t tc_en:1;
991 uint64_t tc_thr:4;
992 uint64_t reserved_22_23:2;
993 uint64_t ds_thr:10;
994 uint64_t reserved_10_11:2;
995 uint64_t iq_thr:10;
996 } cn63xx;
997 };
998
999 union cvmx_npi_rsl_int_blocks {
1000 uint64_t u64;
1001 struct cvmx_npi_rsl_int_blocks_s {
1002 uint64_t reserved_32_63:32;
1003 uint64_t rint_31:1;
1004 uint64_t iob:1;
1005 uint64_t reserved_28_29:2;
1006 uint64_t rint_27:1;
1007 uint64_t rint_26:1;
1008 uint64_t rint_25:1;
1009 uint64_t rint_24:1;
1010 uint64_t asx1:1;
1011 uint64_t asx0:1;
1012 uint64_t rint_21:1;
1013 uint64_t pip:1;
1014 uint64_t spx1:1;
1015 uint64_t spx0:1;
1016 uint64_t lmc:1;
1017 uint64_t l2c:1;
1018 uint64_t rint_15:1;
1019 uint64_t reserved_13_14:2;
1020 uint64_t pow:1;
1021 uint64_t tim:1;
1022 uint64_t pko:1;
1023 uint64_t ipd:1;
1024 uint64_t rint_8:1;
1025 uint64_t zip:1;
1026 uint64_t dfa:1;
1027 uint64_t fpa:1;
1028 uint64_t key:1;
1029 uint64_t npi:1;
1030 uint64_t gmx1:1;
1031 uint64_t gmx0:1;
1032 uint64_t mio:1;
1033 } s;
1034 struct cvmx_npi_rsl_int_blocks_cn30xx {
1035 uint64_t reserved_32_63:32;
1036 uint64_t rint_31:1;
1037 uint64_t iob:1;
1038 uint64_t rint_29:1;
1039 uint64_t rint_28:1;
1040 uint64_t rint_27:1;
1041 uint64_t rint_26:1;
1042 uint64_t rint_25:1;
1043 uint64_t rint_24:1;
1044 uint64_t asx1:1;
1045 uint64_t asx0:1;
1046 uint64_t rint_21:1;
1047 uint64_t pip:1;
1048 uint64_t spx1:1;
1049 uint64_t spx0:1;
1050 uint64_t lmc:1;
1051 uint64_t l2c:1;
1052 uint64_t rint_15:1;
1053 uint64_t rint_14:1;
1054 uint64_t usb:1;
1055 uint64_t pow:1;
1056 uint64_t tim:1;
1057 uint64_t pko:1;
1058 uint64_t ipd:1;
1059 uint64_t rint_8:1;
1060 uint64_t zip:1;
1061 uint64_t dfa:1;
1062 uint64_t fpa:1;
1063 uint64_t key:1;
1064 uint64_t npi:1;
1065 uint64_t gmx1:1;
1066 uint64_t gmx0:1;
1067 uint64_t mio:1;
1068 } cn30xx;
1069 struct cvmx_npi_rsl_int_blocks_cn38xx {
1070 uint64_t reserved_32_63:32;
1071 uint64_t rint_31:1;
1072 uint64_t iob:1;
1073 uint64_t rint_29:1;
1074 uint64_t rint_28:1;
1075 uint64_t rint_27:1;
1076 uint64_t rint_26:1;
1077 uint64_t rint_25:1;
1078 uint64_t rint_24:1;
1079 uint64_t asx1:1;
1080 uint64_t asx0:1;
1081 uint64_t rint_21:1;
1082 uint64_t pip:1;
1083 uint64_t spx1:1;
1084 uint64_t spx0:1;
1085 uint64_t lmc:1;
1086 uint64_t l2c:1;
1087 uint64_t rint_15:1;
1088 uint64_t rint_14:1;
1089 uint64_t rint_13:1;
1090 uint64_t pow:1;
1091 uint64_t tim:1;
1092 uint64_t pko:1;
1093 uint64_t ipd:1;
1094 uint64_t rint_8:1;
1095 uint64_t zip:1;
1096 uint64_t dfa:1;
1097 uint64_t fpa:1;
1098 uint64_t key:1;
1099 uint64_t npi:1;
1100 uint64_t gmx1:1;
1101 uint64_t gmx0:1;
1102 uint64_t mio:1;
1103 } cn38xx;
1104 struct cvmx_npi_rsl_int_blocks_cn50xx {
1105 uint64_t reserved_31_63:33;
1106 uint64_t iob:1;
1107 uint64_t lmc1:1;
1108 uint64_t agl:1;
1109 uint64_t reserved_24_27:4;
1110 uint64_t asx1:1;
1111 uint64_t asx0:1;
1112 uint64_t reserved_21_21:1;
1113 uint64_t pip:1;
1114 uint64_t spx1:1;
1115 uint64_t spx0:1;
1116 uint64_t lmc:1;
1117 uint64_t l2c:1;
1118 uint64_t reserved_15_15:1;
1119 uint64_t rad:1;
1120 uint64_t usb:1;
1121 uint64_t pow:1;
1122 uint64_t tim:1;
1123 uint64_t pko:1;
1124 uint64_t ipd:1;
1125 uint64_t reserved_8_8:1;
1126 uint64_t zip:1;
1127 uint64_t dfa:1;
1128 uint64_t fpa:1;
1129 uint64_t key:1;
1130 uint64_t npi:1;
1131 uint64_t gmx1:1;
1132 uint64_t gmx0:1;
1133 uint64_t mio:1;
1134 } cn50xx;
1135 };
1136
1137 typedef union {
1138 uint64_t u64;
1139 struct {
1140 uint64_t total_bytes:16;
1141 uint64_t segs:6;
1142 uint64_t dontfree:1;
1143 uint64_t ignore_i:1;
1144 uint64_t ipoffp1:7;
1145 uint64_t gather:1;
1146 uint64_t rsp:1;
1147 uint64_t wqp:1;
1148 uint64_t n2:1;
1149 uint64_t le:1;
1150 uint64_t reg0:11;
1151 uint64_t subone0:1;
1152 uint64_t reg1:11;
1153 uint64_t subone1:1;
1154 uint64_t size0:2;
1155 uint64_t size1:2;
1156 } s;
1157 } cvmx_pko_command_word0_t;
1158
1159 union cvmx_ciu_timx {
1160 uint64_t u64;
1161 struct cvmx_ciu_timx_s {
1162 uint64_t reserved_37_63:27;
1163 uint64_t one_shot:1;
1164 uint64_t len:36;
1165 } s;
1166 };
1167
1168 union cvmx_gmxx_rxx_rx_inbnd {
1169 uint64_t u64;
1170 struct cvmx_gmxx_rxx_rx_inbnd_s {
1171 uint64_t status:1;
1172 uint64_t speed:2;
1173 uint64_t duplex:1;
1174 uint64_t reserved_4_63:60;
1175 } s;
1176 };
1177
cvmx_fau_fetch_and_add32(cvmx_fau_reg_32_t reg,int32_t value)1178 static inline int32_t cvmx_fau_fetch_and_add32(cvmx_fau_reg_32_t reg,
1179 int32_t value)
1180 {
1181 return value;
1182 }
1183
cvmx_fau_atomic_add32(cvmx_fau_reg_32_t reg,int32_t value)1184 static inline void cvmx_fau_atomic_add32(cvmx_fau_reg_32_t reg, int32_t value)
1185 { }
1186
cvmx_fau_atomic_write32(cvmx_fau_reg_32_t reg,int32_t value)1187 static inline void cvmx_fau_atomic_write32(cvmx_fau_reg_32_t reg, int32_t value)
1188 { }
1189
cvmx_scratch_read64(uint64_t address)1190 static inline uint64_t cvmx_scratch_read64(uint64_t address)
1191 {
1192 return 0;
1193 }
1194
cvmx_scratch_write64(uint64_t address,uint64_t value)1195 static inline void cvmx_scratch_write64(uint64_t address, uint64_t value)
1196 { }
1197
cvmx_wqe_get_grp(cvmx_wqe_t * work)1198 static inline int cvmx_wqe_get_grp(cvmx_wqe_t *work)
1199 {
1200 return 0;
1201 }
1202
cvmx_phys_to_ptr(uint64_t physical_address)1203 static inline void *cvmx_phys_to_ptr(uint64_t physical_address)
1204 {
1205 return (void *)(uintptr_t)(physical_address);
1206 }
1207
cvmx_ptr_to_phys(void * ptr)1208 static inline uint64_t cvmx_ptr_to_phys(void *ptr)
1209 {
1210 return (unsigned long)ptr;
1211 }
1212
cvmx_helper_get_interface_num(int ipd_port)1213 static inline int cvmx_helper_get_interface_num(int ipd_port)
1214 {
1215 return ipd_port;
1216 }
1217
cvmx_helper_get_interface_index_num(int ipd_port)1218 static inline int cvmx_helper_get_interface_index_num(int ipd_port)
1219 {
1220 return ipd_port;
1221 }
1222
cvmx_fpa_enable(void)1223 static inline void cvmx_fpa_enable(void)
1224 { }
1225
cvmx_read_csr(uint64_t csr_addr)1226 static inline uint64_t cvmx_read_csr(uint64_t csr_addr)
1227 {
1228 return 0;
1229 }
1230
cvmx_write_csr(uint64_t csr_addr,uint64_t val)1231 static inline void cvmx_write_csr(uint64_t csr_addr, uint64_t val)
1232 { }
1233
cvmx_helper_setup_red(int pass_thresh,int drop_thresh)1234 static inline int cvmx_helper_setup_red(int pass_thresh, int drop_thresh)
1235 {
1236 return 0;
1237 }
1238
cvmx_fpa_alloc(uint64_t pool)1239 static inline void *cvmx_fpa_alloc(uint64_t pool)
1240 {
1241 return NULL;
1242 }
1243
cvmx_fpa_free(void * ptr,uint64_t pool,uint64_t num_cache_lines)1244 static inline void cvmx_fpa_free(void *ptr, uint64_t pool,
1245 uint64_t num_cache_lines)
1246 { }
1247
octeon_is_simulation(void)1248 static inline int octeon_is_simulation(void)
1249 {
1250 return 1;
1251 }
1252
cvmx_pip_get_port_status(uint64_t port_num,uint64_t clear,cvmx_pip_port_status_t * status)1253 static inline void cvmx_pip_get_port_status(uint64_t port_num, uint64_t clear,
1254 cvmx_pip_port_status_t *status)
1255 { }
1256
cvmx_pko_get_port_status(uint64_t port_num,uint64_t clear,cvmx_pko_port_status_t * status)1257 static inline void cvmx_pko_get_port_status(uint64_t port_num, uint64_t clear,
1258 cvmx_pko_port_status_t *status)
1259 { }
1260
cvmx_helper_interface_get_mode(int interface)1261 static inline cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int
1262 interface)
1263 {
1264 return 0;
1265 }
1266
cvmx_helper_link_get(int ipd_port)1267 static inline cvmx_helper_link_info_t cvmx_helper_link_get(int ipd_port)
1268 {
1269 cvmx_helper_link_info_t ret = { .u64 = 0 };
1270
1271 return ret;
1272 }
1273
cvmx_helper_link_set(int ipd_port,cvmx_helper_link_info_t link_info)1274 static inline int cvmx_helper_link_set(int ipd_port,
1275 cvmx_helper_link_info_t link_info)
1276 {
1277 return 0;
1278 }
1279
cvmx_helper_initialize_packet_io_global(void)1280 static inline int cvmx_helper_initialize_packet_io_global(void)
1281 {
1282 return 0;
1283 }
1284
cvmx_helper_get_number_of_interfaces(void)1285 static inline int cvmx_helper_get_number_of_interfaces(void)
1286 {
1287 return 2;
1288 }
1289
cvmx_helper_ports_on_interface(int interface)1290 static inline int cvmx_helper_ports_on_interface(int interface)
1291 {
1292 return 1;
1293 }
1294
cvmx_helper_get_ipd_port(int interface,int port)1295 static inline int cvmx_helper_get_ipd_port(int interface, int port)
1296 {
1297 return 0;
1298 }
1299
cvmx_helper_ipd_and_packet_input_enable(void)1300 static inline int cvmx_helper_ipd_and_packet_input_enable(void)
1301 {
1302 return 0;
1303 }
1304
cvmx_ipd_disable(void)1305 static inline void cvmx_ipd_disable(void)
1306 { }
1307
cvmx_ipd_free_ptr(void)1308 static inline void cvmx_ipd_free_ptr(void)
1309 { }
1310
cvmx_pko_disable(void)1311 static inline void cvmx_pko_disable(void)
1312 { }
1313
cvmx_pko_shutdown(void)1314 static inline void cvmx_pko_shutdown(void)
1315 { }
1316
cvmx_pko_get_base_queue_per_core(int port,int core)1317 static inline int cvmx_pko_get_base_queue_per_core(int port, int core)
1318 {
1319 return port;
1320 }
1321
cvmx_pko_get_base_queue(int port)1322 static inline int cvmx_pko_get_base_queue(int port)
1323 {
1324 return port;
1325 }
1326
cvmx_pko_get_num_queues(int port)1327 static inline int cvmx_pko_get_num_queues(int port)
1328 {
1329 return port;
1330 }
1331
cvmx_get_core_num(void)1332 static inline unsigned int cvmx_get_core_num(void)
1333 {
1334 return 0;
1335 }
1336
cvmx_pow_work_request_async_nocheck(int scr_addr,cvmx_pow_wait_t wait)1337 static inline void cvmx_pow_work_request_async_nocheck(int scr_addr,
1338 cvmx_pow_wait_t wait)
1339 { }
1340
cvmx_pow_work_request_async(int scr_addr,cvmx_pow_wait_t wait)1341 static inline void cvmx_pow_work_request_async(int scr_addr,
1342 cvmx_pow_wait_t wait)
1343 { }
1344
cvmx_pow_work_response_async(int scr_addr)1345 static inline cvmx_wqe_t *cvmx_pow_work_response_async(int scr_addr)
1346 {
1347 cvmx_wqe_t *wqe = (void *)(unsigned long)scr_addr;
1348
1349 return wqe;
1350 }
1351
cvmx_pow_work_request_sync(cvmx_pow_wait_t wait)1352 static inline cvmx_wqe_t *cvmx_pow_work_request_sync(cvmx_pow_wait_t wait)
1353 {
1354 return (void *)(unsigned long)wait;
1355 }
1356
cvmx_spi_restart_interface(int interface,cvmx_spi_mode_t mode,int timeout)1357 static inline int cvmx_spi_restart_interface(int interface,
1358 cvmx_spi_mode_t mode, int timeout)
1359 {
1360 return 0;
1361 }
1362
cvmx_fau_async_fetch_and_add32(uint64_t scraddr,cvmx_fau_reg_32_t reg,int32_t value)1363 static inline void cvmx_fau_async_fetch_and_add32(uint64_t scraddr,
1364 cvmx_fau_reg_32_t reg,
1365 int32_t value)
1366 { }
1367
cvmx_spi4000_check_speed(int interface,int port)1368 static inline union cvmx_gmxx_rxx_rx_inbnd cvmx_spi4000_check_speed(
1369 int interface,
1370 int port)
1371 {
1372 union cvmx_gmxx_rxx_rx_inbnd r;
1373 r.u64 = 0;
1374 return r;
1375 }
1376
cvmx_pko_send_packet_prepare(uint64_t port,uint64_t queue,cvmx_pko_lock_t use_locking)1377 static inline void cvmx_pko_send_packet_prepare(uint64_t port, uint64_t queue,
1378 cvmx_pko_lock_t use_locking)
1379 { }
1380
cvmx_pko_send_packet_finish(uint64_t port,uint64_t queue,cvmx_pko_command_word0_t pko_command,union cvmx_buf_ptr packet,cvmx_pko_lock_t use_locking)1381 static inline cvmx_pko_status_t cvmx_pko_send_packet_finish(uint64_t port,
1382 uint64_t queue, cvmx_pko_command_word0_t pko_command,
1383 union cvmx_buf_ptr packet, cvmx_pko_lock_t use_locking)
1384 {
1385 cvmx_pko_status_t ret = 0;
1386
1387 return ret;
1388 }
1389
cvmx_wqe_set_port(cvmx_wqe_t * work,int port)1390 static inline void cvmx_wqe_set_port(cvmx_wqe_t *work, int port)
1391 { }
1392
cvmx_wqe_set_qos(cvmx_wqe_t * work,int qos)1393 static inline void cvmx_wqe_set_qos(cvmx_wqe_t *work, int qos)
1394 { }
1395
cvmx_wqe_get_qos(cvmx_wqe_t * work)1396 static inline int cvmx_wqe_get_qos(cvmx_wqe_t *work)
1397 {
1398 return 0;
1399 }
1400
cvmx_wqe_set_grp(cvmx_wqe_t * work,int grp)1401 static inline void cvmx_wqe_set_grp(cvmx_wqe_t *work, int grp)
1402 { }
1403
cvmx_pow_work_submit(cvmx_wqe_t * wqp,uint32_t tag,enum cvmx_pow_tag_type tag_type,uint64_t qos,uint64_t grp)1404 static inline void cvmx_pow_work_submit(cvmx_wqe_t *wqp, uint32_t tag,
1405 enum cvmx_pow_tag_type tag_type,
1406 uint64_t qos, uint64_t grp)
1407 { }
1408
1409 #define CVMX_ASXX_RX_CLK_SETX(a, b) ((a)+(b))
1410 #define CVMX_ASXX_TX_CLK_SETX(a, b) ((a)+(b))
1411 #define CVMX_CIU_TIMX(a) (a)
1412 #define CVMX_GMXX_RXX_ADR_CAM0(a, b) ((a)+(b))
1413 #define CVMX_GMXX_RXX_ADR_CAM1(a, b) ((a)+(b))
1414 #define CVMX_GMXX_RXX_ADR_CAM2(a, b) ((a)+(b))
1415 #define CVMX_GMXX_RXX_ADR_CAM3(a, b) ((a)+(b))
1416 #define CVMX_GMXX_RXX_ADR_CAM4(a, b) ((a)+(b))
1417 #define CVMX_GMXX_RXX_ADR_CAM5(a, b) ((a)+(b))
1418 #define CVMX_GMXX_RXX_FRM_CTL(a, b) ((a)+(b))
1419 #define CVMX_GMXX_RXX_INT_REG(a, b) ((a)+(b))
1420 #define CVMX_GMXX_SMACX(a, b) ((a)+(b))
1421 #define CVMX_PIP_PRT_TAGX(a) (a)
1422 #define CVMX_POW_PP_GRP_MSKX(a) (a)
1423 #define CVMX_POW_WQ_INT_THRX(a) (a)
1424 #define CVMX_SPXX_INT_MSK(a) (a)
1425 #define CVMX_SPXX_INT_REG(a) (a)
1426 #define CVMX_SSO_PPX_GRP_MSK(a) (a)
1427 #define CVMX_SSO_WQ_INT_THRX(a) (a)
1428 #define CVMX_STXX_INT_MSK(a) (a)
1429 #define CVMX_STXX_INT_REG(a) (a)
1430
