1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright © 2017-2020 MediaTek Inc. 4 * Author: Sean Wang <sean.wang@mediatek.com> 5 * Ryder Lee <ryder.lee@mediatek.com> 6 * 7 */ 8 9#include "mt7623.dtsi" 10#include <dt-bindings/memory/mt2701-larb-port.h> 11 12/ { 13 aliases { 14 rdma0 = &rdma0; 15 rdma1 = &rdma1; 16 }; 17 18 g3dsys: syscon@13000000 { 19 compatible = "mediatek,mt7623-g3dsys", 20 "mediatek,mt2701-g3dsys", 21 "syscon"; 22 reg = <0 0x13000000 0 0x200>; 23 #clock-cells = <1>; 24 #reset-cells = <1>; 25 }; 26 27 mali: gpu@13040000 { 28 compatible = "mediatek,mt7623-mali", "arm,mali-450"; 29 reg = <0 0x13040000 0 0x30000>; 30 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_LOW>, 31 <GIC_SPI 171 IRQ_TYPE_LEVEL_LOW>, 32 <GIC_SPI 172 IRQ_TYPE_LEVEL_LOW>, 33 <GIC_SPI 173 IRQ_TYPE_LEVEL_LOW>, 34 <GIC_SPI 174 IRQ_TYPE_LEVEL_LOW>, 35 <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>, 36 <GIC_SPI 176 IRQ_TYPE_LEVEL_LOW>, 37 <GIC_SPI 177 IRQ_TYPE_LEVEL_LOW>, 38 <GIC_SPI 178 IRQ_TYPE_LEVEL_LOW>, 39 <GIC_SPI 179 IRQ_TYPE_LEVEL_LOW>, 40 <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>; 41 interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", 42 "ppmmu1", "pp2", "ppmmu2", "pp3", "ppmmu3", 43 "pp"; 44 clocks = <&topckgen CLK_TOP_MMPLL>, 45 <&g3dsys CLK_G3DSYS_CORE>; 46 clock-names = "bus", "core"; 47 power-domains = <&scpsys MT2701_POWER_DOMAIN_MFG>; 48 resets = <&g3dsys MT2701_G3DSYS_CORE_RST>; 49 }; 50 51 mmsys: syscon@14000000 { 52 compatible = "mediatek,mt7623-mmsys", 53 "mediatek,mt2701-mmsys", 54 "syscon"; 55 reg = <0 0x14000000 0 0x1000>; 56 #clock-cells = <1>; 57 }; 58 59 larb0: larb@14010000 { 60 compatible = "mediatek,mt7623-smi-larb", 61 "mediatek,mt2701-smi-larb"; 62 reg = <0 0x14010000 0 0x1000>; 63 mediatek,smi = <&smi_common>; 64 mediatek,larb-id = <0>; 65 clocks = <&mmsys CLK_MM_SMI_LARB0>, 66 <&mmsys CLK_MM_SMI_LARB0>; 67 clock-names = "apb", "smi"; 68 power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; 69 }; 70 71 larb1: larb@16010000 { 72 compatible = "mediatek,mt7623-smi-larb", 73 "mediatek,mt2701-smi-larb"; 74 reg = <0 0x16010000 0 0x1000>; 75 mediatek,smi = <&smi_common>; 76 mediatek,larb-id = <1>; 77 clocks = <&vdecsys CLK_VDEC_CKGEN>, 78 <&vdecsys CLK_VDEC_LARB>; 79 clock-names = "apb", "smi"; 80 power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>; 81 }; 82 83 larb2: larb@15001000 { 84 compatible = "mediatek,mt7623-smi-larb", 85 "mediatek,mt2701-smi-larb"; 86 reg = <0 0x15001000 0 0x1000>; 87 mediatek,smi = <&smi_common>; 88 mediatek,larb-id = <2>; 89 clocks = <&imgsys CLK_IMG_SMI_COMM>, 90 <&imgsys CLK_IMG_SMI_COMM>; 91 clock-names = "apb", "smi"; 92 power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; 93 }; 94 95 imgsys: syscon@15000000 { 96 compatible = "mediatek,mt7623-imgsys", 97 "mediatek,mt2701-imgsys", 98 "syscon"; 99 reg = <0 0x15000000 0 0x1000>; 100 #clock-cells = <1>; 101 }; 102 103 iommu: mmsys_iommu@10205000 { 104 compatible = "mediatek,mt7623-m4u", 105 "mediatek,mt2701-m4u"; 106 reg = <0 0x10205000 0 0x1000>; 107 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>; 108 clocks = <&infracfg CLK_INFRA_M4U>; 109 clock-names = "bclk"; 110 mediatek,larbs = <&larb0 &larb1 &larb2>; 111 #iommu-cells = <1>; 112 }; 113 114 jpegdec: jpegdec@15004000 { 115 compatible = "mediatek,mt7623-jpgdec", 116 "mediatek,mt2701-jpgdec"; 117 reg = <0 0x15004000 0 0x1000>; 118 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>; 119 clocks = <&imgsys CLK_IMG_JPGDEC_SMI>, 120 <&imgsys CLK_IMG_JPGDEC>; 121 clock-names = "jpgdec-smi", 122 "jpgdec"; 123 power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; 124 mediatek,larb = <&larb2>; 125 iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>, 126 <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>; 127 }; 128 129 smi_common: smi@1000c000 { 130 compatible = "mediatek,mt7623-smi-common", 131 "mediatek,mt2701-smi-common"; 132 reg = <0 0x1000c000 0 0x1000>; 133 clocks = <&infracfg CLK_INFRA_SMI>, 134 <&mmsys CLK_MM_SMI_COMMON>, 135 <&infracfg CLK_INFRA_SMI>; 136 clock-names = "apb", "smi", "async"; 137 power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; 138 }; 139 140 ovl: ovl@14007000 { 141 compatible = "mediatek,mt7623-disp-ovl", 142 "mediatek,mt2701-disp-ovl"; 143 reg = <0 0x14007000 0 0x1000>; 144 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW>; 145 clocks = <&mmsys CLK_MM_DISP_OVL>; 146 iommus = <&iommu MT2701_M4U_PORT_DISP_OVL_0>; 147 mediatek,larb = <&larb0>; 148 }; 149 150 rdma0: rdma@14008000 { 151 compatible = "mediatek,mt7623-disp-rdma", 152 "mediatek,mt2701-disp-rdma"; 153 reg = <0 0x14008000 0 0x1000>; 154 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>; 155 clocks = <&mmsys CLK_MM_DISP_RDMA>; 156 iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA>; 157 mediatek,larb = <&larb0>; 158 }; 159 160 wdma@14009000 { 161 compatible = "mediatek,mt7623-disp-wdma", 162 "mediatek,mt2701-disp-wdma"; 163 reg = <0 0x14009000 0 0x1000>; 164 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_LOW>; 165 clocks = <&mmsys CLK_MM_DISP_WDMA>; 166 iommus = <&iommu MT2701_M4U_PORT_DISP_WDMA>; 167 mediatek,larb = <&larb0>; 168 }; 169 170 bls: pwm@1400a000 { 171 compatible = "mediatek,mt7623-disp-pwm", 172 "mediatek,mt2701-disp-pwm"; 173 reg = <0 0x1400a000 0 0x1000>; 174 #pwm-cells = <2>; 175 clocks = <&mmsys CLK_MM_MDP_BLS_26M>, 176 <&mmsys CLK_MM_DISP_BLS>; 177 clock-names = "main", "mm"; 178 status = "disabled"; 179 }; 180 181 color: color@1400b000 { 182 compatible = "mediatek,mt7623-disp-color", 183 "mediatek,mt2701-disp-color"; 184 reg = <0 0x1400b000 0 0x1000>; 185 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_LOW>; 186 clocks = <&mmsys CLK_MM_DISP_COLOR>; 187 }; 188 189 dsi: dsi@1400c000 { 190 compatible = "mediatek,mt7623-dsi", 191 "mediatek,mt2701-dsi"; 192 reg = <0 0x1400c000 0 0x1000>; 193 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_LOW>; 194 clocks = <&mmsys CLK_MM_DSI_ENGINE>, 195 <&mmsys CLK_MM_DSI_DIG>, 196 <&mipi_tx0>; 197 clock-names = "engine", "digital", "hs"; 198 phys = <&mipi_tx0>; 199 phy-names = "dphy"; 200 status = "disabled"; 201 }; 202 203 mutex: mutex@1400e000 { 204 compatible = "mediatek,mt7623-disp-mutex", 205 "mediatek,mt2701-disp-mutex"; 206 reg = <0 0x1400e000 0 0x1000>; 207 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>; 208 clocks = <&mmsys CLK_MM_MUTEX_32K>; 209 }; 210 211 rdma1: rdma@14012000 { 212 compatible = "mediatek,mt7623-disp-rdma", 213 "mediatek,mt2701-disp-rdma"; 214 reg = <0 0x14012000 0 0x1000>; 215 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>; 216 clocks = <&mmsys CLK_MM_DISP_RDMA1>; 217 iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA1>; 218 mediatek,larb = <&larb0>; 219 }; 220 221 dpi0: dpi@14014000 { 222 compatible = "mediatek,mt7623-dpi", 223 "mediatek,mt2701-dpi"; 224 reg = <0 0x14014000 0 0x1000>; 225 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; 226 clocks = <&mmsys CLK_MM_DPI1_DIGL>, 227 <&mmsys CLK_MM_DPI1_ENGINE>, 228 <&apmixedsys CLK_APMIXED_TVDPLL>; 229 clock-names = "pixel", "engine", "pll"; 230 status = "disabled"; 231 }; 232 233 hdmi0: hdmi@14015000 { 234 compatible = "mediatek,mt7623-hdmi", 235 "mediatek,mt2701-hdmi"; 236 reg = <0 0x14015000 0 0x400>; 237 clocks = <&mmsys CLK_MM_HDMI_PIXEL>, 238 <&mmsys CLK_MM_HDMI_PLL>, 239 <&mmsys CLK_MM_HDMI_AUDIO>, 240 <&mmsys CLK_MM_HDMI_SPDIF>; 241 clock-names = "pixel", "pll", "bclk", "spdif"; 242 phys = <&hdmi_phy>; 243 phy-names = "hdmi"; 244 mediatek,syscon-hdmi = <&mmsys 0x900>; 245 cec = <&cec>; 246 status = "disabled"; 247 }; 248 249 mipi_tx0: mipi-dphy@10010000 { 250 compatible = "mediatek,mt7623-mipi-tx", 251 "mediatek,mt2701-mipi-tx"; 252 reg = <0 0x10010000 0 0x90>; 253 clocks = <&clk26m>; 254 clock-output-names = "mipi_tx0_pll"; 255 #clock-cells = <0>; 256 #phy-cells = <0>; 257 }; 258 259 cec: cec@10012000 { 260 compatible = "mediatek,mt7623-cec", 261 "mediatek,mt8173-cec"; 262 reg = <0 0x10012000 0 0xbc>; 263 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>; 264 clocks = <&infracfg CLK_INFRA_CEC>; 265 status = "disabled"; 266 }; 267 268 hdmi_phy: phy@10209100 { 269 compatible = "mediatek,mt7623-hdmi-phy", 270 "mediatek,mt2701-hdmi-phy"; 271 reg = <0 0x10209100 0 0x24>; 272 clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>; 273 clock-names = "pll_ref"; 274 clock-output-names = "hdmitx_dig_cts"; 275 #clock-cells = <0>; 276 #phy-cells = <0>; 277 status = "disabled"; 278 }; 279 280 hdmiddc0: i2c@11013000 { 281 compatible = "mediatek,mt7623-hdmi-ddc", 282 "mediatek,mt8173-hdmi-ddc"; 283 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 284 reg = <0 0x11013000 0 0x1C>; 285 clocks = <&pericfg CLK_PERI_I2C3>; 286 clock-names = "ddc-i2c"; 287 status = "disabled"; 288 }; 289}; 290 291&pio { 292 hdmi_pins_a: hdmi-default { 293 pins-hdmi { 294 pinmux = <MT7623_PIN_123_HTPLG_FUNC_HTPLG>; 295 input-enable; 296 bias-pull-down; 297 }; 298 }; 299 300 hdmi_ddc_pins_a: hdmi_ddc-default { 301 pins-hdmi-ddc { 302 pinmux = <MT7623_PIN_124_GPIO124_FUNC_HDMISCK>, 303 <MT7623_PIN_125_GPIO125_FUNC_HDMISD>; 304 }; 305 }; 306}; 307
