1 /* Copyright Statement:
2 *
3 * This software/firmware and related documentation ("MediaTek Software") are
4 * protected under relevant copyright laws. The information contained herein
5 * is confidential and proprietary to MediaTek Inc. and/or its licensors.
6 * Without the prior written permission of MediaTek inc. and/or its licensors,
7 * any reproduction, modification, use or disclosure of MediaTek Software,
8 * and information contained herein, in whole or in part, shall be strictly prohibited.
9 */
10 /* MediaTek Inc. (C) 2010. All rights reserved.
11 *
12 * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
13 * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
14 * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
15 * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
18 * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
19 * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
20 * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
21 * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
22 * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
23 * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
24 * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
25 * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
26 * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
27 * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
28 * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
29 * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
30 *
31 * The following software/firmware and/or related documentation ("MediaTek Software")
32 * have been modified by MediaTek Inc. All revisions are subject to any receiver's
33 * applicable license agreements with MediaTek Inc.
34 */
35
36 #ifndef MT6575_SD_H
37 #define MT6575_SD_H
38
39 #include <linux/bitops.h>
40 #include <linux/mmc/host.h>
41
42 // #include <mach/mt6575_reg_base.h> /* --- by chhung */
43
44 /*--------------------------------------------------------------------------*/
45 /* Common Definition */
46 /*--------------------------------------------------------------------------*/
47 #define MSDC_FIFO_SZ (128)
48 #define MSDC_FIFO_THD (64) // (128)
49 #define MSDC_NUM (4)
50
51 #define MSDC_MS (0)
52 #define MSDC_SDMMC (1)
53
54 #define MSDC_BUS_1BITS (0)
55 #define MSDC_BUS_4BITS (1)
56 #define MSDC_BUS_8BITS (2)
57
58 #define MSDC_BRUST_8B (3)
59 #define MSDC_BRUST_16B (4)
60 #define MSDC_BRUST_32B (5)
61 #define MSDC_BRUST_64B (6)
62
63 #define MSDC_PIN_PULL_NONE (0)
64 #define MSDC_PIN_PULL_DOWN (1)
65 #define MSDC_PIN_PULL_UP (2)
66 #define MSDC_PIN_KEEP (3)
67
68 #define MSDC_MAX_SCLK (48000000) /* +/- by chhung */
69 #define MSDC_MIN_SCLK (260000)
70
71 #define MSDC_AUTOCMD12 (0x0001)
72 #define MSDC_AUTOCMD23 (0x0002)
73 #define MSDC_AUTOCMD19 (0x0003)
74
75 #define MSDC_EMMC_BOOTMODE0 (0) /* Pull low CMD mode */
76 #define MSDC_EMMC_BOOTMODE1 (1) /* Reset CMD mode */
77
78 enum {
79 RESP_NONE = 0,
80 RESP_R1,
81 RESP_R2,
82 RESP_R3,
83 RESP_R4,
84 RESP_R5,
85 RESP_R6,
86 RESP_R7,
87 RESP_R1B
88 };
89
90 /*--------------------------------------------------------------------------*/
91 /* Register Offset */
92 /*--------------------------------------------------------------------------*/
93 #define MSDC_CFG (0x0)
94 #define MSDC_IOCON (0x04)
95 #define MSDC_PS (0x08)
96 #define MSDC_INT (0x0c)
97 #define MSDC_INTEN (0x10)
98 #define MSDC_FIFOCS (0x14)
99 #define MSDC_TXDATA (0x18)
100 #define MSDC_RXDATA (0x1c)
101 #define SDC_CFG (0x30)
102 #define SDC_CMD (0x34)
103 #define SDC_ARG (0x38)
104 #define SDC_STS (0x3c)
105 #define SDC_RESP0 (0x40)
106 #define SDC_RESP1 (0x44)
107 #define SDC_RESP2 (0x48)
108 #define SDC_RESP3 (0x4c)
109 #define SDC_BLK_NUM (0x50)
110 #define SDC_CSTS (0x58)
111 #define SDC_CSTS_EN (0x5c)
112 #define SDC_DCRC_STS (0x60)
113 #define EMMC_CFG0 (0x70)
114 #define EMMC_CFG1 (0x74)
115 #define EMMC_STS (0x78)
116 #define EMMC_IOCON (0x7c)
117 #define SDC_ACMD_RESP (0x80)
118 #define SDC_ACMD19_TRG (0x84)
119 #define SDC_ACMD19_STS (0x88)
120 #define MSDC_DMA_SA (0x90)
121 #define MSDC_DMA_CA (0x94)
122 #define MSDC_DMA_CTRL (0x98)
123 #define MSDC_DMA_CFG (0x9c)
124 #define MSDC_DBG_SEL (0xa0)
125 #define MSDC_DBG_OUT (0xa4)
126 #define MSDC_PATCH_BIT (0xb0)
127 #define MSDC_PATCH_BIT0 MSDC_PATCH_BIT
128 #define MSDC_PATCH_BIT1 (0xb4)
129 #define MSDC_PAD_CTL0 (0xe0)
130 #define MSDC_PAD_CTL1 (0xe4)
131 #define MSDC_PAD_CTL2 (0xe8)
132 #define MSDC_PAD_TUNE (0xec)
133 #define MSDC_DAT_RDDLY0 (0xf0)
134 #define MSDC_DAT_RDDLY1 (0xf4)
135 #define MSDC_HW_DBG (0xf8)
136 #define MSDC_VERSION (0x100)
137 #define MSDC_ECO_VER (0x104)
138
139 /*--------------------------------------------------------------------------*/
140 /* Register Mask */
141 /*--------------------------------------------------------------------------*/
142
143 /* MSDC_CFG mask */
144 #define MSDC_CFG_MODE (0x1 << 0) /* RW */
145 #define MSDC_CFG_CKPDN (0x1 << 1) /* RW */
146 #define MSDC_CFG_RST (0x1 << 2) /* RW */
147 #define MSDC_CFG_PIO (0x1 << 3) /* RW */
148 #define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */
149 #define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */
150 #define MSDC_CFG_BV18PSS (0x1 << 6) /* R */
151 #define MSDC_CFG_CKSTB (0x1 << 7) /* R */
152 #define MSDC_CFG_CKDIV (0xff << 8) /* RW */
153 #define MSDC_CFG_CKMOD (0x3 << 16) /* RW */
154
155 /* MSDC_IOCON mask */
156 #define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */
157 #define MSDC_IOCON_RSPL (0x1 << 1) /* RW */
158 #define MSDC_IOCON_DSPL (0x1 << 2) /* RW */
159 #define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */
160 #define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */
161 #define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */
162 #define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */
163 #define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */
164 #define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */
165 #define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */
166 #define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */
167 #define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */
168 #define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */
169 #define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */
170 #define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */
171
172 /* MSDC_PS mask */
173 #define MSDC_PS_CDEN (0x1 << 0) /* RW */
174 #define MSDC_PS_CDSTS (0x1 << 1) /* R */
175 #define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */
176 #define MSDC_PS_DAT (0xff << 16) /* R */
177 #define MSDC_PS_CMD (0x1 << 24) /* R */
178 #define MSDC_PS_WP (0x1UL << 31) /* R */
179
180 /* MSDC_INT mask */
181 #define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */
182 #define MSDC_INT_CDSC (0x1 << 1) /* W1C */
183 #define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */
184 #define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */
185 #define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */
186 #define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */
187 #define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */
188 #define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */
189 #define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */
190 #define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */
191 #define MSDC_INT_CSTA (0x1 << 11) /* R */
192 #define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */
193 #define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */
194 #define MSDC_INT_DATTMO (0x1 << 14) /* W1C */
195 #define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */
196 #define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */
197
198 /* MSDC_INTEN mask */
199 #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */
200 #define MSDC_INTEN_CDSC (0x1 << 1) /* RW */
201 #define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */
202 #define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */
203 #define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */
204 #define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */
205 #define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */
206 #define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */
207 #define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */
208 #define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */
209 #define MSDC_INTEN_CSTA (0x1 << 11) /* RW */
210 #define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */
211 #define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */
212 #define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */
213 #define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */
214 #define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */
215
216 /* MSDC_FIFOCS mask */
217 #define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */
218 #define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */
219 #define MSDC_FIFOCS_CLR (0x1UL << 31) /* RW */
220
221 /* SDC_CFG mask */
222 #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */
223 #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */
224 #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */
225 #define SDC_CFG_SDIO (0x1 << 19) /* RW */
226 #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */
227 #define SDC_CFG_INTATGAP (0x1 << 21) /* RW */
228 #define SDC_CFG_DTOC (0xffUL << 24) /* RW */
229
230 /* SDC_CMD mask */
231 #define SDC_CMD_OPC (0x3f << 0) /* RW */
232 #define SDC_CMD_BRK (0x1 << 6) /* RW */
233 #define SDC_CMD_RSPTYP (0x7 << 7) /* RW */
234 #define SDC_CMD_DTYP (0x3 << 11) /* RW */
235 #define SDC_CMD_DTYP (0x3 << 11) /* RW */
236 #define SDC_CMD_RW (0x1 << 13) /* RW */
237 #define SDC_CMD_STOP (0x1 << 14) /* RW */
238 #define SDC_CMD_GOIRQ (0x1 << 15) /* RW */
239 #define SDC_CMD_BLKLEN (0xfff << 16) /* RW */
240 #define SDC_CMD_AUTOCMD (0x3 << 28) /* RW */
241 #define SDC_CMD_VOLSWTH (0x1 << 30) /* RW */
242
243 /* SDC_STS mask */
244 #define SDC_STS_SDCBUSY (0x1 << 0) /* RW */
245 #define SDC_STS_CMDBUSY (0x1 << 1) /* RW */
246 #define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */
247
248 /* SDC_DCRC_STS mask */
249 #define SDC_DCRC_STS_NEG (0xf << 8) /* RO */
250 #define SDC_DCRC_STS_POS (0xff << 0) /* RO */
251
252 /* EMMC_CFG0 mask */
253 #define EMMC_CFG0_BOOTSTART (0x1 << 0) /* W */
254 #define EMMC_CFG0_BOOTSTOP (0x1 << 1) /* W */
255 #define EMMC_CFG0_BOOTMODE (0x1 << 2) /* RW */
256 #define EMMC_CFG0_BOOTACKDIS (0x1 << 3) /* RW */
257 #define EMMC_CFG0_BOOTWDLY (0x7 << 12) /* RW */
258 #define EMMC_CFG0_BOOTSUPP (0x1 << 15) /* RW */
259
260 /* EMMC_CFG1 mask */
261 #define EMMC_CFG1_BOOTDATTMC (0xfffff << 0) /* RW */
262 #define EMMC_CFG1_BOOTACKTMC (0xfffUL << 20) /* RW */
263
264 /* EMMC_STS mask */
265 #define EMMC_STS_BOOTCRCERR (0x1 << 0) /* W1C */
266 #define EMMC_STS_BOOTACKERR (0x1 << 1) /* W1C */
267 #define EMMC_STS_BOOTDATTMO (0x1 << 2) /* W1C */
268 #define EMMC_STS_BOOTACKTMO (0x1 << 3) /* W1C */
269 #define EMMC_STS_BOOTUPSTATE (0x1 << 4) /* R */
270 #define EMMC_STS_BOOTACKRCV (0x1 << 5) /* W1C */
271 #define EMMC_STS_BOOTDATRCV (0x1 << 6) /* R */
272
273 /* EMMC_IOCON mask */
274 #define EMMC_IOCON_BOOTRST (0x1 << 0) /* RW */
275
276 /* SDC_ACMD19_TRG mask */
277 #define SDC_ACMD19_TRG_TUNESEL (0xf << 0) /* RW */
278
279 /* MSDC_DMA_CTRL mask */
280 #define MSDC_DMA_CTRL_START (0x1 << 0) /* W */
281 #define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */
282 #define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */
283 #define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */
284 #define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */
285 #define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */
286 #define MSDC_DMA_CTRL_XFERSZ (0xffffUL << 16)/* RW */
287
288 /* MSDC_DMA_CFG mask */
289 #define MSDC_DMA_CFG_STS (0x1 << 0) /* R */
290 #define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */
291 #define MSDC_DMA_CFG_BDCSERR (0x1 << 4) /* R */
292 #define MSDC_DMA_CFG_GPDCSERR (0x1 << 5) /* R */
293
294 /* MSDC_PATCH_BIT mask */
295 #define MSDC_PATCH_BIT_WFLSMODE (0x1 << 0) /* RW */
296 #define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */
297 #define MSDC_PATCH_BIT_CKGEN_CK (0x1 << 6) /* E2: Fixed to 1 */
298 #define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */
299 #define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */
300 #define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */
301 #define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */
302 #define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */
303 #define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */
304 #define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */
305 #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */
306 #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */
307
308 /* MSDC_PATCH_BIT1 mask */
309 #define MSDC_PATCH_BIT1_WRDAT_CRCS (0x7 << 3)
310 #define MSDC_PATCH_BIT1_CMD_RSP (0x7 << 0)
311
312 /* MSDC_PAD_CTL0 mask */
313 #define MSDC_PAD_CTL0_CLKDRVN (0x7 << 0) /* RW */
314 #define MSDC_PAD_CTL0_CLKDRVP (0x7 << 4) /* RW */
315 #define MSDC_PAD_CTL0_CLKSR (0x1 << 8) /* RW */
316 #define MSDC_PAD_CTL0_CLKPD (0x1 << 16) /* RW */
317 #define MSDC_PAD_CTL0_CLKPU (0x1 << 17) /* RW */
318 #define MSDC_PAD_CTL0_CLKSMT (0x1 << 18) /* RW */
319 #define MSDC_PAD_CTL0_CLKIES (0x1 << 19) /* RW */
320 #define MSDC_PAD_CTL0_CLKTDSEL (0xf << 20) /* RW */
321 #define MSDC_PAD_CTL0_CLKRDSEL (0xffUL << 24) /* RW */
322
323 /* MSDC_PAD_CTL1 mask */
324 #define MSDC_PAD_CTL1_CMDDRVN (0x7 << 0) /* RW */
325 #define MSDC_PAD_CTL1_CMDDRVP (0x7 << 4) /* RW */
326 #define MSDC_PAD_CTL1_CMDSR (0x1 << 8) /* RW */
327 #define MSDC_PAD_CTL1_CMDPD (0x1 << 16) /* RW */
328 #define MSDC_PAD_CTL1_CMDPU (0x1 << 17) /* RW */
329 #define MSDC_PAD_CTL1_CMDSMT (0x1 << 18) /* RW */
330 #define MSDC_PAD_CTL1_CMDIES (0x1 << 19) /* RW */
331 #define MSDC_PAD_CTL1_CMDTDSEL (0xf << 20) /* RW */
332 #define MSDC_PAD_CTL1_CMDRDSEL (0xffUL << 24) /* RW */
333
334 /* MSDC_PAD_CTL2 mask */
335 #define MSDC_PAD_CTL2_DATDRVN (0x7 << 0) /* RW */
336 #define MSDC_PAD_CTL2_DATDRVP (0x7 << 4) /* RW */
337 #define MSDC_PAD_CTL2_DATSR (0x1 << 8) /* RW */
338 #define MSDC_PAD_CTL2_DATPD (0x1 << 16) /* RW */
339 #define MSDC_PAD_CTL2_DATPU (0x1 << 17) /* RW */
340 #define MSDC_PAD_CTL2_DATIES (0x1 << 19) /* RW */
341 #define MSDC_PAD_CTL2_DATSMT (0x1 << 18) /* RW */
342 #define MSDC_PAD_CTL2_DATTDSEL (0xf << 20) /* RW */
343 #define MSDC_PAD_CTL2_DATRDSEL (0xffUL << 24) /* RW */
344
345 /* MSDC_PAD_TUNE mask */
346 #define MSDC_PAD_TUNE_DATWRDLY (0x1F << 0) /* RW */
347 #define MSDC_PAD_TUNE_DATRRDLY (0x1F << 8) /* RW */
348 #define MSDC_PAD_TUNE_CMDRDLY (0x1F << 16) /* RW */
349 #define MSDC_PAD_TUNE_CMDRRDLY (0x1FUL << 22) /* RW */
350 #define MSDC_PAD_TUNE_CLKTXDLY (0x1FUL << 27) /* RW */
351
352 /* MSDC_DAT_RDDLY0/1 mask */
353 #define MSDC_DAT_RDDLY0_D0 (0x1F << 0) /* RW */
354 #define MSDC_DAT_RDDLY0_D1 (0x1F << 8) /* RW */
355 #define MSDC_DAT_RDDLY0_D2 (0x1F << 16) /* RW */
356 #define MSDC_DAT_RDDLY0_D3 (0x1F << 24) /* RW */
357
358 #define MSDC_DAT_RDDLY1_D4 (0x1F << 0) /* RW */
359 #define MSDC_DAT_RDDLY1_D5 (0x1F << 8) /* RW */
360 #define MSDC_DAT_RDDLY1_D6 (0x1F << 16) /* RW */
361 #define MSDC_DAT_RDDLY1_D7 (0x1F << 24) /* RW */
362
363 #define MSDC_CKGEN_MSDC_DLY_SEL (0x1F << 10)
364 #define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7)
365 #define MSDC_CKGEN_MSDC_CK_SEL (0x1 << 6)
366 #define CARD_READY_FOR_DATA (1 << 8)
367 #define CARD_CURRENT_STATE(x) ((x & 0x00001E00) >> 9)
368
369 /*--------------------------------------------------------------------------*/
370 /* Descriptor Structure */
371 /*--------------------------------------------------------------------------*/
372 struct gpd {
373 u32 hwo:1; /* could be changed by hw */
374 u32 bdp:1;
375 u32 rsv0:6;
376 u32 chksum:8;
377 u32 intr:1;
378 u32 rsv1:15;
379 void *next;
380 void *ptr;
381 u32 buflen:16;
382 u32 extlen:8;
383 u32 rsv2:8;
384 u32 arg;
385 u32 blknum;
386 u32 cmd;
387 };
388
389 struct bd {
390 u32 eol:1;
391 u32 rsv0:7;
392 u32 chksum:8;
393 u32 rsv1:1;
394 u32 blkpad:1;
395 u32 dwpad:1;
396 u32 rsv2:13;
397 void *next;
398 void *ptr;
399 u32 buflen:16;
400 u32 rsv3:16;
401 };
402
403 struct msdc_dma {
404 struct gpd *gpd; /* pointer to gpd array */
405 struct bd *bd; /* pointer to bd array */
406 dma_addr_t gpd_addr; /* the physical address of gpd array */
407 dma_addr_t bd_addr; /* the physical address of bd array */
408 };
409
410 struct msdc_host {
411 struct msdc_hw *hw;
412
413 struct mmc_host *mmc; /* mmc structure */
414 struct mmc_command *cmd;
415 struct mmc_data *data;
416 struct mmc_request *mrq;
417 int cmd_rsp;
418
419 int error;
420 spinlock_t lock; /* mutex */
421 struct semaphore sem;
422
423 u32 blksz; /* host block size */
424 void __iomem *base; /* host base address */
425 int id; /* host id */
426 int pwr_ref; /* core power reference count */
427
428 u32 xfer_size; /* total transferred size */
429
430 struct msdc_dma dma; /* dma channel */
431 u32 dma_xfer_size; /* dma transfer size in bytes */
432
433 u32 timeout_ns; /* data timeout ns */
434 u32 timeout_clks; /* data timeout clks */
435
436 int irq; /* host interrupt */
437
438 struct delayed_work card_delaywork;
439
440 struct completion cmd_done;
441 struct completion xfer_done;
442 struct pm_message pm_state;
443
444 u32 mclk; /* mmc subsystem clock */
445 u32 hclk; /* host clock speed */
446 u32 sclk; /* SD/MS clock speed */
447 u8 core_clkon; /* Host core clock on ? */
448 u8 card_clkon; /* Card clock on ? */
449 u8 core_power; /* core power */
450 u8 power_mode; /* host power mode */
451 u8 card_inserted; /* card inserted ? */
452 u8 suspend; /* host suspended ? */
453 u8 app_cmd; /* for app command */
454 u32 app_cmd_arg;
455 };
456
sdr_set_bits(void __iomem * reg,u32 bs)457 static inline void sdr_set_bits(void __iomem *reg, u32 bs)
458 {
459 u32 val = readl(reg);
460
461 val |= bs;
462 writel(val, reg);
463 }
464
sdr_clr_bits(void __iomem * reg,u32 bs)465 static inline void sdr_clr_bits(void __iomem *reg, u32 bs)
466 {
467 u32 val = readl(reg);
468
469 val &= ~bs;
470 writel(val, reg);
471 }
472
sdr_set_field(void __iomem * reg,u32 field,u32 val)473 static inline void sdr_set_field(void __iomem *reg, u32 field, u32 val)
474 {
475 unsigned int tv = readl(reg);
476
477 tv &= ~field;
478 tv |= ((val) << (ffs((unsigned int)field) - 1));
479 writel(tv, reg);
480 }
481
sdr_get_field(void __iomem * reg,u32 field,u32 * val)482 static inline void sdr_get_field(void __iomem *reg, u32 field, u32 *val)
483 {
484 unsigned int tv = readl(reg);
485 *val = ((tv & field) >> (ffs((unsigned int)field) - 1));
486 }
487
488 #endif
489
