1 /* 2 * Copyright (C) 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21 #ifndef _mmhub_9_4_0_SH_MASK_HEADER 22 #define _mmhub_9_4_0_SH_MASK_HEADER 23 24 //MMEA0_SDP_ARB_FINAL 25 #define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 26 #define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 27 #define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa 28 #define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf 29 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 30 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 31 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 32 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 33 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 34 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 35 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 36 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 37 #define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 38 #define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a 39 #define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL 40 #define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L 41 #define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L 42 #define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L 43 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L 44 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L 45 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L 46 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L 47 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L 48 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L 49 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L 50 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L 51 #define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L 52 #define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L 53 //MMEA0_EDC_CNT 54 #define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 55 #define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 56 #define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 57 #define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 58 #define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 59 #define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa 60 #define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc 61 #define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe 62 #define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 63 #define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 64 #define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 65 #define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 66 #define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 67 #define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a 68 #define MMEA0_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c 69 #define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 70 #define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 71 #define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 72 #define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 73 #define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 74 #define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 75 #define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L 76 #define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L 77 #define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L 78 #define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L 79 #define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L 80 #define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L 81 #define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L 82 #define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L 83 #define MMEA0_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L 84 //MMEA0_EDC_CNT2 85 #define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 86 #define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 87 #define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 88 #define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 89 #define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 90 #define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa 91 #define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc 92 #define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe 93 #define MMEA0_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT 0x10 94 #define MMEA0_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT 0x12 95 #define MMEA0_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT 0x14 96 #define MMEA0_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT 0x16 97 #define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 98 #define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 99 #define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 100 #define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 101 #define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 102 #define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 103 #define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L 104 #define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L 105 #define MMEA0_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK 0x00030000L 106 #define MMEA0_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L 107 #define MMEA0_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK 0x00300000L 108 #define MMEA0_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L 109 //MMEA0_EDC_MODE 110 #define MMEA0_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 111 #define MMEA0_EDC_MODE__GATE_FUE__SHIFT 0x11 112 #define MMEA0_EDC_MODE__DED_MODE__SHIFT 0x14 113 #define MMEA0_EDC_MODE__PROP_FED__SHIFT 0x1d 114 #define MMEA0_EDC_MODE__BYPASS__SHIFT 0x1f 115 #define MMEA0_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L 116 #define MMEA0_EDC_MODE__GATE_FUE_MASK 0x00020000L 117 #define MMEA0_EDC_MODE__DED_MODE_MASK 0x00300000L 118 #define MMEA0_EDC_MODE__PROP_FED_MASK 0x20000000L 119 #define MMEA0_EDC_MODE__BYPASS_MASK 0x80000000L 120 //MMEA0_ERR_STATUS 121 #define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 122 #define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 123 #define MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 124 #define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa 125 #define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb 126 #define MMEA0_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc 127 #define MMEA0_ERR_STATUS__FUE_FLAG__SHIFT 0xd 128 #define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL 129 #define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L 130 #define MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L 131 #define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L 132 #define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L 133 #define MMEA0_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L 134 #define MMEA0_ERR_STATUS__FUE_FLAG_MASK 0x00002000L 135 //MMEA1_SDP_ARB_FINAL 136 #define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 137 #define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 138 #define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa 139 #define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf 140 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 141 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 142 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 143 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 144 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 145 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 146 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 147 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 148 #define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 149 #define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a 150 #define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL 151 #define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L 152 #define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L 153 #define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L 154 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L 155 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L 156 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L 157 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L 158 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L 159 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L 160 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L 161 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L 162 #define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L 163 #define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L 164 //MMEA1_EDC_CNT 165 #define MMEA1_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 166 #define MMEA1_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 167 #define MMEA1_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 168 #define MMEA1_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 169 #define MMEA1_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 170 #define MMEA1_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa 171 #define MMEA1_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc 172 #define MMEA1_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe 173 #define MMEA1_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 174 #define MMEA1_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 175 #define MMEA1_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 176 #define MMEA1_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 177 #define MMEA1_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 178 #define MMEA1_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a 179 #define MMEA1_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c 180 #define MMEA1_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 181 #define MMEA1_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 182 #define MMEA1_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 183 #define MMEA1_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 184 #define MMEA1_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 185 #define MMEA1_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 186 #define MMEA1_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L 187 #define MMEA1_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L 188 #define MMEA1_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L 189 #define MMEA1_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L 190 #define MMEA1_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L 191 #define MMEA1_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L 192 #define MMEA1_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L 193 #define MMEA1_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L 194 #define MMEA1_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L 195 //MMEA1_EDC_CNT2 196 #define MMEA1_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 197 #define MMEA1_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 198 #define MMEA1_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 199 #define MMEA1_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 200 #define MMEA1_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 201 #define MMEA1_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa 202 #define MMEA1_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc 203 #define MMEA1_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe 204 #define MMEA1_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT 0x10 205 #define MMEA1_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT 0x12 206 #define MMEA1_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT 0x14 207 #define MMEA1_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT 0x16 208 #define MMEA1_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 209 #define MMEA1_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 210 #define MMEA1_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 211 #define MMEA1_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 212 #define MMEA1_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 213 #define MMEA1_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 214 #define MMEA1_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L 215 #define MMEA1_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L 216 #define MMEA1_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK 0x00030000L 217 #define MMEA1_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L 218 #define MMEA1_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK 0x00300000L 219 #define MMEA1_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L 220 //MMEA1_EDC_MODE 221 #define MMEA1_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 222 #define MMEA1_EDC_MODE__GATE_FUE__SHIFT 0x11 223 #define MMEA1_EDC_MODE__DED_MODE__SHIFT 0x14 224 #define MMEA1_EDC_MODE__PROP_FED__SHIFT 0x1d 225 #define MMEA1_EDC_MODE__BYPASS__SHIFT 0x1f 226 #define MMEA1_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L 227 #define MMEA1_EDC_MODE__GATE_FUE_MASK 0x00020000L 228 #define MMEA1_EDC_MODE__DED_MODE_MASK 0x00300000L 229 #define MMEA1_EDC_MODE__PROP_FED_MASK 0x20000000L 230 #define MMEA1_EDC_MODE__BYPASS_MASK 0x80000000L 231 //MMEA1_ERR_STATUS 232 #define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 233 #define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 234 #define MMEA1_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 235 #define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa 236 #define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb 237 #define MMEA1_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc 238 #define MMEA1_ERR_STATUS__FUE_FLAG__SHIFT 0xd 239 #define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL 240 #define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L 241 #define MMEA1_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L 242 #define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L 243 #define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L 244 #define MMEA1_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L 245 #define MMEA1_ERR_STATUS__FUE_FLAG_MASK 0x00002000L 246 247 // addressBlock: mmhub_utcl2_vmsharedpfdec 248 //MC_VM_XGMI_LFB_CNTL 249 #define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION__SHIFT 0x0 250 #define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION__SHIFT 0x4 251 #define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION_MASK 0x00000007L 252 #define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION_MASK 0x00000070L 253 //MC_VM_XGMI_LFB_SIZE 254 #define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE__SHIFT 0x0 255 #define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE_MASK 0x0000FFFFL 256 257 #endif 258
