1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * PKUnity Serial Peripheral Interface (SPI) Registers 4 */ 5 /* 6 * Control reg. 0 SPI_CR0 7 */ 8 #define SPI_CR0 (PKUNITY_SPI_BASE + 0x0000) 9 /* 10 * Control reg. 1 SPI_CR1 11 */ 12 #define SPI_CR1 (PKUNITY_SPI_BASE + 0x0004) 13 /* 14 * Enable reg SPI_SSIENR 15 */ 16 #define SPI_SSIENR (PKUNITY_SPI_BASE + 0x0008) 17 /* 18 * Status reg SPI_SR 19 */ 20 #define SPI_SR (PKUNITY_SPI_BASE + 0x0028) 21 /* 22 * Interrupt Mask reg SPI_IMR 23 */ 24 #define SPI_IMR (PKUNITY_SPI_BASE + 0x002C) 25 /* 26 * Interrupt Status reg SPI_ISR 27 */ 28 #define SPI_ISR (PKUNITY_SPI_BASE + 0x0030) 29 30 /* 31 * Enable SPI Controller SPI_SSIENR_EN 32 */ 33 #define SPI_SSIENR_EN FIELD(1, 1, 0) 34 35 /* 36 * SPI Busy SPI_SR_BUSY 37 */ 38 #define SPI_SR_BUSY FIELD(1, 1, 0) 39 /* 40 * Transmit FIFO Not Full SPI_SR_TFNF 41 */ 42 #define SPI_SR_TFNF FIELD(1, 1, 1) 43 /* 44 * Transmit FIFO Empty SPI_SR_TFE 45 */ 46 #define SPI_SR_TFE FIELD(1, 1, 2) 47 /* 48 * Receive FIFO Not Empty SPI_SR_RFNE 49 */ 50 #define SPI_SR_RFNE FIELD(1, 1, 3) 51 /* 52 * Receive FIFO Full SPI_SR_RFF 53 */ 54 #define SPI_SR_RFF FIELD(1, 1, 4) 55 56 /* 57 * Trans. FIFO Empty Interrupt Status SPI_ISR_TXEIS 58 */ 59 #define SPI_ISR_TXEIS FIELD(1, 1, 0) 60 /* 61 * Trans. FIFO Overflow Interrupt Status SPI_ISR_TXOIS 62 */ 63 #define SPI_ISR_TXOIS FIELD(1, 1, 1) 64 /* 65 * Receiv. FIFO Underflow Interrupt Status SPI_ISR_RXUIS 66 */ 67 #define SPI_ISR_RXUIS FIELD(1, 1, 2) 68 /* 69 * Receiv. FIFO Overflow Interrupt Status SPI_ISR_RXOIS 70 */ 71 #define SPI_ISR_RXOIS FIELD(1, 1, 3) 72 /* 73 * Receiv. FIFO Full Interrupt Status SPI_ISR_RXFIS 74 */ 75 #define SPI_ISR_RXFIS FIELD(1, 1, 4) 76 #define SPI_ISR_MSTIS FIELD(1, 1, 5) 77 78 /* 79 * Trans. FIFO Empty Interrupt Mask SPI_IMR_TXEIM 80 */ 81 #define SPI_IMR_TXEIM FIELD(1, 1, 0) 82 /* 83 * Trans. FIFO Overflow Interrupt Mask SPI_IMR_TXOIM 84 */ 85 #define SPI_IMR_TXOIM FIELD(1, 1, 1) 86 /* 87 * Receiv. FIFO Underflow Interrupt Mask SPI_IMR_RXUIM 88 */ 89 #define SPI_IMR_RXUIM FIELD(1, 1, 2) 90 /* 91 * Receiv. FIFO Overflow Interrupt Mask SPI_IMR_RXOIM 92 */ 93 #define SPI_IMR_RXOIM FIELD(1, 1, 3) 94 /* 95 * Receiv. FIFO Full Interrupt Mask SPI_IMR_RXFIM 96 */ 97 #define SPI_IMR_RXFIM FIELD(1, 1, 4) 98 #define SPI_IMR_MSTIM FIELD(1, 1, 5) 99 100
