1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * PKUnity Multi-Media Card and Security Digital Card (MMC/SD) Registers 4 */ 5 /* 6 * Clock Control Reg SDC_CCR 7 */ 8 #define SDC_CCR (PKUNITY_SDC_BASE + 0x0000) 9 /* 10 * Software Reset Reg SDC_SRR 11 */ 12 #define SDC_SRR (PKUNITY_SDC_BASE + 0x0004) 13 /* 14 * Argument Reg SDC_ARGUMENT 15 */ 16 #define SDC_ARGUMENT (PKUNITY_SDC_BASE + 0x0008) 17 /* 18 * Command Reg SDC_COMMAND 19 */ 20 #define SDC_COMMAND (PKUNITY_SDC_BASE + 0x000C) 21 /* 22 * Block Size Reg SDC_BLOCKSIZE 23 */ 24 #define SDC_BLOCKSIZE (PKUNITY_SDC_BASE + 0x0010) 25 /* 26 * Block Cound Reg SDC_BLOCKCOUNT 27 */ 28 #define SDC_BLOCKCOUNT (PKUNITY_SDC_BASE + 0x0014) 29 /* 30 * Transfer Mode Reg SDC_TMR 31 */ 32 #define SDC_TMR (PKUNITY_SDC_BASE + 0x0018) 33 /* 34 * Response Reg. 0 SDC_RES0 35 */ 36 #define SDC_RES0 (PKUNITY_SDC_BASE + 0x001C) 37 /* 38 * Response Reg. 1 SDC_RES1 39 */ 40 #define SDC_RES1 (PKUNITY_SDC_BASE + 0x0020) 41 /* 42 * Response Reg. 2 SDC_RES2 43 */ 44 #define SDC_RES2 (PKUNITY_SDC_BASE + 0x0024) 45 /* 46 * Response Reg. 3 SDC_RES3 47 */ 48 #define SDC_RES3 (PKUNITY_SDC_BASE + 0x0028) 49 /* 50 * Read Timeout Control Reg SDC_RTCR 51 */ 52 #define SDC_RTCR (PKUNITY_SDC_BASE + 0x002C) 53 /* 54 * Interrupt Status Reg SDC_ISR 55 */ 56 #define SDC_ISR (PKUNITY_SDC_BASE + 0x0030) 57 /* 58 * Interrupt Status Mask Reg SDC_ISMR 59 */ 60 #define SDC_ISMR (PKUNITY_SDC_BASE + 0x0034) 61 /* 62 * RX FIFO SDC_RXFIFO 63 */ 64 #define SDC_RXFIFO (PKUNITY_SDC_BASE + 0x0038) 65 /* 66 * TX FIFO SDC_TXFIFO 67 */ 68 #define SDC_TXFIFO (PKUNITY_SDC_BASE + 0x003C) 69 70 /* 71 * SD Clock Enable SDC_CCR_CLKEN 72 */ 73 #define SDC_CCR_CLKEN FIELD(1, 1, 2) 74 /* 75 * [15:8] SDC_CCR_PDIV(v) 76 */ 77 #define SDC_CCR_PDIV(v) FIELD((v), 8, 8) 78 79 /* 80 * Software reset enable SDC_SRR_ENABLE 81 */ 82 #define SDC_SRR_ENABLE FIELD(0, 1, 0) 83 /* 84 * Software reset disable SDC_SRR_DISABLE 85 */ 86 #define SDC_SRR_DISABLE FIELD(1, 1, 0) 87 88 /* 89 * Response type SDC_COMMAND_RESTYPE_MASK 90 */ 91 #define SDC_COMMAND_RESTYPE_MASK FMASK(2, 0) 92 /* 93 * No response SDC_COMMAND_RESTYPE_NONE 94 */ 95 #define SDC_COMMAND_RESTYPE_NONE FIELD(0, 2, 0) 96 /* 97 * 136-bit long response SDC_COMMAND_RESTYPE_LONG 98 */ 99 #define SDC_COMMAND_RESTYPE_LONG FIELD(1, 2, 0) 100 /* 101 * 48-bit short response SDC_COMMAND_RESTYPE_SHORT 102 */ 103 #define SDC_COMMAND_RESTYPE_SHORT FIELD(2, 2, 0) 104 /* 105 * 48-bit short and test if busy response SDC_COMMAND_RESTYPE_SHORTBUSY 106 */ 107 #define SDC_COMMAND_RESTYPE_SHORTBUSY FIELD(3, 2, 0) 108 /* 109 * data ready SDC_COMMAND_DATAREADY 110 */ 111 #define SDC_COMMAND_DATAREADY FIELD(1, 1, 2) 112 #define SDC_COMMAND_CMDEN FIELD(1, 1, 3) 113 /* 114 * [10:5] SDC_COMMAND_CMDINDEX(v) 115 */ 116 #define SDC_COMMAND_CMDINDEX(v) FIELD((v), 6, 5) 117 118 /* 119 * [10:0] SDC_BLOCKSIZE_BSMASK(v) 120 */ 121 #define SDC_BLOCKSIZE_BSMASK(v) FIELD((v), 11, 0) 122 /* 123 * [11:0] SDC_BLOCKCOUNT_BCMASK(v) 124 */ 125 #define SDC_BLOCKCOUNT_BCMASK(v) FIELD((v), 12, 0) 126 127 /* 128 * Data Width 1bit SDC_TMR_WTH_1BIT 129 */ 130 #define SDC_TMR_WTH_1BIT FIELD(0, 1, 0) 131 /* 132 * Data Width 4bit SDC_TMR_WTH_4BIT 133 */ 134 #define SDC_TMR_WTH_4BIT FIELD(1, 1, 0) 135 /* 136 * Read SDC_TMR_DIR_READ 137 */ 138 #define SDC_TMR_DIR_READ FIELD(0, 1, 1) 139 /* 140 * Write SDC_TMR_DIR_WRITE 141 */ 142 #define SDC_TMR_DIR_WRITE FIELD(1, 1, 1) 143 144 #define SDC_IR_MASK FMASK(13, 0) 145 #define SDC_IR_RESTIMEOUT FIELD(1, 1, 0) 146 #define SDC_IR_WRITECRC FIELD(1, 1, 1) 147 #define SDC_IR_READCRC FIELD(1, 1, 2) 148 #define SDC_IR_TXFIFOREAD FIELD(1, 1, 3) 149 #define SDC_IR_RXFIFOWRITE FIELD(1, 1, 4) 150 #define SDC_IR_READTIMEOUT FIELD(1, 1, 5) 151 #define SDC_IR_DATACOMPLETE FIELD(1, 1, 6) 152 #define SDC_IR_CMDCOMPLETE FIELD(1, 1, 7) 153 #define SDC_IR_RXFIFOFULL FIELD(1, 1, 8) 154 #define SDC_IR_RXFIFOEMPTY FIELD(1, 1, 9) 155 #define SDC_IR_TXFIFOFULL FIELD(1, 1, 10) 156 #define SDC_IR_TXFIFOEMPTY FIELD(1, 1, 11) 157 #define SDC_IR_ENDCMDWITHRES FIELD(1, 1, 12) 158